Moved the old firmware for STM32L011 to fw_old and migrated the firmware to STM32L031 in fw. I2C and TIM21 seem functional. USART2 is receiving correctly, but the modbus test is not receiving messages.
This commit is contained in:
David Žaitlík
@@ -1,10 +1,10 @@
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/**
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******************************************************************************
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* @file stm32l011xx.h
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* @file stm32l031xx.h
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* @author MCD Application Team
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* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File.
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* This file contains all the peripheral register's definitions, bits
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* definitions and memory mapping for stm32l011xx devices.
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* definitions and memory mapping for stm32l031xx devices.
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*
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* This file contains:
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* - Data structures and the address mapping for all peripherals
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@@ -29,12 +29,12 @@
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* @{
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*/
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/** @addtogroup stm32l011xx
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/** @addtogroup stm32l031xx
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* @{
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*/
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#ifndef __STM32L011xx_H
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#define __STM32L011xx_H
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#ifndef __STM32L031xx_H
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#define __STM32L031xx_H
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#ifdef __cplusplus
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extern "C" {
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@@ -62,7 +62,7 @@
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*/
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/**
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* @brief stm32l011xx Interrupt Number Definition, according to the selected device
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* @brief stm32l031xx Interrupt Number Definition, according to the selected device
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* in @ref Library_configuration_section
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*/
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@@ -87,11 +87,12 @@ typedef enum
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EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */
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DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */
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DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */
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DMA1_Channel4_5_IRQn = 11, /*!< DMA1 Channel 4 and Channel 5 Interrupts */
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DMA1_Channel4_5_6_7_IRQn = 11, /*!< DMA1 Channel 4, Channel 5, Channel 6 and Channel 7 Interrupts */
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ADC1_COMP_IRQn = 12, /*!< ADC1, COMP1 and COMP2 Interrupts */
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LPTIM1_IRQn = 13, /*!< LPTIM1 Interrupt */
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TIM2_IRQn = 15, /*!< TIM2 Interrupt */
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TIM21_IRQn = 20, /*!< TIM21 Interrupt */
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TIM22_IRQn = 22, /*!< TIM22 Interrupt */
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I2C1_IRQn = 23, /*!< I2C1 Interrupt */
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SPI1_IRQn = 25, /*!< SPI1 Interrupt */
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USART2_IRQn = 28, /*!< USART2 Interrupt */
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@@ -478,9 +479,9 @@ typedef struct
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#define FLASH_BASE (0x08000000UL) /*!< FLASH base address in the alias region */
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#define DATA_EEPROM_BASE (0x08080000UL) /*!< DATA_EEPROM base address in the alias region */
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#define DATA_EEPROM_END (0x080801FFUL) /*!< DATA EEPROM end address in the alias region */
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#define DATA_EEPROM_END (0x080803FFUL) /*!< DATA EEPROM end address in the alias region */
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#define SRAM_BASE (0x20000000UL) /*!< SRAM base address in the alias region */
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#define SRAM_SIZE_MAX (0x00000800UL) /*!< maximum SRAM size (up to 2KBytes) */
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#define SRAM_SIZE_MAX (0x00002000UL) /*!< maximum SRAM size (up to 8KBytes) */
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#define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address in the alias region */
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@@ -505,6 +506,7 @@ typedef struct
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#define COMP12_COMMON ((COMP_Common_TypeDef *) COMP1_BASE)
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#define EXTI_BASE (APBPERIPH_BASE + 0x00010400UL)
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#define TIM21_BASE (APBPERIPH_BASE + 0x00010800UL)
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#define TIM22_BASE (APBPERIPH_BASE + 0x00011400UL)
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#define ADC1_BASE (APBPERIPH_BASE + 0x00012400UL)
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#define ADC_BASE (APBPERIPH_BASE + 0x00012708UL)
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#define SPI1_BASE (APBPERIPH_BASE + 0x00013000UL)
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@@ -516,6 +518,8 @@ typedef struct
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#define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030UL)
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#define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044UL)
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#define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058UL)
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#define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006CUL)
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#define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080UL)
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#define DMA1_CSELR_BASE (DMA1_BASE + 0x000000A8UL)
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@@ -529,6 +533,7 @@ typedef struct
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#define GPIOA_BASE (IOPPERIPH_BASE + 0x00000000UL)
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#define GPIOB_BASE (IOPPERIPH_BASE + 0x00000400UL)
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#define GPIOC_BASE (IOPPERIPH_BASE + 0x00000800UL)
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#define GPIOH_BASE (IOPPERIPH_BASE + 0x00001C00UL)
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/**
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* @}
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@@ -553,6 +558,7 @@ typedef struct
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#define COMP2 ((COMP_TypeDef *) COMP2_BASE)
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#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
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#define TIM21 ((TIM_TypeDef *) TIM21_BASE)
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#define TIM22 ((TIM_TypeDef *) TIM22_BASE)
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#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
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#define ADC1_COMMON ((ADC_Common_TypeDef *) ADC_BASE)
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/* Legacy defines */
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@@ -566,6 +572,8 @@ typedef struct
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#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
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#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
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#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
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#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
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#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
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#define DMA1_CSELR ((DMA_Request_TypeDef *) DMA1_CSELR_BASE)
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@@ -577,6 +585,7 @@ typedef struct
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#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
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#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
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#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
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#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
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/**
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* @}
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@@ -585,6 +594,15 @@ typedef struct
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/** @addtogroup Exported_constants
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* @{
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*/
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/** @addtogroup Hardware_Constant_Definition
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* @{
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*/
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#define LSI_STARTUP_TIME 200U /*!< LSI Maximum startup time in us */
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/**
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* @}
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*/
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/** @addtogroup Peripheral_Registers_Bits_Definition
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* @{
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@@ -1056,6 +1074,9 @@ typedef struct
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#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Pos) /*!< 0x80000000 */
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#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Msk /*!< LPTIM1 counter stopped when core is halted */
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/****************** Bit definition for DBGMCU_APB2_FZ register **************/
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#define DBGMCU_APB2_FZ_DBG_TIM22_STOP_Pos (5U)
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#define DBGMCU_APB2_FZ_DBG_TIM22_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM22_STOP_Pos) /*!< 0x00000020 */
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#define DBGMCU_APB2_FZ_DBG_TIM22_STOP DBGMCU_APB2_FZ_DBG_TIM22_STOP_Msk /*!< TIM22 counter stopped when core is halted */
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#define DBGMCU_APB2_FZ_DBG_TIM21_STOP_Pos (2U)
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#define DBGMCU_APB2_FZ_DBG_TIM21_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM21_STOP_Pos) /*!< 0x00000004 */
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#define DBGMCU_APB2_FZ_DBG_TIM21_STOP DBGMCU_APB2_FZ_DBG_TIM21_STOP_Msk /*!< TIM21 counter stopped when core is halted */
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@@ -1127,6 +1148,30 @@ typedef struct
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#define DMA_ISR_TEIF5_Pos (19U)
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#define DMA_ISR_TEIF5_Msk (0x1UL << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */
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#define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */
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#define DMA_ISR_GIF6_Pos (20U)
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#define DMA_ISR_GIF6_Msk (0x1UL << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */
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#define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */
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#define DMA_ISR_TCIF6_Pos (21U)
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#define DMA_ISR_TCIF6_Msk (0x1UL << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */
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#define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */
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#define DMA_ISR_HTIF6_Pos (22U)
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#define DMA_ISR_HTIF6_Msk (0x1UL << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */
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#define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */
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#define DMA_ISR_TEIF6_Pos (23U)
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#define DMA_ISR_TEIF6_Msk (0x1UL << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */
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#define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */
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#define DMA_ISR_GIF7_Pos (24U)
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#define DMA_ISR_GIF7_Msk (0x1UL << DMA_ISR_GIF7_Pos) /*!< 0x01000000 */
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#define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */
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#define DMA_ISR_TCIF7_Pos (25U)
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#define DMA_ISR_TCIF7_Msk (0x1UL << DMA_ISR_TCIF7_Pos) /*!< 0x02000000 */
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#define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */
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#define DMA_ISR_HTIF7_Pos (26U)
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#define DMA_ISR_HTIF7_Msk (0x1UL << DMA_ISR_HTIF7_Pos) /*!< 0x04000000 */
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#define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */
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#define DMA_ISR_TEIF7_Pos (27U)
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#define DMA_ISR_TEIF7_Msk (0x1UL << DMA_ISR_TEIF7_Pos) /*!< 0x08000000 */
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#define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */
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/******************* Bit definition for DMA_IFCR register *******************/
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#define DMA_IFCR_CGIF1_Pos (0U)
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@@ -1189,6 +1234,30 @@ typedef struct
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#define DMA_IFCR_CTEIF5_Pos (19U)
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#define DMA_IFCR_CTEIF5_Msk (0x1UL << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */
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#define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */
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#define DMA_IFCR_CGIF6_Pos (20U)
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#define DMA_IFCR_CGIF6_Msk (0x1UL << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */
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#define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */
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#define DMA_IFCR_CTCIF6_Pos (21U)
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#define DMA_IFCR_CTCIF6_Msk (0x1UL << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */
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#define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */
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#define DMA_IFCR_CHTIF6_Pos (22U)
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#define DMA_IFCR_CHTIF6_Msk (0x1UL << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */
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#define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */
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#define DMA_IFCR_CTEIF6_Pos (23U)
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#define DMA_IFCR_CTEIF6_Msk (0x1UL << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */
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#define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */
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#define DMA_IFCR_CGIF7_Pos (24U)
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#define DMA_IFCR_CGIF7_Msk (0x1UL << DMA_IFCR_CGIF7_Pos) /*!< 0x01000000 */
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#define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */
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#define DMA_IFCR_CTCIF7_Pos (25U)
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#define DMA_IFCR_CTCIF7_Msk (0x1UL << DMA_IFCR_CTCIF7_Pos) /*!< 0x02000000 */
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#define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */
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#define DMA_IFCR_CHTIF7_Pos (26U)
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#define DMA_IFCR_CHTIF7_Msk (0x1UL << DMA_IFCR_CHTIF7_Pos) /*!< 0x04000000 */
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#define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */
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#define DMA_IFCR_CTEIF7_Pos (27U)
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#define DMA_IFCR_CTEIF7_Msk (0x1UL << DMA_IFCR_CTEIF7_Pos) /*!< 0x08000000 */
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#define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */
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/******************* Bit definition for DMA_CCR register ********************/
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#define DMA_CCR_EN_Pos (0U)
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@@ -1270,6 +1339,12 @@ typedef struct
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#define DMA_CSELR_C5S_Pos (16U)
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#define DMA_CSELR_C5S_Msk (0xFUL << DMA_CSELR_C5S_Pos) /*!< 0x000F0000 */
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#define DMA_CSELR_C5S DMA_CSELR_C5S_Msk /*!< Channel 5 Selection */
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#define DMA_CSELR_C6S_Pos (20U)
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#define DMA_CSELR_C6S_Msk (0xFUL << DMA_CSELR_C6S_Pos) /*!< 0x00F00000 */
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#define DMA_CSELR_C6S DMA_CSELR_C6S_Msk /*!< Channel 6 Selection */
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#define DMA_CSELR_C7S_Pos (24U)
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#define DMA_CSELR_C7S_Msk (0xFUL << DMA_CSELR_C7S_Pos) /*!< 0x0F000000 */
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#define DMA_CSELR_C7S DMA_CSELR_C7S_Msk /*!< Channel 7 Selection */
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/******************************************************************************/
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/* */
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@@ -3045,9 +3120,6 @@ typedef struct
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#define PWR_CR_LPRUN_Pos (14U)
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#define PWR_CR_LPRUN_Msk (0x1UL << PWR_CR_LPRUN_Pos) /*!< 0x00004000 */
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#define PWR_CR_LPRUN PWR_CR_LPRUN_Msk /*!< Low power run mode */
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#define PWR_CR_LPDS_Pos (16U)
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#define PWR_CR_LPDS_Msk (0x1UL << PWR_CR_LPDS_Pos) /*!< 0x00010000 */
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#define PWR_CR_LPDS PWR_CR_LPDS_Msk /*!< regulator in low power deepsleep mode */
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/******************* Bit definition for PWR_CSR register ********************/
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#define PWR_CSR_WUF_Pos (0U)
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@@ -3072,6 +3144,9 @@ typedef struct
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#define PWR_CSR_EWUP1_Pos (8U)
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#define PWR_CSR_EWUP1_Msk (0x1UL << PWR_CSR_EWUP1_Pos) /*!< 0x00000100 */
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#define PWR_CSR_EWUP1 PWR_CSR_EWUP1_Msk /*!< Enable WKUP pin 1 */
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#define PWR_CSR_EWUP2_Pos (9U)
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#define PWR_CSR_EWUP2_Msk (0x1UL << PWR_CSR_EWUP2_Pos) /*!< 0x00000200 */
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#define PWR_CSR_EWUP2 PWR_CSR_EWUP2_Msk /*!< Enable WKUP pin 2 */
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#define PWR_CSR_EWUP3_Pos (10U)
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#define PWR_CSR_EWUP3_Msk (0x1UL << PWR_CSR_EWUP3_Pos) /*!< 0x00000400 */
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#define PWR_CSR_EWUP3 PWR_CSR_EWUP3_Msk /*!< Enable WKUP pin 3 */
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@@ -3084,7 +3159,9 @@ typedef struct
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/*
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* @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
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*/
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/* Note: No specific macro feature on this device */
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#define RCC_HSECSS_SUPPORT /*!< HSE CSS feature activation support */
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#define RCC_MCO3_SUPPORT /*!<Support MCO3 */
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#define RCC_MCO3_AF2_SUPPORT /*!<Support MCO3 on Alternate Function AF0 */
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/******************** Bit definition for RCC_CR register ********************/
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#define RCC_CR_HSION_Pos (0U)
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@@ -3120,6 +3197,9 @@ typedef struct
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#define RCC_CR_HSEBYP_Pos (18U)
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#define RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
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#define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed clock Bypass */
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#define RCC_CR_CSSHSEON_Pos (19U)
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#define RCC_CR_CSSHSEON_Msk (0x1UL << RCC_CR_CSSHSEON_Pos) /*!< 0x00080000 */
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#define RCC_CR_CSSHSEON RCC_CR_CSSHSEON_Msk /*!< HSE Clock Security System enable */
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#define RCC_CR_RTCPRE_Pos (20U)
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#define RCC_CR_RTCPRE_Msk (0x3UL << RCC_CR_RTCPRE_Pos) /*!< 0x00300000 */
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#define RCC_CR_RTCPRE RCC_CR_RTCPRE_Msk /*!< RTC prescaler [1:0] bits */
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@@ -3133,6 +3213,7 @@ typedef struct
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#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< PLL clock ready flag */
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/* Reference defines */
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#define RCC_CR_CSSON RCC_CR_CSSHSEON
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/******************** Bit definition for RCC_ICSCR register *****************/
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#define RCC_ICSCR_HSICAL_Pos (0U)
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@@ -3394,9 +3475,13 @@ typedef struct
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#define RCC_CIFR_CSSLSEF_Pos (7U)
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#define RCC_CIFR_CSSLSEF_Msk (0x1UL << RCC_CIFR_CSSLSEF_Pos) /*!< 0x00000080 */
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#define RCC_CIFR_CSSLSEF RCC_CIFR_CSSLSEF_Msk /*!< LSE Clock Security System Interrupt flag */
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#define RCC_CIFR_CSSHSEF_Pos (8U)
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#define RCC_CIFR_CSSHSEF_Msk (0x1UL << RCC_CIFR_CSSHSEF_Pos) /*!< 0x00000100 */
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#define RCC_CIFR_CSSHSEF RCC_CIFR_CSSHSEF_Msk /*!< HSE Clock Security System Interrupt flag */
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/* Reference defines */
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#define RCC_CIFR_LSECSSF RCC_CIFR_CSSLSEF
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#define RCC_CIFR_CSSF RCC_CIFR_CSSHSEF
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/*!<****************** Bit definition for RCC_CICR register ********************/
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#define RCC_CICR_LSIRDYC_Pos (0U)
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@@ -3420,9 +3505,13 @@ typedef struct
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#define RCC_CICR_CSSLSEC_Pos (7U)
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#define RCC_CICR_CSSLSEC_Msk (0x1UL << RCC_CICR_CSSLSEC_Pos) /*!< 0x00000080 */
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#define RCC_CICR_CSSLSEC RCC_CICR_CSSLSEC_Msk /*!< LSE Clock Security System Interrupt Clear */
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#define RCC_CICR_CSSHSEC_Pos (8U)
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#define RCC_CICR_CSSHSEC_Msk (0x1UL << RCC_CICR_CSSHSEC_Pos) /*!< 0x00000100 */
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#define RCC_CICR_CSSHSEC RCC_CICR_CSSHSEC_Msk /*!< HSE Clock Security System Interrupt Clear */
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/* Reference defines */
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#define RCC_CICR_LSECSSC RCC_CICR_CSSLSEC
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#define RCC_CICR_CSSC RCC_CICR_CSSHSEC
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/***************** Bit definition for RCC_IOPRSTR register ******************/
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#define RCC_IOPRSTR_IOPARST_Pos (0U)
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#define RCC_IOPRSTR_IOPARST_Msk (0x1UL << RCC_IOPRSTR_IOPARST_Pos) /*!< 0x00000001 */
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@@ -3433,11 +3522,15 @@ typedef struct
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#define RCC_IOPRSTR_IOPCRST_Pos (2U)
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#define RCC_IOPRSTR_IOPCRST_Msk (0x1UL << RCC_IOPRSTR_IOPCRST_Pos) /*!< 0x00000004 */
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#define RCC_IOPRSTR_IOPCRST RCC_IOPRSTR_IOPCRST_Msk /*!< GPIO port C reset */
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#define RCC_IOPRSTR_IOPHRST_Pos (7U)
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#define RCC_IOPRSTR_IOPHRST_Msk (0x1UL << RCC_IOPRSTR_IOPHRST_Pos) /*!< 0x00000080 */
|
||||
#define RCC_IOPRSTR_IOPHRST RCC_IOPRSTR_IOPHRST_Msk /*!< GPIO port H reset */
|
||||
|
||||
/* Reference defines */
|
||||
#define RCC_IOPRSTR_GPIOARST RCC_IOPRSTR_IOPARST /*!< GPIO port A reset */
|
||||
#define RCC_IOPRSTR_GPIOBRST RCC_IOPRSTR_IOPBRST /*!< GPIO port B reset */
|
||||
#define RCC_IOPRSTR_GPIOCRST RCC_IOPRSTR_IOPCRST /*!< GPIO port C reset */
|
||||
#define RCC_IOPRSTR_GPIOHRST RCC_IOPRSTR_IOPHRST /*!< GPIO port H reset */
|
||||
|
||||
|
||||
/****************** Bit definition for RCC_AHBRST register ******************/
|
||||
@@ -3461,6 +3554,9 @@ typedef struct
|
||||
#define RCC_APB2RSTR_TIM21RST_Pos (2U)
|
||||
#define RCC_APB2RSTR_TIM21RST_Msk (0x1UL << RCC_APB2RSTR_TIM21RST_Pos) /*!< 0x00000004 */
|
||||
#define RCC_APB2RSTR_TIM21RST RCC_APB2RSTR_TIM21RST_Msk /*!< TIM21 reset */
|
||||
#define RCC_APB2RSTR_TIM22RST_Pos (5U)
|
||||
#define RCC_APB2RSTR_TIM22RST_Msk (0x1UL << RCC_APB2RSTR_TIM22RST_Pos) /*!< 0x00000020 */
|
||||
#define RCC_APB2RSTR_TIM22RST RCC_APB2RSTR_TIM22RST_Msk /*!< TIM22 reset */
|
||||
#define RCC_APB2RSTR_ADCRST_Pos (9U)
|
||||
#define RCC_APB2RSTR_ADCRST_Msk (0x1UL << RCC_APB2RSTR_ADCRST_Pos) /*!< 0x00000200 */
|
||||
#define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk /*!< ADC1 reset */
|
||||
@@ -3508,11 +3604,15 @@ typedef struct
|
||||
#define RCC_IOPENR_IOPCEN_Pos (2U)
|
||||
#define RCC_IOPENR_IOPCEN_Msk (0x1UL << RCC_IOPENR_IOPCEN_Pos) /*!< 0x00000004 */
|
||||
#define RCC_IOPENR_IOPCEN RCC_IOPENR_IOPCEN_Msk /*!< GPIO port C clock enable */
|
||||
#define RCC_IOPENR_IOPHEN_Pos (7U)
|
||||
#define RCC_IOPENR_IOPHEN_Msk (0x1UL << RCC_IOPENR_IOPHEN_Pos) /*!< 0x00000080 */
|
||||
#define RCC_IOPENR_IOPHEN RCC_IOPENR_IOPHEN_Msk /*!< GPIO port H clock enable */
|
||||
|
||||
/* Reference defines */
|
||||
#define RCC_IOPENR_GPIOAEN RCC_IOPENR_IOPAEN /*!< GPIO port A clock enable */
|
||||
#define RCC_IOPENR_GPIOBEN RCC_IOPENR_IOPBEN /*!< GPIO port B clock enable */
|
||||
#define RCC_IOPENR_GPIOCEN RCC_IOPENR_IOPCEN /*!< GPIO port C clock enable */
|
||||
#define RCC_IOPENR_GPIOHEN RCC_IOPENR_IOPHEN /*!< GPIO port H clock enable */
|
||||
|
||||
/***************** Bit definition for RCC_AHBENR register ******************/
|
||||
#define RCC_AHBENR_DMAEN_Pos (0U)
|
||||
@@ -3535,6 +3635,9 @@ typedef struct
|
||||
#define RCC_APB2ENR_TIM21EN_Pos (2U)
|
||||
#define RCC_APB2ENR_TIM21EN_Msk (0x1UL << RCC_APB2ENR_TIM21EN_Pos) /*!< 0x00000004 */
|
||||
#define RCC_APB2ENR_TIM21EN RCC_APB2ENR_TIM21EN_Msk /*!< TIM21 clock enable */
|
||||
#define RCC_APB2ENR_TIM22EN_Pos (5U)
|
||||
#define RCC_APB2ENR_TIM22EN_Msk (0x1UL << RCC_APB2ENR_TIM22EN_Pos) /*!< 0x00000020 */
|
||||
#define RCC_APB2ENR_TIM22EN RCC_APB2ENR_TIM22EN_Msk /*!< TIM22 clock enable */
|
||||
#define RCC_APB2ENR_FWEN_Pos (7U)
|
||||
#define RCC_APB2ENR_FWEN_Msk (0x1UL << RCC_APB2ENR_FWEN_Pos) /*!< 0x00000080 */
|
||||
#define RCC_APB2ENR_FWEN RCC_APB2ENR_FWEN_Msk /*!< MiFare Firewall clock enable */
|
||||
@@ -3587,11 +3690,15 @@ typedef struct
|
||||
#define RCC_IOPSMENR_IOPCSMEN_Pos (2U)
|
||||
#define RCC_IOPSMENR_IOPCSMEN_Msk (0x1UL << RCC_IOPSMENR_IOPCSMEN_Pos) /*!< 0x00000004 */
|
||||
#define RCC_IOPSMENR_IOPCSMEN RCC_IOPSMENR_IOPCSMEN_Msk /*!< GPIO port C clock enabled in sleep mode */
|
||||
#define RCC_IOPSMENR_IOPHSMEN_Pos (7U)
|
||||
#define RCC_IOPSMENR_IOPHSMEN_Msk (0x1UL << RCC_IOPSMENR_IOPHSMEN_Pos) /*!< 0x00000080 */
|
||||
#define RCC_IOPSMENR_IOPHSMEN RCC_IOPSMENR_IOPHSMEN_Msk /*!< GPIO port H clock enabled in sleep mode */
|
||||
|
||||
/* Reference defines */
|
||||
#define RCC_IOPSMENR_GPIOASMEN RCC_IOPSMENR_IOPASMEN /*!< GPIO port A clock enabled in sleep mode */
|
||||
#define RCC_IOPSMENR_GPIOBSMEN RCC_IOPSMENR_IOPBSMEN /*!< GPIO port B clock enabled in sleep mode */
|
||||
#define RCC_IOPSMENR_GPIOCSMEN RCC_IOPSMENR_IOPCSMEN /*!< GPIO port C clock enabled in sleep mode */
|
||||
#define RCC_IOPSMENR_GPIOHSMEN RCC_IOPSMENR_IOPHSMEN /*!< GPIO port H clock enabled in sleep mode */
|
||||
|
||||
/***************** Bit definition for RCC_AHBSMENR register ******************/
|
||||
#define RCC_AHBSMENR_DMASMEN_Pos (0U)
|
||||
@@ -3617,6 +3724,9 @@ typedef struct
|
||||
#define RCC_APB2SMENR_TIM21SMEN_Pos (2U)
|
||||
#define RCC_APB2SMENR_TIM21SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM21SMEN_Pos) /*!< 0x00000004 */
|
||||
#define RCC_APB2SMENR_TIM21SMEN RCC_APB2SMENR_TIM21SMEN_Msk /*!< TIM21 clock enabled in sleep mode */
|
||||
#define RCC_APB2SMENR_TIM22SMEN_Pos (5U)
|
||||
#define RCC_APB2SMENR_TIM22SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM22SMEN_Pos) /*!< 0x00000020 */
|
||||
#define RCC_APB2SMENR_TIM22SMEN RCC_APB2SMENR_TIM22SMEN_Msk /*!< TIM22 clock enabled in sleep mode */
|
||||
#define RCC_APB2SMENR_ADCSMEN_Pos (9U)
|
||||
#define RCC_APB2SMENR_ADCSMEN_Msk (0x1UL << RCC_APB2SMENR_ADCSMEN_Pos) /*!< 0x00000200 */
|
||||
#define RCC_APB2SMENR_ADCSMEN RCC_APB2SMENR_ADCSMEN_Msk /*!< ADC1 clock enabled in sleep mode */
|
||||
@@ -3742,6 +3852,9 @@ typedef struct
|
||||
#define RCC_CSR_RMVF_Pos (23U)
|
||||
#define RCC_CSR_RMVF_Msk (0x1UL << RCC_CSR_RMVF_Pos) /*!< 0x00800000 */
|
||||
#define RCC_CSR_RMVF RCC_CSR_RMVF_Msk /*!< Remove reset flag */
|
||||
#define RCC_CSR_FWRSTF_Pos (24U)
|
||||
#define RCC_CSR_FWRSTF_Msk (0x1UL << RCC_CSR_FWRSTF_Pos) /*!< 0x01000000 */
|
||||
#define RCC_CSR_FWRSTF RCC_CSR_FWRSTF_Msk /*!< Mifare Firewall reset flag */
|
||||
#define RCC_CSR_OBLRSTF_Pos (25U)
|
||||
#define RCC_CSR_OBLRSTF_Msk (0x1UL << RCC_CSR_OBLRSTF_Pos) /*!< 0x02000000 */
|
||||
#define RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF_Msk /*!< OBL reset flag */
|
||||
@@ -3776,6 +3889,7 @@ typedef struct
|
||||
/*
|
||||
* @brief Specific device feature definitions
|
||||
*/
|
||||
#define RTC_TAMPER1_SUPPORT
|
||||
#define RTC_TAMPER2_SUPPORT
|
||||
#define RTC_TAMPER3_SUPPORT
|
||||
#define RTC_WAKEUP_SUPPORT
|
||||
@@ -3945,6 +4059,9 @@ typedef struct
|
||||
#define RTC_ISR_TAMP2F_Pos (14U)
|
||||
#define RTC_ISR_TAMP2F_Msk (0x1UL << RTC_ISR_TAMP2F_Pos) /*!< 0x00004000 */
|
||||
#define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk /*!< */
|
||||
#define RTC_ISR_TAMP1F_Pos (13U)
|
||||
#define RTC_ISR_TAMP1F_Msk (0x1UL << RTC_ISR_TAMP1F_Pos) /*!< 0x00002000 */
|
||||
#define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk /*!< */
|
||||
#define RTC_ISR_TSOVF_Pos (12U)
|
||||
#define RTC_ISR_TSOVF_Msk (0x1UL << RTC_ISR_TSOVF_Pos) /*!< 0x00001000 */
|
||||
#define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk /*!< */
|
||||
@@ -4291,6 +4408,15 @@ typedef struct
|
||||
#define RTC_TAMPCR_TAMP2IE_Pos (19U)
|
||||
#define RTC_TAMPCR_TAMP2IE_Msk (0x1UL << RTC_TAMPCR_TAMP2IE_Pos) /*!< 0x00080000 */
|
||||
#define RTC_TAMPCR_TAMP2IE RTC_TAMPCR_TAMP2IE_Msk /*!< */
|
||||
#define RTC_TAMPCR_TAMP1MF_Pos (18U)
|
||||
#define RTC_TAMPCR_TAMP1MF_Msk (0x1UL << RTC_TAMPCR_TAMP1MF_Pos) /*!< 0x00040000 */
|
||||
#define RTC_TAMPCR_TAMP1MF RTC_TAMPCR_TAMP1MF_Msk /*!< */
|
||||
#define RTC_TAMPCR_TAMP1NOERASE_Pos (17U)
|
||||
#define RTC_TAMPCR_TAMP1NOERASE_Msk (0x1UL << RTC_TAMPCR_TAMP1NOERASE_Pos) /*!< 0x00020000 */
|
||||
#define RTC_TAMPCR_TAMP1NOERASE RTC_TAMPCR_TAMP1NOERASE_Msk /*!< */
|
||||
#define RTC_TAMPCR_TAMP1IE_Pos (16U)
|
||||
#define RTC_TAMPCR_TAMP1IE_Msk (0x1UL << RTC_TAMPCR_TAMP1IE_Pos) /*!< 0x00010000 */
|
||||
#define RTC_TAMPCR_TAMP1IE RTC_TAMPCR_TAMP1IE_Msk /*!< */
|
||||
#define RTC_TAMPCR_TAMPPUDIS_Pos (15U)
|
||||
#define RTC_TAMPCR_TAMPPUDIS_Msk (0x1UL << RTC_TAMPCR_TAMPPUDIS_Pos) /*!< 0x00008000 */
|
||||
#define RTC_TAMPCR_TAMPPUDIS RTC_TAMPCR_TAMPPUDIS_Msk /*!< */
|
||||
@@ -4328,6 +4454,12 @@ typedef struct
|
||||
#define RTC_TAMPCR_TAMPIE_Pos (2U)
|
||||
#define RTC_TAMPCR_TAMPIE_Msk (0x1UL << RTC_TAMPCR_TAMPIE_Pos) /*!< 0x00000004 */
|
||||
#define RTC_TAMPCR_TAMPIE RTC_TAMPCR_TAMPIE_Msk /*!< */
|
||||
#define RTC_TAMPCR_TAMP1TRG_Pos (1U)
|
||||
#define RTC_TAMPCR_TAMP1TRG_Msk (0x1UL << RTC_TAMPCR_TAMP1TRG_Pos) /*!< 0x00000002 */
|
||||
#define RTC_TAMPCR_TAMP1TRG RTC_TAMPCR_TAMP1TRG_Msk /*!< */
|
||||
#define RTC_TAMPCR_TAMP1E_Pos (0U)
|
||||
#define RTC_TAMPCR_TAMP1E_Msk (0x1UL << RTC_TAMPCR_TAMP1E_Pos) /*!< 0x00000001 */
|
||||
#define RTC_TAMPCR_TAMP1E RTC_TAMPCR_TAMP1E_Msk /*!< */
|
||||
|
||||
/******************** Bits definition for RTC_ALRMASSR register *************/
|
||||
#define RTC_ALRMASSR_MASKSS_Pos (24U)
|
||||
@@ -5238,6 +5370,17 @@ typedef struct
|
||||
#define TIM21_OR_TI2_RMP_Msk (0x1UL << TIM21_OR_TI2_RMP_Pos) /*!< 0x00000020 */
|
||||
#define TIM21_OR_TI2_RMP TIM21_OR_TI2_RMP_Msk /*!<TI2_RMP bit (TIM21 Input 2 remap) */
|
||||
|
||||
#define TIM22_OR_ETR_RMP_Pos (0U)
|
||||
#define TIM22_OR_ETR_RMP_Msk (0x3UL << TIM22_OR_ETR_RMP_Pos) /*!< 0x00000003 */
|
||||
#define TIM22_OR_ETR_RMP TIM22_OR_ETR_RMP_Msk /*!<ETR_RMP[1:0] bits (TIM22 ETR remap) */
|
||||
#define TIM22_OR_ETR_RMP_0 (0x1UL << TIM22_OR_ETR_RMP_Pos) /*!< 0x00000001 */
|
||||
#define TIM22_OR_ETR_RMP_1 (0x2UL << TIM22_OR_ETR_RMP_Pos) /*!< 0x00000002 */
|
||||
#define TIM22_OR_TI1_RMP_Pos (2U)
|
||||
#define TIM22_OR_TI1_RMP_Msk (0x3UL << TIM22_OR_TI1_RMP_Pos) /*!< 0x0000000C */
|
||||
#define TIM22_OR_TI1_RMP TIM22_OR_TI1_RMP_Msk /*!<TI1_RMP[2:0] bits (TIM22 Input 1 remap) */
|
||||
#define TIM22_OR_TI1_RMP_0 (0x1UL << TIM22_OR_TI1_RMP_Pos) /*!< 0x00000004 */
|
||||
#define TIM22_OR_TI1_RMP_1 (0x2UL << TIM22_OR_TI1_RMP_Pos) /*!< 0x00000008 */
|
||||
|
||||
|
||||
/******************************************************************************/
|
||||
/* */
|
||||
@@ -5248,7 +5391,7 @@ typedef struct
|
||||
/*
|
||||
* @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
|
||||
*/
|
||||
#define USART_TCBGT_SUPPORT /*!< Transmission completed before guard time interrupt support */
|
||||
/* Note: No specific macro feature on this device */
|
||||
|
||||
/****************** Bit definition for USART_CR1 register *******************/
|
||||
#define USART_CR1_UE_Pos (0U)
|
||||
@@ -5453,9 +5596,6 @@ typedef struct
|
||||
#define USART_CR3_UCESM_Pos (23U)
|
||||
#define USART_CR3_UCESM_Msk (0x1UL << USART_CR3_UCESM_Pos) /*!< 0x00800000 */
|
||||
#define USART_CR3_UCESM USART_CR3_UCESM_Msk /*!< Clock Enable in Stop mode */
|
||||
#define USART_CR3_TCBGTIE_Pos (24U)
|
||||
#define USART_CR3_TCBGTIE_Msk (0x1UL << USART_CR3_TCBGTIE_Pos) /*!< 0x01000000 */
|
||||
#define USART_CR3_TCBGTIE USART_CR3_TCBGTIE_Msk /*!< Transmission Complete Before Guard Time Interrupt Enable */
|
||||
|
||||
/****************** Bit definition for USART_BRR register *******************/
|
||||
#define USART_BRR_DIV_FRACTION_Pos (0U)
|
||||
@@ -5566,9 +5706,6 @@ typedef struct
|
||||
#define USART_ISR_REACK_Pos (22U)
|
||||
#define USART_ISR_REACK_Msk (0x1UL << USART_ISR_REACK_Pos) /*!< 0x00400000 */
|
||||
#define USART_ISR_REACK USART_ISR_REACK_Msk /*!< Receive Enable Acknowledge Flag */
|
||||
#define USART_ISR_TCBGT_Pos (25U)
|
||||
#define USART_ISR_TCBGT_Msk (0x1UL << USART_ISR_TCBGT_Pos) /*!< 0x02000000 */
|
||||
#define USART_ISR_TCBGT USART_ISR_TCBGT_Msk /*!< Transmission Complete Before Guard Time Completion Flag */
|
||||
|
||||
/******************* Bit definition for USART_ICR register ******************/
|
||||
#define USART_ICR_PECF_Pos (0U)
|
||||
@@ -5589,9 +5726,6 @@ typedef struct
|
||||
#define USART_ICR_TCCF_Pos (6U)
|
||||
#define USART_ICR_TCCF_Msk (0x1UL << USART_ICR_TCCF_Pos) /*!< 0x00000040 */
|
||||
#define USART_ICR_TCCF USART_ICR_TCCF_Msk /*!< Transmission Complete Clear Flag */
|
||||
#define USART_ICR_TCBGTCF_Pos (7U)
|
||||
#define USART_ICR_TCBGTCF_Msk (0x1UL << USART_ICR_TCBGTCF_Pos) /*!< 0x00000080 */
|
||||
#define USART_ICR_TCBGTCF USART_ICR_TCBGTCF_Msk /*!< Transmission Complete Before Guard Time Clear Flag */
|
||||
#define USART_ICR_LBDCF_Pos (8U)
|
||||
#define USART_ICR_LBDCF_Msk (0x1UL << USART_ICR_LBDCF_Pos) /*!< 0x00000100 */
|
||||
#define USART_ICR_LBDCF USART_ICR_LBDCF_Msk /*!< LIN Break Detection Clear Flag */
|
||||
@@ -5725,15 +5859,19 @@ typedef struct
|
||||
((INSTANCE) == DMA1_Channel2) || \
|
||||
((INSTANCE) == DMA1_Channel3) || \
|
||||
((INSTANCE) == DMA1_Channel4) || \
|
||||
((INSTANCE) == DMA1_Channel5))
|
||||
((INSTANCE) == DMA1_Channel5) || \
|
||||
((INSTANCE) == DMA1_Channel6) || \
|
||||
((INSTANCE) == DMA1_Channel7))
|
||||
|
||||
/******************************* GPIO Instances *******************************/
|
||||
#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
|
||||
((INSTANCE) == GPIOB) || \
|
||||
((INSTANCE) == GPIOC))
|
||||
((INSTANCE) == GPIOC) || \
|
||||
((INSTANCE) == GPIOH))
|
||||
|
||||
#define IS_GPIO_AF_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
|
||||
((INSTANCE) == GPIOB))
|
||||
((INSTANCE) == GPIOB) || \
|
||||
((INSTANCE) == GPIOC))
|
||||
|
||||
/******************************** I2C Instances *******************************/
|
||||
#define IS_I2C_ALL_INSTANCE(INSTANCE) ((INSTANCE) == I2C1)
|
||||
@@ -5761,15 +5899,18 @@ typedef struct
|
||||
|
||||
/****************** TIM Instances : All supported instances *******************/
|
||||
#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
|
||||
((INSTANCE) == TIM21))
|
||||
((INSTANCE) == TIM21) || \
|
||||
((INSTANCE) == TIM22))
|
||||
|
||||
/************* TIM Instances : at least 1 capture/compare channel *************/
|
||||
#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
|
||||
((INSTANCE) == TIM21))
|
||||
((INSTANCE) == TIM21) || \
|
||||
((INSTANCE) == TIM22))
|
||||
|
||||
/************ TIM Instances : at least 2 capture/compare channels *************/
|
||||
#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
|
||||
((INSTANCE) == TIM21))
|
||||
((INSTANCE) == TIM21) || \
|
||||
((INSTANCE) == TIM22))
|
||||
|
||||
/************ TIM Instances : at least 3 capture/compare channels *************/
|
||||
#define IS_TIM_CC3_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
|
||||
@@ -5795,12 +5936,17 @@ typedef struct
|
||||
((CHANNEL) == TIM_CHANNEL_4))) \
|
||||
|| \
|
||||
(((INSTANCE) == TIM21) && \
|
||||
(((CHANNEL) == TIM_CHANNEL_1) || \
|
||||
((CHANNEL) == TIM_CHANNEL_2))) \
|
||||
|| \
|
||||
(((INSTANCE) == TIM22) && \
|
||||
(((CHANNEL) == TIM_CHANNEL_1) || \
|
||||
((CHANNEL) == TIM_CHANNEL_2))))
|
||||
|
||||
/****************** TIM Instances : supporting clock division *****************/
|
||||
#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
|
||||
((INSTANCE) == TIM21))
|
||||
((INSTANCE) == TIM21) || \
|
||||
((INSTANCE) == TIM22))
|
||||
|
||||
/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
|
||||
#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
|
||||
@@ -5808,7 +5954,8 @@ typedef struct
|
||||
|
||||
/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
|
||||
#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
|
||||
((INSTANCE) == TIM21))
|
||||
((INSTANCE) == TIM21) || \
|
||||
((INSTANCE) == TIM22))
|
||||
|
||||
/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
|
||||
#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
|
||||
@@ -5816,31 +5963,38 @@ typedef struct
|
||||
|
||||
/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
|
||||
#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
|
||||
((INSTANCE) == TIM21))
|
||||
((INSTANCE) == TIM21) || \
|
||||
((INSTANCE) == TIM22))
|
||||
|
||||
/****************** TIM Instances : supporting counting mode selection ********/
|
||||
#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
|
||||
((INSTANCE) == TIM21))
|
||||
((INSTANCE) == TIM21) || \
|
||||
((INSTANCE) == TIM22))
|
||||
|
||||
/****************** TIM Instances : supporting encoder interface **************/
|
||||
#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
|
||||
((INSTANCE) == TIM21))
|
||||
((INSTANCE) == TIM21) || \
|
||||
((INSTANCE) == TIM22))
|
||||
|
||||
/***************** TIM Instances : external trigger input availabe ************/
|
||||
#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
|
||||
((INSTANCE) == TIM21))
|
||||
((INSTANCE) == TIM21) || \
|
||||
((INSTANCE) == TIM22))
|
||||
|
||||
/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
|
||||
#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
|
||||
((INSTANCE) == TIM21))
|
||||
((INSTANCE) == TIM21) || \
|
||||
((INSTANCE) == TIM22))
|
||||
|
||||
/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
|
||||
#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
|
||||
((INSTANCE) == TIM21))
|
||||
((INSTANCE) == TIM21) || \
|
||||
((INSTANCE) == TIM22))
|
||||
|
||||
/****************** TIM Instances : remapping capability **********************/
|
||||
#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
|
||||
((INSTANCE) == TIM21))
|
||||
((INSTANCE) == TIM21) || \
|
||||
((INSTANCE) == TIM22))
|
||||
|
||||
/******************* TIM Instances : output(s) OCXEC register *****************/
|
||||
#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
|
||||
@@ -5852,11 +6006,11 @@ typedef struct
|
||||
#define IS_UART_INSTANCE(INSTANCE) ((INSTANCE) == USART2)
|
||||
|
||||
/******************** USART Instances : Synchronous mode **********************/
|
||||
#define IS_USART_INSTANCE(INSTANCE) (1 == 0)
|
||||
#define IS_USART_INSTANCE(INSTANCE) ((INSTANCE) == USART2)
|
||||
|
||||
/****************** USART Instances : Auto Baud Rate detection ****************/
|
||||
|
||||
#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (1 == 0)
|
||||
#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) ((INSTANCE) == USART2)
|
||||
|
||||
/****************** UART Instances : Driver Enable *****************/
|
||||
#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART2) || \
|
||||
@@ -5867,10 +6021,11 @@ typedef struct
|
||||
((INSTANCE) == LPUART1))
|
||||
|
||||
/******************** UART Instances : LIN mode **********************/
|
||||
#define IS_UART_LIN_INSTANCE(INSTANCE) (1==0)
|
||||
#define IS_UART_LIN_INSTANCE(INSTANCE) ((INSTANCE) == USART2)
|
||||
|
||||
/******************** UART Instances : Wake-up from Stop mode **********************/
|
||||
#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1)
|
||||
#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART2) || \
|
||||
((INSTANCE) == LPUART1))
|
||||
|
||||
/****************** UART Instances : Hardware Flow control ********************/
|
||||
#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART2) || \
|
||||
@@ -5909,7 +6064,7 @@ typedef struct
|
||||
#define AES_LPUART1_IRQn LPUART1_IRQn
|
||||
#define AES_RNG_LPUART1_IRQn LPUART1_IRQn
|
||||
#define RCC_CRS_IRQn RCC_IRQn
|
||||
#define DMA1_Channel4_5_6_7_IRQn DMA1_Channel4_5_IRQn
|
||||
#define DMA1_Channel4_5_IRQn DMA1_Channel4_5_6_7_IRQn
|
||||
#define ADC1_IRQn ADC1_COMP_IRQn
|
||||
|
||||
/* Aliases for __IRQHandler */
|
||||
@@ -5917,7 +6072,7 @@ typedef struct
|
||||
#define AES_LPUART1_IRQHandler LPUART1_IRQHandler
|
||||
#define AES_RNG_LPUART1_IRQHandler LPUART1_IRQHandler
|
||||
#define RCC_CRS_IRQHandler RCC_IRQHandler
|
||||
#define DMA1_Channel4_5_6_7_IRQHandler DMA1_Channel4_5_IRQHandler
|
||||
#define DMA1_Channel4_5_IRQHandler DMA1_Channel4_5_6_7_IRQHandler
|
||||
#define ADC1_IRQHandler ADC1_COMP_IRQHandler
|
||||
|
||||
/**
|
||||
@@ -5932,7 +6087,7 @@ typedef struct
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* __STM32L011xx_H */
|
||||
#endif /* __STM32L031xx_H */
|
||||
|
||||
|
||||
|
||||
@@ -104,7 +104,7 @@
|
||||
*/
|
||||
#define __STM32L0xx_CMSIS_VERSION_MAIN (0x01) /*!< [31:24] main version */
|
||||
#define __STM32L0xx_CMSIS_VERSION_SUB1 (0x09) /*!< [23:16] sub1 version */
|
||||
#define __STM32L0xx_CMSIS_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */
|
||||
#define __STM32L0xx_CMSIS_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */
|
||||
#define __STM32L0xx_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
|
||||
#define __STM32L0xx_CMSIS_VERSION ((__STM32L0xx_CMSIS_VERSION_MAIN << 24)\
|
||||
|(__STM32L0xx_CMSIS_VERSION_SUB1 << 16)\
|
||||
@@ -208,6 +208,46 @@ typedef enum
|
||||
|
||||
#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
|
||||
|
||||
/* Use of interrupt control for register exclusive access */
|
||||
/* Atomic 32-bit register access macro to set one or several bits */
|
||||
#define ATOMIC_SET_BIT(REG, BIT) \
|
||||
do { \
|
||||
uint32_t primask; \
|
||||
primask = __get_PRIMASK(); \
|
||||
__set_PRIMASK(1); \
|
||||
SET_BIT((REG), (BIT)); \
|
||||
__set_PRIMASK(primask); \
|
||||
} while(0)
|
||||
|
||||
/* Atomic 32-bit register access macro to clear one or several bits */
|
||||
#define ATOMIC_CLEAR_BIT(REG, BIT) \
|
||||
do { \
|
||||
uint32_t primask; \
|
||||
primask = __get_PRIMASK(); \
|
||||
__set_PRIMASK(1); \
|
||||
CLEAR_BIT((REG), (BIT)); \
|
||||
__set_PRIMASK(primask); \
|
||||
} while(0)
|
||||
|
||||
/* Atomic 32-bit register access macro to clear and set one or several bits */
|
||||
#define ATOMIC_MODIFY_REG(REG, CLEARMSK, SETMASK) \
|
||||
do { \
|
||||
uint32_t primask; \
|
||||
primask = __get_PRIMASK(); \
|
||||
__set_PRIMASK(1); \
|
||||
MODIFY_REG((REG), (CLEARMSK), (SETMASK)); \
|
||||
__set_PRIMASK(primask); \
|
||||
} while(0)
|
||||
|
||||
/* Atomic 16-bit register access macro to set one or several bits */
|
||||
#define ATOMIC_SETH_BIT(REG, BIT) ATOMIC_SET_BIT(REG, BIT) \
|
||||
|
||||
/* Atomic 16-bit register access macro to clear one or several bits */
|
||||
#define ATOMIC_CLEARH_BIT(REG, BIT) ATOMIC_CLEAR_BIT(REG, BIT) \
|
||||
|
||||
/* Atomic 16-bit register access macro to clear and set one or several bits */
|
||||
#define ATOMIC_MODIFYH_REG(REG, CLEARMSK, SETMASK) ATOMIC_MODIFY_REG(REG, CLEARMSK, SETMASK) \
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
Reference in New Issue
Block a user