Moved the old firmware for STM32L011 to fw_old and migrated the firmware to STM32L031 in fw. I2C and TIM21 seem functional. USART2 is receiving correctly, but the modbus test is not receiving messages.
This commit is contained in:
David Žaitlík
583
fw/.cproject
583
fw/.cproject
@@ -1,396 +1,191 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||
<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
|
||||
|
||||
<storageModule moduleId="org.eclipse.cdt.core.settings">
|
||||
|
||||
<cconfiguration id="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.debug.1512690796">
|
||||
|
||||
<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.debug.1512690796" moduleId="org.eclipse.cdt.core.settings" name="Debug">
|
||||
|
||||
<externalSettings/>
|
||||
|
||||
<extensions>
|
||||
|
||||
<extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/>
|
||||
|
||||
<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
|
||||
|
||||
<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
|
||||
|
||||
<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
|
||||
|
||||
<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
|
||||
|
||||
<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
|
||||
|
||||
</extensions>
|
||||
|
||||
</storageModule>
|
||||
|
||||
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
|
||||
|
||||
<configuration artifactExtension="elf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug" cleanCommand="rm -rf" description="" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.debug.1512690796" name="Debug" parent="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.debug">
|
||||
|
||||
<folderInfo id="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.debug.1512690796." name="/" resourcePath="">
|
||||
|
||||
<toolChain id="com.st.stm32cube.ide.mcu.gnu.managedbuild.toolchain.exe.debug.1532842771" name="MCU ARM GCC" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.toolchain.exe.debug">
|
||||
|
||||
<option id="com.st.stm32cube.ide.mcu.option.internal.toolchain.type.1880621660" name="Internal Toolchain Type" superClass="com.st.stm32cube.ide.mcu.option.internal.toolchain.type" useByScannerDiscovery="false" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.toolchain.base.gnu-tools-for-stm32" valueType="string"/>
|
||||
|
||||
<option id="com.st.stm32cube.ide.mcu.option.internal.toolchain.version.1279721468" name="Internal Toolchain Version" superClass="com.st.stm32cube.ide.mcu.option.internal.toolchain.version" useByScannerDiscovery="false" value="7-2018-q2-update" valueType="string"/>
|
||||
|
||||
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_mcu.27712989" name="Mcu" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_mcu" useByScannerDiscovery="true" value="STM32L011F4Ux" valueType="string"/>
|
||||
|
||||
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_cpuid.1986434241" name="CpuId" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_cpuid" useByScannerDiscovery="false" value="0" valueType="string"/>
|
||||
|
||||
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_coreid.731481840" name="CpuCoreId" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_coreid" useByScannerDiscovery="false" value="0" valueType="string"/>
|
||||
|
||||
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_board.1992458385" name="Board" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_board" useByScannerDiscovery="false" value="genericBoard" valueType="string"/>
|
||||
|
||||
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.defaults.1211256952" name="Defaults" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.defaults" useByScannerDiscovery="false" value="com.st.stm32cube.ide.common.services.build.inputs.revA.1.0.4 || Debug || true || Executable || com.st.stm32cube.ide.mcu.gnu.managedbuild.toolchain.base.gnu-tools-for-stm32 || STM32L011F4Ux || 0 || 0 || arm-none-eabi- || ${gnu_tools_for_stm32_compiler_path} || ../Drivers/CMSIS/Include | ../Core/Inc | ../Drivers/STM32L0xx_HAL_Driver/Inc | ../Drivers/CMSIS/Device/ST/STM32L0xx/Include || || || HSE_VALUE=8000000 | HSE_STARTUP_TIMEOUT=100 | HSI_VALUE=16000000 | LSE_STARTUP_TIMEOUT=5000 | LSE_VALUE=32768 | DATA_CACHE_ENABLE=1 | LSI_VALUE=37000 | MSI_VALUE=2097000 | VDD_VALUE=3300 | INSTRUCTION_CACHE_ENABLE=1 | STM32L011xx | USE_FULL_LL_DRIVER | PREFETCH_ENABLE=0 || || Drivers | Core/Startup | Core || || || ${workspace_loc:/${ProjName}/STM32L011F4UX_FLASH.ld} || true || NonSecure || || secure_nsclib.o || || None" valueType="string"/>
|
||||
|
||||
<targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.ELF" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.targetplatform.445833440" isAbstract="false" osList="all" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.targetplatform"/>
|
||||
|
||||
<builder buildPath="${workspace_loc:/iaq_wired_sensor}/Debug" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.builder.1606920792" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" parallelBuildOn="true" parallelizationNumber="optimal" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.builder"/>
|
||||
|
||||
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.469616765" name="MCU GCC Assembler" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler">
|
||||
|
||||
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.debuglevel.1770109039" name="Debug level" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.debuglevel" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.debuglevel.value.g3" valueType="enumerated"/>
|
||||
|
||||
<inputType id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.input.1171754034" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.input"/>
|
||||
|
||||
</tool>
|
||||
|
||||
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.1515672988" name="MCU GCC Compiler" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler">
|
||||
|
||||
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.debuglevel.1650648268" name="Debug level" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.debuglevel" useByScannerDiscovery="false" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.debuglevel.value.g3" valueType="enumerated"/>
|
||||
|
||||
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.optimization.level.622042" name="Optimization level" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.optimization.level" useByScannerDiscovery="false" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.optimization.level.value.o0" valueType="enumerated"/>
|
||||
|
||||
<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.definedsymbols.2027210563" name="Define symbols (-D)" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.definedsymbols" useByScannerDiscovery="false" valueType="definedSymbols">
|
||||
|
||||
<listOptionValue builtIn="false" value="STM32L011xx"/>
|
||||
|
||||
<listOptionValue builtIn="false" value="DEBUG"/>
|
||||
|
||||
<listOptionValue builtIn="false" value="USE_FULL_LL_DRIVER"/>
|
||||
|
||||
<listOptionValue builtIn="false" value="HSE_VALUE=8000000"/>
|
||||
|
||||
<listOptionValue builtIn="false" value="HSE_STARTUP_TIMEOUT=100"/>
|
||||
|
||||
<listOptionValue builtIn="false" value="LSE_STARTUP_TIMEOUT=5000"/>
|
||||
|
||||
<listOptionValue builtIn="false" value="LSE_VALUE=32768"/>
|
||||
|
||||
<listOptionValue builtIn="false" value="MSI_VALUE=2097000"/>
|
||||
|
||||
<listOptionValue builtIn="false" value="HSI_VALUE=16000000"/>
|
||||
|
||||
<listOptionValue builtIn="false" value="LSI_VALUE=37000"/>
|
||||
|
||||
<listOptionValue builtIn="false" value="VDD_VALUE=3300"/>
|
||||
|
||||
<listOptionValue builtIn="false" value="PREFETCH_ENABLE=0"/>
|
||||
|
||||
<listOptionValue builtIn="false" value="INSTRUCTION_CACHE_ENABLE=1"/>
|
||||
|
||||
<listOptionValue builtIn="false" value="DATA_CACHE_ENABLE=1"/>
|
||||
|
||||
</option>
|
||||
|
||||
<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.includepaths.922066001" name="Include paths (-I)" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.includepaths" useByScannerDiscovery="false" valueType="includePath">
|
||||
|
||||
<listOptionValue builtIn="false" value="../Core/Inc"/>
|
||||
|
||||
<listOptionValue builtIn="false" value="../Drivers/STM32L0xx_HAL_Driver/Inc"/>
|
||||
|
||||
<listOptionValue builtIn="false" value="../Drivers/CMSIS/Device/ST/STM32L0xx/Include"/>
|
||||
|
||||
<listOptionValue builtIn="false" value="../Drivers/CMSIS/Include"/>
|
||||
|
||||
</option>
|
||||
|
||||
<inputType id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.input.c.348969831" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.input.c"/>
|
||||
|
||||
</tool>
|
||||
|
||||
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.1766327030" name="MCU G++ Compiler" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler">
|
||||
|
||||
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.debuglevel.1658652644" name="Debug level" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.debuglevel" useByScannerDiscovery="false" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.debuglevel.value.g3" valueType="enumerated"/>
|
||||
|
||||
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.optimization.level.436451405" name="Optimization level" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.optimization.level" useByScannerDiscovery="false"/>
|
||||
|
||||
</tool>
|
||||
|
||||
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.1892130945" name="MCU GCC Linker" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker">
|
||||
|
||||
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.option.script.1479501762" name="Linker Script (-T)" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.option.script" value="${workspace_loc:/${ProjName}/STM32L011F4UX_FLASH.ld}" valueType="string"/>
|
||||
|
||||
<inputType id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.input.375300198" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.input">
|
||||
|
||||
<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
|
||||
|
||||
<additionalInput kind="additionalinput" paths="$(LIBS)"/>
|
||||
|
||||
</inputType>
|
||||
|
||||
</tool>
|
||||
|
||||
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.linker.687987514" name="MCU G++ Linker" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.linker"/>
|
||||
|
||||
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.archiver.1319199919" name="MCU GCC Archiver" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.archiver"/>
|
||||
|
||||
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.size.809423493" name="MCU Size" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.size"/>
|
||||
|
||||
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objdump.listfile.823263977" name="MCU Output Converter list file" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objdump.listfile"/>
|
||||
|
||||
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.hex.1991227472" name="MCU Output Converter Hex" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.hex"/>
|
||||
|
||||
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.binary.106500396" name="MCU Output Converter Binary" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.binary"/>
|
||||
|
||||
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.verilog.1266735667" name="MCU Output Converter Verilog" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.verilog"/>
|
||||
|
||||
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.srec.1533131337" name="MCU Output Converter Motorola S-rec" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.srec"/>
|
||||
|
||||
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.symbolsrec.1351831132" name="MCU Output Converter Motorola S-rec with symbols" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.symbolsrec"/>
|
||||
|
||||
</toolChain>
|
||||
|
||||
</folderInfo>
|
||||
|
||||
<sourceEntries>
|
||||
|
||||
<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Core"/>
|
||||
|
||||
<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Drivers"/>
|
||||
|
||||
</sourceEntries>
|
||||
|
||||
</configuration>
|
||||
|
||||
</storageModule>
|
||||
|
||||
<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
|
||||
|
||||
</cconfiguration>
|
||||
|
||||
<cconfiguration id="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.release.1380902389">
|
||||
|
||||
<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.release.1380902389" moduleId="org.eclipse.cdt.core.settings" name="Release">
|
||||
|
||||
<externalSettings/>
|
||||
|
||||
<extensions>
|
||||
|
||||
<extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/>
|
||||
|
||||
<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
|
||||
|
||||
<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
|
||||
|
||||
<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
|
||||
|
||||
<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
|
||||
|
||||
<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
|
||||
|
||||
</extensions>
|
||||
|
||||
</storageModule>
|
||||
|
||||
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
|
||||
|
||||
<configuration artifactExtension="elf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.release" cleanCommand="rm -rf" description="" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.release.1380902389" name="Release" parent="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.release">
|
||||
|
||||
<folderInfo id="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.release.1380902389." name="/" resourcePath="">
|
||||
|
||||
<toolChain id="com.st.stm32cube.ide.mcu.gnu.managedbuild.toolchain.exe.release.1445955470" name="MCU ARM GCC" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.toolchain.exe.release">
|
||||
|
||||
<option id="com.st.stm32cube.ide.mcu.option.internal.toolchain.type.663451956" name="Internal Toolchain Type" superClass="com.st.stm32cube.ide.mcu.option.internal.toolchain.type" useByScannerDiscovery="false" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.toolchain.base.gnu-tools-for-stm32" valueType="string"/>
|
||||
|
||||
<option id="com.st.stm32cube.ide.mcu.option.internal.toolchain.version.1559134767" name="Internal Toolchain Version" superClass="com.st.stm32cube.ide.mcu.option.internal.toolchain.version" useByScannerDiscovery="false" value="7-2018-q2-update" valueType="string"/>
|
||||
|
||||
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_mcu.1052616256" name="Mcu" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_mcu" useByScannerDiscovery="true" value="STM32L011F4Ux" valueType="string"/>
|
||||
|
||||
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_cpuid.621141533" name="CpuId" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_cpuid" useByScannerDiscovery="false" value="0" valueType="string"/>
|
||||
|
||||
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_coreid.2032497927" name="CpuCoreId" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_coreid" useByScannerDiscovery="false" value="0" valueType="string"/>
|
||||
|
||||
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_board.1944321553" name="Board" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_board" useByScannerDiscovery="false" value="genericBoard" valueType="string"/>
|
||||
|
||||
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.defaults.1781594695" name="Defaults" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.defaults" useByScannerDiscovery="false" value="com.st.stm32cube.ide.common.services.build.inputs.revA.1.0.4 || Release || false || Executable || com.st.stm32cube.ide.mcu.gnu.managedbuild.toolchain.base.gnu-tools-for-stm32 || STM32L011F4Ux || 0 || 0 || arm-none-eabi- || ${gnu_tools_for_stm32_compiler_path} || ../Drivers/CMSIS/Include | ../Core/Inc | ../Drivers/STM32L0xx_HAL_Driver/Inc | ../Drivers/CMSIS/Device/ST/STM32L0xx/Include || || || HSE_VALUE=8000000 | HSE_STARTUP_TIMEOUT=100 | HSI_VALUE=16000000 | LSE_STARTUP_TIMEOUT=5000 | LSE_VALUE=32768 | DATA_CACHE_ENABLE=1 | LSI_VALUE=37000 | MSI_VALUE=2097000 | VDD_VALUE=3300 | INSTRUCTION_CACHE_ENABLE=1 | STM32L011xx | USE_FULL_LL_DRIVER | PREFETCH_ENABLE=0 || || Drivers | Core/Startup | Core || || || ${workspace_loc:/${ProjName}/STM32L011F4UX_FLASH.ld} || true || NonSecure || || secure_nsclib.o || || None" valueType="string"/>
|
||||
|
||||
<targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.ELF" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.targetplatform.1728902878" isAbstract="false" osList="all" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.targetplatform"/>
|
||||
|
||||
<builder buildPath="${workspace_loc:/iaq_wired_sensor}/Release" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.builder.613343674" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" parallelBuildOn="true" parallelizationNumber="optimal" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.builder"/>
|
||||
|
||||
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.677900669" name="MCU GCC Assembler" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler">
|
||||
|
||||
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.debuglevel.973718199" name="Debug level" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.debuglevel" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.debuglevel.value.g0" valueType="enumerated"/>
|
||||
|
||||
<inputType id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.input.919710092" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.input"/>
|
||||
|
||||
</tool>
|
||||
|
||||
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.907108133" name="MCU GCC Compiler" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler">
|
||||
|
||||
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.debuglevel.904946934" name="Debug level" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.debuglevel" useByScannerDiscovery="false" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.debuglevel.value.g0" valueType="enumerated"/>
|
||||
|
||||
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.optimization.level.737673998" name="Optimization level" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.optimization.level" useByScannerDiscovery="false" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.optimization.level.value.os" valueType="enumerated"/>
|
||||
|
||||
<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.definedsymbols.866907149" name="Define symbols (-D)" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.definedsymbols" useByScannerDiscovery="false" valueType="definedSymbols">
|
||||
|
||||
<listOptionValue builtIn="false" value="STM32L011xx"/>
|
||||
|
||||
<listOptionValue builtIn="false" value="USE_FULL_LL_DRIVER"/>
|
||||
|
||||
<listOptionValue builtIn="false" value="HSE_VALUE=8000000"/>
|
||||
|
||||
<listOptionValue builtIn="false" value="HSE_STARTUP_TIMEOUT=100"/>
|
||||
|
||||
<listOptionValue builtIn="false" value="LSE_STARTUP_TIMEOUT=5000"/>
|
||||
|
||||
<listOptionValue builtIn="false" value="LSE_VALUE=32768"/>
|
||||
|
||||
<listOptionValue builtIn="false" value="MSI_VALUE=2097000"/>
|
||||
|
||||
<listOptionValue builtIn="false" value="HSI_VALUE=16000000"/>
|
||||
|
||||
<listOptionValue builtIn="false" value="LSI_VALUE=37000"/>
|
||||
|
||||
<listOptionValue builtIn="false" value="VDD_VALUE=3300"/>
|
||||
|
||||
<listOptionValue builtIn="false" value="PREFETCH_ENABLE=0"/>
|
||||
|
||||
<listOptionValue builtIn="false" value="INSTRUCTION_CACHE_ENABLE=1"/>
|
||||
|
||||
<listOptionValue builtIn="false" value="DATA_CACHE_ENABLE=1"/>
|
||||
|
||||
</option>
|
||||
|
||||
<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.includepaths.1311622028" name="Include paths (-I)" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.includepaths" useByScannerDiscovery="false" valueType="includePath">
|
||||
|
||||
<listOptionValue builtIn="false" value="../Core/Inc"/>
|
||||
|
||||
<listOptionValue builtIn="false" value="../Drivers/STM32L0xx_HAL_Driver/Inc"/>
|
||||
|
||||
<listOptionValue builtIn="false" value="../Drivers/CMSIS/Device/ST/STM32L0xx/Include"/>
|
||||
|
||||
<listOptionValue builtIn="false" value="../Drivers/CMSIS/Include"/>
|
||||
|
||||
</option>
|
||||
|
||||
<inputType id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.input.c.904229759" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.input.c"/>
|
||||
|
||||
</tool>
|
||||
|
||||
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.901350998" name="MCU G++ Compiler" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler">
|
||||
|
||||
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.debuglevel.553068789" name="Debug level" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.debuglevel" useByScannerDiscovery="false" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.debuglevel.value.g0" valueType="enumerated"/>
|
||||
|
||||
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.optimization.level.1603146879" name="Optimization level" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.optimization.level" useByScannerDiscovery="false" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.optimization.level.value.os" valueType="enumerated"/>
|
||||
|
||||
</tool>
|
||||
|
||||
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.2114561486" name="MCU GCC Linker" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker">
|
||||
|
||||
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.option.script.30176910" name="Linker Script (-T)" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.option.script" value="${workspace_loc:/${ProjName}/STM32L011F4UX_FLASH.ld}" valueType="string"/>
|
||||
|
||||
<inputType id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.input.1549737908" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.input">
|
||||
|
||||
<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
|
||||
|
||||
<additionalInput kind="additionalinput" paths="$(LIBS)"/>
|
||||
|
||||
</inputType>
|
||||
|
||||
</tool>
|
||||
|
||||
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.linker.101235267" name="MCU G++ Linker" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.linker"/>
|
||||
|
||||
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.archiver.243077328" name="MCU GCC Archiver" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.archiver"/>
|
||||
|
||||
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.size.1798550859" name="MCU Size" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.size"/>
|
||||
|
||||
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objdump.listfile.915880004" name="MCU Output Converter list file" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objdump.listfile"/>
|
||||
|
||||
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.hex.1373160599" name="MCU Output Converter Hex" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.hex"/>
|
||||
|
||||
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.binary.1367637434" name="MCU Output Converter Binary" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.binary"/>
|
||||
|
||||
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.verilog.1240598448" name="MCU Output Converter Verilog" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.verilog"/>
|
||||
|
||||
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.srec.1238512966" name="MCU Output Converter Motorola S-rec" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.srec"/>
|
||||
|
||||
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.symbolsrec.1432092923" name="MCU Output Converter Motorola S-rec with symbols" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.symbolsrec"/>
|
||||
|
||||
</toolChain>
|
||||
|
||||
</folderInfo>
|
||||
|
||||
<sourceEntries>
|
||||
|
||||
<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Core"/>
|
||||
|
||||
<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Drivers"/>
|
||||
|
||||
</sourceEntries>
|
||||
|
||||
</configuration>
|
||||
|
||||
</storageModule>
|
||||
|
||||
<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
|
||||
|
||||
</cconfiguration>
|
||||
|
||||
</storageModule>
|
||||
|
||||
<storageModule moduleId="org.eclipse.cdt.core.pathentry"/>
|
||||
|
||||
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
|
||||
|
||||
<project id="iaq_wired_sensor.null.1619035790" name="iaq_wired_sensor"/>
|
||||
|
||||
</storageModule>
|
||||
|
||||
<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
|
||||
|
||||
<storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/>
|
||||
|
||||
<storageModule moduleId="scannerConfiguration">
|
||||
|
||||
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
|
||||
|
||||
<scannerConfigBuildInfo instanceId="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.release.1380902389;com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.release.1380902389.;com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.907108133;com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.input.c.904229759">
|
||||
|
||||
<autodiscovery enabled="false" problemReportingEnabled="true" selectedProfileId=""/>
|
||||
|
||||
</scannerConfigBuildInfo>
|
||||
|
||||
<scannerConfigBuildInfo instanceId="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.debug.1512690796;com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.debug.1512690796.;com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.1515672988;com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.input.c.348969831">
|
||||
|
||||
<autodiscovery enabled="false" problemReportingEnabled="true" selectedProfileId=""/>
|
||||
|
||||
</scannerConfigBuildInfo>
|
||||
|
||||
</storageModule>
|
||||
|
||||
<storageModule moduleId="refreshScope" versionNumber="2">
|
||||
|
||||
<configuration configurationName="Debug">
|
||||
|
||||
<resource resourceType="PROJECT" workspacePath="/iaq_wired_sensor"/>
|
||||
|
||||
</configuration>
|
||||
|
||||
<configuration configurationName="Release">
|
||||
|
||||
<resource resourceType="PROJECT" workspacePath="/iaq_wired_sensor"/>
|
||||
|
||||
</configuration>
|
||||
|
||||
</storageModule>
|
||||
|
||||
</cproject>
|
||||
<storageModule moduleId="org.eclipse.cdt.core.settings">
|
||||
<cconfiguration id="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.debug.583977815">
|
||||
<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.debug.583977815" moduleId="org.eclipse.cdt.core.settings" name="Debug">
|
||||
<externalSettings/>
|
||||
<extensions>
|
||||
<extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/>
|
||||
<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
|
||||
<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
|
||||
<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
|
||||
<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
|
||||
<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
|
||||
</extensions>
|
||||
</storageModule>
|
||||
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
|
||||
<configuration artifactExtension="elf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug" cleanCommand="rm -rf" description="" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.debug.583977815" name="Debug" parent="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.debug">
|
||||
<folderInfo id="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.debug.583977815." name="/" resourcePath="">
|
||||
<toolChain id="com.st.stm32cube.ide.mcu.gnu.managedbuild.toolchain.exe.debug.2029743242" name="MCU ARM GCC" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.toolchain.exe.debug">
|
||||
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_mcu.1153055369" name="MCU" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_mcu" useByScannerDiscovery="true" value="STM32L031G6Ux" valueType="string"/>
|
||||
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_cpuid.1505988584" name="CPU" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_cpuid" useByScannerDiscovery="false" value="0" valueType="string"/>
|
||||
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_coreid.1754745317" name="Core" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_coreid" useByScannerDiscovery="false" value="0" valueType="string"/>
|
||||
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_board.867577247" name="Board" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_board" useByScannerDiscovery="false" value="genericBoard" valueType="string"/>
|
||||
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.defaults.1391568853" name="Defaults" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.defaults" useByScannerDiscovery="false" value="com.st.stm32cube.ide.common.services.build.inputs.revA.1.0.5 || Debug || true || Executable || com.st.stm32cube.ide.mcu.gnu.managedbuild.option.toolchain.value.workspace || STM32L031G6Ux || 0 || 0 || arm-none-eabi- || ${gnu_tools_for_stm32_compiler_path} || ../Drivers/CMSIS/Include | ../Core/Inc | ../Drivers/STM32L0xx_HAL_Driver/Inc | ../Drivers/CMSIS/Device/ST/STM32L0xx/Include || || || HSE_VALUE=8000000 | HSE_STARTUP_TIMEOUT=100 | HSI_VALUE=16000000 | LSE_STARTUP_TIMEOUT=5000 | LSE_VALUE=32768 | DATA_CACHE_ENABLE=1 | LSI_VALUE=37000 | MSI_VALUE=2097000 | VDD_VALUE=3300 | INSTRUCTION_CACHE_ENABLE=1 | STM32L031xx | USE_FULL_LL_DRIVER | PREFETCH_ENABLE=0 || || Drivers | Core/Startup | Core || || || ${workspace_loc:/${ProjName}/STM32L031G6UX_FLASH.ld} || true || NonSecure || || secure_nsclib.o || || None || " valueType="string"/>
|
||||
<targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.ELF" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.targetplatform.2062446076" isAbstract="false" osList="all" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.targetplatform"/>
|
||||
<builder buildPath="${workspace_loc:/iaq_wired_sensor}/Debug" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.builder.1773727162" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" parallelBuildOn="true" parallelizationNumber="optimal" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.builder"/>
|
||||
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.606108895" name="MCU GCC Assembler" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler">
|
||||
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.debuglevel.471998169" name="Debug level" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.debuglevel" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.debuglevel.value.g3" valueType="enumerated"/>
|
||||
<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.definedsymbols.757865890" name="Define symbols (-D)" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.definedsymbols" valueType="definedSymbols">
|
||||
<listOptionValue builtIn="false" value="DEBUG"/>
|
||||
</option>
|
||||
<inputType id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.input.366934534" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.input"/>
|
||||
</tool>
|
||||
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.632390373" name="MCU GCC Compiler" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler">
|
||||
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.debuglevel.1522682025" name="Debug level" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.debuglevel" useByScannerDiscovery="false" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.debuglevel.value.g3" valueType="enumerated"/>
|
||||
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.optimization.level.1801014298" name="Optimization level" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.optimization.level" useByScannerDiscovery="false"/>
|
||||
<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.definedsymbols.1372852757" name="Define symbols (-D)" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.definedsymbols" useByScannerDiscovery="false" valueType="definedSymbols">
|
||||
<listOptionValue builtIn="false" value="DEBUG"/>
|
||||
<listOptionValue builtIn="false" value="STM32L031xx"/>
|
||||
<listOptionValue builtIn="false" value="USE_FULL_LL_DRIVER"/>
|
||||
<listOptionValue builtIn="false" value="HSE_VALUE=8000000"/>
|
||||
<listOptionValue builtIn="false" value="HSE_STARTUP_TIMEOUT=100"/>
|
||||
<listOptionValue builtIn="false" value="LSE_STARTUP_TIMEOUT=5000"/>
|
||||
<listOptionValue builtIn="false" value="LSE_VALUE=32768"/>
|
||||
<listOptionValue builtIn="false" value="MSI_VALUE=2097000"/>
|
||||
<listOptionValue builtIn="false" value="HSI_VALUE=16000000"/>
|
||||
<listOptionValue builtIn="false" value="LSI_VALUE=37000"/>
|
||||
<listOptionValue builtIn="false" value="VDD_VALUE=3300"/>
|
||||
<listOptionValue builtIn="false" value="PREFETCH_ENABLE=0"/>
|
||||
<listOptionValue builtIn="false" value="INSTRUCTION_CACHE_ENABLE=1"/>
|
||||
<listOptionValue builtIn="false" value="DATA_CACHE_ENABLE=1"/>
|
||||
</option>
|
||||
<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.includepaths.946149329" name="Include paths (-I)" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.includepaths" useByScannerDiscovery="false" valueType="includePath">
|
||||
<listOptionValue builtIn="false" value="../Core/Inc"/>
|
||||
<listOptionValue builtIn="false" value="../Drivers/STM32L0xx_HAL_Driver/Inc"/>
|
||||
<listOptionValue builtIn="false" value="../Drivers/CMSIS/Device/ST/STM32L0xx/Include"/>
|
||||
<listOptionValue builtIn="false" value="../Drivers/CMSIS/Include"/>
|
||||
</option>
|
||||
<inputType id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.input.c.1544503170" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.input.c"/>
|
||||
</tool>
|
||||
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.301849200" name="MCU G++ Compiler" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler">
|
||||
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.debuglevel.155930402" name="Debug level" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.debuglevel" useByScannerDiscovery="false" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.debuglevel.value.g3" valueType="enumerated"/>
|
||||
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.optimization.level.1962175978" name="Optimization level" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.optimization.level" useByScannerDiscovery="false"/>
|
||||
</tool>
|
||||
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.2099198825" name="MCU GCC Linker" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker">
|
||||
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.option.script.484597079" name="Linker Script (-T)" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.option.script" value="${workspace_loc:/${ProjName}/STM32L031G6UX_FLASH.ld}" valueType="string"/>
|
||||
<inputType id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.input.851999185" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.input">
|
||||
<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
|
||||
<additionalInput kind="additionalinput" paths="$(LIBS)"/>
|
||||
</inputType>
|
||||
</tool>
|
||||
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.linker.1133881163" name="MCU G++ Linker" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.linker"/>
|
||||
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.archiver.652442764" name="MCU GCC Archiver" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.archiver"/>
|
||||
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.size.1866567555" name="MCU Size" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.size"/>
|
||||
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objdump.listfile.107840215" name="MCU Output Converter list file" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objdump.listfile"/>
|
||||
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.hex.775784024" name="MCU Output Converter Hex" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.hex"/>
|
||||
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.binary.1006686144" name="MCU Output Converter Binary" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.binary"/>
|
||||
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.verilog.1872222239" name="MCU Output Converter Verilog" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.verilog"/>
|
||||
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.srec.1071618158" name="MCU Output Converter Motorola S-rec" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.srec"/>
|
||||
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.symbolsrec.2064647262" name="MCU Output Converter Motorola S-rec with symbols" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.symbolsrec"/>
|
||||
</toolChain>
|
||||
</folderInfo>
|
||||
<sourceEntries>
|
||||
<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Core"/>
|
||||
<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Drivers"/>
|
||||
</sourceEntries>
|
||||
</configuration>
|
||||
</storageModule>
|
||||
<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
|
||||
</cconfiguration>
|
||||
<cconfiguration id="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.release.781650198">
|
||||
<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.release.781650198" moduleId="org.eclipse.cdt.core.settings" name="Release">
|
||||
<externalSettings/>
|
||||
<extensions>
|
||||
<extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/>
|
||||
<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
|
||||
<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
|
||||
<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
|
||||
<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
|
||||
<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
|
||||
</extensions>
|
||||
</storageModule>
|
||||
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
|
||||
<configuration artifactExtension="elf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.release" cleanCommand="rm -rf" description="" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.release.781650198" name="Release" parent="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.release">
|
||||
<folderInfo id="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.release.781650198." name="/" resourcePath="">
|
||||
<toolChain id="com.st.stm32cube.ide.mcu.gnu.managedbuild.toolchain.exe.release.1954020355" name="MCU ARM GCC" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.toolchain.exe.release">
|
||||
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_mcu.1791773732" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_mcu" useByScannerDiscovery="true" value="STM32L031G6Ux" valueType="string"/>
|
||||
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_cpuid.1379739425" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_cpuid" useByScannerDiscovery="false" value="0" valueType="string"/>
|
||||
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_coreid.892262605" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_coreid" useByScannerDiscovery="false" value="0" valueType="string"/>
|
||||
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_board.1892826908" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_board" useByScannerDiscovery="false" value="genericBoard" valueType="string"/>
|
||||
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.defaults.1537311264" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.defaults" useByScannerDiscovery="false" value="com.st.stm32cube.ide.common.services.build.inputs.revA.1.0.5 || Release || false || Executable || com.st.stm32cube.ide.mcu.gnu.managedbuild.option.toolchain.value.workspace || STM32L031G6Ux || 0 || 0 || arm-none-eabi- || ${gnu_tools_for_stm32_compiler_path} || ../Drivers/CMSIS/Include | ../Core/Inc | ../Drivers/STM32L0xx_HAL_Driver/Inc | ../Drivers/CMSIS/Device/ST/STM32L0xx/Include || || || HSE_VALUE=8000000 | HSE_STARTUP_TIMEOUT=100 | HSI_VALUE=16000000 | LSE_STARTUP_TIMEOUT=5000 | LSE_VALUE=32768 | DATA_CACHE_ENABLE=1 | LSI_VALUE=37000 | MSI_VALUE=2097000 | VDD_VALUE=3300 | INSTRUCTION_CACHE_ENABLE=1 | STM32L031xx | USE_FULL_LL_DRIVER | PREFETCH_ENABLE=0 || || Drivers | Core/Startup | Core || || || ${workspace_loc:/${ProjName}/STM32L031G6UX_FLASH.ld} || true || NonSecure || || secure_nsclib.o || || None || " valueType="string"/>
|
||||
<targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.ELF" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.targetplatform.1782859951" isAbstract="false" osList="all" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.targetplatform"/>
|
||||
<builder buildPath="${workspace_loc:/iaq_wired_sensor}/Release" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.builder.1634455695" managedBuildOn="true" name="Gnu Make Builder.Release" parallelBuildOn="true" parallelizationNumber="optimal" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.builder"/>
|
||||
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.1354085929" name="MCU GCC Assembler" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler">
|
||||
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.debuglevel.375884652" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.debuglevel" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.debuglevel.value.g0" valueType="enumerated"/>
|
||||
<inputType id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.input.1707174983" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.input"/>
|
||||
</tool>
|
||||
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.35876175" name="MCU GCC Compiler" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler">
|
||||
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.debuglevel.2107783365" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.debuglevel" useByScannerDiscovery="false" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.debuglevel.value.g0" valueType="enumerated"/>
|
||||
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.optimization.level.227778796" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.optimization.level" useByScannerDiscovery="false" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.optimization.level.value.os" valueType="enumerated"/>
|
||||
<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.definedsymbols.10117233" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.definedsymbols" useByScannerDiscovery="false" valueType="definedSymbols">
|
||||
<listOptionValue builtIn="false" value="STM32L031xx"/>
|
||||
<listOptionValue builtIn="false" value="USE_FULL_LL_DRIVER"/>
|
||||
<listOptionValue builtIn="false" value="HSE_VALUE=8000000"/>
|
||||
<listOptionValue builtIn="false" value="HSE_STARTUP_TIMEOUT=100"/>
|
||||
<listOptionValue builtIn="false" value="LSE_STARTUP_TIMEOUT=5000"/>
|
||||
<listOptionValue builtIn="false" value="LSE_VALUE=32768"/>
|
||||
<listOptionValue builtIn="false" value="MSI_VALUE=2097000"/>
|
||||
<listOptionValue builtIn="false" value="HSI_VALUE=16000000"/>
|
||||
<listOptionValue builtIn="false" value="LSI_VALUE=37000"/>
|
||||
<listOptionValue builtIn="false" value="VDD_VALUE=3300"/>
|
||||
<listOptionValue builtIn="false" value="PREFETCH_ENABLE=0"/>
|
||||
<listOptionValue builtIn="false" value="INSTRUCTION_CACHE_ENABLE=1"/>
|
||||
<listOptionValue builtIn="false" value="DATA_CACHE_ENABLE=1"/>
|
||||
</option>
|
||||
<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.includepaths.300786558" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.includepaths" useByScannerDiscovery="false" valueType="includePath">
|
||||
<listOptionValue builtIn="false" value="../Core/Inc"/>
|
||||
<listOptionValue builtIn="false" value="../Drivers/STM32L0xx_HAL_Driver/Inc"/>
|
||||
<listOptionValue builtIn="false" value="../Drivers/CMSIS/Device/ST/STM32L0xx/Include"/>
|
||||
<listOptionValue builtIn="false" value="../Drivers/CMSIS/Include"/>
|
||||
</option>
|
||||
<inputType id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.input.c.1160143889" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.input.c"/>
|
||||
</tool>
|
||||
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.543872720" name="MCU G++ Compiler" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler">
|
||||
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.debuglevel.450268074" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.debuglevel" useByScannerDiscovery="false" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.debuglevel.value.g0" valueType="enumerated"/>
|
||||
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.optimization.level.2070767313" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.optimization.level" useByScannerDiscovery="false" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.optimization.level.value.os" valueType="enumerated"/>
|
||||
</tool>
|
||||
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.1437191537" name="MCU GCC Linker" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker">
|
||||
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.option.script.581268614" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.option.script" value="${workspace_loc:/${ProjName}/STM32L031G6UX_FLASH.ld}" valueType="string"/>
|
||||
<inputType id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.input.1903039419" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.input">
|
||||
<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
|
||||
<additionalInput kind="additionalinput" paths="$(LIBS)"/>
|
||||
</inputType>
|
||||
</tool>
|
||||
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.linker.1009981428" name="MCU G++ Linker" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.linker"/>
|
||||
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.archiver.107642643" name="MCU GCC Archiver" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.archiver"/>
|
||||
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.size.588822294" name="MCU Size" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.size"/>
|
||||
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objdump.listfile.40664822" name="MCU Output Converter list file" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objdump.listfile"/>
|
||||
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.hex.260472045" name="MCU Output Converter Hex" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.hex"/>
|
||||
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.binary.583631048" name="MCU Output Converter Binary" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.binary"/>
|
||||
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.verilog.599715282" name="MCU Output Converter Verilog" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.verilog"/>
|
||||
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.srec.419142639" name="MCU Output Converter Motorola S-rec" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.srec"/>
|
||||
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.symbolsrec.1187494996" name="MCU Output Converter Motorola S-rec with symbols" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.objcopy.symbolsrec"/>
|
||||
</toolChain>
|
||||
</folderInfo>
|
||||
<sourceEntries>
|
||||
<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Core"/>
|
||||
<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Drivers"/>
|
||||
</sourceEntries>
|
||||
</configuration>
|
||||
</storageModule>
|
||||
<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
|
||||
</cconfiguration>
|
||||
</storageModule>
|
||||
<storageModule moduleId="org.eclipse.cdt.core.pathentry"/>
|
||||
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
|
||||
<project id="iaq_wired_sensor.null.742915967" name="iaq_wired_sensor"/>
|
||||
</storageModule>
|
||||
<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
|
||||
<storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/>
|
||||
<storageModule moduleId="scannerConfiguration">
|
||||
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
|
||||
<scannerConfigBuildInfo instanceId="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.release.781650198;com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.release.781650198.;com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.35876175;com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.input.c.1160143889">
|
||||
<autodiscovery enabled="false" problemReportingEnabled="true" selectedProfileId=""/>
|
||||
</scannerConfigBuildInfo>
|
||||
<scannerConfigBuildInfo instanceId="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.debug.583977815;com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.debug.583977815.;com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.632390373;com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.input.c.1544503170">
|
||||
<autodiscovery enabled="false" problemReportingEnabled="true" selectedProfileId=""/>
|
||||
</scannerConfigBuildInfo>
|
||||
</storageModule>
|
||||
<storageModule moduleId="refreshScope"/>
|
||||
</cproject>
|
||||
@@ -1,10 +1,10 @@
|
||||
[PreviousLibFiles]
|
||||
LibFiles=Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_crs.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_pwr.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_crs.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h;Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l011xx.h;Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h;Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h;Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/system_stm32l0xx.c;Drivers/CMSIS/Include/cmsis_iccarm.h;Drivers/CMSIS/Include/cmsis_gcc.h;Drivers/CMSIS/Include/core_sc000.h;Drivers/CMSIS/Include/cmsis_armclang.h;Drivers/CMSIS/Include/core_cm1.h;Drivers/CMSIS/Include/core_armv8mbl.h;Drivers/CMSIS/Include/core_cm33.h;Drivers/CMSIS/Include/cmsis_version.h;Drivers/CMSIS/Include/cmsis_compiler.h;Drivers/CMSIS/Include/mpu_armv7.h;Drivers/CMSIS/Include/mpu_armv8.h;Drivers/CMSIS/Include/core_cm0plus.h;Drivers/CMSIS/Include/core_sc300.h;Drivers/CMSIS/Include/tz_context.h;Drivers/CMSIS/Include/core_cm0.h;Drivers/CMSIS/Include/core_cm7.h;Drivers/CMSIS/Include/core_cm23.h;Drivers/CMSIS/Include/core_armv8mml.h;Drivers/CMSIS/Include/core_cm4.h;Drivers/CMSIS/Include/cmsis_armcc.h;Drivers/CMSIS/Include/core_cm3.h;
|
||||
LibFiles=Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_crs.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_pwr.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_crs.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h;Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l031xx.h;Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h;Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h;Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/system_stm32l0xx.c;Drivers/CMSIS/Include/cmsis_iccarm.h;Drivers/CMSIS/Include/cmsis_gcc.h;Drivers/CMSIS/Include/core_sc000.h;Drivers/CMSIS/Include/cmsis_armclang.h;Drivers/CMSIS/Include/core_cm1.h;Drivers/CMSIS/Include/core_armv8mbl.h;Drivers/CMSIS/Include/core_cm33.h;Drivers/CMSIS/Include/cmsis_version.h;Drivers/CMSIS/Include/cmsis_compiler.h;Drivers/CMSIS/Include/mpu_armv7.h;Drivers/CMSIS/Include/mpu_armv8.h;Drivers/CMSIS/Include/core_cm0plus.h;Drivers/CMSIS/Include/core_sc300.h;Drivers/CMSIS/Include/tz_context.h;Drivers/CMSIS/Include/core_cm0.h;Drivers/CMSIS/Include/core_cm7.h;Drivers/CMSIS/Include/core_cm23.h;Drivers/CMSIS/Include/core_armv8mml.h;Drivers/CMSIS/Include/core_cm4.h;Drivers/CMSIS/Include/cmsis_armcc.h;Drivers/CMSIS/Include/core_cm3.h;
|
||||
|
||||
[PreviousUsedCubeIDEFiles]
|
||||
SourceFiles=Core/Src/main.c;Core/Src/stm32l0xx_it.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_pwr.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c;Core/Src/system_stm32l0xx.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_pwr.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c;Core/Src/system_stm32l0xx.c;Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/system_stm32l0xx.c;;
|
||||
SourceFiles=Core/Src/main.c;Core/Src/stm32l0xx_it.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_pwr.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c;Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/system_stm32l0xx.c;Core/Src/system_stm32l0xx.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_pwr.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c;Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/system_stm32l0xx.c;Core/Src/system_stm32l0xx.c;;;
|
||||
HeaderPath=Drivers/STM32L0xx_HAL_Driver/Inc;Drivers/CMSIS/Device/ST/STM32L0xx/Include;Drivers/CMSIS/Include;Core/Inc;
|
||||
CDefines=USE_FULL_LL_DRIVER;HSE_VALUE:8000000;HSE_STARTUP_TIMEOUT:100;LSE_STARTUP_TIMEOUT:5000;LSE_VALUE:32768;MSI_VALUE:2097000;HSI_VALUE:16000000;LSI_VALUE:37000;VDD_VALUE:3300;PREFETCH_ENABLE:0;INSTRUCTION_CACHE_ENABLE:1;DATA_CACHE_ENABLE:1;STM32L011xx;USE_FULL_LL_DRIVER;HSE_VALUE:8000000;HSE_STARTUP_TIMEOUT:100;LSE_STARTUP_TIMEOUT:5000;LSE_VALUE:32768;MSI_VALUE:2097000;HSI_VALUE:16000000;LSI_VALUE:37000;VDD_VALUE:3300;PREFETCH_ENABLE:0;INSTRUCTION_CACHE_ENABLE:1;DATA_CACHE_ENABLE:1;
|
||||
CDefines=USE_FULL_LL_DRIVER;HSE_VALUE:8000000;HSE_STARTUP_TIMEOUT:100;LSE_STARTUP_TIMEOUT:5000;LSE_VALUE:32768;MSI_VALUE:2097000;HSI_VALUE:16000000;LSI_VALUE:37000;VDD_VALUE:3300;PREFETCH_ENABLE:0;INSTRUCTION_CACHE_ENABLE:1;DATA_CACHE_ENABLE:1;STM32L031xx;USE_FULL_LL_DRIVER;HSE_VALUE:8000000;HSE_STARTUP_TIMEOUT:100;LSE_STARTUP_TIMEOUT:5000;LSE_VALUE:32768;MSI_VALUE:2097000;HSI_VALUE:16000000;LSI_VALUE:37000;VDD_VALUE:3300;PREFETCH_ENABLE:0;INSTRUCTION_CACHE_ENABLE:1;DATA_CACHE_ENABLE:1;
|
||||
|
||||
[PreviousGenFiles]
|
||||
AdvancedFolderStructure=true
|
||||
|
||||
@@ -24,7 +24,6 @@
|
||||
<nature>org.eclipse.cdt.core.cnature</nature>
|
||||
<nature>com.st.stm32cube.ide.mcu.MCUCubeIdeServicesRevAev2ProjectNature</nature>
|
||||
<nature>com.st.stm32cube.ide.mcu.MCUAdvancedStructureProjectNature</nature>
|
||||
<nature>com.st.stm32cube.ide.mcu.MCUEndUserDisabledTrustZoneProjectNature</nature>
|
||||
<nature>com.st.stm32cube.ide.mcu.MCUSingleCpuProjectNature</nature>
|
||||
<nature>com.st.stm32cube.ide.mcu.MCURootProjectNature</nature>
|
||||
<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
|
||||
|
||||
@@ -1,3 +1,4 @@
|
||||
8DF89ED150041C4CBC7CB9A9CAA90856=295E78E9D51884086204F31037537306
|
||||
DC22A860405A8BF2F2C095E5B6529F12=295E78E9D51884086204F31037537306
|
||||
66BE74F758C12D739921AEA421D593D3=11
|
||||
8DF89ED150041C4CBC7CB9A9CAA90856=807411C90E25B050C1E13646B7FEB5AA
|
||||
DC22A860405A8BF2F2C095E5B6529F12=807411C90E25B050C1E13646B7FEB5AA
|
||||
eclipse.preferences.version=1
|
||||
|
||||
@@ -29,9 +29,8 @@ extern "C" {
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32l0xx_ll_i2c.h"
|
||||
#include "stm32l0xx_ll_lpuart.h"
|
||||
#include "stm32l0xx_ll_rcc.h"
|
||||
#include "stm32l0xx_ll_crs.h"
|
||||
#include "stm32l0xx_ll_rcc.h"
|
||||
#include "stm32l0xx_ll_bus.h"
|
||||
#include "stm32l0xx_ll_system.h"
|
||||
#include "stm32l0xx_ll_exti.h"
|
||||
@@ -40,6 +39,7 @@ extern "C" {
|
||||
#include "stm32l0xx_ll_pwr.h"
|
||||
#include "stm32l0xx_ll_dma.h"
|
||||
#include "stm32l0xx_ll_tim.h"
|
||||
#include "stm32l0xx_ll_usart.h"
|
||||
#include "stm32l0xx_ll_gpio.h"
|
||||
|
||||
#if defined(USE_FULL_ASSERT)
|
||||
@@ -102,10 +102,10 @@ int8_t uart_enable_interrupts(void);
|
||||
/* USER CODE BEGIN Private defines */
|
||||
#define MEASUREMENT_PERIOD_MS 600000
|
||||
|
||||
extern uint16_t lpuart1_rx_message_index;
|
||||
extern uint16_t lpuart1_rx_message_len;
|
||||
extern uint8_t lpuart1_rx_done;
|
||||
extern uint8_t lpuart1_rx_message_too_long;
|
||||
extern uint16_t usart2_rx_message_index;
|
||||
extern uint16_t usart2_rx_message_len;
|
||||
extern uint8_t usart2_rx_done;
|
||||
extern uint8_t usart2_rx_message_too_long;
|
||||
|
||||
extern uint8_t tim21_elapsed_period;
|
||||
|
||||
|
||||
@@ -52,7 +52,7 @@ void SVC_Handler(void);
|
||||
void PendSV_Handler(void);
|
||||
void SysTick_Handler(void);
|
||||
void TIM21_IRQHandler(void);
|
||||
void LPUART1_IRQHandler(void);
|
||||
void USART2_IRQHandler(void);
|
||||
/* USER CODE BEGIN EFP */
|
||||
/* USER CODE END EFP */
|
||||
|
||||
|
||||
@@ -6,7 +6,7 @@
|
||||
*/
|
||||
|
||||
#include "i2c.h"
|
||||
#include "stm32l0xx_ll_lpuart.h"
|
||||
#include "stm32l0xx_ll_usart.h"
|
||||
|
||||
i2c_context_t *i2c_context;
|
||||
|
||||
|
||||
@@ -118,10 +118,10 @@ uint8_t co2_valid = 0;
|
||||
void SystemClock_Config(void);
|
||||
static void MX_GPIO_Init(void);
|
||||
static void MX_I2C1_Init(void);
|
||||
static void MX_LPUART1_UART_Init(void);
|
||||
static void MX_USART2_UART_Init(void);
|
||||
static void MX_TIM21_Init(void);
|
||||
/* USER CODE BEGIN PFP */
|
||||
void LPUART1_TX_Buffer(uint8_t* buffer_tx, uint16_t buffer_tx_len);
|
||||
void USART2_TX_Buffer(uint8_t* buffer_tx, uint16_t buffer_tx_len);
|
||||
/* USER CODE END PFP */
|
||||
|
||||
/* Private user code ---------------------------------------------------------*/
|
||||
@@ -147,6 +147,8 @@ int main(void)
|
||||
LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR);
|
||||
|
||||
/* System interrupt init*/
|
||||
/* SysTick_IRQn interrupt configuration */
|
||||
NVIC_SetPriority(SysTick_IRQn, 3);
|
||||
|
||||
/* USER CODE BEGIN Init */
|
||||
|
||||
@@ -174,7 +176,7 @@ int main(void)
|
||||
/* Initialize all configured peripherals */
|
||||
MX_GPIO_Init();
|
||||
MX_I2C1_Init();
|
||||
MX_LPUART1_UART_Init();
|
||||
MX_USART2_UART_Init();
|
||||
MX_TIM21_Init();
|
||||
/* USER CODE BEGIN 2 */
|
||||
|
||||
@@ -191,7 +193,7 @@ int main(void)
|
||||
modbus_slave_set_address(sensor_config.modbus_addr);
|
||||
|
||||
/* Enable UART for RS485 */
|
||||
LL_LPUART_Enable(LPUART1);
|
||||
LL_USART_Enable(USART2);
|
||||
|
||||
/* Start the timer for measurement triggering */
|
||||
LL_TIM_EnableCounter(TIM21);
|
||||
@@ -202,6 +204,8 @@ int main(void)
|
||||
i2c_context.i2c = I2C1;
|
||||
i2c_init(&i2c_context);
|
||||
|
||||
LL_mDelay(2000);
|
||||
|
||||
scd4x_start_periodic_measurement();
|
||||
uint8_t scd4x_is_connected = 1;
|
||||
uint8_t sps30_is_connected = 0;
|
||||
@@ -227,34 +231,34 @@ int main(void)
|
||||
/* SHT4x Init Time: max 1 ms (datasheet pg. 8) */
|
||||
/* SCD4x Init Time: max 1000 ms (datasheet pg. 6) */
|
||||
/* SPS30 Init Time: max 30000 ms (datasheet pg. 2) */
|
||||
LL_mDelay(1000);
|
||||
LL_mDelay(5000);
|
||||
|
||||
static uint32_t new_baud;
|
||||
|
||||
/* Enter the main loop */
|
||||
while (1)
|
||||
{
|
||||
if (lpuart1_rx_done == 1)
|
||||
if (usart2_rx_done == 1)
|
||||
{
|
||||
/* Process the message */
|
||||
if (lpuart1_rx_message_too_long)
|
||||
if (usart2_rx_message_too_long)
|
||||
{
|
||||
/* Do nothing, just delete the buffer and set the flag back to zero*/
|
||||
lpuart1_rx_message_too_long = 0;
|
||||
usart2_rx_message_too_long = 0;
|
||||
} else
|
||||
{
|
||||
/* Process the message:
|
||||
* message is stored in modbus_buffer[], no copying necessary;
|
||||
* but we need to make sure that modbus_buffer[] will not be used while
|
||||
* processing the message: this can be done by disabling RX interrupt */
|
||||
LL_LPUART_DisableIT_RXNE(LPUART1);
|
||||
modbus_slave_process_msg(modbus_buffer, lpuart1_rx_message_len);
|
||||
LL_USART_DisableIT_RXNE(USART2);
|
||||
modbus_slave_process_msg(modbus_buffer, usart2_rx_message_len);
|
||||
/* Reset the RX DONE flag */
|
||||
lpuart1_rx_done = 0;
|
||||
LL_LPUART_EnableIT_RXNE(LPUART1);
|
||||
usart2_rx_done = 0;
|
||||
LL_USART_EnableIT_RXNE(USART2);
|
||||
}
|
||||
/* Reset the RX DONE flag */
|
||||
lpuart1_rx_done = 0;
|
||||
usart2_rx_done = 0;
|
||||
}
|
||||
/* if config changed (MODBUS write), reflect changes to EEPROM */
|
||||
if (sensor_config_pending_write) {
|
||||
@@ -268,23 +272,16 @@ int main(void)
|
||||
}
|
||||
if (baudrate_changed)
|
||||
{
|
||||
while (!LL_LPUART_IsActiveFlag_TXE(LPUART1));
|
||||
while (!LL_USART_IsActiveFlag_TXE(USART2));
|
||||
uart_disable_interrupts();
|
||||
// LL_LPUART_Disable(LPUART1);
|
||||
// LL_LPUART_DisableIT_IDLE(LPUART1);
|
||||
// LL_LPUART_EnableIT_RXNE(LPUART1);
|
||||
|
||||
LL_LPUART_SetBaudRate(LPUART1, SYSTICK_FREQ_HZ, config_baudrates[sensor_config.baudrate_index]);
|
||||
|
||||
// LL_LPUART_Enable(LPUART1);
|
||||
// LL_LPUART_EnableIT_IDLE(LPUART1);
|
||||
// LL_LPUART_EnableIT_RXNE(LPUART1);
|
||||
LL_USART_SetBaudRate(USART2, SYSTICK_FREQ_HZ, LL_USART_OVERSAMPLING_16, config_baudrates[sensor_config.baudrate_index]);
|
||||
uart_enable_interrupts();
|
||||
LL_LPUART_EnableDirectionRx(LPUART1);
|
||||
LL_LPUART_EnableDirectionTx(LPUART1);
|
||||
LL_USART_EnableDirectionRx(USART2);
|
||||
LL_USART_EnableDirectionTx(USART2);
|
||||
baudrate_changed = 0;
|
||||
|
||||
new_baud = LL_LPUART_GetBaudRate(LPUART1, SYSTICK_FREQ_HZ);
|
||||
new_baud = LL_USART_GetBaudRate(USART2, SYSTICK_FREQ_HZ, LL_USART_OVERSAMPLING_16);
|
||||
}
|
||||
|
||||
/* It is time for measurement */
|
||||
@@ -399,7 +396,7 @@ void SystemClock_Config(void)
|
||||
LL_Init1msTick(12000000);
|
||||
|
||||
LL_SetSystemCoreClock(12000000);
|
||||
LL_RCC_SetLPUARTClockSource(LL_RCC_LPUART1_CLKSOURCE_PCLK1);
|
||||
LL_RCC_SetUSARTClockSource(LL_RCC_USART2_CLKSOURCE_PCLK1);
|
||||
LL_RCC_SetI2CClockSource(LL_RCC_I2C1_CLKSOURCE_PCLK1);
|
||||
}
|
||||
|
||||
@@ -466,89 +463,6 @@ static void MX_I2C1_Init(void)
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief LPUART1 Initialization Function
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
static void MX_LPUART1_UART_Init(void)
|
||||
{
|
||||
|
||||
/* USER CODE BEGIN LPUART1_Init 0 */
|
||||
|
||||
/* USER CODE END LPUART1_Init 0 */
|
||||
|
||||
LL_LPUART_InitTypeDef LPUART_InitStruct = {0};
|
||||
|
||||
LL_GPIO_InitTypeDef GPIO_InitStruct = {0};
|
||||
|
||||
/* Peripheral clock enable */
|
||||
LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_LPUART1);
|
||||
|
||||
LL_IOP_GRP1_EnableClock(LL_IOP_GRP1_PERIPH_GPIOA);
|
||||
LL_IOP_GRP1_EnableClock(LL_IOP_GRP1_PERIPH_GPIOB);
|
||||
/**LPUART1 GPIO Configuration
|
||||
PA0-CK_IN ------> LPUART1_RX
|
||||
PA1 ------> LPUART1_TX
|
||||
PB1 ------> LPUART1_DE
|
||||
*/
|
||||
GPIO_InitStruct.Pin = LL_GPIO_PIN_0;
|
||||
GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE;
|
||||
GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH;
|
||||
GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;
|
||||
GPIO_InitStruct.Pull = LL_GPIO_PULL_UP;
|
||||
GPIO_InitStruct.Alternate = LL_GPIO_AF_6;
|
||||
LL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
||||
|
||||
GPIO_InitStruct.Pin = LL_GPIO_PIN_1;
|
||||
GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE;
|
||||
GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH;
|
||||
GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;
|
||||
GPIO_InitStruct.Pull = LL_GPIO_PULL_UP;
|
||||
GPIO_InitStruct.Alternate = LL_GPIO_AF_6;
|
||||
LL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
||||
|
||||
GPIO_InitStruct.Pin = LL_GPIO_PIN_1;
|
||||
GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE;
|
||||
GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH;
|
||||
GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;
|
||||
GPIO_InitStruct.Pull = LL_GPIO_PULL_NO;
|
||||
GPIO_InitStruct.Alternate = LL_GPIO_AF_4;
|
||||
LL_GPIO_Init(GPIOB, &GPIO_InitStruct);
|
||||
|
||||
/* LPUART1 interrupt Init */
|
||||
NVIC_SetPriority(LPUART1_IRQn, 0);
|
||||
NVIC_EnableIRQ(LPUART1_IRQn);
|
||||
|
||||
/* USER CODE BEGIN LPUART1_Init 1 */
|
||||
|
||||
/* USER CODE END LPUART1_Init 1 */
|
||||
LPUART_InitStruct.BaudRate = config_baudrates[sensor_config.baudrate_index];
|
||||
LPUART_InitStruct.DataWidth = LL_LPUART_DATAWIDTH_9B;
|
||||
LPUART_InitStruct.StopBits = LL_LPUART_STOPBITS_1;
|
||||
LPUART_InitStruct.Parity = LL_LPUART_PARITY_EVEN;
|
||||
LPUART_InitStruct.TransferDirection = LL_LPUART_DIRECTION_TX_RX;
|
||||
LPUART_InitStruct.HardwareFlowControl = LL_LPUART_HWCONTROL_NONE;
|
||||
LL_LPUART_Init(LPUART1, &LPUART_InitStruct);
|
||||
LL_LPUART_EnableDEMode(LPUART1);
|
||||
LL_LPUART_SetDESignalPolarity(LPUART1, LL_LPUART_DE_POLARITY_HIGH);
|
||||
LL_LPUART_SetDEAssertionTime(LPUART1, 0);
|
||||
LL_LPUART_SetDEDeassertionTime(LPUART1, 0);
|
||||
/* USER CODE BEGIN LPUART1_Init 2 */
|
||||
|
||||
/* Enable IDLE Interrupt */
|
||||
LL_LPUART_EnableIT_IDLE(LPUART1);
|
||||
|
||||
/* Enable RX Not Empty Interrupt */
|
||||
LL_LPUART_EnableIT_RXNE(LPUART1);
|
||||
|
||||
LL_LPUART_EnableDirectionRx(LPUART1);
|
||||
LL_LPUART_EnableDirectionTx(LPUART1);
|
||||
LL_LPUART_Enable(LPUART1);
|
||||
/* USER CODE END LPUART1_Init 2 */
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief TIM21 Initialization Function
|
||||
* @param None
|
||||
@@ -588,6 +502,91 @@ static void MX_TIM21_Init(void)
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief USART2 Initialization Function
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
static void MX_USART2_UART_Init(void)
|
||||
{
|
||||
|
||||
/* USER CODE BEGIN USART2_Init 0 */
|
||||
|
||||
/* USER CODE END USART2_Init 0 */
|
||||
|
||||
LL_USART_InitTypeDef USART_InitStruct = {0};
|
||||
|
||||
LL_GPIO_InitTypeDef GPIO_InitStruct = {0};
|
||||
|
||||
/* Peripheral clock enable */
|
||||
LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_USART2);
|
||||
|
||||
LL_IOP_GRP1_EnableClock(LL_IOP_GRP1_PERIPH_GPIOA);
|
||||
/**USART2 GPIO Configuration
|
||||
PA1 ------> USART2_DE
|
||||
PA2 ------> USART2_TX
|
||||
PA3 ------> USART2_RX
|
||||
*/
|
||||
GPIO_InitStruct.Pin = LL_GPIO_PIN_1;
|
||||
GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE;
|
||||
GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH;
|
||||
GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;
|
||||
GPIO_InitStruct.Pull = LL_GPIO_PULL_NO;
|
||||
GPIO_InitStruct.Alternate = LL_GPIO_AF_4;
|
||||
LL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
||||
|
||||
GPIO_InitStruct.Pin = LL_GPIO_PIN_2;
|
||||
GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE;
|
||||
GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH;
|
||||
GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;
|
||||
GPIO_InitStruct.Pull = LL_GPIO_PULL_NO;
|
||||
GPIO_InitStruct.Alternate = LL_GPIO_AF_4;
|
||||
LL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
||||
|
||||
GPIO_InitStruct.Pin = LL_GPIO_PIN_3;
|
||||
GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE;
|
||||
GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH;
|
||||
GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;
|
||||
GPIO_InitStruct.Pull = LL_GPIO_PULL_NO;
|
||||
GPIO_InitStruct.Alternate = LL_GPIO_AF_4;
|
||||
LL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
||||
|
||||
/* USART2 interrupt Init */
|
||||
NVIC_SetPriority(USART2_IRQn, 0);
|
||||
NVIC_EnableIRQ(USART2_IRQn);
|
||||
|
||||
/* USER CODE BEGIN USART2_Init 1 */
|
||||
|
||||
/* USER CODE END USART2_Init 1 */
|
||||
USART_InitStruct.BaudRate = config_baudrates[sensor_config.baudrate_index];
|
||||
USART_InitStruct.DataWidth = LL_USART_DATAWIDTH_9B;
|
||||
USART_InitStruct.StopBits = LL_USART_STOPBITS_1;
|
||||
USART_InitStruct.Parity = LL_USART_PARITY_EVEN;
|
||||
USART_InitStruct.TransferDirection = LL_USART_DIRECTION_TX_RX;
|
||||
USART_InitStruct.HardwareFlowControl = LL_USART_HWCONTROL_NONE;
|
||||
USART_InitStruct.OverSampling = LL_USART_OVERSAMPLING_16;
|
||||
LL_USART_Init(USART2, &USART_InitStruct);
|
||||
LL_USART_EnableDEMode(USART2);
|
||||
LL_USART_SetDESignalPolarity(USART2, LL_USART_DE_POLARITY_HIGH);
|
||||
LL_USART_SetDEAssertionTime(USART2, 0);
|
||||
LL_USART_SetDEDeassertionTime(USART2, 0);
|
||||
LL_USART_ConfigAsyncMode(USART2);
|
||||
LL_USART_Enable(USART2);
|
||||
/* USER CODE BEGIN USART2_Init 2 */
|
||||
|
||||
/* Enable IDLE Interrupt */
|
||||
LL_USART_EnableIT_IDLE(USART2);
|
||||
|
||||
/* Enable RX Not Empty Interrupt */
|
||||
LL_USART_EnableIT_RXNE(USART2);
|
||||
|
||||
LL_USART_EnableDirectionRx(USART2);
|
||||
LL_USART_EnableDirectionTx(USART2);
|
||||
LL_USART_Enable(USART2);
|
||||
/* USER CODE END USART2_Init 2 */
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief GPIO Initialization Function
|
||||
* @param None
|
||||
@@ -601,13 +600,13 @@ static void MX_GPIO_Init(void)
|
||||
LL_IOP_GRP1_EnableClock(LL_IOP_GRP1_PERIPH_GPIOA);
|
||||
|
||||
/**/
|
||||
LL_GPIO_SetOutputPin(LED_B_GPIO_Port, LED_B_Pin);
|
||||
LL_GPIO_ResetOutputPin(LED_B_GPIO_Port, LED_B_Pin);
|
||||
|
||||
/**/
|
||||
LL_GPIO_SetOutputPin(LED_G_GPIO_Port, LED_G_Pin);
|
||||
LL_GPIO_ResetOutputPin(LED_G_GPIO_Port, LED_G_Pin);
|
||||
|
||||
/**/
|
||||
LL_GPIO_SetOutputPin(LED_R_GPIO_Port, LED_R_Pin);
|
||||
LL_GPIO_ResetOutputPin(LED_R_GPIO_Port, LED_R_Pin);
|
||||
|
||||
/**/
|
||||
GPIO_InitStruct.Pin = LED_B_Pin;
|
||||
@@ -636,31 +635,31 @@ static void MX_GPIO_Init(void)
|
||||
}
|
||||
|
||||
/* USER CODE BEGIN 4 */
|
||||
void LPUART1_TX_Buffer(uint8_t* buffer_tx, uint16_t buffer_tx_len)
|
||||
void USART2_TX_Buffer(uint8_t* buffer_tx, uint16_t buffer_tx_len)
|
||||
{
|
||||
__disable_irq();
|
||||
for (uint16_t i = 0; i < buffer_tx_len; i++)
|
||||
{
|
||||
LL_LPUART_TransmitData9(LPUART1, buffer_tx[i]);
|
||||
while (!LL_LPUART_IsActiveFlag_TXE(LPUART1));
|
||||
LL_USART_TransmitData9(USART2, buffer_tx[i]);
|
||||
while (!LL_USART_IsActiveFlag_TXE(USART2));
|
||||
}
|
||||
__enable_irq();
|
||||
}
|
||||
|
||||
int8_t uart_disable_interrupts(void)
|
||||
{
|
||||
LL_LPUART_Disable(LPUART1);
|
||||
LL_LPUART_DisableIT_IDLE(LPUART1);
|
||||
LL_LPUART_EnableIT_RXNE(LPUART1);
|
||||
LL_USART_Disable(USART2);
|
||||
LL_USART_DisableIT_IDLE(USART2);
|
||||
LL_USART_EnableIT_RXNE(USART2);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int8_t uart_enable_interrupts(void)
|
||||
{
|
||||
LL_LPUART_Enable(LPUART1);
|
||||
LL_LPUART_EnableIT_IDLE(LPUART1);
|
||||
LL_LPUART_EnableIT_RXNE(LPUART1);
|
||||
LL_USART_Enable(USART2);
|
||||
LL_USART_EnableIT_IDLE(USART2);
|
||||
LL_USART_EnableIT_RXNE(USART2);
|
||||
|
||||
return 0;
|
||||
}
|
||||
@@ -787,7 +786,7 @@ int8_t modbus_slave_callback(modbus_transaction_t *transaction)
|
||||
int8_t modbus_transmit_function(uint8_t *buffer, uint16_t data_len)
|
||||
{
|
||||
/* TODO */
|
||||
LPUART1_TX_Buffer(buffer, data_len);
|
||||
USART2_TX_Buffer(buffer, data_len);
|
||||
return MODBUS_OK;
|
||||
}
|
||||
/* USER CODE END 4 */
|
||||
|
||||
@@ -43,17 +43,17 @@
|
||||
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* USER CODE BEGIN PV */
|
||||
uint16_t lpuart1_rx_message_index = 0;
|
||||
uint16_t lpuart1_rx_message_len = 0;
|
||||
uint8_t lpuart1_rx_done = 0;
|
||||
uint8_t lpuart1_rx_message_too_long = 0;
|
||||
uint16_t usart2_rx_message_index = 0;
|
||||
uint16_t usart2_rx_message_len = 0;
|
||||
uint8_t usart2_rx_done = 0;
|
||||
uint8_t usart2_rx_message_too_long = 0;
|
||||
|
||||
uint8_t tim21_elapsed_period = 0;
|
||||
/* USER CODE END PV */
|
||||
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* USER CODE BEGIN PFP */
|
||||
void LPUART1_CharReception_Callback( void );
|
||||
void USART2_CharReception_Callback( void );
|
||||
/* USER CODE END PFP */
|
||||
|
||||
/* Private user code ---------------------------------------------------------*/
|
||||
@@ -71,7 +71,7 @@ void LPUART1_CharReception_Callback( void );
|
||||
/* Cortex-M0+ Processor Interruption and Exception Handlers */
|
||||
/******************************************************************************/
|
||||
/**
|
||||
* @brief This function handles Non maskable interrupt.
|
||||
* @brief This function handles Non maskable Interrupt.
|
||||
*/
|
||||
void NMI_Handler(void)
|
||||
{
|
||||
@@ -154,7 +154,6 @@ void TIM21_IRQHandler(void)
|
||||
/* USER CODE BEGIN TIM21_IRQn 0 */
|
||||
LL_TIM_ClearFlag_UPDATE(TIM21);
|
||||
tim21_elapsed_period = 1;
|
||||
|
||||
/* USER CODE END TIM21_IRQn 0 */
|
||||
/* USER CODE BEGIN TIM21_IRQn 1 */
|
||||
|
||||
@@ -162,47 +161,47 @@ void TIM21_IRQHandler(void)
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function handles LPUART1 global interrupt / LPUART1 wake-up interrupt through EXTI line 28.
|
||||
* @brief This function handles USART2 global interrupt / USART2 wake-up interrupt through EXTI line 26.
|
||||
*/
|
||||
void LPUART1_IRQHandler(void)
|
||||
void USART2_IRQHandler(void)
|
||||
{
|
||||
/* USER CODE BEGIN LPUART1_IRQn 0 */
|
||||
/* USER CODE BEGIN USART2_IRQn 0 */
|
||||
/* Check RXNE flag value in SR register */
|
||||
if(LL_LPUART_IsActiveFlag_RXNE(LPUART1) && LL_LPUART_IsEnabledIT_RXNE(LPUART1))
|
||||
if(LL_USART_IsActiveFlag_RXNE(USART2) && LL_USART_IsEnabledIT_RXNE(USART2))
|
||||
{
|
||||
/* RXNE flag will be cleared by reading of DR register (done in call) */
|
||||
/* Call function in charge of handling Character reception */
|
||||
LPUART1_CharReception_Callback();
|
||||
USART2_CharReception_Callback();
|
||||
}
|
||||
/* USER CODE END LPUART1_IRQn 0 */
|
||||
/* USER CODE BEGIN LPUART1_IRQn 1 */
|
||||
/* USER CODE END USART2_IRQn 0 */
|
||||
/* USER CODE BEGIN USART2_IRQn 1 */
|
||||
/* If the IDLE flag is active */
|
||||
if (LL_LPUART_IsActiveFlag_IDLE(LPUART1) && LL_LPUART_IsEnabledIT_IDLE(LPUART1))
|
||||
if (LL_USART_IsActiveFlag_IDLE(USART2) && LL_USART_IsEnabledIT_IDLE(USART2))
|
||||
{
|
||||
/* Clear the IDLE flag */
|
||||
LL_LPUART_ClearFlag_IDLE(LPUART1);
|
||||
LL_USART_ClearFlag_IDLE(USART2);
|
||||
|
||||
/* Reset the buffer index */
|
||||
lpuart1_rx_message_len = lpuart1_rx_message_index;
|
||||
lpuart1_rx_message_index = 0;
|
||||
lpuart1_rx_done = 1;
|
||||
if (lpuart1_rx_message_len > MODBUS_MAX_RTU_FRAME_SIZE)
|
||||
usart2_rx_message_len = usart2_rx_message_index;
|
||||
usart2_rx_message_index = 0;
|
||||
usart2_rx_done = 1;
|
||||
if (usart2_rx_message_len > MODBUS_MAX_RTU_FRAME_SIZE)
|
||||
{
|
||||
lpuart1_rx_message_too_long = 1;
|
||||
usart2_rx_message_too_long = 1;
|
||||
}
|
||||
}
|
||||
/* USER CODE END LPUART1_IRQn 1 */
|
||||
/* USER CODE END USART2_IRQn 1 */
|
||||
}
|
||||
|
||||
/* USER CODE BEGIN 1 */
|
||||
void LPUART1_CharReception_Callback( void )
|
||||
void USART2_CharReception_Callback( void )
|
||||
{
|
||||
uint16_t lpuart1_rx_bit = LL_LPUART_ReceiveData9(LPUART1);
|
||||
if (lpuart1_rx_message_index < MODBUS_MAX_RTU_FRAME_SIZE)
|
||||
uint16_t usart2_rx_bit = LL_USART_ReceiveData9(USART2);
|
||||
if (usart2_rx_message_index < MODBUS_MAX_RTU_FRAME_SIZE)
|
||||
{
|
||||
modbus_buffer[lpuart1_rx_message_index] = (uint8_t)lpuart1_rx_bit;
|
||||
modbus_buffer[usart2_rx_message_index] = (uint8_t)usart2_rx_bit;
|
||||
}
|
||||
lpuart1_rx_message_index++;
|
||||
usart2_rx_message_index++;
|
||||
}
|
||||
/* USER CODE END 1 */
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
||||
@@ -1,8 +1,8 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file startup_stm32l011xx.s
|
||||
* @file startup_stm32l031xx.s
|
||||
* @author MCD Application Team
|
||||
* @brief STM32L011xx Devices vector table for GCC toolchain.
|
||||
* @brief STM32L031xx Devices vector table for GCC toolchain.
|
||||
* This module performs:
|
||||
* - Set the initial SP
|
||||
* - Set the initial PC == Reset_Handler,
|
||||
@@ -52,26 +52,6 @@ Reset_Handler:
|
||||
ldr r0, =_estack
|
||||
mov sp, r0 /* set stack pointer */
|
||||
|
||||
/*Check if boot space corresponds to system memory*/
|
||||
|
||||
LDR R0,=0x00000004
|
||||
LDR R1, [R0]
|
||||
LSRS R1, R1, #24
|
||||
LDR R2,=0x1F
|
||||
CMP R1, R2
|
||||
BNE ApplicationStart
|
||||
|
||||
/*SYSCFG clock enable*/
|
||||
LDR R0,=0x40021034
|
||||
LDR R1,=0x00000001
|
||||
STR R1, [R0]
|
||||
|
||||
/*Set CFGR1 register with flash memory remap at address 0*/
|
||||
LDR R0,=0x40010000
|
||||
LDR R1,=0x00000000
|
||||
STR R1, [R0]
|
||||
|
||||
ApplicationStart:
|
||||
/* Copy the data segment initializers from flash to SRAM */
|
||||
ldr r0, =_sdata
|
||||
ldr r1, =_edata
|
||||
@@ -169,7 +149,7 @@ g_pfnVectors:
|
||||
.word 0 /* Reserved */
|
||||
.word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */
|
||||
.word DMA1_Channel2_3_IRQHandler /* DMA1 Channel 2 and Channel 3 */
|
||||
.word DMA1_Channel4_5_IRQHandler /* DMA1 Channel 4 and Channel 5 */
|
||||
.word DMA1_Channel4_5_6_7_IRQHandler /* DMA1 Channel 4, Channel 5, Channel 6 and Channel 7*/
|
||||
.word ADC1_COMP_IRQHandler /* ADC1, COMP1 and COMP2 */
|
||||
.word LPTIM1_IRQHandler /* LPTIM1 */
|
||||
.word 0 /* Reserved */
|
||||
@@ -180,7 +160,7 @@ g_pfnVectors:
|
||||
.word 0 /* Reserved */
|
||||
.word TIM21_IRQHandler /* TIM21 */
|
||||
.word 0 /* Reserved */
|
||||
.word 0 /* Reserved */
|
||||
.word TIM22_IRQHandler /* TIM22 */
|
||||
.word I2C1_IRQHandler /* I2C1 */
|
||||
.word 0 /* Reserved */
|
||||
.word SPI1_IRQHandler /* SPI1 */
|
||||
@@ -244,8 +224,8 @@ g_pfnVectors:
|
||||
.weak DMA1_Channel2_3_IRQHandler
|
||||
.thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel4_5_IRQHandler
|
||||
.thumb_set DMA1_Channel4_5_IRQHandler,Default_Handler
|
||||
.weak DMA1_Channel4_5_6_7_IRQHandler
|
||||
.thumb_set DMA1_Channel4_5_6_7_IRQHandler,Default_Handler
|
||||
|
||||
.weak ADC1_COMP_IRQHandler
|
||||
.thumb_set ADC1_COMP_IRQHandler,Default_Handler
|
||||
@@ -259,6 +239,9 @@ g_pfnVectors:
|
||||
.weak TIM21_IRQHandler
|
||||
.thumb_set TIM21_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM22_IRQHandler
|
||||
.thumb_set TIM22_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C1_IRQHandler
|
||||
.thumb_set I2C1_IRQHandler,Default_Handler
|
||||
|
||||
@@ -1,10 +1,10 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32l011xx.h
|
||||
* @file stm32l031xx.h
|
||||
* @author MCD Application Team
|
||||
* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File.
|
||||
* This file contains all the peripheral register's definitions, bits
|
||||
* definitions and memory mapping for stm32l011xx devices.
|
||||
* definitions and memory mapping for stm32l031xx devices.
|
||||
*
|
||||
* This file contains:
|
||||
* - Data structures and the address mapping for all peripherals
|
||||
@@ -29,12 +29,12 @@
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup stm32l011xx
|
||||
/** @addtogroup stm32l031xx
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef __STM32L011xx_H
|
||||
#define __STM32L011xx_H
|
||||
#ifndef __STM32L031xx_H
|
||||
#define __STM32L031xx_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
@@ -62,7 +62,7 @@
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief stm32l011xx Interrupt Number Definition, according to the selected device
|
||||
* @brief stm32l031xx Interrupt Number Definition, according to the selected device
|
||||
* in @ref Library_configuration_section
|
||||
*/
|
||||
|
||||
@@ -87,11 +87,12 @@ typedef enum
|
||||
EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */
|
||||
DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */
|
||||
DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */
|
||||
DMA1_Channel4_5_IRQn = 11, /*!< DMA1 Channel 4 and Channel 5 Interrupts */
|
||||
DMA1_Channel4_5_6_7_IRQn = 11, /*!< DMA1 Channel 4, Channel 5, Channel 6 and Channel 7 Interrupts */
|
||||
ADC1_COMP_IRQn = 12, /*!< ADC1, COMP1 and COMP2 Interrupts */
|
||||
LPTIM1_IRQn = 13, /*!< LPTIM1 Interrupt */
|
||||
TIM2_IRQn = 15, /*!< TIM2 Interrupt */
|
||||
TIM21_IRQn = 20, /*!< TIM21 Interrupt */
|
||||
TIM22_IRQn = 22, /*!< TIM22 Interrupt */
|
||||
I2C1_IRQn = 23, /*!< I2C1 Interrupt */
|
||||
SPI1_IRQn = 25, /*!< SPI1 Interrupt */
|
||||
USART2_IRQn = 28, /*!< USART2 Interrupt */
|
||||
@@ -478,9 +479,9 @@ typedef struct
|
||||
#define FLASH_BASE (0x08000000UL) /*!< FLASH base address in the alias region */
|
||||
|
||||
#define DATA_EEPROM_BASE (0x08080000UL) /*!< DATA_EEPROM base address in the alias region */
|
||||
#define DATA_EEPROM_END (0x080801FFUL) /*!< DATA EEPROM end address in the alias region */
|
||||
#define DATA_EEPROM_END (0x080803FFUL) /*!< DATA EEPROM end address in the alias region */
|
||||
#define SRAM_BASE (0x20000000UL) /*!< SRAM base address in the alias region */
|
||||
#define SRAM_SIZE_MAX (0x00000800UL) /*!< maximum SRAM size (up to 2KBytes) */
|
||||
#define SRAM_SIZE_MAX (0x00002000UL) /*!< maximum SRAM size (up to 8KBytes) */
|
||||
|
||||
#define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address in the alias region */
|
||||
|
||||
@@ -505,6 +506,7 @@ typedef struct
|
||||
#define COMP12_COMMON ((COMP_Common_TypeDef *) COMP1_BASE)
|
||||
#define EXTI_BASE (APBPERIPH_BASE + 0x00010400UL)
|
||||
#define TIM21_BASE (APBPERIPH_BASE + 0x00010800UL)
|
||||
#define TIM22_BASE (APBPERIPH_BASE + 0x00011400UL)
|
||||
#define ADC1_BASE (APBPERIPH_BASE + 0x00012400UL)
|
||||
#define ADC_BASE (APBPERIPH_BASE + 0x00012708UL)
|
||||
#define SPI1_BASE (APBPERIPH_BASE + 0x00013000UL)
|
||||
@@ -516,6 +518,8 @@ typedef struct
|
||||
#define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030UL)
|
||||
#define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044UL)
|
||||
#define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058UL)
|
||||
#define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006CUL)
|
||||
#define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080UL)
|
||||
#define DMA1_CSELR_BASE (DMA1_BASE + 0x000000A8UL)
|
||||
|
||||
|
||||
@@ -529,6 +533,7 @@ typedef struct
|
||||
#define GPIOA_BASE (IOPPERIPH_BASE + 0x00000000UL)
|
||||
#define GPIOB_BASE (IOPPERIPH_BASE + 0x00000400UL)
|
||||
#define GPIOC_BASE (IOPPERIPH_BASE + 0x00000800UL)
|
||||
#define GPIOH_BASE (IOPPERIPH_BASE + 0x00001C00UL)
|
||||
|
||||
/**
|
||||
* @}
|
||||
@@ -553,6 +558,7 @@ typedef struct
|
||||
#define COMP2 ((COMP_TypeDef *) COMP2_BASE)
|
||||
#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
|
||||
#define TIM21 ((TIM_TypeDef *) TIM21_BASE)
|
||||
#define TIM22 ((TIM_TypeDef *) TIM22_BASE)
|
||||
#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
|
||||
#define ADC1_COMMON ((ADC_Common_TypeDef *) ADC_BASE)
|
||||
/* Legacy defines */
|
||||
@@ -566,6 +572,8 @@ typedef struct
|
||||
#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
|
||||
#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
|
||||
#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
|
||||
#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
|
||||
#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
|
||||
#define DMA1_CSELR ((DMA_Request_TypeDef *) DMA1_CSELR_BASE)
|
||||
|
||||
|
||||
@@ -577,6 +585,7 @@ typedef struct
|
||||
#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
|
||||
#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
|
||||
#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
|
||||
#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
|
||||
|
||||
/**
|
||||
* @}
|
||||
@@ -585,6 +594,15 @@ typedef struct
|
||||
/** @addtogroup Exported_constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup Hardware_Constant_Definition
|
||||
* @{
|
||||
*/
|
||||
#define LSI_STARTUP_TIME 200U /*!< LSI Maximum startup time in us */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup Peripheral_Registers_Bits_Definition
|
||||
* @{
|
||||
@@ -1056,6 +1074,9 @@ typedef struct
|
||||
#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Pos) /*!< 0x80000000 */
|
||||
#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Msk /*!< LPTIM1 counter stopped when core is halted */
|
||||
/****************** Bit definition for DBGMCU_APB2_FZ register **************/
|
||||
#define DBGMCU_APB2_FZ_DBG_TIM22_STOP_Pos (5U)
|
||||
#define DBGMCU_APB2_FZ_DBG_TIM22_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM22_STOP_Pos) /*!< 0x00000020 */
|
||||
#define DBGMCU_APB2_FZ_DBG_TIM22_STOP DBGMCU_APB2_FZ_DBG_TIM22_STOP_Msk /*!< TIM22 counter stopped when core is halted */
|
||||
#define DBGMCU_APB2_FZ_DBG_TIM21_STOP_Pos (2U)
|
||||
#define DBGMCU_APB2_FZ_DBG_TIM21_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM21_STOP_Pos) /*!< 0x00000004 */
|
||||
#define DBGMCU_APB2_FZ_DBG_TIM21_STOP DBGMCU_APB2_FZ_DBG_TIM21_STOP_Msk /*!< TIM21 counter stopped when core is halted */
|
||||
@@ -1127,6 +1148,30 @@ typedef struct
|
||||
#define DMA_ISR_TEIF5_Pos (19U)
|
||||
#define DMA_ISR_TEIF5_Msk (0x1UL << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */
|
||||
#define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */
|
||||
#define DMA_ISR_GIF6_Pos (20U)
|
||||
#define DMA_ISR_GIF6_Msk (0x1UL << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */
|
||||
#define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */
|
||||
#define DMA_ISR_TCIF6_Pos (21U)
|
||||
#define DMA_ISR_TCIF6_Msk (0x1UL << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */
|
||||
#define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */
|
||||
#define DMA_ISR_HTIF6_Pos (22U)
|
||||
#define DMA_ISR_HTIF6_Msk (0x1UL << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */
|
||||
#define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */
|
||||
#define DMA_ISR_TEIF6_Pos (23U)
|
||||
#define DMA_ISR_TEIF6_Msk (0x1UL << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */
|
||||
#define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */
|
||||
#define DMA_ISR_GIF7_Pos (24U)
|
||||
#define DMA_ISR_GIF7_Msk (0x1UL << DMA_ISR_GIF7_Pos) /*!< 0x01000000 */
|
||||
#define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */
|
||||
#define DMA_ISR_TCIF7_Pos (25U)
|
||||
#define DMA_ISR_TCIF7_Msk (0x1UL << DMA_ISR_TCIF7_Pos) /*!< 0x02000000 */
|
||||
#define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */
|
||||
#define DMA_ISR_HTIF7_Pos (26U)
|
||||
#define DMA_ISR_HTIF7_Msk (0x1UL << DMA_ISR_HTIF7_Pos) /*!< 0x04000000 */
|
||||
#define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */
|
||||
#define DMA_ISR_TEIF7_Pos (27U)
|
||||
#define DMA_ISR_TEIF7_Msk (0x1UL << DMA_ISR_TEIF7_Pos) /*!< 0x08000000 */
|
||||
#define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */
|
||||
|
||||
/******************* Bit definition for DMA_IFCR register *******************/
|
||||
#define DMA_IFCR_CGIF1_Pos (0U)
|
||||
@@ -1189,6 +1234,30 @@ typedef struct
|
||||
#define DMA_IFCR_CTEIF5_Pos (19U)
|
||||
#define DMA_IFCR_CTEIF5_Msk (0x1UL << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */
|
||||
#define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */
|
||||
#define DMA_IFCR_CGIF6_Pos (20U)
|
||||
#define DMA_IFCR_CGIF6_Msk (0x1UL << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */
|
||||
#define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */
|
||||
#define DMA_IFCR_CTCIF6_Pos (21U)
|
||||
#define DMA_IFCR_CTCIF6_Msk (0x1UL << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */
|
||||
#define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */
|
||||
#define DMA_IFCR_CHTIF6_Pos (22U)
|
||||
#define DMA_IFCR_CHTIF6_Msk (0x1UL << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */
|
||||
#define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */
|
||||
#define DMA_IFCR_CTEIF6_Pos (23U)
|
||||
#define DMA_IFCR_CTEIF6_Msk (0x1UL << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */
|
||||
#define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */
|
||||
#define DMA_IFCR_CGIF7_Pos (24U)
|
||||
#define DMA_IFCR_CGIF7_Msk (0x1UL << DMA_IFCR_CGIF7_Pos) /*!< 0x01000000 */
|
||||
#define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */
|
||||
#define DMA_IFCR_CTCIF7_Pos (25U)
|
||||
#define DMA_IFCR_CTCIF7_Msk (0x1UL << DMA_IFCR_CTCIF7_Pos) /*!< 0x02000000 */
|
||||
#define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */
|
||||
#define DMA_IFCR_CHTIF7_Pos (26U)
|
||||
#define DMA_IFCR_CHTIF7_Msk (0x1UL << DMA_IFCR_CHTIF7_Pos) /*!< 0x04000000 */
|
||||
#define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */
|
||||
#define DMA_IFCR_CTEIF7_Pos (27U)
|
||||
#define DMA_IFCR_CTEIF7_Msk (0x1UL << DMA_IFCR_CTEIF7_Pos) /*!< 0x08000000 */
|
||||
#define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */
|
||||
|
||||
/******************* Bit definition for DMA_CCR register ********************/
|
||||
#define DMA_CCR_EN_Pos (0U)
|
||||
@@ -1270,6 +1339,12 @@ typedef struct
|
||||
#define DMA_CSELR_C5S_Pos (16U)
|
||||
#define DMA_CSELR_C5S_Msk (0xFUL << DMA_CSELR_C5S_Pos) /*!< 0x000F0000 */
|
||||
#define DMA_CSELR_C5S DMA_CSELR_C5S_Msk /*!< Channel 5 Selection */
|
||||
#define DMA_CSELR_C6S_Pos (20U)
|
||||
#define DMA_CSELR_C6S_Msk (0xFUL << DMA_CSELR_C6S_Pos) /*!< 0x00F00000 */
|
||||
#define DMA_CSELR_C6S DMA_CSELR_C6S_Msk /*!< Channel 6 Selection */
|
||||
#define DMA_CSELR_C7S_Pos (24U)
|
||||
#define DMA_CSELR_C7S_Msk (0xFUL << DMA_CSELR_C7S_Pos) /*!< 0x0F000000 */
|
||||
#define DMA_CSELR_C7S DMA_CSELR_C7S_Msk /*!< Channel 7 Selection */
|
||||
|
||||
/******************************************************************************/
|
||||
/* */
|
||||
@@ -3045,9 +3120,6 @@ typedef struct
|
||||
#define PWR_CR_LPRUN_Pos (14U)
|
||||
#define PWR_CR_LPRUN_Msk (0x1UL << PWR_CR_LPRUN_Pos) /*!< 0x00004000 */
|
||||
#define PWR_CR_LPRUN PWR_CR_LPRUN_Msk /*!< Low power run mode */
|
||||
#define PWR_CR_LPDS_Pos (16U)
|
||||
#define PWR_CR_LPDS_Msk (0x1UL << PWR_CR_LPDS_Pos) /*!< 0x00010000 */
|
||||
#define PWR_CR_LPDS PWR_CR_LPDS_Msk /*!< regulator in low power deepsleep mode */
|
||||
|
||||
/******************* Bit definition for PWR_CSR register ********************/
|
||||
#define PWR_CSR_WUF_Pos (0U)
|
||||
@@ -3072,6 +3144,9 @@ typedef struct
|
||||
#define PWR_CSR_EWUP1_Pos (8U)
|
||||
#define PWR_CSR_EWUP1_Msk (0x1UL << PWR_CSR_EWUP1_Pos) /*!< 0x00000100 */
|
||||
#define PWR_CSR_EWUP1 PWR_CSR_EWUP1_Msk /*!< Enable WKUP pin 1 */
|
||||
#define PWR_CSR_EWUP2_Pos (9U)
|
||||
#define PWR_CSR_EWUP2_Msk (0x1UL << PWR_CSR_EWUP2_Pos) /*!< 0x00000200 */
|
||||
#define PWR_CSR_EWUP2 PWR_CSR_EWUP2_Msk /*!< Enable WKUP pin 2 */
|
||||
#define PWR_CSR_EWUP3_Pos (10U)
|
||||
#define PWR_CSR_EWUP3_Msk (0x1UL << PWR_CSR_EWUP3_Pos) /*!< 0x00000400 */
|
||||
#define PWR_CSR_EWUP3 PWR_CSR_EWUP3_Msk /*!< Enable WKUP pin 3 */
|
||||
@@ -3084,7 +3159,9 @@ typedef struct
|
||||
/*
|
||||
* @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
|
||||
*/
|
||||
/* Note: No specific macro feature on this device */
|
||||
#define RCC_HSECSS_SUPPORT /*!< HSE CSS feature activation support */
|
||||
#define RCC_MCO3_SUPPORT /*!<Support MCO3 */
|
||||
#define RCC_MCO3_AF2_SUPPORT /*!<Support MCO3 on Alternate Function AF0 */
|
||||
|
||||
/******************** Bit definition for RCC_CR register ********************/
|
||||
#define RCC_CR_HSION_Pos (0U)
|
||||
@@ -3120,6 +3197,9 @@ typedef struct
|
||||
#define RCC_CR_HSEBYP_Pos (18U)
|
||||
#define RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
|
||||
#define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed clock Bypass */
|
||||
#define RCC_CR_CSSHSEON_Pos (19U)
|
||||
#define RCC_CR_CSSHSEON_Msk (0x1UL << RCC_CR_CSSHSEON_Pos) /*!< 0x00080000 */
|
||||
#define RCC_CR_CSSHSEON RCC_CR_CSSHSEON_Msk /*!< HSE Clock Security System enable */
|
||||
#define RCC_CR_RTCPRE_Pos (20U)
|
||||
#define RCC_CR_RTCPRE_Msk (0x3UL << RCC_CR_RTCPRE_Pos) /*!< 0x00300000 */
|
||||
#define RCC_CR_RTCPRE RCC_CR_RTCPRE_Msk /*!< RTC prescaler [1:0] bits */
|
||||
@@ -3133,6 +3213,7 @@ typedef struct
|
||||
#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< PLL clock ready flag */
|
||||
|
||||
/* Reference defines */
|
||||
#define RCC_CR_CSSON RCC_CR_CSSHSEON
|
||||
|
||||
/******************** Bit definition for RCC_ICSCR register *****************/
|
||||
#define RCC_ICSCR_HSICAL_Pos (0U)
|
||||
@@ -3394,9 +3475,13 @@ typedef struct
|
||||
#define RCC_CIFR_CSSLSEF_Pos (7U)
|
||||
#define RCC_CIFR_CSSLSEF_Msk (0x1UL << RCC_CIFR_CSSLSEF_Pos) /*!< 0x00000080 */
|
||||
#define RCC_CIFR_CSSLSEF RCC_CIFR_CSSLSEF_Msk /*!< LSE Clock Security System Interrupt flag */
|
||||
#define RCC_CIFR_CSSHSEF_Pos (8U)
|
||||
#define RCC_CIFR_CSSHSEF_Msk (0x1UL << RCC_CIFR_CSSHSEF_Pos) /*!< 0x00000100 */
|
||||
#define RCC_CIFR_CSSHSEF RCC_CIFR_CSSHSEF_Msk /*!< HSE Clock Security System Interrupt flag */
|
||||
|
||||
/* Reference defines */
|
||||
#define RCC_CIFR_LSECSSF RCC_CIFR_CSSLSEF
|
||||
#define RCC_CIFR_CSSF RCC_CIFR_CSSHSEF
|
||||
|
||||
/*!<****************** Bit definition for RCC_CICR register ********************/
|
||||
#define RCC_CICR_LSIRDYC_Pos (0U)
|
||||
@@ -3420,9 +3505,13 @@ typedef struct
|
||||
#define RCC_CICR_CSSLSEC_Pos (7U)
|
||||
#define RCC_CICR_CSSLSEC_Msk (0x1UL << RCC_CICR_CSSLSEC_Pos) /*!< 0x00000080 */
|
||||
#define RCC_CICR_CSSLSEC RCC_CICR_CSSLSEC_Msk /*!< LSE Clock Security System Interrupt Clear */
|
||||
#define RCC_CICR_CSSHSEC_Pos (8U)
|
||||
#define RCC_CICR_CSSHSEC_Msk (0x1UL << RCC_CICR_CSSHSEC_Pos) /*!< 0x00000100 */
|
||||
#define RCC_CICR_CSSHSEC RCC_CICR_CSSHSEC_Msk /*!< HSE Clock Security System Interrupt Clear */
|
||||
|
||||
/* Reference defines */
|
||||
#define RCC_CICR_LSECSSC RCC_CICR_CSSLSEC
|
||||
#define RCC_CICR_CSSC RCC_CICR_CSSHSEC
|
||||
/***************** Bit definition for RCC_IOPRSTR register ******************/
|
||||
#define RCC_IOPRSTR_IOPARST_Pos (0U)
|
||||
#define RCC_IOPRSTR_IOPARST_Msk (0x1UL << RCC_IOPRSTR_IOPARST_Pos) /*!< 0x00000001 */
|
||||
@@ -3433,11 +3522,15 @@ typedef struct
|
||||
#define RCC_IOPRSTR_IOPCRST_Pos (2U)
|
||||
#define RCC_IOPRSTR_IOPCRST_Msk (0x1UL << RCC_IOPRSTR_IOPCRST_Pos) /*!< 0x00000004 */
|
||||
#define RCC_IOPRSTR_IOPCRST RCC_IOPRSTR_IOPCRST_Msk /*!< GPIO port C reset */
|
||||
#define RCC_IOPRSTR_IOPHRST_Pos (7U)
|
||||
#define RCC_IOPRSTR_IOPHRST_Msk (0x1UL << RCC_IOPRSTR_IOPHRST_Pos) /*!< 0x00000080 */
|
||||
#define RCC_IOPRSTR_IOPHRST RCC_IOPRSTR_IOPHRST_Msk /*!< GPIO port H reset */
|
||||
|
||||
/* Reference defines */
|
||||
#define RCC_IOPRSTR_GPIOARST RCC_IOPRSTR_IOPARST /*!< GPIO port A reset */
|
||||
#define RCC_IOPRSTR_GPIOBRST RCC_IOPRSTR_IOPBRST /*!< GPIO port B reset */
|
||||
#define RCC_IOPRSTR_GPIOCRST RCC_IOPRSTR_IOPCRST /*!< GPIO port C reset */
|
||||
#define RCC_IOPRSTR_GPIOHRST RCC_IOPRSTR_IOPHRST /*!< GPIO port H reset */
|
||||
|
||||
|
||||
/****************** Bit definition for RCC_AHBRST register ******************/
|
||||
@@ -3461,6 +3554,9 @@ typedef struct
|
||||
#define RCC_APB2RSTR_TIM21RST_Pos (2U)
|
||||
#define RCC_APB2RSTR_TIM21RST_Msk (0x1UL << RCC_APB2RSTR_TIM21RST_Pos) /*!< 0x00000004 */
|
||||
#define RCC_APB2RSTR_TIM21RST RCC_APB2RSTR_TIM21RST_Msk /*!< TIM21 reset */
|
||||
#define RCC_APB2RSTR_TIM22RST_Pos (5U)
|
||||
#define RCC_APB2RSTR_TIM22RST_Msk (0x1UL << RCC_APB2RSTR_TIM22RST_Pos) /*!< 0x00000020 */
|
||||
#define RCC_APB2RSTR_TIM22RST RCC_APB2RSTR_TIM22RST_Msk /*!< TIM22 reset */
|
||||
#define RCC_APB2RSTR_ADCRST_Pos (9U)
|
||||
#define RCC_APB2RSTR_ADCRST_Msk (0x1UL << RCC_APB2RSTR_ADCRST_Pos) /*!< 0x00000200 */
|
||||
#define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk /*!< ADC1 reset */
|
||||
@@ -3508,11 +3604,15 @@ typedef struct
|
||||
#define RCC_IOPENR_IOPCEN_Pos (2U)
|
||||
#define RCC_IOPENR_IOPCEN_Msk (0x1UL << RCC_IOPENR_IOPCEN_Pos) /*!< 0x00000004 */
|
||||
#define RCC_IOPENR_IOPCEN RCC_IOPENR_IOPCEN_Msk /*!< GPIO port C clock enable */
|
||||
#define RCC_IOPENR_IOPHEN_Pos (7U)
|
||||
#define RCC_IOPENR_IOPHEN_Msk (0x1UL << RCC_IOPENR_IOPHEN_Pos) /*!< 0x00000080 */
|
||||
#define RCC_IOPENR_IOPHEN RCC_IOPENR_IOPHEN_Msk /*!< GPIO port H clock enable */
|
||||
|
||||
/* Reference defines */
|
||||
#define RCC_IOPENR_GPIOAEN RCC_IOPENR_IOPAEN /*!< GPIO port A clock enable */
|
||||
#define RCC_IOPENR_GPIOBEN RCC_IOPENR_IOPBEN /*!< GPIO port B clock enable */
|
||||
#define RCC_IOPENR_GPIOCEN RCC_IOPENR_IOPCEN /*!< GPIO port C clock enable */
|
||||
#define RCC_IOPENR_GPIOHEN RCC_IOPENR_IOPHEN /*!< GPIO port H clock enable */
|
||||
|
||||
/***************** Bit definition for RCC_AHBENR register ******************/
|
||||
#define RCC_AHBENR_DMAEN_Pos (0U)
|
||||
@@ -3535,6 +3635,9 @@ typedef struct
|
||||
#define RCC_APB2ENR_TIM21EN_Pos (2U)
|
||||
#define RCC_APB2ENR_TIM21EN_Msk (0x1UL << RCC_APB2ENR_TIM21EN_Pos) /*!< 0x00000004 */
|
||||
#define RCC_APB2ENR_TIM21EN RCC_APB2ENR_TIM21EN_Msk /*!< TIM21 clock enable */
|
||||
#define RCC_APB2ENR_TIM22EN_Pos (5U)
|
||||
#define RCC_APB2ENR_TIM22EN_Msk (0x1UL << RCC_APB2ENR_TIM22EN_Pos) /*!< 0x00000020 */
|
||||
#define RCC_APB2ENR_TIM22EN RCC_APB2ENR_TIM22EN_Msk /*!< TIM22 clock enable */
|
||||
#define RCC_APB2ENR_FWEN_Pos (7U)
|
||||
#define RCC_APB2ENR_FWEN_Msk (0x1UL << RCC_APB2ENR_FWEN_Pos) /*!< 0x00000080 */
|
||||
#define RCC_APB2ENR_FWEN RCC_APB2ENR_FWEN_Msk /*!< MiFare Firewall clock enable */
|
||||
@@ -3587,11 +3690,15 @@ typedef struct
|
||||
#define RCC_IOPSMENR_IOPCSMEN_Pos (2U)
|
||||
#define RCC_IOPSMENR_IOPCSMEN_Msk (0x1UL << RCC_IOPSMENR_IOPCSMEN_Pos) /*!< 0x00000004 */
|
||||
#define RCC_IOPSMENR_IOPCSMEN RCC_IOPSMENR_IOPCSMEN_Msk /*!< GPIO port C clock enabled in sleep mode */
|
||||
#define RCC_IOPSMENR_IOPHSMEN_Pos (7U)
|
||||
#define RCC_IOPSMENR_IOPHSMEN_Msk (0x1UL << RCC_IOPSMENR_IOPHSMEN_Pos) /*!< 0x00000080 */
|
||||
#define RCC_IOPSMENR_IOPHSMEN RCC_IOPSMENR_IOPHSMEN_Msk /*!< GPIO port H clock enabled in sleep mode */
|
||||
|
||||
/* Reference defines */
|
||||
#define RCC_IOPSMENR_GPIOASMEN RCC_IOPSMENR_IOPASMEN /*!< GPIO port A clock enabled in sleep mode */
|
||||
#define RCC_IOPSMENR_GPIOBSMEN RCC_IOPSMENR_IOPBSMEN /*!< GPIO port B clock enabled in sleep mode */
|
||||
#define RCC_IOPSMENR_GPIOCSMEN RCC_IOPSMENR_IOPCSMEN /*!< GPIO port C clock enabled in sleep mode */
|
||||
#define RCC_IOPSMENR_GPIOHSMEN RCC_IOPSMENR_IOPHSMEN /*!< GPIO port H clock enabled in sleep mode */
|
||||
|
||||
/***************** Bit definition for RCC_AHBSMENR register ******************/
|
||||
#define RCC_AHBSMENR_DMASMEN_Pos (0U)
|
||||
@@ -3617,6 +3724,9 @@ typedef struct
|
||||
#define RCC_APB2SMENR_TIM21SMEN_Pos (2U)
|
||||
#define RCC_APB2SMENR_TIM21SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM21SMEN_Pos) /*!< 0x00000004 */
|
||||
#define RCC_APB2SMENR_TIM21SMEN RCC_APB2SMENR_TIM21SMEN_Msk /*!< TIM21 clock enabled in sleep mode */
|
||||
#define RCC_APB2SMENR_TIM22SMEN_Pos (5U)
|
||||
#define RCC_APB2SMENR_TIM22SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM22SMEN_Pos) /*!< 0x00000020 */
|
||||
#define RCC_APB2SMENR_TIM22SMEN RCC_APB2SMENR_TIM22SMEN_Msk /*!< TIM22 clock enabled in sleep mode */
|
||||
#define RCC_APB2SMENR_ADCSMEN_Pos (9U)
|
||||
#define RCC_APB2SMENR_ADCSMEN_Msk (0x1UL << RCC_APB2SMENR_ADCSMEN_Pos) /*!< 0x00000200 */
|
||||
#define RCC_APB2SMENR_ADCSMEN RCC_APB2SMENR_ADCSMEN_Msk /*!< ADC1 clock enabled in sleep mode */
|
||||
@@ -3742,6 +3852,9 @@ typedef struct
|
||||
#define RCC_CSR_RMVF_Pos (23U)
|
||||
#define RCC_CSR_RMVF_Msk (0x1UL << RCC_CSR_RMVF_Pos) /*!< 0x00800000 */
|
||||
#define RCC_CSR_RMVF RCC_CSR_RMVF_Msk /*!< Remove reset flag */
|
||||
#define RCC_CSR_FWRSTF_Pos (24U)
|
||||
#define RCC_CSR_FWRSTF_Msk (0x1UL << RCC_CSR_FWRSTF_Pos) /*!< 0x01000000 */
|
||||
#define RCC_CSR_FWRSTF RCC_CSR_FWRSTF_Msk /*!< Mifare Firewall reset flag */
|
||||
#define RCC_CSR_OBLRSTF_Pos (25U)
|
||||
#define RCC_CSR_OBLRSTF_Msk (0x1UL << RCC_CSR_OBLRSTF_Pos) /*!< 0x02000000 */
|
||||
#define RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF_Msk /*!< OBL reset flag */
|
||||
@@ -3776,6 +3889,7 @@ typedef struct
|
||||
/*
|
||||
* @brief Specific device feature definitions
|
||||
*/
|
||||
#define RTC_TAMPER1_SUPPORT
|
||||
#define RTC_TAMPER2_SUPPORT
|
||||
#define RTC_TAMPER3_SUPPORT
|
||||
#define RTC_WAKEUP_SUPPORT
|
||||
@@ -3945,6 +4059,9 @@ typedef struct
|
||||
#define RTC_ISR_TAMP2F_Pos (14U)
|
||||
#define RTC_ISR_TAMP2F_Msk (0x1UL << RTC_ISR_TAMP2F_Pos) /*!< 0x00004000 */
|
||||
#define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk /*!< */
|
||||
#define RTC_ISR_TAMP1F_Pos (13U)
|
||||
#define RTC_ISR_TAMP1F_Msk (0x1UL << RTC_ISR_TAMP1F_Pos) /*!< 0x00002000 */
|
||||
#define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk /*!< */
|
||||
#define RTC_ISR_TSOVF_Pos (12U)
|
||||
#define RTC_ISR_TSOVF_Msk (0x1UL << RTC_ISR_TSOVF_Pos) /*!< 0x00001000 */
|
||||
#define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk /*!< */
|
||||
@@ -4291,6 +4408,15 @@ typedef struct
|
||||
#define RTC_TAMPCR_TAMP2IE_Pos (19U)
|
||||
#define RTC_TAMPCR_TAMP2IE_Msk (0x1UL << RTC_TAMPCR_TAMP2IE_Pos) /*!< 0x00080000 */
|
||||
#define RTC_TAMPCR_TAMP2IE RTC_TAMPCR_TAMP2IE_Msk /*!< */
|
||||
#define RTC_TAMPCR_TAMP1MF_Pos (18U)
|
||||
#define RTC_TAMPCR_TAMP1MF_Msk (0x1UL << RTC_TAMPCR_TAMP1MF_Pos) /*!< 0x00040000 */
|
||||
#define RTC_TAMPCR_TAMP1MF RTC_TAMPCR_TAMP1MF_Msk /*!< */
|
||||
#define RTC_TAMPCR_TAMP1NOERASE_Pos (17U)
|
||||
#define RTC_TAMPCR_TAMP1NOERASE_Msk (0x1UL << RTC_TAMPCR_TAMP1NOERASE_Pos) /*!< 0x00020000 */
|
||||
#define RTC_TAMPCR_TAMP1NOERASE RTC_TAMPCR_TAMP1NOERASE_Msk /*!< */
|
||||
#define RTC_TAMPCR_TAMP1IE_Pos (16U)
|
||||
#define RTC_TAMPCR_TAMP1IE_Msk (0x1UL << RTC_TAMPCR_TAMP1IE_Pos) /*!< 0x00010000 */
|
||||
#define RTC_TAMPCR_TAMP1IE RTC_TAMPCR_TAMP1IE_Msk /*!< */
|
||||
#define RTC_TAMPCR_TAMPPUDIS_Pos (15U)
|
||||
#define RTC_TAMPCR_TAMPPUDIS_Msk (0x1UL << RTC_TAMPCR_TAMPPUDIS_Pos) /*!< 0x00008000 */
|
||||
#define RTC_TAMPCR_TAMPPUDIS RTC_TAMPCR_TAMPPUDIS_Msk /*!< */
|
||||
@@ -4328,6 +4454,12 @@ typedef struct
|
||||
#define RTC_TAMPCR_TAMPIE_Pos (2U)
|
||||
#define RTC_TAMPCR_TAMPIE_Msk (0x1UL << RTC_TAMPCR_TAMPIE_Pos) /*!< 0x00000004 */
|
||||
#define RTC_TAMPCR_TAMPIE RTC_TAMPCR_TAMPIE_Msk /*!< */
|
||||
#define RTC_TAMPCR_TAMP1TRG_Pos (1U)
|
||||
#define RTC_TAMPCR_TAMP1TRG_Msk (0x1UL << RTC_TAMPCR_TAMP1TRG_Pos) /*!< 0x00000002 */
|
||||
#define RTC_TAMPCR_TAMP1TRG RTC_TAMPCR_TAMP1TRG_Msk /*!< */
|
||||
#define RTC_TAMPCR_TAMP1E_Pos (0U)
|
||||
#define RTC_TAMPCR_TAMP1E_Msk (0x1UL << RTC_TAMPCR_TAMP1E_Pos) /*!< 0x00000001 */
|
||||
#define RTC_TAMPCR_TAMP1E RTC_TAMPCR_TAMP1E_Msk /*!< */
|
||||
|
||||
/******************** Bits definition for RTC_ALRMASSR register *************/
|
||||
#define RTC_ALRMASSR_MASKSS_Pos (24U)
|
||||
@@ -5238,6 +5370,17 @@ typedef struct
|
||||
#define TIM21_OR_TI2_RMP_Msk (0x1UL << TIM21_OR_TI2_RMP_Pos) /*!< 0x00000020 */
|
||||
#define TIM21_OR_TI2_RMP TIM21_OR_TI2_RMP_Msk /*!<TI2_RMP bit (TIM21 Input 2 remap) */
|
||||
|
||||
#define TIM22_OR_ETR_RMP_Pos (0U)
|
||||
#define TIM22_OR_ETR_RMP_Msk (0x3UL << TIM22_OR_ETR_RMP_Pos) /*!< 0x00000003 */
|
||||
#define TIM22_OR_ETR_RMP TIM22_OR_ETR_RMP_Msk /*!<ETR_RMP[1:0] bits (TIM22 ETR remap) */
|
||||
#define TIM22_OR_ETR_RMP_0 (0x1UL << TIM22_OR_ETR_RMP_Pos) /*!< 0x00000001 */
|
||||
#define TIM22_OR_ETR_RMP_1 (0x2UL << TIM22_OR_ETR_RMP_Pos) /*!< 0x00000002 */
|
||||
#define TIM22_OR_TI1_RMP_Pos (2U)
|
||||
#define TIM22_OR_TI1_RMP_Msk (0x3UL << TIM22_OR_TI1_RMP_Pos) /*!< 0x0000000C */
|
||||
#define TIM22_OR_TI1_RMP TIM22_OR_TI1_RMP_Msk /*!<TI1_RMP[2:0] bits (TIM22 Input 1 remap) */
|
||||
#define TIM22_OR_TI1_RMP_0 (0x1UL << TIM22_OR_TI1_RMP_Pos) /*!< 0x00000004 */
|
||||
#define TIM22_OR_TI1_RMP_1 (0x2UL << TIM22_OR_TI1_RMP_Pos) /*!< 0x00000008 */
|
||||
|
||||
|
||||
/******************************************************************************/
|
||||
/* */
|
||||
@@ -5248,7 +5391,7 @@ typedef struct
|
||||
/*
|
||||
* @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
|
||||
*/
|
||||
#define USART_TCBGT_SUPPORT /*!< Transmission completed before guard time interrupt support */
|
||||
/* Note: No specific macro feature on this device */
|
||||
|
||||
/****************** Bit definition for USART_CR1 register *******************/
|
||||
#define USART_CR1_UE_Pos (0U)
|
||||
@@ -5453,9 +5596,6 @@ typedef struct
|
||||
#define USART_CR3_UCESM_Pos (23U)
|
||||
#define USART_CR3_UCESM_Msk (0x1UL << USART_CR3_UCESM_Pos) /*!< 0x00800000 */
|
||||
#define USART_CR3_UCESM USART_CR3_UCESM_Msk /*!< Clock Enable in Stop mode */
|
||||
#define USART_CR3_TCBGTIE_Pos (24U)
|
||||
#define USART_CR3_TCBGTIE_Msk (0x1UL << USART_CR3_TCBGTIE_Pos) /*!< 0x01000000 */
|
||||
#define USART_CR3_TCBGTIE USART_CR3_TCBGTIE_Msk /*!< Transmission Complete Before Guard Time Interrupt Enable */
|
||||
|
||||
/****************** Bit definition for USART_BRR register *******************/
|
||||
#define USART_BRR_DIV_FRACTION_Pos (0U)
|
||||
@@ -5566,9 +5706,6 @@ typedef struct
|
||||
#define USART_ISR_REACK_Pos (22U)
|
||||
#define USART_ISR_REACK_Msk (0x1UL << USART_ISR_REACK_Pos) /*!< 0x00400000 */
|
||||
#define USART_ISR_REACK USART_ISR_REACK_Msk /*!< Receive Enable Acknowledge Flag */
|
||||
#define USART_ISR_TCBGT_Pos (25U)
|
||||
#define USART_ISR_TCBGT_Msk (0x1UL << USART_ISR_TCBGT_Pos) /*!< 0x02000000 */
|
||||
#define USART_ISR_TCBGT USART_ISR_TCBGT_Msk /*!< Transmission Complete Before Guard Time Completion Flag */
|
||||
|
||||
/******************* Bit definition for USART_ICR register ******************/
|
||||
#define USART_ICR_PECF_Pos (0U)
|
||||
@@ -5589,9 +5726,6 @@ typedef struct
|
||||
#define USART_ICR_TCCF_Pos (6U)
|
||||
#define USART_ICR_TCCF_Msk (0x1UL << USART_ICR_TCCF_Pos) /*!< 0x00000040 */
|
||||
#define USART_ICR_TCCF USART_ICR_TCCF_Msk /*!< Transmission Complete Clear Flag */
|
||||
#define USART_ICR_TCBGTCF_Pos (7U)
|
||||
#define USART_ICR_TCBGTCF_Msk (0x1UL << USART_ICR_TCBGTCF_Pos) /*!< 0x00000080 */
|
||||
#define USART_ICR_TCBGTCF USART_ICR_TCBGTCF_Msk /*!< Transmission Complete Before Guard Time Clear Flag */
|
||||
#define USART_ICR_LBDCF_Pos (8U)
|
||||
#define USART_ICR_LBDCF_Msk (0x1UL << USART_ICR_LBDCF_Pos) /*!< 0x00000100 */
|
||||
#define USART_ICR_LBDCF USART_ICR_LBDCF_Msk /*!< LIN Break Detection Clear Flag */
|
||||
@@ -5725,15 +5859,19 @@ typedef struct
|
||||
((INSTANCE) == DMA1_Channel2) || \
|
||||
((INSTANCE) == DMA1_Channel3) || \
|
||||
((INSTANCE) == DMA1_Channel4) || \
|
||||
((INSTANCE) == DMA1_Channel5))
|
||||
((INSTANCE) == DMA1_Channel5) || \
|
||||
((INSTANCE) == DMA1_Channel6) || \
|
||||
((INSTANCE) == DMA1_Channel7))
|
||||
|
||||
/******************************* GPIO Instances *******************************/
|
||||
#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
|
||||
((INSTANCE) == GPIOB) || \
|
||||
((INSTANCE) == GPIOC))
|
||||
((INSTANCE) == GPIOC) || \
|
||||
((INSTANCE) == GPIOH))
|
||||
|
||||
#define IS_GPIO_AF_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
|
||||
((INSTANCE) == GPIOB))
|
||||
((INSTANCE) == GPIOB) || \
|
||||
((INSTANCE) == GPIOC))
|
||||
|
||||
/******************************** I2C Instances *******************************/
|
||||
#define IS_I2C_ALL_INSTANCE(INSTANCE) ((INSTANCE) == I2C1)
|
||||
@@ -5761,15 +5899,18 @@ typedef struct
|
||||
|
||||
/****************** TIM Instances : All supported instances *******************/
|
||||
#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
|
||||
((INSTANCE) == TIM21))
|
||||
((INSTANCE) == TIM21) || \
|
||||
((INSTANCE) == TIM22))
|
||||
|
||||
/************* TIM Instances : at least 1 capture/compare channel *************/
|
||||
#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
|
||||
((INSTANCE) == TIM21))
|
||||
((INSTANCE) == TIM21) || \
|
||||
((INSTANCE) == TIM22))
|
||||
|
||||
/************ TIM Instances : at least 2 capture/compare channels *************/
|
||||
#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
|
||||
((INSTANCE) == TIM21))
|
||||
((INSTANCE) == TIM21) || \
|
||||
((INSTANCE) == TIM22))
|
||||
|
||||
/************ TIM Instances : at least 3 capture/compare channels *************/
|
||||
#define IS_TIM_CC3_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
|
||||
@@ -5795,12 +5936,17 @@ typedef struct
|
||||
((CHANNEL) == TIM_CHANNEL_4))) \
|
||||
|| \
|
||||
(((INSTANCE) == TIM21) && \
|
||||
(((CHANNEL) == TIM_CHANNEL_1) || \
|
||||
((CHANNEL) == TIM_CHANNEL_2))) \
|
||||
|| \
|
||||
(((INSTANCE) == TIM22) && \
|
||||
(((CHANNEL) == TIM_CHANNEL_1) || \
|
||||
((CHANNEL) == TIM_CHANNEL_2))))
|
||||
|
||||
/****************** TIM Instances : supporting clock division *****************/
|
||||
#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
|
||||
((INSTANCE) == TIM21))
|
||||
((INSTANCE) == TIM21) || \
|
||||
((INSTANCE) == TIM22))
|
||||
|
||||
/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
|
||||
#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
|
||||
@@ -5808,7 +5954,8 @@ typedef struct
|
||||
|
||||
/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
|
||||
#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
|
||||
((INSTANCE) == TIM21))
|
||||
((INSTANCE) == TIM21) || \
|
||||
((INSTANCE) == TIM22))
|
||||
|
||||
/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
|
||||
#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
|
||||
@@ -5816,31 +5963,38 @@ typedef struct
|
||||
|
||||
/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
|
||||
#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
|
||||
((INSTANCE) == TIM21))
|
||||
((INSTANCE) == TIM21) || \
|
||||
((INSTANCE) == TIM22))
|
||||
|
||||
/****************** TIM Instances : supporting counting mode selection ********/
|
||||
#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
|
||||
((INSTANCE) == TIM21))
|
||||
((INSTANCE) == TIM21) || \
|
||||
((INSTANCE) == TIM22))
|
||||
|
||||
/****************** TIM Instances : supporting encoder interface **************/
|
||||
#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
|
||||
((INSTANCE) == TIM21))
|
||||
((INSTANCE) == TIM21) || \
|
||||
((INSTANCE) == TIM22))
|
||||
|
||||
/***************** TIM Instances : external trigger input availabe ************/
|
||||
#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
|
||||
((INSTANCE) == TIM21))
|
||||
((INSTANCE) == TIM21) || \
|
||||
((INSTANCE) == TIM22))
|
||||
|
||||
/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
|
||||
#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
|
||||
((INSTANCE) == TIM21))
|
||||
((INSTANCE) == TIM21) || \
|
||||
((INSTANCE) == TIM22))
|
||||
|
||||
/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
|
||||
#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
|
||||
((INSTANCE) == TIM21))
|
||||
((INSTANCE) == TIM21) || \
|
||||
((INSTANCE) == TIM22))
|
||||
|
||||
/****************** TIM Instances : remapping capability **********************/
|
||||
#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
|
||||
((INSTANCE) == TIM21))
|
||||
((INSTANCE) == TIM21) || \
|
||||
((INSTANCE) == TIM22))
|
||||
|
||||
/******************* TIM Instances : output(s) OCXEC register *****************/
|
||||
#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
|
||||
@@ -5852,11 +6006,11 @@ typedef struct
|
||||
#define IS_UART_INSTANCE(INSTANCE) ((INSTANCE) == USART2)
|
||||
|
||||
/******************** USART Instances : Synchronous mode **********************/
|
||||
#define IS_USART_INSTANCE(INSTANCE) (1 == 0)
|
||||
#define IS_USART_INSTANCE(INSTANCE) ((INSTANCE) == USART2)
|
||||
|
||||
/****************** USART Instances : Auto Baud Rate detection ****************/
|
||||
|
||||
#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (1 == 0)
|
||||
#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) ((INSTANCE) == USART2)
|
||||
|
||||
/****************** UART Instances : Driver Enable *****************/
|
||||
#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART2) || \
|
||||
@@ -5867,10 +6021,11 @@ typedef struct
|
||||
((INSTANCE) == LPUART1))
|
||||
|
||||
/******************** UART Instances : LIN mode **********************/
|
||||
#define IS_UART_LIN_INSTANCE(INSTANCE) (1==0)
|
||||
#define IS_UART_LIN_INSTANCE(INSTANCE) ((INSTANCE) == USART2)
|
||||
|
||||
/******************** UART Instances : Wake-up from Stop mode **********************/
|
||||
#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1)
|
||||
#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART2) || \
|
||||
((INSTANCE) == LPUART1))
|
||||
|
||||
/****************** UART Instances : Hardware Flow control ********************/
|
||||
#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART2) || \
|
||||
@@ -5909,7 +6064,7 @@ typedef struct
|
||||
#define AES_LPUART1_IRQn LPUART1_IRQn
|
||||
#define AES_RNG_LPUART1_IRQn LPUART1_IRQn
|
||||
#define RCC_CRS_IRQn RCC_IRQn
|
||||
#define DMA1_Channel4_5_6_7_IRQn DMA1_Channel4_5_IRQn
|
||||
#define DMA1_Channel4_5_IRQn DMA1_Channel4_5_6_7_IRQn
|
||||
#define ADC1_IRQn ADC1_COMP_IRQn
|
||||
|
||||
/* Aliases for __IRQHandler */
|
||||
@@ -5917,7 +6072,7 @@ typedef struct
|
||||
#define AES_LPUART1_IRQHandler LPUART1_IRQHandler
|
||||
#define AES_RNG_LPUART1_IRQHandler LPUART1_IRQHandler
|
||||
#define RCC_CRS_IRQHandler RCC_IRQHandler
|
||||
#define DMA1_Channel4_5_6_7_IRQHandler DMA1_Channel4_5_IRQHandler
|
||||
#define DMA1_Channel4_5_IRQHandler DMA1_Channel4_5_6_7_IRQHandler
|
||||
#define ADC1_IRQHandler ADC1_COMP_IRQHandler
|
||||
|
||||
/**
|
||||
@@ -5932,7 +6087,7 @@ typedef struct
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* __STM32L011xx_H */
|
||||
#endif /* __STM32L031xx_H */
|
||||
|
||||
|
||||
|
||||
@@ -104,7 +104,7 @@
|
||||
*/
|
||||
#define __STM32L0xx_CMSIS_VERSION_MAIN (0x01) /*!< [31:24] main version */
|
||||
#define __STM32L0xx_CMSIS_VERSION_SUB1 (0x09) /*!< [23:16] sub1 version */
|
||||
#define __STM32L0xx_CMSIS_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */
|
||||
#define __STM32L0xx_CMSIS_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */
|
||||
#define __STM32L0xx_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
|
||||
#define __STM32L0xx_CMSIS_VERSION ((__STM32L0xx_CMSIS_VERSION_MAIN << 24)\
|
||||
|(__STM32L0xx_CMSIS_VERSION_SUB1 << 16)\
|
||||
@@ -208,6 +208,46 @@ typedef enum
|
||||
|
||||
#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
|
||||
|
||||
/* Use of interrupt control for register exclusive access */
|
||||
/* Atomic 32-bit register access macro to set one or several bits */
|
||||
#define ATOMIC_SET_BIT(REG, BIT) \
|
||||
do { \
|
||||
uint32_t primask; \
|
||||
primask = __get_PRIMASK(); \
|
||||
__set_PRIMASK(1); \
|
||||
SET_BIT((REG), (BIT)); \
|
||||
__set_PRIMASK(primask); \
|
||||
} while(0)
|
||||
|
||||
/* Atomic 32-bit register access macro to clear one or several bits */
|
||||
#define ATOMIC_CLEAR_BIT(REG, BIT) \
|
||||
do { \
|
||||
uint32_t primask; \
|
||||
primask = __get_PRIMASK(); \
|
||||
__set_PRIMASK(1); \
|
||||
CLEAR_BIT((REG), (BIT)); \
|
||||
__set_PRIMASK(primask); \
|
||||
} while(0)
|
||||
|
||||
/* Atomic 32-bit register access macro to clear and set one or several bits */
|
||||
#define ATOMIC_MODIFY_REG(REG, CLEARMSK, SETMASK) \
|
||||
do { \
|
||||
uint32_t primask; \
|
||||
primask = __get_PRIMASK(); \
|
||||
__set_PRIMASK(1); \
|
||||
MODIFY_REG((REG), (CLEARMSK), (SETMASK)); \
|
||||
__set_PRIMASK(primask); \
|
||||
} while(0)
|
||||
|
||||
/* Atomic 16-bit register access macro to set one or several bits */
|
||||
#define ATOMIC_SETH_BIT(REG, BIT) ATOMIC_SET_BIT(REG, BIT) \
|
||||
|
||||
/* Atomic 16-bit register access macro to clear one or several bits */
|
||||
#define ATOMIC_CLEARH_BIT(REG, BIT) ATOMIC_CLEAR_BIT(REG, BIT) \
|
||||
|
||||
/* Atomic 16-bit register access macro to clear and set one or several bits */
|
||||
#define ATOMIC_MODIFYH_REG(REG, CLEARMSK, SETMASK) ATOMIC_MODIFY_REG(REG, CLEARMSK, SETMASK) \
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
@@ -10,7 +10,7 @@
|
||||
[..]
|
||||
The LL CORTEX driver contains a set of generic APIs that can be
|
||||
used by user:
|
||||
(+) SYSTICK configuration used by @ref LL_mDelay and @ref LL_Init1msTick
|
||||
(+) SYSTICK configuration used by LL_mDelay and LL_Init1msTick
|
||||
functions
|
||||
(+) Low power mode configuration (SCB register of Cortex-MCU)
|
||||
(+) MPU API to configure and enable regions
|
||||
|
||||
@@ -69,38 +69,46 @@ typedef struct
|
||||
uint32_t PeripheralMode; /*!< Specifies the peripheral mode.
|
||||
This parameter can be a value of @ref I2C_LL_EC_PERIPHERAL_MODE.
|
||||
|
||||
This feature can be modified afterwards using unitary function @ref LL_I2C_SetMode(). */
|
||||
This feature can be modified afterwards using unitary function
|
||||
@ref LL_I2C_SetMode(). */
|
||||
|
||||
uint32_t Timing; /*!< Specifies the SDA setup, hold time and the SCL high, low period values.
|
||||
This parameter must be set by referring to the STM32CubeMX Tool and
|
||||
the helper macro @ref __LL_I2C_CONVERT_TIMINGS().
|
||||
|
||||
This feature can be modified afterwards using unitary function @ref LL_I2C_SetTiming(). */
|
||||
This feature can be modified afterwards using unitary function
|
||||
@ref LL_I2C_SetTiming(). */
|
||||
|
||||
uint32_t AnalogFilter; /*!< Enables or disables analog noise filter.
|
||||
This parameter can be a value of @ref I2C_LL_EC_ANALOGFILTER_SELECTION.
|
||||
|
||||
This feature can be modified afterwards using unitary functions @ref LL_I2C_EnableAnalogFilter() or LL_I2C_DisableAnalogFilter(). */
|
||||
This feature can be modified afterwards using unitary functions
|
||||
@ref LL_I2C_EnableAnalogFilter() or LL_I2C_DisableAnalogFilter(). */
|
||||
|
||||
uint32_t DigitalFilter; /*!< Configures the digital noise filter.
|
||||
This parameter can be a number between Min_Data = 0x00 and Max_Data = 0x0F.
|
||||
|
||||
This feature can be modified afterwards using unitary function @ref LL_I2C_SetDigitalFilter(). */
|
||||
This feature can be modified afterwards using unitary function
|
||||
@ref LL_I2C_SetDigitalFilter(). */
|
||||
|
||||
uint32_t OwnAddress1; /*!< Specifies the device own address 1.
|
||||
This parameter must be a value between Min_Data = 0x00 and Max_Data = 0x3FF.
|
||||
|
||||
This feature can be modified afterwards using unitary function @ref LL_I2C_SetOwnAddress1(). */
|
||||
This feature can be modified afterwards using unitary function
|
||||
@ref LL_I2C_SetOwnAddress1(). */
|
||||
|
||||
uint32_t TypeAcknowledge; /*!< Specifies the ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte.
|
||||
uint32_t TypeAcknowledge; /*!< Specifies the ACKnowledge or Non ACKnowledge condition after the address receive
|
||||
match code or next received byte.
|
||||
This parameter can be a value of @ref I2C_LL_EC_I2C_ACKNOWLEDGE.
|
||||
|
||||
This feature can be modified afterwards using unitary function @ref LL_I2C_AcknowledgeNextData(). */
|
||||
This feature can be modified afterwards using unitary function
|
||||
@ref LL_I2C_AcknowledgeNextData(). */
|
||||
|
||||
uint32_t OwnAddrSize; /*!< Specifies the device own address 1 size (7-bit or 10-bit).
|
||||
This parameter can be a value of @ref I2C_LL_EC_OWNADDRESS1.
|
||||
|
||||
This feature can be modified afterwards using unitary function @ref LL_I2C_SetOwnAddress1(). */
|
||||
This feature can be modified afterwards using unitary function
|
||||
@ref LL_I2C_SetOwnAddress1(). */
|
||||
} LL_I2C_InitTypeDef;
|
||||
/**
|
||||
* @}
|
||||
@@ -170,10 +178,11 @@ typedef struct
|
||||
/** @defgroup I2C_LL_EC_PERIPHERAL_MODE Peripheral Mode
|
||||
* @{
|
||||
*/
|
||||
#define LL_I2C_MODE_I2C 0x00000000U /*!< I2C Master or Slave mode */
|
||||
#define LL_I2C_MODE_SMBUS_HOST I2C_CR1_SMBHEN /*!< SMBus Host address acknowledge */
|
||||
#define LL_I2C_MODE_SMBUS_DEVICE 0x00000000U /*!< SMBus Device default mode (Default address not acknowledge) */
|
||||
#define LL_I2C_MODE_SMBUS_DEVICE_ARP I2C_CR1_SMBDEN /*!< SMBus Device Default address acknowledge */
|
||||
#define LL_I2C_MODE_I2C 0x00000000U /*!< I2C Master or Slave mode */
|
||||
#define LL_I2C_MODE_SMBUS_HOST I2C_CR1_SMBHEN /*!< SMBus Host address acknowledge */
|
||||
#define LL_I2C_MODE_SMBUS_DEVICE 0x00000000U /*!< SMBus Device default mode
|
||||
(Default address not acknowledge) */
|
||||
#define LL_I2C_MODE_SMBUS_DEVICE_ARP I2C_CR1_SMBDEN /*!< SMBus Device Default address acknowledge */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@@ -208,14 +217,15 @@ typedef struct
|
||||
/** @defgroup I2C_LL_EC_OWNADDRESS2 Own Address 2 Masks
|
||||
* @{
|
||||
*/
|
||||
#define LL_I2C_OWNADDRESS2_NOMASK I2C_OAR2_OA2NOMASK /*!< Own Address2 No mask. */
|
||||
#define LL_I2C_OWNADDRESS2_MASK01 I2C_OAR2_OA2MASK01 /*!< Only Address2 bits[7:2] are compared. */
|
||||
#define LL_I2C_OWNADDRESS2_MASK02 I2C_OAR2_OA2MASK02 /*!< Only Address2 bits[7:3] are compared. */
|
||||
#define LL_I2C_OWNADDRESS2_MASK03 I2C_OAR2_OA2MASK03 /*!< Only Address2 bits[7:4] are compared. */
|
||||
#define LL_I2C_OWNADDRESS2_MASK04 I2C_OAR2_OA2MASK04 /*!< Only Address2 bits[7:5] are compared. */
|
||||
#define LL_I2C_OWNADDRESS2_MASK05 I2C_OAR2_OA2MASK05 /*!< Only Address2 bits[7:6] are compared. */
|
||||
#define LL_I2C_OWNADDRESS2_MASK06 I2C_OAR2_OA2MASK06 /*!< Only Address2 bits[7] are compared. */
|
||||
#define LL_I2C_OWNADDRESS2_MASK07 I2C_OAR2_OA2MASK07 /*!< No comparison is done. All Address2 are acknowledged.*/
|
||||
#define LL_I2C_OWNADDRESS2_NOMASK I2C_OAR2_OA2NOMASK /*!< Own Address2 No mask. */
|
||||
#define LL_I2C_OWNADDRESS2_MASK01 I2C_OAR2_OA2MASK01 /*!< Only Address2 bits[7:2] are compared. */
|
||||
#define LL_I2C_OWNADDRESS2_MASK02 I2C_OAR2_OA2MASK02 /*!< Only Address2 bits[7:3] are compared. */
|
||||
#define LL_I2C_OWNADDRESS2_MASK03 I2C_OAR2_OA2MASK03 /*!< Only Address2 bits[7:4] are compared. */
|
||||
#define LL_I2C_OWNADDRESS2_MASK04 I2C_OAR2_OA2MASK04 /*!< Only Address2 bits[7:5] are compared. */
|
||||
#define LL_I2C_OWNADDRESS2_MASK05 I2C_OAR2_OA2MASK05 /*!< Only Address2 bits[7:6] are compared. */
|
||||
#define LL_I2C_OWNADDRESS2_MASK06 I2C_OAR2_OA2MASK06 /*!< Only Address2 bits[7] are compared. */
|
||||
#define LL_I2C_OWNADDRESS2_MASK07 I2C_OAR2_OA2MASK07 /*!< No comparison is done.
|
||||
All Address2 are acknowledged. */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@@ -250,14 +260,21 @@ typedef struct
|
||||
/** @defgroup I2C_LL_EC_MODE Transfer End Mode
|
||||
* @{
|
||||
*/
|
||||
#define LL_I2C_MODE_RELOAD I2C_CR2_RELOAD /*!< Enable I2C Reload mode. */
|
||||
#define LL_I2C_MODE_AUTOEND I2C_CR2_AUTOEND /*!< Enable I2C Automatic end mode with no HW PEC comparison. */
|
||||
#define LL_I2C_MODE_SOFTEND 0x00000000U /*!< Enable I2C Software end mode with no HW PEC comparison. */
|
||||
#define LL_I2C_MODE_SMBUS_RELOAD LL_I2C_MODE_RELOAD /*!< Enable SMBUS Automatic end mode with HW PEC comparison. */
|
||||
#define LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC LL_I2C_MODE_AUTOEND /*!< Enable SMBUS Automatic end mode with HW PEC comparison. */
|
||||
#define LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC LL_I2C_MODE_SOFTEND /*!< Enable SMBUS Software end mode with HW PEC comparison. */
|
||||
#define LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC (uint32_t)(LL_I2C_MODE_AUTOEND | I2C_CR2_PECBYTE) /*!< Enable SMBUS Automatic end mode with HW PEC comparison. */
|
||||
#define LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC (uint32_t)(LL_I2C_MODE_SOFTEND | I2C_CR2_PECBYTE) /*!< Enable SMBUS Software end mode with HW PEC comparison. */
|
||||
#define LL_I2C_MODE_RELOAD I2C_CR2_RELOAD /*!< Enable I2C Reload mode. */
|
||||
#define LL_I2C_MODE_AUTOEND I2C_CR2_AUTOEND /*!< Enable I2C Automatic end mode
|
||||
with no HW PEC comparison. */
|
||||
#define LL_I2C_MODE_SOFTEND 0x00000000U /*!< Enable I2C Software end mode
|
||||
with no HW PEC comparison. */
|
||||
#define LL_I2C_MODE_SMBUS_RELOAD LL_I2C_MODE_RELOAD /*!< Enable SMBUS Automatic end mode
|
||||
with HW PEC comparison. */
|
||||
#define LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC LL_I2C_MODE_AUTOEND /*!< Enable SMBUS Automatic end mode
|
||||
with HW PEC comparison. */
|
||||
#define LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC LL_I2C_MODE_SOFTEND /*!< Enable SMBUS Software end mode
|
||||
with HW PEC comparison. */
|
||||
#define LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC (uint32_t)(LL_I2C_MODE_AUTOEND | I2C_CR2_PECBYTE)
|
||||
/*!< Enable SMBUS Automatic end mode with HW PEC comparison. */
|
||||
#define LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC (uint32_t)(LL_I2C_MODE_SOFTEND | I2C_CR2_PECBYTE)
|
||||
/*!< Enable SMBUS Software end mode with HW PEC comparison. */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@@ -265,14 +282,23 @@ typedef struct
|
||||
/** @defgroup I2C_LL_EC_GENERATE Start And Stop Generation
|
||||
* @{
|
||||
*/
|
||||
#define LL_I2C_GENERATE_NOSTARTSTOP 0x00000000U /*!< Don't Generate Stop and Start condition. */
|
||||
#define LL_I2C_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP) /*!< Generate Stop condition (Size should be set to 0). */
|
||||
#define LL_I2C_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN) /*!< Generate Start for read request. */
|
||||
#define LL_I2C_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START) /*!< Generate Start for write request. */
|
||||
#define LL_I2C_GENERATE_RESTART_7BIT_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN) /*!< Generate Restart for read request, slave 7Bit address. */
|
||||
#define LL_I2C_GENERATE_RESTART_7BIT_WRITE (uint32_t)(0x80000000U | I2C_CR2_START) /*!< Generate Restart for write request, slave 7Bit address. */
|
||||
#define LL_I2C_GENERATE_RESTART_10BIT_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN | I2C_CR2_HEAD10R) /*!< Generate Restart for read request, slave 10Bit address. */
|
||||
#define LL_I2C_GENERATE_RESTART_10BIT_WRITE (uint32_t)(0x80000000U | I2C_CR2_START) /*!< Generate Restart for write request, slave 10Bit address.*/
|
||||
#define LL_I2C_GENERATE_NOSTARTSTOP 0x00000000U
|
||||
/*!< Don't Generate Stop and Start condition. */
|
||||
#define LL_I2C_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP)
|
||||
/*!< Generate Stop condition (Size should be set to 0). */
|
||||
#define LL_I2C_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
|
||||
/*!< Generate Start for read request. */
|
||||
#define LL_I2C_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)
|
||||
/*!< Generate Start for write request. */
|
||||
#define LL_I2C_GENERATE_RESTART_7BIT_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
|
||||
/*!< Generate Restart for read request, slave 7Bit address. */
|
||||
#define LL_I2C_GENERATE_RESTART_7BIT_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)
|
||||
/*!< Generate Restart for write request, slave 7Bit address. */
|
||||
#define LL_I2C_GENERATE_RESTART_10BIT_READ (uint32_t)(0x80000000U | I2C_CR2_START | \
|
||||
I2C_CR2_RD_WRN | I2C_CR2_HEAD10R)
|
||||
/*!< Generate Restart for read request, slave 10Bit address. */
|
||||
#define LL_I2C_GENERATE_RESTART_10BIT_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)
|
||||
/*!< Generate Restart for write request, slave 10Bit address.*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@@ -280,8 +306,10 @@ typedef struct
|
||||
/** @defgroup I2C_LL_EC_DIRECTION Read Write Direction
|
||||
* @{
|
||||
*/
|
||||
#define LL_I2C_DIRECTION_WRITE 0x00000000U /*!< Write transfer request by master, slave enters receiver mode. */
|
||||
#define LL_I2C_DIRECTION_READ I2C_ISR_DIR /*!< Read transfer request by master, slave enters transmitter mode.*/
|
||||
#define LL_I2C_DIRECTION_WRITE 0x00000000U /*!< Write transfer request by master,
|
||||
slave enters receiver mode. */
|
||||
#define LL_I2C_DIRECTION_READ I2C_ISR_DIR /*!< Read transfer request by master,
|
||||
slave enters transmitter mode.*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@@ -289,8 +317,10 @@ typedef struct
|
||||
/** @defgroup I2C_LL_EC_DMA_REG_DATA DMA Register Data
|
||||
* @{
|
||||
*/
|
||||
#define LL_I2C_DMA_REG_DATA_TRANSMIT 0x00000000U /*!< Get address of data register used for transmission */
|
||||
#define LL_I2C_DMA_REG_DATA_RECEIVE 0x00000001U /*!< Get address of data register used for reception */
|
||||
#define LL_I2C_DMA_REG_DATA_TRANSMIT 0x00000000U /*!< Get address of data register used for
|
||||
transmission */
|
||||
#define LL_I2C_DMA_REG_DATA_RECEIVE 0x00000001U /*!< Get address of data register used for
|
||||
reception */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@@ -298,8 +328,10 @@ typedef struct
|
||||
/** @defgroup I2C_LL_EC_SMBUS_TIMEOUTA_MODE SMBus TimeoutA Mode SCL SDA Timeout
|
||||
* @{
|
||||
*/
|
||||
#define LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW 0x00000000U /*!< TimeoutA is used to detect SCL low level timeout. */
|
||||
#define LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH I2C_TIMEOUTR_TIDLE /*!< TimeoutA is used to detect both SCL and SDA high level timeout.*/
|
||||
#define LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW 0x00000000U /*!< TimeoutA is used to detect
|
||||
SCL low level timeout. */
|
||||
#define LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH I2C_TIMEOUTR_TIDLE /*!< TimeoutA is used to detect
|
||||
both SCL and SDA high level timeout.*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@@ -307,9 +339,12 @@ typedef struct
|
||||
/** @defgroup I2C_LL_EC_SMBUS_TIMEOUT_SELECTION SMBus Timeout Selection
|
||||
* @{
|
||||
*/
|
||||
#define LL_I2C_SMBUS_TIMEOUTA I2C_TIMEOUTR_TIMOUTEN /*!< TimeoutA enable bit */
|
||||
#define LL_I2C_SMBUS_TIMEOUTB I2C_TIMEOUTR_TEXTEN /*!< TimeoutB (extended clock) enable bit */
|
||||
#define LL_I2C_SMBUS_ALL_TIMEOUT (uint32_t)(I2C_TIMEOUTR_TIMOUTEN | I2C_TIMEOUTR_TEXTEN) /*!< TimeoutA and TimeoutB (extended clock) enable bits */
|
||||
#define LL_I2C_SMBUS_TIMEOUTA I2C_TIMEOUTR_TIMOUTEN /*!< TimeoutA enable bit */
|
||||
#define LL_I2C_SMBUS_TIMEOUTB I2C_TIMEOUTR_TEXTEN /*!< TimeoutB (extended clock)
|
||||
enable bit */
|
||||
#define LL_I2C_SMBUS_ALL_TIMEOUT (uint32_t)(I2C_TIMEOUTR_TIMOUTEN | \
|
||||
I2C_TIMEOUTR_TEXTEN) /*!< TimeoutA and TimeoutB
|
||||
(extended clock) enable bits */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@@ -353,18 +388,22 @@ typedef struct
|
||||
/**
|
||||
* @brief Configure the SDA setup, hold time and the SCL high, low period.
|
||||
* @param __PRESCALER__ This parameter must be a value between Min_Data=0 and Max_Data=0xF.
|
||||
* @param __DATA_SETUP_TIME__ This parameter must be a value between Min_Data=0 and Max_Data=0xF. (tscldel = (SCLDEL+1)xtpresc)
|
||||
* @param __DATA_HOLD_TIME__ This parameter must be a value between Min_Data=0 and Max_Data=0xF. (tsdadel = SDADELxtpresc)
|
||||
* @param __CLOCK_HIGH_PERIOD__ This parameter must be a value between Min_Data=0 and Max_Data=0xFF. (tsclh = (SCLH+1)xtpresc)
|
||||
* @param __CLOCK_LOW_PERIOD__ This parameter must be a value between Min_Data=0 and Max_Data=0xFF. (tscll = (SCLL+1)xtpresc)
|
||||
* @param __SETUP_TIME__ This parameter must be a value between Min_Data=0 and Max_Data=0xF.
|
||||
(tscldel = (SCLDEL+1)xtpresc)
|
||||
* @param __HOLD_TIME__ This parameter must be a value between Min_Data=0 and Max_Data=0xF.
|
||||
(tsdadel = SDADELxtpresc)
|
||||
* @param __SCLH_PERIOD__ This parameter must be a value between Min_Data=0 and Max_Data=0xFF.
|
||||
(tsclh = (SCLH+1)xtpresc)
|
||||
* @param __SCLL_PERIOD__ This parameter must be a value between Min_Data=0 and Max_Data=0xFF.
|
||||
(tscll = (SCLL+1)xtpresc)
|
||||
* @retval Value between Min_Data=0 and Max_Data=0xFFFFFFFF
|
||||
*/
|
||||
#define __LL_I2C_CONVERT_TIMINGS(__PRESCALER__, __DATA_SETUP_TIME__, __DATA_HOLD_TIME__, __CLOCK_HIGH_PERIOD__, __CLOCK_LOW_PERIOD__) \
|
||||
((((uint32_t)(__PRESCALER__) << I2C_TIMINGR_PRESC_Pos) & I2C_TIMINGR_PRESC) | \
|
||||
(((uint32_t)(__DATA_SETUP_TIME__) << I2C_TIMINGR_SCLDEL_Pos) & I2C_TIMINGR_SCLDEL) | \
|
||||
(((uint32_t)(__DATA_HOLD_TIME__) << I2C_TIMINGR_SDADEL_Pos) & I2C_TIMINGR_SDADEL) | \
|
||||
(((uint32_t)(__CLOCK_HIGH_PERIOD__) << I2C_TIMINGR_SCLH_Pos) & I2C_TIMINGR_SCLH) | \
|
||||
(((uint32_t)(__CLOCK_LOW_PERIOD__) << I2C_TIMINGR_SCLL_Pos) & I2C_TIMINGR_SCLL))
|
||||
#define __LL_I2C_CONVERT_TIMINGS(__PRESCALER__, __SETUP_TIME__, __HOLD_TIME__, __SCLH_PERIOD__, __SCLL_PERIOD__) \
|
||||
((((uint32_t)(__PRESCALER__) << I2C_TIMINGR_PRESC_Pos) & I2C_TIMINGR_PRESC) | \
|
||||
(((uint32_t)(__SETUP_TIME__) << I2C_TIMINGR_SCLDEL_Pos) & I2C_TIMINGR_SCLDEL) | \
|
||||
(((uint32_t)(__HOLD_TIME__) << I2C_TIMINGR_SDADEL_Pos) & I2C_TIMINGR_SDADEL) | \
|
||||
(((uint32_t)(__SCLH_PERIOD__) << I2C_TIMINGR_SCLH_Pos) & I2C_TIMINGR_SCLH) | \
|
||||
(((uint32_t)(__SCLL_PERIOD__) << I2C_TIMINGR_SCLL_Pos) & I2C_TIMINGR_SCLL))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@@ -428,7 +467,8 @@ __STATIC_INLINE uint32_t LL_I2C_IsEnabled(I2C_TypeDef *I2Cx)
|
||||
* @param AnalogFilter This parameter can be one of the following values:
|
||||
* @arg @ref LL_I2C_ANALOGFILTER_ENABLE
|
||||
* @arg @ref LL_I2C_ANALOGFILTER_DISABLE
|
||||
* @param DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled) and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk).
|
||||
* @param DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled)
|
||||
and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk).
|
||||
* This parameter is used to configure the digital noise filter on SDA and SCL input.
|
||||
* The digital filter will filter spikes with a length of up to DNF[3:0]*ti2cclk.
|
||||
* @retval None
|
||||
@@ -444,7 +484,8 @@ __STATIC_INLINE void LL_I2C_ConfigFilters(I2C_TypeDef *I2Cx, uint32_t AnalogFilt
|
||||
* This filter can only be programmed when the I2C is disabled (PE = 0).
|
||||
* @rmtoll CR1 DNF LL_I2C_SetDigitalFilter
|
||||
* @param I2Cx I2C Instance.
|
||||
* @param DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled) and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk).
|
||||
* @param DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled)
|
||||
and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk).
|
||||
* This parameter is used to configure the digital noise filter on SDA and SCL input.
|
||||
* The digital filter will filter spikes with a length of up to DNF[3:0]*ti2cclk.
|
||||
* @retval None
|
||||
@@ -664,7 +705,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsEnabledSlaveByteControl(I2C_TypeDef *I2Cx)
|
||||
|
||||
/**
|
||||
* @brief Enable Wakeup from STOP.
|
||||
* @note Macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
|
||||
* @note The macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
|
||||
* WakeUpFromStop feature is supported by the I2Cx Instance.
|
||||
* @note This bit can only be programmed when Digital Filter is disabled.
|
||||
* @rmtoll CR1 WUPEN LL_I2C_EnableWakeUpFromStop
|
||||
@@ -678,7 +719,7 @@ __STATIC_INLINE void LL_I2C_EnableWakeUpFromStop(I2C_TypeDef *I2Cx)
|
||||
|
||||
/**
|
||||
* @brief Disable Wakeup from STOP.
|
||||
* @note Macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
|
||||
* @note The macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
|
||||
* WakeUpFromStop feature is supported by the I2Cx Instance.
|
||||
* @rmtoll CR1 WUPEN LL_I2C_DisableWakeUpFromStop
|
||||
* @param I2Cx I2C Instance.
|
||||
@@ -691,7 +732,7 @@ __STATIC_INLINE void LL_I2C_DisableWakeUpFromStop(I2C_TypeDef *I2Cx)
|
||||
|
||||
/**
|
||||
* @brief Check if Wakeup from STOP is enabled or disabled.
|
||||
* @note Macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
|
||||
* @note The macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
|
||||
* WakeUpFromStop feature is supported by the I2Cx Instance.
|
||||
* @rmtoll CR1 WUPEN LL_I2C_IsEnabledWakeUpFromStop
|
||||
* @param I2Cx I2C Instance.
|
||||
@@ -941,7 +982,7 @@ __STATIC_INLINE uint32_t LL_I2C_GetDataSetupTime(I2C_TypeDef *I2Cx)
|
||||
|
||||
/**
|
||||
* @brief Configure peripheral mode.
|
||||
* @note Macro IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
|
||||
* @note The macro IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
|
||||
* SMBus feature is supported by the I2Cx Instance.
|
||||
* @rmtoll CR1 SMBHEN LL_I2C_SetMode\n
|
||||
* CR1 SMBDEN LL_I2C_SetMode
|
||||
@@ -960,7 +1001,7 @@ __STATIC_INLINE void LL_I2C_SetMode(I2C_TypeDef *I2Cx, uint32_t PeripheralMode)
|
||||
|
||||
/**
|
||||
* @brief Get peripheral mode.
|
||||
* @note Macro IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
|
||||
* @note The macro IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
|
||||
* SMBus feature is supported by the I2Cx Instance.
|
||||
* @rmtoll CR1 SMBHEN LL_I2C_GetMode\n
|
||||
* CR1 SMBDEN LL_I2C_GetMode
|
||||
@@ -978,7 +1019,7 @@ __STATIC_INLINE uint32_t LL_I2C_GetMode(I2C_TypeDef *I2Cx)
|
||||
|
||||
/**
|
||||
* @brief Enable SMBus alert (Host or Device mode)
|
||||
* @note Macro IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
|
||||
* @note The macro IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
|
||||
* SMBus feature is supported by the I2Cx Instance.
|
||||
* @note SMBus Device mode:
|
||||
* - SMBus Alert pin is drived low and
|
||||
@@ -996,7 +1037,7 @@ __STATIC_INLINE void LL_I2C_EnableSMBusAlert(I2C_TypeDef *I2Cx)
|
||||
|
||||
/**
|
||||
* @brief Disable SMBus alert (Host or Device mode)
|
||||
* @note Macro IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
|
||||
* @note The macro IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
|
||||
* SMBus feature is supported by the I2Cx Instance.
|
||||
* @note SMBus Device mode:
|
||||
* - SMBus Alert pin is not drived (can be used as a standard GPIO) and
|
||||
@@ -1014,7 +1055,7 @@ __STATIC_INLINE void LL_I2C_DisableSMBusAlert(I2C_TypeDef *I2Cx)
|
||||
|
||||
/**
|
||||
* @brief Check if SMBus alert (Host or Device mode) is enabled or disabled.
|
||||
* @note Macro IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
|
||||
* @note The macro IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
|
||||
* SMBus feature is supported by the I2Cx Instance.
|
||||
* @rmtoll CR1 ALERTEN LL_I2C_IsEnabledSMBusAlert
|
||||
* @param I2Cx I2C Instance.
|
||||
@@ -1027,7 +1068,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusAlert(I2C_TypeDef *I2Cx)
|
||||
|
||||
/**
|
||||
* @brief Enable SMBus Packet Error Calculation (PEC).
|
||||
* @note Macro IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
|
||||
* @note The macro IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
|
||||
* SMBus feature is supported by the I2Cx Instance.
|
||||
* @rmtoll CR1 PECEN LL_I2C_EnableSMBusPEC
|
||||
* @param I2Cx I2C Instance.
|
||||
@@ -1040,7 +1081,7 @@ __STATIC_INLINE void LL_I2C_EnableSMBusPEC(I2C_TypeDef *I2Cx)
|
||||
|
||||
/**
|
||||
* @brief Disable SMBus Packet Error Calculation (PEC).
|
||||
* @note Macro IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
|
||||
* @note The macro IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
|
||||
* SMBus feature is supported by the I2Cx Instance.
|
||||
* @rmtoll CR1 PECEN LL_I2C_DisableSMBusPEC
|
||||
* @param I2Cx I2C Instance.
|
||||
@@ -1053,7 +1094,7 @@ __STATIC_INLINE void LL_I2C_DisableSMBusPEC(I2C_TypeDef *I2Cx)
|
||||
|
||||
/**
|
||||
* @brief Check if SMBus Packet Error Calculation (PEC) is enabled or disabled.
|
||||
* @note Macro IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
|
||||
* @note The macro IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
|
||||
* SMBus feature is supported by the I2Cx Instance.
|
||||
* @rmtoll CR1 PECEN LL_I2C_IsEnabledSMBusPEC
|
||||
* @param I2Cx I2C Instance.
|
||||
@@ -1066,7 +1107,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPEC(I2C_TypeDef *I2Cx)
|
||||
|
||||
/**
|
||||
* @brief Configure the SMBus Clock Timeout.
|
||||
* @note Macro IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
|
||||
* @note The macro IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
|
||||
* SMBus feature is supported by the I2Cx Instance.
|
||||
* @note This configuration can only be programmed when associated Timeout is disabled (TimeoutA and/orTimeoutB).
|
||||
* @rmtoll TIMEOUTR TIMEOUTA LL_I2C_ConfigSMBusTimeout\n
|
||||
@@ -1089,7 +1130,7 @@ __STATIC_INLINE void LL_I2C_ConfigSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t Timeo
|
||||
|
||||
/**
|
||||
* @brief Configure the SMBus Clock TimeoutA (SCL low timeout or SCL and SDA high timeout depends on TimeoutA mode).
|
||||
* @note Macro IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
|
||||
* @note The macro IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
|
||||
* SMBus feature is supported by the I2Cx Instance.
|
||||
* @note These bits can only be programmed when TimeoutA is disabled.
|
||||
* @rmtoll TIMEOUTR TIMEOUTA LL_I2C_SetSMBusTimeoutA
|
||||
@@ -1104,7 +1145,7 @@ __STATIC_INLINE void LL_I2C_SetSMBusTimeoutA(I2C_TypeDef *I2Cx, uint32_t Timeout
|
||||
|
||||
/**
|
||||
* @brief Get the SMBus Clock TimeoutA setting.
|
||||
* @note Macro IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
|
||||
* @note The macro IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
|
||||
* SMBus feature is supported by the I2Cx Instance.
|
||||
* @rmtoll TIMEOUTR TIMEOUTA LL_I2C_GetSMBusTimeoutA
|
||||
* @param I2Cx I2C Instance.
|
||||
@@ -1117,7 +1158,7 @@ __STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutA(I2C_TypeDef *I2Cx)
|
||||
|
||||
/**
|
||||
* @brief Set the SMBus Clock TimeoutA mode.
|
||||
* @note Macro IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
|
||||
* @note The macro IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
|
||||
* SMBus feature is supported by the I2Cx Instance.
|
||||
* @note This bit can only be programmed when TimeoutA is disabled.
|
||||
* @rmtoll TIMEOUTR TIDLE LL_I2C_SetSMBusTimeoutAMode
|
||||
@@ -1134,7 +1175,7 @@ __STATIC_INLINE void LL_I2C_SetSMBusTimeoutAMode(I2C_TypeDef *I2Cx, uint32_t Tim
|
||||
|
||||
/**
|
||||
* @brief Get the SMBus Clock TimeoutA mode.
|
||||
* @note Macro IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
|
||||
* @note The macro IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
|
||||
* SMBus feature is supported by the I2Cx Instance.
|
||||
* @rmtoll TIMEOUTR TIDLE LL_I2C_GetSMBusTimeoutAMode
|
||||
* @param I2Cx I2C Instance.
|
||||
@@ -1149,7 +1190,7 @@ __STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutAMode(I2C_TypeDef *I2Cx)
|
||||
|
||||
/**
|
||||
* @brief Configure the SMBus Extended Cumulative Clock TimeoutB (Master or Slave mode).
|
||||
* @note Macro IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
|
||||
* @note The macro IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
|
||||
* SMBus feature is supported by the I2Cx Instance.
|
||||
* @note These bits can only be programmed when TimeoutB is disabled.
|
||||
* @rmtoll TIMEOUTR TIMEOUTB LL_I2C_SetSMBusTimeoutB
|
||||
@@ -1164,7 +1205,7 @@ __STATIC_INLINE void LL_I2C_SetSMBusTimeoutB(I2C_TypeDef *I2Cx, uint32_t Timeout
|
||||
|
||||
/**
|
||||
* @brief Get the SMBus Extended Cumulative Clock TimeoutB setting.
|
||||
* @note Macro IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
|
||||
* @note The macro IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
|
||||
* SMBus feature is supported by the I2Cx Instance.
|
||||
* @rmtoll TIMEOUTR TIMEOUTB LL_I2C_GetSMBusTimeoutB
|
||||
* @param I2Cx I2C Instance.
|
||||
@@ -1177,7 +1218,7 @@ __STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutB(I2C_TypeDef *I2Cx)
|
||||
|
||||
/**
|
||||
* @brief Enable the SMBus Clock Timeout.
|
||||
* @note Macro IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
|
||||
* @note The macro IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
|
||||
* SMBus feature is supported by the I2Cx Instance.
|
||||
* @rmtoll TIMEOUTR TIMOUTEN LL_I2C_EnableSMBusTimeout\n
|
||||
* TIMEOUTR TEXTEN LL_I2C_EnableSMBusTimeout
|
||||
@@ -1195,7 +1236,7 @@ __STATIC_INLINE void LL_I2C_EnableSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t Clock
|
||||
|
||||
/**
|
||||
* @brief Disable the SMBus Clock Timeout.
|
||||
* @note Macro IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
|
||||
* @note The macro IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
|
||||
* SMBus feature is supported by the I2Cx Instance.
|
||||
* @rmtoll TIMEOUTR TIMOUTEN LL_I2C_DisableSMBusTimeout\n
|
||||
* TIMEOUTR TEXTEN LL_I2C_DisableSMBusTimeout
|
||||
@@ -1213,7 +1254,7 @@ __STATIC_INLINE void LL_I2C_DisableSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t Cloc
|
||||
|
||||
/**
|
||||
* @brief Check if the SMBus Clock Timeout is enabled or disabled.
|
||||
* @note Macro IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
|
||||
* @note The macro IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
|
||||
* SMBus feature is supported by the I2Cx Instance.
|
||||
* @rmtoll TIMEOUTR TIMOUTEN LL_I2C_IsEnabledSMBusTimeout\n
|
||||
* TIMEOUTR TEXTEN LL_I2C_IsEnabledSMBusTimeout
|
||||
@@ -1226,7 +1267,8 @@ __STATIC_INLINE void LL_I2C_DisableSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t Cloc
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->TIMEOUTR, (I2C_TIMEOUTR_TIMOUTEN | I2C_TIMEOUTR_TEXTEN)) == (ClockTimeout)) ? 1UL : 0UL);
|
||||
return ((READ_BIT(I2Cx->TIMEOUTR, (I2C_TIMEOUTR_TIMOUTEN | I2C_TIMEOUTR_TEXTEN)) == \
|
||||
(ClockTimeout)) ? 1UL : 0UL);
|
||||
}
|
||||
|
||||
/**
|
||||
@@ -1443,7 +1485,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TC(I2C_TypeDef *I2Cx)
|
||||
|
||||
/**
|
||||
* @brief Enable Error interrupts.
|
||||
* @note Macro IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
|
||||
* @note The macro IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
|
||||
* SMBus feature is supported by the I2Cx Instance.
|
||||
* @note Any of these errors will generate interrupt :
|
||||
* Arbitration Loss (ARLO)
|
||||
@@ -1463,7 +1505,7 @@ __STATIC_INLINE void LL_I2C_EnableIT_ERR(I2C_TypeDef *I2Cx)
|
||||
|
||||
/**
|
||||
* @brief Disable Error interrupts.
|
||||
* @note Macro IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
|
||||
* @note The macro IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
|
||||
* SMBus feature is supported by the I2Cx Instance.
|
||||
* @note Any of these errors will generate interrupt :
|
||||
* Arbitration Loss (ARLO)
|
||||
@@ -1645,7 +1687,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR(I2C_TypeDef *I2Cx)
|
||||
|
||||
/**
|
||||
* @brief Indicate the status of SMBus PEC error flag in reception.
|
||||
* @note Macro IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
|
||||
* @note The macro IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
|
||||
* SMBus feature is supported by the I2Cx Instance.
|
||||
* @note RESET: Clear default value.
|
||||
* SET: When the received PEC does not match with the PEC register content.
|
||||
@@ -1660,7 +1702,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
|
||||
|
||||
/**
|
||||
* @brief Indicate the status of SMBus Timeout detection flag.
|
||||
* @note Macro IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
|
||||
* @note The macro IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
|
||||
* SMBus feature is supported by the I2Cx Instance.
|
||||
* @note RESET: Clear default value.
|
||||
* SET: When a timeout or extended clock timeout occurs.
|
||||
@@ -1675,7 +1717,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
|
||||
|
||||
/**
|
||||
* @brief Indicate the status of SMBus alert flag.
|
||||
* @note Macro IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
|
||||
* @note The macro IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
|
||||
* SMBus feature is supported by the I2Cx Instance.
|
||||
* @note RESET: Clear default value.
|
||||
* SET: When SMBus host configuration, SMBus alert enabled and
|
||||
@@ -1782,7 +1824,7 @@ __STATIC_INLINE void LL_I2C_ClearFlag_OVR(I2C_TypeDef *I2Cx)
|
||||
|
||||
/**
|
||||
* @brief Clear SMBus PEC error flag.
|
||||
* @note Macro IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
|
||||
* @note The macro IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
|
||||
* SMBus feature is supported by the I2Cx Instance.
|
||||
* @rmtoll ICR PECCF LL_I2C_ClearSMBusFlag_PECERR
|
||||
* @param I2Cx I2C Instance.
|
||||
@@ -1795,7 +1837,7 @@ __STATIC_INLINE void LL_I2C_ClearSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
|
||||
|
||||
/**
|
||||
* @brief Clear SMBus Timeout detection flag.
|
||||
* @note Macro IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
|
||||
* @note The macro IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
|
||||
* SMBus feature is supported by the I2Cx Instance.
|
||||
* @rmtoll ICR TIMOUTCF LL_I2C_ClearSMBusFlag_TIMEOUT
|
||||
* @param I2Cx I2C Instance.
|
||||
@@ -1808,7 +1850,7 @@ __STATIC_INLINE void LL_I2C_ClearSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
|
||||
|
||||
/**
|
||||
* @brief Clear SMBus Alert flag.
|
||||
* @note Macro IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
|
||||
* @note The macro IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
|
||||
* SMBus feature is supported by the I2Cx Instance.
|
||||
* @rmtoll ICR ALERTCF LL_I2C_ClearSMBusFlag_ALERT
|
||||
* @param I2Cx I2C Instance.
|
||||
@@ -1923,7 +1965,8 @@ __STATIC_INLINE uint32_t LL_I2C_GetTransferSize(I2C_TypeDef *I2Cx)
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Prepare the generation of a ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte.
|
||||
* @brief Prepare the generation of a ACKnowledge or Non ACKnowledge condition after the address receive match code
|
||||
or next received byte.
|
||||
* @note Usage in Slave mode only.
|
||||
* @rmtoll CR2 NACK LL_I2C_AcknowledgeNextData
|
||||
* @param I2Cx I2C Instance.
|
||||
@@ -1964,7 +2007,8 @@ __STATIC_INLINE void LL_I2C_GenerateStopCondition(I2C_TypeDef *I2Cx)
|
||||
/**
|
||||
* @brief Enable automatic RESTART Read request condition for 10bit address header (master mode).
|
||||
* @note The master sends the complete 10bit slave address read sequence :
|
||||
* Start + 2 bytes 10bit address in Write direction + Restart + first 7 bits of 10bit address in Read direction.
|
||||
* Start + 2 bytes 10bit address in Write direction + Restart + first 7 bits of 10bit address
|
||||
in Read direction.
|
||||
* @rmtoll CR2 HEAD10R LL_I2C_EnableAuto10BitRead
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval None
|
||||
@@ -2125,9 +2169,10 @@ __STATIC_INLINE uint32_t LL_I2C_GetAddressMatchCode(I2C_TypeDef *I2Cx)
|
||||
|
||||
/**
|
||||
* @brief Enable internal comparison of the SMBus Packet Error byte (transmission or reception mode).
|
||||
* @note Macro IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
|
||||
* @note The macro IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
|
||||
* SMBus feature is supported by the I2Cx Instance.
|
||||
* @note This feature is cleared by hardware when the PEC byte is transferred, or when a STOP condition or an Address Matched is received.
|
||||
* @note This feature is cleared by hardware when the PEC byte is transferred, or when a STOP condition
|
||||
or an Address Matched is received.
|
||||
* This bit has no effect when RELOAD bit is set.
|
||||
* This bit has no effect in device mode when SBC bit is not set.
|
||||
* @rmtoll CR2 PECBYTE LL_I2C_EnableSMBusPECCompare
|
||||
@@ -2141,7 +2186,7 @@ __STATIC_INLINE void LL_I2C_EnableSMBusPECCompare(I2C_TypeDef *I2Cx)
|
||||
|
||||
/**
|
||||
* @brief Check if the SMBus Packet Error byte internal comparison is requested or not.
|
||||
* @note Macro IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
|
||||
* @note The macro IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
|
||||
* SMBus feature is supported by the I2Cx Instance.
|
||||
* @rmtoll CR2 PECBYTE LL_I2C_IsEnabledSMBusPECCompare
|
||||
* @param I2Cx I2C Instance.
|
||||
@@ -2154,7 +2199,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPECCompare(I2C_TypeDef *I2Cx)
|
||||
|
||||
/**
|
||||
* @brief Get the SMBus Packet Error byte calculated.
|
||||
* @note Macro IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
|
||||
* @note The macro IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not
|
||||
* SMBus feature is supported by the I2Cx Instance.
|
||||
* @rmtoll PECR PEC LL_I2C_GetSMBusPEC
|
||||
* @param I2Cx I2C Instance.
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -150,24 +150,29 @@ typedef struct
|
||||
uint16_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
|
||||
This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
|
||||
|
||||
This feature can be modified afterwards using unitary function @ref LL_TIM_SetPrescaler().*/
|
||||
This feature can be modified afterwards using unitary function
|
||||
@ref LL_TIM_SetPrescaler().*/
|
||||
|
||||
uint32_t CounterMode; /*!< Specifies the counter mode.
|
||||
This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE.
|
||||
|
||||
This feature can be modified afterwards using unitary function @ref LL_TIM_SetCounterMode().*/
|
||||
This feature can be modified afterwards using unitary function
|
||||
@ref LL_TIM_SetCounterMode().*/
|
||||
|
||||
uint32_t Autoreload; /*!< Specifies the auto reload value to be loaded into the active
|
||||
Auto-Reload Register at the next update event.
|
||||
This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
|
||||
Some timer instances may support 32 bits counters. In that case this parameter must be a number between 0x0000 and 0xFFFFFFFF.
|
||||
Some timer instances may support 32 bits counters. In that case this parameter must
|
||||
be a number between 0x0000 and 0xFFFFFFFF.
|
||||
|
||||
This feature can be modified afterwards using unitary function @ref LL_TIM_SetAutoReload().*/
|
||||
This feature can be modified afterwards using unitary function
|
||||
@ref LL_TIM_SetAutoReload().*/
|
||||
|
||||
uint32_t ClockDivision; /*!< Specifies the clock division.
|
||||
This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION.
|
||||
|
||||
This feature can be modified afterwards using unitary function @ref LL_TIM_SetClockDivision().*/
|
||||
This feature can be modified afterwards using unitary function
|
||||
@ref LL_TIM_SetClockDivision().*/
|
||||
} LL_TIM_InitTypeDef;
|
||||
|
||||
/**
|
||||
@@ -178,22 +183,26 @@ typedef struct
|
||||
uint32_t OCMode; /*!< Specifies the output mode.
|
||||
This parameter can be a value of @ref TIM_LL_EC_OCMODE.
|
||||
|
||||
This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetMode().*/
|
||||
This feature can be modified afterwards using unitary function
|
||||
@ref LL_TIM_OC_SetMode().*/
|
||||
|
||||
uint32_t OCState; /*!< Specifies the TIM Output Compare state.
|
||||
This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
|
||||
|
||||
This feature can be modified afterwards using unitary functions @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
|
||||
This feature can be modified afterwards using unitary functions
|
||||
@ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
|
||||
|
||||
uint32_t CompareValue; /*!< Specifies the Compare value to be loaded into the Capture Compare Register.
|
||||
This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
|
||||
|
||||
This feature can be modified afterwards using unitary function LL_TIM_OC_SetCompareCHx (x=1..6).*/
|
||||
This feature can be modified afterwards using unitary function
|
||||
LL_TIM_OC_SetCompareCHx (x=1..6).*/
|
||||
|
||||
uint32_t OCPolarity; /*!< Specifies the output polarity.
|
||||
This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
|
||||
|
||||
This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetPolarity().*/
|
||||
This feature can be modified afterwards using unitary function
|
||||
@ref LL_TIM_OC_SetPolarity().*/
|
||||
|
||||
|
||||
} LL_TIM_OC_InitTypeDef;
|
||||
@@ -208,22 +217,26 @@ typedef struct
|
||||
uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
|
||||
This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
|
||||
|
||||
This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
|
||||
This feature can be modified afterwards using unitary function
|
||||
@ref LL_TIM_IC_SetPolarity().*/
|
||||
|
||||
uint32_t ICActiveInput; /*!< Specifies the input.
|
||||
This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
|
||||
|
||||
This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
|
||||
This feature can be modified afterwards using unitary function
|
||||
@ref LL_TIM_IC_SetActiveInput().*/
|
||||
|
||||
uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
|
||||
This parameter can be a value of @ref TIM_LL_EC_ICPSC.
|
||||
|
||||
This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
|
||||
This feature can be modified afterwards using unitary function
|
||||
@ref LL_TIM_IC_SetPrescaler().*/
|
||||
|
||||
uint32_t ICFilter; /*!< Specifies the input capture filter.
|
||||
This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
|
||||
|
||||
This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
|
||||
This feature can be modified afterwards using unitary function
|
||||
@ref LL_TIM_IC_SetFilter().*/
|
||||
} LL_TIM_IC_InitTypeDef;
|
||||
|
||||
|
||||
@@ -235,47 +248,56 @@ typedef struct
|
||||
uint32_t EncoderMode; /*!< Specifies the encoder resolution (x2 or x4).
|
||||
This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE.
|
||||
|
||||
This feature can be modified afterwards using unitary function @ref LL_TIM_SetEncoderMode().*/
|
||||
This feature can be modified afterwards using unitary function
|
||||
@ref LL_TIM_SetEncoderMode().*/
|
||||
|
||||
uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
|
||||
This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
|
||||
|
||||
This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
|
||||
This feature can be modified afterwards using unitary function
|
||||
@ref LL_TIM_IC_SetPolarity().*/
|
||||
|
||||
uint32_t IC1ActiveInput; /*!< Specifies the TI1 input source
|
||||
This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
|
||||
|
||||
This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
|
||||
This feature can be modified afterwards using unitary function
|
||||
@ref LL_TIM_IC_SetActiveInput().*/
|
||||
|
||||
uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
|
||||
This parameter can be a value of @ref TIM_LL_EC_ICPSC.
|
||||
|
||||
This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
|
||||
This feature can be modified afterwards using unitary function
|
||||
@ref LL_TIM_IC_SetPrescaler().*/
|
||||
|
||||
uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
|
||||
This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
|
||||
|
||||
This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
|
||||
This feature can be modified afterwards using unitary function
|
||||
@ref LL_TIM_IC_SetFilter().*/
|
||||
|
||||
uint32_t IC2Polarity; /*!< Specifies the active edge of TI2 input.
|
||||
This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
|
||||
|
||||
This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
|
||||
This feature can be modified afterwards using unitary function
|
||||
@ref LL_TIM_IC_SetPolarity().*/
|
||||
|
||||
uint32_t IC2ActiveInput; /*!< Specifies the TI2 input source
|
||||
This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
|
||||
|
||||
This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
|
||||
This feature can be modified afterwards using unitary function
|
||||
@ref LL_TIM_IC_SetActiveInput().*/
|
||||
|
||||
uint32_t IC2Prescaler; /*!< Specifies the TI2 input prescaler value.
|
||||
This parameter can be a value of @ref TIM_LL_EC_ICPSC.
|
||||
|
||||
This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
|
||||
This feature can be modified afterwards using unitary function
|
||||
@ref LL_TIM_IC_SetPrescaler().*/
|
||||
|
||||
uint32_t IC2Filter; /*!< Specifies the TI2 input filter.
|
||||
This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
|
||||
|
||||
This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
|
||||
This feature can be modified afterwards using unitary function
|
||||
@ref LL_TIM_IC_SetFilter().*/
|
||||
|
||||
} LL_TIM_ENCODER_InitTypeDef;
|
||||
|
||||
@@ -334,8 +356,8 @@ typedef struct
|
||||
/** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode
|
||||
* @{
|
||||
*/
|
||||
#define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /*!< Counter is not stopped at update event */
|
||||
#define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /*!< Counter stops counting at the next update event */
|
||||
#define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */
|
||||
#define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@@ -822,7 +844,8 @@ typedef struct
|
||||
((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U))) - 1U) : 0U)
|
||||
|
||||
/**
|
||||
* @brief HELPER macro calculating the compare value required to achieve the required timer output compare active/inactive delay.
|
||||
* @brief HELPER macro calculating the compare value required to achieve the required timer output compare
|
||||
* active/inactive delay.
|
||||
* @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10);
|
||||
* @param __TIMCLK__ timer input clock frequency (in Hz)
|
||||
* @param __PSC__ prescaler
|
||||
@@ -834,7 +857,8 @@ typedef struct
|
||||
/ ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
|
||||
|
||||
/**
|
||||
* @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration (when the timer operates in one pulse mode).
|
||||
* @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration
|
||||
* (when the timer operates in one pulse mode).
|
||||
* @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20);
|
||||
* @param __TIMCLK__ timer input clock frequency (in Hz)
|
||||
* @param __PSC__ prescaler
|
||||
@@ -1091,7 +1115,8 @@ __STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(TIM_TypeDef *TIMx)
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.
|
||||
* @brief Set the division ratio between the timer clock and the sampling clock used by the dead-time generators
|
||||
* (when supported) and the digital filters.
|
||||
* @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
|
||||
* whether or not the clock division feature is supported by the timer
|
||||
* instance.
|
||||
@@ -1109,7 +1134,8 @@ __STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDi
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the actual division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.
|
||||
* @brief Get the actual division ratio between the timer clock and the sampling clock used by the dead-time
|
||||
* generators (when supported) and the digital filters.
|
||||
* @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
|
||||
* whether or not the clock division feature is supported by the timer
|
||||
* instance.
|
||||
@@ -1368,7 +1394,7 @@ __STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint
|
||||
{
|
||||
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
|
||||
MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]);
|
||||
MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]);
|
||||
}
|
||||
|
||||
/**
|
||||
@@ -1397,7 +1423,7 @@ __STATIC_INLINE uint32_t LL_TIM_OC_GetMode(TIM_TypeDef *TIMx, uint32_t Channel)
|
||||
{
|
||||
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
|
||||
return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]);
|
||||
return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]);
|
||||
}
|
||||
|
||||
/**
|
||||
@@ -1804,7 +1830,8 @@ __STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint3
|
||||
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
|
||||
MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]),
|
||||
((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) << SHIFT_TAB_ICxx[iChannel]);
|
||||
((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) \
|
||||
<< SHIFT_TAB_ICxx[iChannel]);
|
||||
MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
|
||||
(Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]);
|
||||
}
|
||||
@@ -2685,7 +2712,8 @@ __STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx)
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set (Capture/Compare 1 interrupt is pending).
|
||||
* @brief Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set
|
||||
* (Capture/Compare 1 interrupt is pending).
|
||||
* @rmtoll SR CC1OF LL_TIM_IsActiveFlag_CC1OVR
|
||||
* @param TIMx Timer instance
|
||||
* @retval State of bit (1 or 0).
|
||||
@@ -2707,7 +2735,8 @@ __STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx)
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set (Capture/Compare 2 over-capture interrupt is pending).
|
||||
* @brief Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set
|
||||
* (Capture/Compare 2 over-capture interrupt is pending).
|
||||
* @rmtoll SR CC2OF LL_TIM_IsActiveFlag_CC2OVR
|
||||
* @param TIMx Timer instance
|
||||
* @retval State of bit (1 or 0).
|
||||
@@ -2729,7 +2758,8 @@ __STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx)
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set (Capture/Compare 3 over-capture interrupt is pending).
|
||||
* @brief Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set
|
||||
* (Capture/Compare 3 over-capture interrupt is pending).
|
||||
* @rmtoll SR CC3OF LL_TIM_IsActiveFlag_CC3OVR
|
||||
* @param TIMx Timer instance
|
||||
* @retval State of bit (1 or 0).
|
||||
@@ -2751,7 +2781,8 @@ __STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx)
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set (Capture/Compare 4 over-capture interrupt is pending).
|
||||
* @brief Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set
|
||||
* (Capture/Compare 4 over-capture interrupt is pending).
|
||||
* @rmtoll SR CC4OF LL_TIM_IsActiveFlag_CC4OVR
|
||||
* @param TIMx Timer instance
|
||||
* @retval State of bit (1 or 0).
|
||||
@@ -2970,7 +3001,7 @@ __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(TIM_TypeDef *TIMx)
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM_LL_EF_DMA_Management DMA-Management
|
||||
/** @defgroup TIM_LL_EF_DMA_Management DMA Management
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
|
||||
3751
fw/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h
Normal file
3751
fw/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_usart.h
Normal file
File diff suppressed because it is too large
Load Diff
@@ -25,7 +25,7 @@
|
||||
#include "stm32_assert.h"
|
||||
#else
|
||||
#define assert_param(expr) ((void)0U)
|
||||
#endif
|
||||
#endif /* USE_FULL_ASSERT */
|
||||
|
||||
/** @addtogroup STM32L0xx_LL_Driver
|
||||
* @{
|
||||
@@ -109,7 +109,7 @@ ErrorStatus LL_I2C_DeInit(I2C_TypeDef *I2Cx)
|
||||
LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C2);
|
||||
|
||||
}
|
||||
#endif
|
||||
#endif /* I2C2 */
|
||||
#if defined(I2C3)
|
||||
else if (I2Cx == I2C3)
|
||||
{
|
||||
@@ -119,7 +119,7 @@ ErrorStatus LL_I2C_DeInit(I2C_TypeDef *I2Cx)
|
||||
/* Release reset of I2C clock */
|
||||
LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C3);
|
||||
}
|
||||
#endif
|
||||
#endif /* I2C3 */
|
||||
else
|
||||
{
|
||||
status = ERROR;
|
||||
|
||||
@@ -1,264 +0,0 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32l0xx_ll_lpuart.c
|
||||
* @author MCD Application Team
|
||||
* @brief LPUART LL module driver.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
#if defined(USE_FULL_LL_DRIVER)
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32l0xx_ll_lpuart.h"
|
||||
#include "stm32l0xx_ll_rcc.h"
|
||||
#include "stm32l0xx_ll_bus.h"
|
||||
#ifdef USE_FULL_ASSERT
|
||||
#include "stm32_assert.h"
|
||||
#else
|
||||
#define assert_param(expr) ((void)0U)
|
||||
#endif /* USE_FULL_ASSERT */
|
||||
|
||||
/** @addtogroup STM32L0xx_LL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined (LPUART1)
|
||||
|
||||
/** @addtogroup LPUART_LL
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/** @addtogroup LPUART_LL_Private_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @addtogroup LPUART_LL_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Check of parameters for configuration of LPUART registers */
|
||||
|
||||
/* __BAUDRATE__ Depending on constraints applicable for LPUART BRR register */
|
||||
/* value : */
|
||||
/* - fck must be in the range [3 x baudrate, 4096 x baudrate] */
|
||||
/* - LPUART_BRR register value should be >= 0x300 */
|
||||
/* - LPUART_BRR register value should be <= 0xFFFFF (20 bits) */
|
||||
/* Baudrate specified by the user should belong to [8, 10600000].*/
|
||||
#define IS_LL_LPUART_BAUDRATE(__BAUDRATE__) (((__BAUDRATE__) <= 10600000U) && ((__BAUDRATE__) >= 8U))
|
||||
|
||||
/* __VALUE__ BRR content must be greater than or equal to 0x300. */
|
||||
#define IS_LL_LPUART_BRR_MIN(__VALUE__) ((__VALUE__) >= 0x300U)
|
||||
|
||||
/* __VALUE__ BRR content must be lower than or equal to 0xFFFFF. */
|
||||
#define IS_LL_LPUART_BRR_MAX(__VALUE__) ((__VALUE__) <= 0x000FFFFFU)
|
||||
|
||||
#define IS_LL_LPUART_DIRECTION(__VALUE__) (((__VALUE__) == LL_LPUART_DIRECTION_NONE) \
|
||||
|| ((__VALUE__) == LL_LPUART_DIRECTION_RX) \
|
||||
|| ((__VALUE__) == LL_LPUART_DIRECTION_TX) \
|
||||
|| ((__VALUE__) == LL_LPUART_DIRECTION_TX_RX))
|
||||
|
||||
#define IS_LL_LPUART_PARITY(__VALUE__) (((__VALUE__) == LL_LPUART_PARITY_NONE) \
|
||||
|| ((__VALUE__) == LL_LPUART_PARITY_EVEN) \
|
||||
|| ((__VALUE__) == LL_LPUART_PARITY_ODD))
|
||||
|
||||
#define IS_LL_LPUART_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_LPUART_DATAWIDTH_7B) \
|
||||
|| ((__VALUE__) == LL_LPUART_DATAWIDTH_8B) \
|
||||
|| ((__VALUE__) == LL_LPUART_DATAWIDTH_9B))
|
||||
|
||||
#define IS_LL_LPUART_STOPBITS(__VALUE__) (((__VALUE__) == LL_LPUART_STOPBITS_1) \
|
||||
|| ((__VALUE__) == LL_LPUART_STOPBITS_2))
|
||||
|
||||
#define IS_LL_LPUART_HWCONTROL(__VALUE__) (((__VALUE__) == LL_LPUART_HWCONTROL_NONE) \
|
||||
|| ((__VALUE__) == LL_LPUART_HWCONTROL_RTS) \
|
||||
|| ((__VALUE__) == LL_LPUART_HWCONTROL_CTS) \
|
||||
|| ((__VALUE__) == LL_LPUART_HWCONTROL_RTS_CTS))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup LPUART_LL_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup LPUART_LL_EF_Init
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief De-initialize LPUART registers (Registers restored to their default values).
|
||||
* @param LPUARTx LPUART Instance
|
||||
* @retval An ErrorStatus enumeration value:
|
||||
* - SUCCESS: LPUART registers are de-initialized
|
||||
* - ERROR: not applicable
|
||||
*/
|
||||
ErrorStatus LL_LPUART_DeInit(USART_TypeDef *LPUARTx)
|
||||
{
|
||||
ErrorStatus status = SUCCESS;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_LPUART_INSTANCE(LPUARTx));
|
||||
|
||||
if (LPUARTx == LPUART1)
|
||||
{
|
||||
/* Force reset of LPUART peripheral */
|
||||
LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_LPUART1);
|
||||
|
||||
/* Release reset of LPUART peripheral */
|
||||
LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_LPUART1);
|
||||
}
|
||||
else
|
||||
{
|
||||
status = ERROR;
|
||||
}
|
||||
|
||||
return (status);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initialize LPUART registers according to the specified
|
||||
* parameters in LPUART_InitStruct.
|
||||
* @note As some bits in LPUART configuration registers can only be written when
|
||||
* the LPUART is disabled (USART_CR1_UE bit =0),
|
||||
* LPUART Peripheral should be in disabled state prior calling this function.
|
||||
* Otherwise, ERROR result will be returned.
|
||||
* @note Baud rate value stored in LPUART_InitStruct BaudRate field, should be valid (different from 0).
|
||||
* @param LPUARTx LPUART Instance
|
||||
* @param LPUART_InitStruct pointer to a @ref LL_LPUART_InitTypeDef structure
|
||||
* that contains the configuration information for the specified LPUART peripheral.
|
||||
* @retval An ErrorStatus enumeration value:
|
||||
* - SUCCESS: LPUART registers are initialized according to LPUART_InitStruct content
|
||||
* - ERROR: Problem occurred during LPUART Registers initialization
|
||||
*/
|
||||
ErrorStatus LL_LPUART_Init(USART_TypeDef *LPUARTx, LL_LPUART_InitTypeDef *LPUART_InitStruct)
|
||||
{
|
||||
ErrorStatus status = ERROR;
|
||||
uint32_t periphclk;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_LPUART_INSTANCE(LPUARTx));
|
||||
assert_param(IS_LL_LPUART_BAUDRATE(LPUART_InitStruct->BaudRate));
|
||||
assert_param(IS_LL_LPUART_DATAWIDTH(LPUART_InitStruct->DataWidth));
|
||||
assert_param(IS_LL_LPUART_STOPBITS(LPUART_InitStruct->StopBits));
|
||||
assert_param(IS_LL_LPUART_PARITY(LPUART_InitStruct->Parity));
|
||||
assert_param(IS_LL_LPUART_DIRECTION(LPUART_InitStruct->TransferDirection));
|
||||
assert_param(IS_LL_LPUART_HWCONTROL(LPUART_InitStruct->HardwareFlowControl));
|
||||
|
||||
/* LPUART needs to be in disabled state, in order to be able to configure some bits in
|
||||
CRx registers. Otherwise (LPUART not in Disabled state) => return ERROR */
|
||||
if (LL_LPUART_IsEnabled(LPUARTx) == 0U)
|
||||
{
|
||||
/*---------------------------- LPUART CR1 Configuration -----------------------
|
||||
* Configure LPUARTx CR1 (LPUART Word Length, Parity and Transfer Direction bits) with parameters:
|
||||
* - DataWidth: USART_CR1_M bits according to LPUART_InitStruct->DataWidth value
|
||||
* - Parity: USART_CR1_PCE, USART_CR1_PS bits according to LPUART_InitStruct->Parity value
|
||||
* - TransferDirection: USART_CR1_TE, USART_CR1_RE bits according to LPUART_InitStruct->TransferDirection value
|
||||
*/
|
||||
MODIFY_REG(LPUARTx->CR1,
|
||||
(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE),
|
||||
(LPUART_InitStruct->DataWidth | LPUART_InitStruct->Parity | LPUART_InitStruct->TransferDirection));
|
||||
|
||||
/*---------------------------- LPUART CR2 Configuration -----------------------
|
||||
* Configure LPUARTx CR2 (Stop bits) with parameters:
|
||||
* - Stop Bits: USART_CR2_STOP bits according to LPUART_InitStruct->StopBits value.
|
||||
*/
|
||||
LL_LPUART_SetStopBitsLength(LPUARTx, LPUART_InitStruct->StopBits);
|
||||
|
||||
/*---------------------------- LPUART CR3 Configuration -----------------------
|
||||
* Configure LPUARTx CR3 (Hardware Flow Control) with parameters:
|
||||
* - HardwareFlowControl: USART_CR3_RTSE, USART_CR3_CTSE bits according
|
||||
* to LPUART_InitStruct->HardwareFlowControl value.
|
||||
*/
|
||||
LL_LPUART_SetHWFlowCtrl(LPUARTx, LPUART_InitStruct->HardwareFlowControl);
|
||||
|
||||
/*---------------------------- LPUART BRR Configuration -----------------------
|
||||
* Retrieve Clock frequency used for LPUART Peripheral
|
||||
*/
|
||||
periphclk = LL_RCC_GetLPUARTClockFreq(LL_RCC_LPUART1_CLKSOURCE);
|
||||
|
||||
/* Configure the LPUART Baud Rate :
|
||||
- valid baud rate value (different from 0) is required
|
||||
- Peripheral clock as returned by RCC service, should be valid (different from 0).
|
||||
*/
|
||||
if ((periphclk != LL_RCC_PERIPH_FREQUENCY_NO)
|
||||
&& (LPUART_InitStruct->BaudRate != 0U))
|
||||
{
|
||||
status = SUCCESS;
|
||||
LL_LPUART_SetBaudRate(LPUARTx,
|
||||
periphclk,
|
||||
LPUART_InitStruct->BaudRate);
|
||||
|
||||
/* Check BRR is greater than or equal to 0x300 */
|
||||
assert_param(IS_LL_LPUART_BRR_MIN(LPUARTx->BRR));
|
||||
|
||||
/* Check BRR is lower than or equal to 0xFFFFF */
|
||||
assert_param(IS_LL_LPUART_BRR_MAX(LPUARTx->BRR));
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
return (status);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set each @ref LL_LPUART_InitTypeDef field to default value.
|
||||
* @param LPUART_InitStruct pointer to a @ref LL_LPUART_InitTypeDef structure
|
||||
* whose fields will be set to default values.
|
||||
* @retval None
|
||||
*/
|
||||
|
||||
void LL_LPUART_StructInit(LL_LPUART_InitTypeDef *LPUART_InitStruct)
|
||||
{
|
||||
/* Set LPUART_InitStruct fields to default values */
|
||||
LPUART_InitStruct->BaudRate = 9600U;
|
||||
LPUART_InitStruct->DataWidth = LL_LPUART_DATAWIDTH_8B;
|
||||
LPUART_InitStruct->StopBits = LL_LPUART_STOPBITS_1;
|
||||
LPUART_InitStruct->Parity = LL_LPUART_PARITY_NONE ;
|
||||
LPUART_InitStruct->TransferDirection = LL_LPUART_DIRECTION_TX_RX;
|
||||
LPUART_InitStruct->HardwareFlowControl = LL_LPUART_HWCONTROL_NONE;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* LPUART1 */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* USE_FULL_LL_DRIVER */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
||||
@@ -75,11 +75,11 @@
|
||||
/** @defgroup RCC_LL_Private_Functions RCC Private functions
|
||||
* @{
|
||||
*/
|
||||
uint32_t RCC_GetSystemClockFreq(void);
|
||||
uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency);
|
||||
uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency);
|
||||
uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency);
|
||||
uint32_t RCC_PLL_GetFreqDomain_SYS(void);
|
||||
static uint32_t RCC_GetSystemClockFreq(void);
|
||||
static uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency);
|
||||
static uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency);
|
||||
static uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency);
|
||||
static uint32_t RCC_PLL_GetFreqDomain_SYS(void);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@@ -576,7 +576,7 @@ uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource)
|
||||
* @brief Return SYSTEM clock frequency
|
||||
* @retval SYSTEM clock frequency (in Hz)
|
||||
*/
|
||||
uint32_t RCC_GetSystemClockFreq(void)
|
||||
static uint32_t RCC_GetSystemClockFreq(void)
|
||||
{
|
||||
uint32_t frequency;
|
||||
|
||||
@@ -619,7 +619,7 @@ uint32_t RCC_GetSystemClockFreq(void)
|
||||
* @param SYSCLK_Frequency SYSCLK clock frequency
|
||||
* @retval HCLK clock frequency (in Hz)
|
||||
*/
|
||||
uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency)
|
||||
static uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency)
|
||||
{
|
||||
/* HCLK clock frequency */
|
||||
return __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, LL_RCC_GetAHBPrescaler());
|
||||
@@ -630,7 +630,7 @@ uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency)
|
||||
* @param HCLK_Frequency HCLK clock frequency
|
||||
* @retval PCLK1 clock frequency (in Hz)
|
||||
*/
|
||||
uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency)
|
||||
static uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency)
|
||||
{
|
||||
/* PCLK1 clock frequency */
|
||||
return __LL_RCC_CALC_PCLK1_FREQ(HCLK_Frequency, LL_RCC_GetAPB1Prescaler());
|
||||
@@ -641,7 +641,7 @@ uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency)
|
||||
* @param HCLK_Frequency HCLK clock frequency
|
||||
* @retval PCLK2 clock frequency (in Hz)
|
||||
*/
|
||||
uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency)
|
||||
static uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency)
|
||||
{
|
||||
/* PCLK2 clock frequency */
|
||||
return __LL_RCC_CALC_PCLK2_FREQ(HCLK_Frequency, LL_RCC_GetAPB2Prescaler());
|
||||
@@ -651,7 +651,7 @@ uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency)
|
||||
* @brief Return PLL clock frequency used for system domain
|
||||
* @retval PLL clock frequency (in Hz)
|
||||
*/
|
||||
uint32_t RCC_PLL_GetFreqDomain_SYS(void)
|
||||
static uint32_t RCC_PLL_GetFreqDomain_SYS(void)
|
||||
{
|
||||
uint32_t pllinputfreq, pllsource;
|
||||
|
||||
|
||||
@@ -214,7 +214,8 @@ void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct)
|
||||
/**
|
||||
* @brief Configure the TIMx time base unit.
|
||||
* @param TIMx Timer Instance
|
||||
* @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (TIMx time base unit configuration data structure)
|
||||
* @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure
|
||||
* (TIMx time base unit configuration data structure)
|
||||
* @retval An ErrorStatus enumeration value:
|
||||
* - SUCCESS: TIMx registers are de-initialized
|
||||
* - ERROR: not applicable
|
||||
@@ -260,7 +261,8 @@ ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct)
|
||||
/**
|
||||
* @brief Set the fields of the TIMx output channel configuration data
|
||||
* structure to their default values.
|
||||
* @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (the output channel configuration data structure)
|
||||
* @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure
|
||||
* (the output channel configuration data structure)
|
||||
* @retval None
|
||||
*/
|
||||
void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
|
||||
@@ -280,7 +282,8 @@ void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
|
||||
* @arg @ref LL_TIM_CHANNEL_CH2
|
||||
* @arg @ref LL_TIM_CHANNEL_CH3
|
||||
* @arg @ref LL_TIM_CHANNEL_CH4
|
||||
* @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (TIMx output channel configuration data structure)
|
||||
* @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (TIMx output channel configuration
|
||||
* data structure)
|
||||
* @retval An ErrorStatus enumeration value:
|
||||
* - SUCCESS: TIMx output channel is initialized
|
||||
* - ERROR: TIMx output channel is not initialized
|
||||
@@ -313,7 +316,8 @@ ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTy
|
||||
/**
|
||||
* @brief Set the fields of the TIMx input channel configuration data
|
||||
* structure to their default values.
|
||||
* @param TIM_ICInitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (the input channel configuration data structure)
|
||||
* @param TIM_ICInitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (the input channel configuration
|
||||
* data structure)
|
||||
* @retval None
|
||||
*/
|
||||
void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
|
||||
@@ -333,7 +337,8 @@ void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
|
||||
* @arg @ref LL_TIM_CHANNEL_CH2
|
||||
* @arg @ref LL_TIM_CHANNEL_CH3
|
||||
* @arg @ref LL_TIM_CHANNEL_CH4
|
||||
* @param TIM_IC_InitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (TIMx input channel configuration data structure)
|
||||
* @param TIM_IC_InitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (TIMx input channel configuration data
|
||||
* structure)
|
||||
* @retval An ErrorStatus enumeration value:
|
||||
* - SUCCESS: TIMx output channel is initialized
|
||||
* - ERROR: TIMx output channel is not initialized
|
||||
@@ -365,7 +370,8 @@ ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTy
|
||||
|
||||
/**
|
||||
* @brief Fills each TIM_EncoderInitStruct field with its default value
|
||||
* @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (encoder interface configuration data structure)
|
||||
* @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (encoder interface
|
||||
* configuration data structure)
|
||||
* @retval None
|
||||
*/
|
||||
void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
|
||||
@@ -385,7 +391,8 @@ void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct
|
||||
/**
|
||||
* @brief Configure the encoder interface of the timer instance.
|
||||
* @param TIMx Timer Instance
|
||||
* @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (TIMx encoder interface configuration data structure)
|
||||
* @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (TIMx encoder interface
|
||||
* configuration data structure)
|
||||
* @retval An ErrorStatus enumeration value:
|
||||
* - SUCCESS: TIMx registers are de-initialized
|
||||
* - ERROR: not applicable
|
||||
|
||||
420
fw/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c
Normal file
420
fw/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_usart.c
Normal file
@@ -0,0 +1,420 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32l0xx_ll_usart.c
|
||||
* @author MCD Application Team
|
||||
* @brief USART LL module driver.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
#if defined(USE_FULL_LL_DRIVER)
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32l0xx_ll_usart.h"
|
||||
#include "stm32l0xx_ll_rcc.h"
|
||||
#include "stm32l0xx_ll_bus.h"
|
||||
#ifdef USE_FULL_ASSERT
|
||||
#include "stm32_assert.h"
|
||||
#else
|
||||
#define assert_param(expr) ((void)0U)
|
||||
#endif /* USE_FULL_ASSERT */
|
||||
|
||||
/** @addtogroup STM32L0xx_LL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined (USART1) || defined (USART2) || defined (USART4) || defined (USART5)
|
||||
|
||||
/** @addtogroup USART_LL
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @addtogroup USART_LL_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* __BAUDRATE__ The maximum Baud Rate is derived from the maximum clock available
|
||||
* divided by the smallest oversampling used on the USART (i.e. 8) */
|
||||
#define IS_LL_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) <= 4000000U)
|
||||
|
||||
/* __VALUE__ In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d. */
|
||||
#define IS_LL_USART_BRR_MIN(__VALUE__) ((__VALUE__) >= 16U)
|
||||
|
||||
#define IS_LL_USART_DIRECTION(__VALUE__) (((__VALUE__) == LL_USART_DIRECTION_NONE) \
|
||||
|| ((__VALUE__) == LL_USART_DIRECTION_RX) \
|
||||
|| ((__VALUE__) == LL_USART_DIRECTION_TX) \
|
||||
|| ((__VALUE__) == LL_USART_DIRECTION_TX_RX))
|
||||
|
||||
#define IS_LL_USART_PARITY(__VALUE__) (((__VALUE__) == LL_USART_PARITY_NONE) \
|
||||
|| ((__VALUE__) == LL_USART_PARITY_EVEN) \
|
||||
|| ((__VALUE__) == LL_USART_PARITY_ODD))
|
||||
|
||||
#define IS_LL_USART_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_USART_DATAWIDTH_7B) \
|
||||
|| ((__VALUE__) == LL_USART_DATAWIDTH_8B) \
|
||||
|| ((__VALUE__) == LL_USART_DATAWIDTH_9B))
|
||||
|
||||
#define IS_LL_USART_OVERSAMPLING(__VALUE__) (((__VALUE__) == LL_USART_OVERSAMPLING_16) \
|
||||
|| ((__VALUE__) == LL_USART_OVERSAMPLING_8))
|
||||
|
||||
#define IS_LL_USART_LASTBITCLKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_LASTCLKPULSE_NO_OUTPUT) \
|
||||
|| ((__VALUE__) == LL_USART_LASTCLKPULSE_OUTPUT))
|
||||
|
||||
#define IS_LL_USART_CLOCKPHASE(__VALUE__) (((__VALUE__) == LL_USART_PHASE_1EDGE) \
|
||||
|| ((__VALUE__) == LL_USART_PHASE_2EDGE))
|
||||
|
||||
#define IS_LL_USART_CLOCKPOLARITY(__VALUE__) (((__VALUE__) == LL_USART_POLARITY_LOW) \
|
||||
|| ((__VALUE__) == LL_USART_POLARITY_HIGH))
|
||||
|
||||
#define IS_LL_USART_CLOCKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_CLOCK_DISABLE) \
|
||||
|| ((__VALUE__) == LL_USART_CLOCK_ENABLE))
|
||||
|
||||
#define IS_LL_USART_STOPBITS(__VALUE__) (((__VALUE__) == LL_USART_STOPBITS_0_5) \
|
||||
|| ((__VALUE__) == LL_USART_STOPBITS_1) \
|
||||
|| ((__VALUE__) == LL_USART_STOPBITS_1_5) \
|
||||
|| ((__VALUE__) == LL_USART_STOPBITS_2))
|
||||
|
||||
#define IS_LL_USART_HWCONTROL(__VALUE__) (((__VALUE__) == LL_USART_HWCONTROL_NONE) \
|
||||
|| ((__VALUE__) == LL_USART_HWCONTROL_RTS) \
|
||||
|| ((__VALUE__) == LL_USART_HWCONTROL_CTS) \
|
||||
|| ((__VALUE__) == LL_USART_HWCONTROL_RTS_CTS))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup USART_LL_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup USART_LL_EF_Init
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief De-initialize USART registers (Registers restored to their default values).
|
||||
* @param USARTx USART Instance
|
||||
* @retval An ErrorStatus enumeration value:
|
||||
* - SUCCESS: USART registers are de-initialized
|
||||
* - ERROR: USART registers are not de-initialized
|
||||
*/
|
||||
ErrorStatus LL_USART_DeInit(USART_TypeDef *USARTx)
|
||||
{
|
||||
ErrorStatus status = SUCCESS;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_UART_INSTANCE(USARTx));
|
||||
|
||||
#if defined(USART1)
|
||||
if (USARTx == USART1)
|
||||
{
|
||||
/* Force reset of USART clock */
|
||||
LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_USART1);
|
||||
|
||||
/* Release reset of USART clock */
|
||||
LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_USART1);
|
||||
}
|
||||
#endif /* USART1 */
|
||||
#if defined(USART1)
|
||||
else if (USARTx == USART2)
|
||||
#else
|
||||
if (USARTx == USART2)
|
||||
#endif /* USART1 */
|
||||
{
|
||||
/* Force reset of USART clock */
|
||||
LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART2);
|
||||
|
||||
/* Release reset of USART clock */
|
||||
LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART2);
|
||||
}
|
||||
#if defined(USART4)
|
||||
else if (USARTx == USART4)
|
||||
{
|
||||
/* Force reset of USART clock */
|
||||
LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART4);
|
||||
|
||||
/* Release reset of USART clock */
|
||||
LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART4);
|
||||
}
|
||||
#endif /* USART4 */
|
||||
#if defined(USART5)
|
||||
else if (USARTx == USART5)
|
||||
{
|
||||
/* Force reset of USART clock */
|
||||
LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART5);
|
||||
|
||||
/* Release reset of USART clock */
|
||||
LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART5);
|
||||
}
|
||||
#endif /* USART5 */
|
||||
else
|
||||
{
|
||||
status = ERROR;
|
||||
}
|
||||
|
||||
return (status);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initialize USART registers according to the specified
|
||||
* parameters in USART_InitStruct.
|
||||
* @note As some bits in USART configuration registers can only be written when
|
||||
* the USART is disabled (USART_CR1_UE bit =0), USART Peripheral should be in disabled state prior calling
|
||||
* this function. Otherwise, ERROR result will be returned.
|
||||
* @note Baud rate value stored in USART_InitStruct BaudRate field, should be valid (different from 0).
|
||||
* @param USARTx USART Instance
|
||||
* @param USART_InitStruct pointer to a LL_USART_InitTypeDef structure
|
||||
* that contains the configuration information for the specified USART peripheral.
|
||||
* @retval An ErrorStatus enumeration value:
|
||||
* - SUCCESS: USART registers are initialized according to USART_InitStruct content
|
||||
* - ERROR: Problem occurred during USART Registers initialization
|
||||
*/
|
||||
ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_InitStruct)
|
||||
{
|
||||
ErrorStatus status = ERROR;
|
||||
uint32_t periphclk = LL_RCC_PERIPH_FREQUENCY_NO;
|
||||
#if defined(USART4) || defined(USART5)
|
||||
LL_RCC_ClocksTypeDef RCC_Clocks;
|
||||
#endif /* USART4 || USART5 */
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_UART_INSTANCE(USARTx));
|
||||
assert_param(IS_LL_USART_BAUDRATE(USART_InitStruct->BaudRate));
|
||||
assert_param(IS_LL_USART_DATAWIDTH(USART_InitStruct->DataWidth));
|
||||
assert_param(IS_LL_USART_STOPBITS(USART_InitStruct->StopBits));
|
||||
assert_param(IS_LL_USART_PARITY(USART_InitStruct->Parity));
|
||||
assert_param(IS_LL_USART_DIRECTION(USART_InitStruct->TransferDirection));
|
||||
assert_param(IS_LL_USART_HWCONTROL(USART_InitStruct->HardwareFlowControl));
|
||||
assert_param(IS_LL_USART_OVERSAMPLING(USART_InitStruct->OverSampling));
|
||||
|
||||
/* USART needs to be in disabled state, in order to be able to configure some bits in
|
||||
CRx registers */
|
||||
if (LL_USART_IsEnabled(USARTx) == 0U)
|
||||
{
|
||||
/*---------------------------- USART CR1 Configuration ---------------------
|
||||
* Configure USARTx CR1 (USART Word Length, Parity, Mode and Oversampling bits) with parameters:
|
||||
* - DataWidth: USART_CR1_M bits according to USART_InitStruct->DataWidth value
|
||||
* - Parity: USART_CR1_PCE, USART_CR1_PS bits according to USART_InitStruct->Parity value
|
||||
* - TransferDirection: USART_CR1_TE, USART_CR1_RE bits according to USART_InitStruct->TransferDirection value
|
||||
* - Oversampling: USART_CR1_OVER8 bit according to USART_InitStruct->OverSampling value.
|
||||
*/
|
||||
MODIFY_REG(USARTx->CR1,
|
||||
(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS |
|
||||
USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8),
|
||||
(USART_InitStruct->DataWidth | USART_InitStruct->Parity |
|
||||
USART_InitStruct->TransferDirection | USART_InitStruct->OverSampling));
|
||||
|
||||
/*---------------------------- USART CR2 Configuration ---------------------
|
||||
* Configure USARTx CR2 (Stop bits) with parameters:
|
||||
* - Stop Bits: USART_CR2_STOP bits according to USART_InitStruct->StopBits value.
|
||||
* - CLKEN, CPOL, CPHA and LBCL bits are to be configured using LL_USART_ClockInit().
|
||||
*/
|
||||
LL_USART_SetStopBitsLength(USARTx, USART_InitStruct->StopBits);
|
||||
|
||||
/*---------------------------- USART CR3 Configuration ---------------------
|
||||
* Configure USARTx CR3 (Hardware Flow Control) with parameters:
|
||||
* - HardwareFlowControl: USART_CR3_RTSE, USART_CR3_CTSE bits according to
|
||||
* USART_InitStruct->HardwareFlowControl value.
|
||||
*/
|
||||
LL_USART_SetHWFlowCtrl(USARTx, USART_InitStruct->HardwareFlowControl);
|
||||
|
||||
/*---------------------------- USART BRR Configuration ---------------------
|
||||
* Retrieve Clock frequency used for USART Peripheral
|
||||
*/
|
||||
#if defined(USART1)
|
||||
if (USARTx == USART1)
|
||||
{
|
||||
periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART1_CLKSOURCE);
|
||||
}
|
||||
#endif /* USART1 */
|
||||
#if defined(USART1)
|
||||
else if (USARTx == USART2)
|
||||
#else
|
||||
if (USARTx == USART2)
|
||||
#endif /* USART1 */
|
||||
{
|
||||
periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART2_CLKSOURCE);
|
||||
}
|
||||
#if defined(USART4)
|
||||
else if (USARTx == USART4)
|
||||
{
|
||||
/* USART4 clock is PCLK1 */
|
||||
LL_RCC_GetSystemClocksFreq(&RCC_Clocks);
|
||||
periphclk = RCC_Clocks.PCLK1_Frequency;
|
||||
}
|
||||
#endif /* USART4 */
|
||||
#if defined(USART5)
|
||||
else if (USARTx == USART5)
|
||||
{
|
||||
/* USART5 clock is PCLK1 */
|
||||
LL_RCC_GetSystemClocksFreq(&RCC_Clocks);
|
||||
periphclk = RCC_Clocks.PCLK1_Frequency;
|
||||
}
|
||||
#endif /* USART5 */
|
||||
else
|
||||
{
|
||||
/* Nothing to do, as error code is already assigned to ERROR value */
|
||||
}
|
||||
|
||||
/* Configure the USART Baud Rate :
|
||||
- valid baud rate value (different from 0) is required
|
||||
- Peripheral clock as returned by RCC service, should be valid (different from 0).
|
||||
*/
|
||||
if ((periphclk != LL_RCC_PERIPH_FREQUENCY_NO)
|
||||
&& (USART_InitStruct->BaudRate != 0U))
|
||||
{
|
||||
status = SUCCESS;
|
||||
LL_USART_SetBaudRate(USARTx,
|
||||
periphclk,
|
||||
USART_InitStruct->OverSampling,
|
||||
USART_InitStruct->BaudRate);
|
||||
|
||||
/* Check BRR is greater than or equal to 16d */
|
||||
assert_param(IS_LL_USART_BRR_MIN(USARTx->BRR));
|
||||
}
|
||||
}
|
||||
/* Endif (=> USART not in Disabled state => return ERROR) */
|
||||
|
||||
return (status);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set each @ref LL_USART_InitTypeDef field to default value.
|
||||
* @param USART_InitStruct pointer to a @ref LL_USART_InitTypeDef structure
|
||||
* whose fields will be set to default values.
|
||||
* @retval None
|
||||
*/
|
||||
|
||||
void LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct)
|
||||
{
|
||||
/* Set USART_InitStruct fields to default values */
|
||||
USART_InitStruct->BaudRate = 9600U;
|
||||
USART_InitStruct->DataWidth = LL_USART_DATAWIDTH_8B;
|
||||
USART_InitStruct->StopBits = LL_USART_STOPBITS_1;
|
||||
USART_InitStruct->Parity = LL_USART_PARITY_NONE ;
|
||||
USART_InitStruct->TransferDirection = LL_USART_DIRECTION_TX_RX;
|
||||
USART_InitStruct->HardwareFlowControl = LL_USART_HWCONTROL_NONE;
|
||||
USART_InitStruct->OverSampling = LL_USART_OVERSAMPLING_16;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initialize USART Clock related settings according to the
|
||||
* specified parameters in the USART_ClockInitStruct.
|
||||
* @note As some bits in USART configuration registers can only be written when
|
||||
* the USART is disabled (USART_CR1_UE bit =0), USART Peripheral should be in disabled state prior calling
|
||||
* this function. Otherwise, ERROR result will be returned.
|
||||
* @param USARTx USART Instance
|
||||
* @param USART_ClockInitStruct pointer to a @ref LL_USART_ClockInitTypeDef structure
|
||||
* that contains the Clock configuration information for the specified USART peripheral.
|
||||
* @retval An ErrorStatus enumeration value:
|
||||
* - SUCCESS: USART registers related to Clock settings are initialized according
|
||||
* to USART_ClockInitStruct content
|
||||
* - ERROR: Problem occurred during USART Registers initialization
|
||||
*/
|
||||
ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
|
||||
{
|
||||
ErrorStatus status = SUCCESS;
|
||||
|
||||
/* Check USART Instance and Clock signal output parameters */
|
||||
assert_param(IS_UART_INSTANCE(USARTx));
|
||||
assert_param(IS_LL_USART_CLOCKOUTPUT(USART_ClockInitStruct->ClockOutput));
|
||||
|
||||
/* USART needs to be in disabled state, in order to be able to configure some bits in
|
||||
CRx registers */
|
||||
if (LL_USART_IsEnabled(USARTx) == 0U)
|
||||
{
|
||||
/* If USART Clock signal is disabled */
|
||||
if (USART_ClockInitStruct->ClockOutput == LL_USART_CLOCK_DISABLE)
|
||||
{
|
||||
/* Deactivate Clock signal delivery :
|
||||
* - Disable Clock Output: USART_CR2_CLKEN cleared
|
||||
*/
|
||||
LL_USART_DisableSCLKOutput(USARTx);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Ensure USART instance is USART capable */
|
||||
assert_param(IS_USART_INSTANCE(USARTx));
|
||||
|
||||
/* Check clock related parameters */
|
||||
assert_param(IS_LL_USART_CLOCKPOLARITY(USART_ClockInitStruct->ClockPolarity));
|
||||
assert_param(IS_LL_USART_CLOCKPHASE(USART_ClockInitStruct->ClockPhase));
|
||||
assert_param(IS_LL_USART_LASTBITCLKOUTPUT(USART_ClockInitStruct->LastBitClockPulse));
|
||||
|
||||
/*---------------------------- USART CR2 Configuration -----------------------
|
||||
* Configure USARTx CR2 (Clock signal related bits) with parameters:
|
||||
* - Enable Clock Output: USART_CR2_CLKEN set
|
||||
* - Clock Polarity: USART_CR2_CPOL bit according to USART_ClockInitStruct->ClockPolarity value
|
||||
* - Clock Phase: USART_CR2_CPHA bit according to USART_ClockInitStruct->ClockPhase value
|
||||
* - Last Bit Clock Pulse Output: USART_CR2_LBCL bit according to USART_ClockInitStruct->LastBitClockPulse value.
|
||||
*/
|
||||
MODIFY_REG(USARTx->CR2,
|
||||
USART_CR2_CLKEN | USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL,
|
||||
USART_CR2_CLKEN | USART_ClockInitStruct->ClockPolarity |
|
||||
USART_ClockInitStruct->ClockPhase | USART_ClockInitStruct->LastBitClockPulse);
|
||||
}
|
||||
}
|
||||
/* Else (USART not in Disabled state => return ERROR */
|
||||
else
|
||||
{
|
||||
status = ERROR;
|
||||
}
|
||||
|
||||
return (status);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set each field of a @ref LL_USART_ClockInitTypeDef type structure to default value.
|
||||
* @param USART_ClockInitStruct pointer to a @ref LL_USART_ClockInitTypeDef structure
|
||||
* whose fields will be set to default values.
|
||||
* @retval None
|
||||
*/
|
||||
void LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
|
||||
{
|
||||
/* Set LL_USART_ClockInitStruct fields with default values */
|
||||
USART_ClockInitStruct->ClockOutput = LL_USART_CLOCK_DISABLE;
|
||||
USART_ClockInitStruct->ClockPolarity = LL_USART_POLARITY_LOW; /* Not relevant when ClockOutput =
|
||||
LL_USART_CLOCK_DISABLE */
|
||||
USART_ClockInitStruct->ClockPhase = LL_USART_PHASE_1EDGE; /* Not relevant when ClockOutput =
|
||||
LL_USART_CLOCK_DISABLE */
|
||||
USART_ClockInitStruct->LastBitClockPulse = LL_USART_LASTCLKPULSE_NO_OUTPUT; /* Not relevant when ClockOutput =
|
||||
LL_USART_CLOCK_DISABLE */
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* USART1 || USART2 || USART4 || USART5 */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* USE_FULL_LL_DRIVER */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
||||
@@ -1,43 +1,52 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file LinkerScript.ld
|
||||
* @author Auto-generated by STM32CubeIDE
|
||||
* @brief Linker script for STM32L011F4Ux Device from STM32L0 series
|
||||
* 16Kbytes FLASH
|
||||
* 2Kbytes RAM
|
||||
*
|
||||
* Set heap size, stack size and stack location according
|
||||
* to application requirements.
|
||||
*
|
||||
* Set memory bank area and size if external memory is used
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2020 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
/*
|
||||
******************************************************************************
|
||||
**
|
||||
** @file : LinkerScript.ld
|
||||
**
|
||||
** @author : Auto-generated by STM32CubeIDE
|
||||
**
|
||||
** @brief : Linker script for STM32L031G6Ux Device from STM32L0 series
|
||||
** 32Kbytes FLASH
|
||||
** 8Kbytes RAM
|
||||
**
|
||||
** Set heap size, stack size and stack location according
|
||||
** to application requirements.
|
||||
**
|
||||
** Set memory bank area and size if external memory is used
|
||||
**
|
||||
** Target : STMicroelectronics STM32
|
||||
**
|
||||
** Distribution: The file is distributed as is, without any warranty
|
||||
** of any kind.
|
||||
**
|
||||
******************************************************************************
|
||||
** @attention
|
||||
**
|
||||
** <h2><center>© Copyright (c) 2021 STMicroelectronics.
|
||||
** All rights reserved.</center></h2>
|
||||
**
|
||||
** This software component is licensed by ST under BSD 3-Clause license,
|
||||
** the "License"; You may not use this file except in compliance with the
|
||||
** License. You may obtain a copy of the License at:
|
||||
** opensource.org/licenses/BSD-3-Clause
|
||||
**
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Entry Point */
|
||||
ENTRY(Reset_Handler)
|
||||
|
||||
/* Highest address of the user mode stack */
|
||||
_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
|
||||
_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
|
||||
|
||||
_Min_Heap_Size = 0x200 ; /* required amount of heap */
|
||||
_Min_Stack_Size = 0x400 ; /* required amount of stack */
|
||||
_Min_Heap_Size = 0x200 ; /* required amount of heap */
|
||||
_Min_Stack_Size = 0x400 ; /* required amount of stack */
|
||||
|
||||
/* Memories definition */
|
||||
MEMORY
|
||||
{
|
||||
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 2K
|
||||
FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 16K
|
||||
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 8K
|
||||
FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 32K
|
||||
}
|
||||
|
||||
/* Sections */
|
||||
@@ -5,6 +5,8 @@
|
||||
<booleanAttribute key="com.st.stm32cube.ide.mcu.debug.launch.enable_swv" value="false"/>
|
||||
<intAttribute key="com.st.stm32cube.ide.mcu.debug.launch.formatVersion" value="2"/>
|
||||
<stringAttribute key="com.st.stm32cube.ide.mcu.debug.launch.ip_address_local" value="localhost"/>
|
||||
<booleanAttribute key="com.st.stm32cube.ide.mcu.debug.launch.limit_swo_clock.enabled" value="false"/>
|
||||
<stringAttribute key="com.st.stm32cube.ide.mcu.debug.launch.limit_swo_clock.value" value=""/>
|
||||
<stringAttribute key="com.st.stm32cube.ide.mcu.debug.launch.loadList" value="{"fItems":[{"fIsFromMainTab":true,"fPath":"Debug/iaq_wired_sensor.elf","fProjectName":"iaq_wired_sensor","fPerformBuild":true,"fDownload":true,"fLoadSymbols":true}]}"/>
|
||||
<stringAttribute key="com.st.stm32cube.ide.mcu.debug.launch.override_start_address_mode" value="default"/>
|
||||
<stringAttribute key="com.st.stm32cube.ide.mcu.debug.launch.remoteCommand" value="target remote"/>
|
||||
@@ -14,7 +16,6 @@
|
||||
<booleanAttribute key="com.st.stm32cube.ide.mcu.debug.launch.startuptab.haltonexception" value="true"/>
|
||||
<booleanAttribute key="com.st.stm32cube.ide.mcu.debug.launch.swd_mode" value="true"/>
|
||||
<stringAttribute key="com.st.stm32cube.ide.mcu.debug.launch.swv_port" value="61235"/>
|
||||
<stringAttribute key="com.st.stm32cube.ide.mcu.debug.launch.swv_trace_div" value="8"/>
|
||||
<stringAttribute key="com.st.stm32cube.ide.mcu.debug.launch.swv_trace_hclk" value="16000000"/>
|
||||
<booleanAttribute key="com.st.stm32cube.ide.mcu.debug.launch.useRemoteTarget" value="true"/>
|
||||
<stringAttribute key="com.st.stm32cube.ide.mcu.debug.launch.vector_table" value=""/>
|
||||
@@ -27,22 +28,28 @@
|
||||
<booleanAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.enable_shared_stlink" value="false"/>
|
||||
<stringAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.external_loader" value=""/>
|
||||
<booleanAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.external_loader_init" value="false"/>
|
||||
<stringAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.frequency" value="0"/>
|
||||
<stringAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.frequency" value="24000"/>
|
||||
<booleanAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.halt_all_on_reset" value="false"/>
|
||||
<stringAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.log_file" value="/home/user/STM32CubeIDE/workspace_1.5.0/iaq_wired_sensor/Debug/st-link_gdbserver_log.txt"/>
|
||||
<stringAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.log_file" value="/home/mrs/Personal/HDIoT/Smart_Household/iaq_wired_sensor/fw/Debug/st-link_gdbserver_log.txt"/>
|
||||
<stringAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.low_power_debug" value="enable"/>
|
||||
<stringAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.max_halt_delay" value="2"/>
|
||||
<stringAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.reset_strategy" value="connect_under_reset"/>
|
||||
<booleanAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.stlink_check_serial_number" value="false"/>
|
||||
<stringAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.stlink_txt_serial_number" value=""/>
|
||||
<stringAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.watchdog_config" value="none"/>
|
||||
<booleanAttribute key="com.st.stm32cube.ide.mcu.debug.stlinkenable_rtos" value="false"/>
|
||||
<stringAttribute key="com.st.stm32cube.ide.mcu.debug.stlinkrestart_configurations" value="{"fItems":[{"fDisplayName":"Reset","fIsSuppressible":false,"fResetAttribute":"Software system reset","fResetStrategies":[{"fDisplayName":"Software system reset","fLaunchAttribute":"system_reset","fGdbCommands":["monitor reset\n"],"fCmdOptions":["-g"]},{"fDisplayName":"Hardware reset","fLaunchAttribute":"hardware_reset","fGdbCommands":["monitor reset hardware\n"],"fCmdOptions":["-g"]},{"fDisplayName":"Core reset","fLaunchAttribute":"core_reset","fGdbCommands":["monitor reset core\n"],"fCmdOptions":["-g"]},{"fDisplayName":"None","fLaunchAttribute":"no_reset","fGdbCommands":[],"fCmdOptions":["-g"]}],"fGdbCommandGroup":{"name":"Additional commands","commands":[]}}]}"/>
|
||||
<booleanAttribute key="com.st.stm32cube.ide.mcu.debug.swv.swv_wait_for_sync" value="true"/>
|
||||
<booleanAttribute key="com.st.stm32cube.ide.mcu.rtosproxy.enableRtosProxy" value="false"/>
|
||||
<stringAttribute key="com.st.stm32cube.ide.mcu.rtosproxy.rtosProxyCustomProperties" value=""/>
|
||||
<stringAttribute key="com.st.stm32cube.ide.mcu.rtosproxy.rtosProxyDriver" value="threadx"/>
|
||||
<booleanAttribute key="com.st.stm32cube.ide.mcu.rtosproxy.rtosProxyDriverAuto" value="false"/>
|
||||
<stringAttribute key="com.st.stm32cube.ide.mcu.rtosproxy.rtosProxyDriverPort" value="cortex_m0"/>
|
||||
<intAttribute key="com.st.stm32cube.ide.mcu.rtosproxy.rtosProxyPort" value="60000"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.doHalt" value="false"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.doReset" value="false"/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.initCommands" value=""/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.ipAddress" value="localhost"/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.jtagDevice" value="ST-LINK (ST-LINK GDB server)"/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.jtagDeviceId" value="com.st.stm32cube.ide.mcu.debug.stlink"/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.pcRegister" value=""/>
|
||||
<intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.portNumber" value="61234"/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.runCommands" value=""/>
|
||||
@@ -61,13 +68,13 @@
|
||||
<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Debug/iaq_wired_sensor.elf"/>
|
||||
<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="iaq_wired_sensor"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_AUTO_ATTR" value="true"/>
|
||||
<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.debug.1512690796"/>
|
||||
<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.debug.583977815"/>
|
||||
<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
|
||||
<listEntry value="/iaq_wired_sensor"/>
|
||||
</listAttribute>
|
||||
<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
|
||||
<listEntry value="4"/>
|
||||
</listAttribute>
|
||||
<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?><memoryBlockExpressionList context="reserved-for-future-use"><gdbmemoryBlockExpression address="134742016" label="0x08080000"/><gdbmemoryBlockExpression address="134742020" label="0x08080004"/><gdbmemoryBlockExpression address="134742016" label="0x08080000"/></memoryBlockExpressionList>"/>
|
||||
<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?><memoryBlockExpressionList context="reserved-for-future-use"/>"/>
|
||||
<stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/>
|
||||
</launchConfiguration>
|
||||
|
||||
@@ -4,77 +4,70 @@ GPIO.groupedBy=Group By Peripherals
|
||||
I2C1.IPParameters=Timing
|
||||
I2C1.Timing=0x40000A0B
|
||||
KeepUserPlacement=false
|
||||
LPUART1.BaudRate=115200
|
||||
LPUART1.IPParameters=BaudRate,SwapParam,OneBitSampling,WordLength,Parity
|
||||
LPUART1.OneBitSampling=UART_ONE_BIT_SAMPLE_ENABLE
|
||||
LPUART1.Parity=UART_PARITY_EVEN
|
||||
LPUART1.SwapParam=UART_ADVFEATURE_SWAP_ENABLE
|
||||
LPUART1.WordLength=UART_WORDLENGTH_9B
|
||||
Mcu.Family=STM32L0
|
||||
Mcu.IP0=I2C1
|
||||
Mcu.IP1=LPUART1
|
||||
Mcu.IP2=NVIC
|
||||
Mcu.IP3=RCC
|
||||
Mcu.IP4=SYS
|
||||
Mcu.IP5=TIM21
|
||||
Mcu.IP1=NVIC
|
||||
Mcu.IP2=RCC
|
||||
Mcu.IP3=SYS
|
||||
Mcu.IP4=TIM21
|
||||
Mcu.IP5=USART2
|
||||
Mcu.IPNb=6
|
||||
Mcu.Name=STM32L011F(3-4)Ux
|
||||
Mcu.Package=UFQFPN20
|
||||
Mcu.Pin0=PA0-CK_IN
|
||||
Mcu.Pin1=PA1
|
||||
Mcu.Pin10=VP_TIM21_VS_ClockSourceINT
|
||||
Mcu.Pin2=PA5
|
||||
Mcu.Pin3=PA6
|
||||
Mcu.Pin4=PA7
|
||||
Mcu.Pin5=PA9
|
||||
Mcu.Pin6=PA10
|
||||
Mcu.Pin7=PA13
|
||||
Mcu.Pin8=PA14
|
||||
Mcu.Pin9=VP_SYS_VS_Systick
|
||||
Mcu.PinsNb=11
|
||||
Mcu.Name=STM32L031G(4-6)Ux
|
||||
Mcu.Package=UFQFPN28
|
||||
Mcu.Pin0=PA1
|
||||
Mcu.Pin1=PA2
|
||||
Mcu.Pin10=VP_SYS_VS_Systick
|
||||
Mcu.Pin11=VP_TIM21_VS_ClockSourceINT
|
||||
Mcu.Pin2=PA3
|
||||
Mcu.Pin3=PA5
|
||||
Mcu.Pin4=PA6
|
||||
Mcu.Pin5=PA7
|
||||
Mcu.Pin6=PA9
|
||||
Mcu.Pin7=PA10
|
||||
Mcu.Pin8=PA13
|
||||
Mcu.Pin9=PA14
|
||||
Mcu.PinsNb=12
|
||||
Mcu.ThirdPartyNb=0
|
||||
Mcu.UserConstants=
|
||||
Mcu.UserName=STM32L011F4Ux
|
||||
MxCube.Version=6.2.1
|
||||
MxDb.Version=DB.6.0.21
|
||||
Mcu.UserName=STM32L031G6Ux
|
||||
MxCube.Version=6.3.0
|
||||
MxDb.Version=DB.6.0.30
|
||||
NVIC.ForceEnableDMAVector=true
|
||||
NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
|
||||
NVIC.LPUART1_IRQn=true\:0\:0\:false\:false\:true\:true\:true
|
||||
NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false
|
||||
NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false
|
||||
NVIC.SVC_IRQn=true\:0\:0\:false\:false\:true\:false\:false
|
||||
NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false\:true
|
||||
NVIC.SysTick_IRQn=true\:3\:0\:false\:false\:true\:false\:true
|
||||
NVIC.TIM21_IRQn=true\:0\:0\:false\:false\:true\:true\:true
|
||||
PA0-CK_IN.GPIOParameters=GPIO_PuPd
|
||||
PA0-CK_IN.GPIO_PuPd=GPIO_PULLUP
|
||||
PA0-CK_IN.Mode=Asynchronous
|
||||
PA0-CK_IN.Signal=LPUART1_RX
|
||||
PA1.GPIOParameters=GPIO_PuPd
|
||||
PA1.GPIO_PuPd=GPIO_PULLUP
|
||||
PA1.Mode=Asynchronous
|
||||
PA1.Signal=LPUART1_TX
|
||||
NVIC.USART2_IRQn=true\:0\:0\:false\:false\:true\:true\:true
|
||||
PA1.Mode=Hardware Flow Control (RS485)
|
||||
PA1.Signal=USART2_DE
|
||||
PA10.GPIOParameters=GPIO_Pu
|
||||
PA10.GPIO_Pu=GPIO_PULLUP
|
||||
PA10.Mode=I2C
|
||||
PA10.Signal=I2C1_SDA
|
||||
PA13.Mode=Serial_Wire
|
||||
PA13.Signal=SYS_SWDIO
|
||||
PA14.Mode=Serial_Wire
|
||||
PA14.Signal=SYS_SWCLK
|
||||
PA5.GPIOParameters=PinState,GPIO_Label
|
||||
PA2.Mode=Asynchronous
|
||||
PA2.Signal=USART2_TX
|
||||
PA3.Mode=Asynchronous
|
||||
PA3.Signal=USART2_RX
|
||||
PA5.GPIOParameters=GPIO_Label
|
||||
PA5.GPIO_Label=LED_B
|
||||
PA5.Locked=true
|
||||
PA5.PinState=GPIO_PIN_SET
|
||||
PA5.Signal=GPIO_Output
|
||||
PA6.GPIOParameters=PinState,GPIO_Label
|
||||
PA6.GPIOParameters=GPIO_Label
|
||||
PA6.GPIO_Label=LED_G
|
||||
PA6.Locked=true
|
||||
PA6.PinState=GPIO_PIN_SET
|
||||
PA6.Signal=GPIO_Output
|
||||
PA7.GPIOParameters=PinState,GPIO_Label
|
||||
PA7.GPIOParameters=GPIO_Label
|
||||
PA7.GPIO_Label=LED_R
|
||||
PA7.Locked=true
|
||||
PA7.PinState=GPIO_PIN_SET
|
||||
PA7.Signal=GPIO_Output
|
||||
PA9.Locked=true
|
||||
PA9.GPIOParameters=GPIO_Pu
|
||||
PA9.GPIO_Pu=GPIO_PULLUP
|
||||
PA9.Mode=I2C
|
||||
PA9.Signal=I2C1_SCL
|
||||
PinOutPanel.RotationAngle=0
|
||||
@@ -86,8 +79,8 @@ ProjectManager.CoupleFile=false
|
||||
ProjectManager.CustomerFirmwarePackage=
|
||||
ProjectManager.DefaultFWLocation=true
|
||||
ProjectManager.DeletePrevious=true
|
||||
ProjectManager.DeviceId=STM32L011F4Ux
|
||||
ProjectManager.FirmwarePackage=STM32Cube FW_L0 V1.12.0
|
||||
ProjectManager.DeviceId=STM32L031G6Ux
|
||||
ProjectManager.FirmwarePackage=STM32Cube FW_L0 V1.12.1
|
||||
ProjectManager.FreePins=false
|
||||
ProjectManager.HalAssertFull=false
|
||||
ProjectManager.HeapSize=0x200
|
||||
@@ -105,7 +98,7 @@ ProjectManager.StackSize=0x400
|
||||
ProjectManager.TargetToolchain=STM32CubeIDE
|
||||
ProjectManager.ToolChainLocation=
|
||||
ProjectManager.UnderRoot=true
|
||||
ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-LL-true,2-SystemClock_Config-RCC-false-LL-false,3-MX_I2C1_Init-I2C1-false-LL-true,4-MX_LPUART1_UART_Init-LPUART1-false-LL-true,5-MX_TIM21_Init-TIM21-false-LL-true
|
||||
ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-LL-false,2-MX_GPIO_Init-GPIO-false-LL-true,3-MX_I2C1_Init-I2C1-false-LL-true,4-MX_USART2_UART_Init-USART2-false-LL-true,5-MX_TIM21_Init-TIM21-false-LL-true
|
||||
RCC.AHBFreq_Value=12000000
|
||||
RCC.APB1Freq_Value=12000000
|
||||
RCC.APB1TimFreq_Value=12000000
|
||||
@@ -138,13 +131,20 @@ RCC.USART2Freq_Value=12000000
|
||||
RCC.VCOOutputFreq_Value=48000000
|
||||
RCC.WatchDogFreq_Value=37000
|
||||
TIM21.AutoReloadPreload=TIM_AUTORELOAD_PRELOAD_ENABLE
|
||||
TIM21.ClockDivision=TIM_CLOCKDIVISION_DIV1
|
||||
TIM21.IPParameters=Prescaler,Period,AutoReloadPreload,ClockDivision
|
||||
TIM21.IPParameters=Prescaler,Period,AutoReloadPreload
|
||||
TIM21.IPParametersWithoutCheck=Prescaler,Period
|
||||
TIM21.Period=tim21_period
|
||||
TIM21.Prescaler=tim21_prescaler
|
||||
USART2.BaudRate=config_baudrates[sensor_config.baudrate_index]
|
||||
USART2.IPParameters=VirtualMode-Asynchronous,VirtualMode-Hardware Flow Control (RS485),BaudRate,WordLength,Parity
|
||||
USART2.IPParametersWithoutCheck=BaudRate
|
||||
USART2.Parity=PARITY_EVEN
|
||||
USART2.VirtualMode-Asynchronous=VM_ASYNC
|
||||
USART2.VirtualMode-Hardware\ Flow\ Control\ (RS485)=VM_ASYNC
|
||||
USART2.WordLength=WORDLENGTH_9B
|
||||
VP_SYS_VS_Systick.Mode=SysTick
|
||||
VP_SYS_VS_Systick.Signal=SYS_VS_Systick
|
||||
VP_TIM21_VS_ClockSourceINT.Mode=Internal
|
||||
VP_TIM21_VS_ClockSourceINT.Signal=TIM21_VS_ClockSourceINT
|
||||
board=custom
|
||||
isbadioc=false
|
||||
|
||||
Reference in New Issue
Block a user