Created a testing panel
This commit is contained in:
David Žaitlík
parent
6f610a474a
commit
8b6c134d04
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{
|
||||
"Type": "Legend",
|
||||
"Notes": "Layer B.SilkS"
|
||||
}
|
||||
]
|
||||
}
|
||||
76070
PCB_25x25mm_4Layers/Test_Panel/fp-info-cache
Normal file
76070
PCB_25x25mm_4Layers/Test_Panel/fp-info-cache
Normal file
File diff suppressed because it is too large
Load Diff
12095
PCB_25x25mm_4Layers/Test_Panel/rht_wired_sensor_panel2x2.kicad_pcb
Normal file
12095
PCB_25x25mm_4Layers/Test_Panel/rht_wired_sensor_panel2x2.kicad_pcb
Normal file
File diff suppressed because it is too large
Load Diff
12095
PCB_25x25mm_4Layers/Test_Panel/rht_wired_sensor_panel2x2.kicad_pcb-bak
Normal file
12095
PCB_25x25mm_4Layers/Test_Panel/rht_wired_sensor_panel2x2.kicad_pcb-bak
Normal file
File diff suppressed because it is too large
Load Diff
33
PCB_25x25mm_4Layers/Test_Panel/rht_wired_sensor_panel2x2.pro
Normal file
33
PCB_25x25mm_4Layers/Test_Panel/rht_wired_sensor_panel2x2.pro
Normal file
@ -0,0 +1,33 @@
|
||||
update=22/05/2015 07:44:53
|
||||
version=1
|
||||
last_client=kicad
|
||||
[general]
|
||||
version=1
|
||||
RootSch=
|
||||
BoardNm=
|
||||
[pcbnew]
|
||||
version=1
|
||||
LastNetListRead=
|
||||
UseCmpFile=1
|
||||
PadDrill=0.600000000000
|
||||
PadDrillOvalY=0.600000000000
|
||||
PadSizeH=1.500000000000
|
||||
PadSizeV=1.500000000000
|
||||
PcbTextSizeV=1.500000000000
|
||||
PcbTextSizeH=1.500000000000
|
||||
PcbTextThickness=0.300000000000
|
||||
ModuleTextSizeV=1.000000000000
|
||||
ModuleTextSizeH=1.000000000000
|
||||
ModuleTextSizeThickness=0.150000000000
|
||||
SolderMaskClearance=0.000000000000
|
||||
SolderMaskMinWidth=0.000000000000
|
||||
DrawSegmentWidth=0.200000000000
|
||||
BoardOutlineThickness=0.100000000000
|
||||
ModuleOutlineThickness=0.150000000000
|
||||
[cvpcb]
|
||||
version=1
|
||||
NetIExt=net
|
||||
[eeschema]
|
||||
version=1
|
||||
LibDir=
|
||||
[eeschema/libraries]
|
||||
Loading…
Reference in New Issue
Block a user