diff --git a/fw/.cproject b/fw/.cproject
new file mode 100644
index 0000000..d0b83b4
--- /dev/null
+++ b/fw/.cproject
@@ -0,0 +1,171 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
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diff --git a/fw/.mxproject b/fw/.mxproject
new file mode 100644
index 0000000..7c0e167
--- /dev/null
+++ b/fw/.mxproject
@@ -0,0 +1,25 @@
+[PreviousLibFiles]
+LibFiles=Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h;Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma_ex.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_exti.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h;Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma_ex.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_exti.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h;Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l011xx.h;Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h;Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h;Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/system_stm32l0xx.c;Drivers/CMSIS/Include/core_cm0.h;Drivers/CMSIS/Include/core_armv8mbl.h;Drivers/CMSIS/Include/core_cm1.h;Drivers/CMSIS/Include/cmsis_gcc.h;Drivers/CMSIS/Include/mpu_armv8.h;Drivers/CMSIS/Include/core_cm3.h;Drivers/CMSIS/Include/core_sc300.h;Drivers/CMSIS/Include/core_cm23.h;Drivers/CMSIS/Include/core_cm7.h;Drivers/CMSIS/Include/tz_context.h;Drivers/CMSIS/Include/mpu_armv7.h;Drivers/CMSIS/Include/core_armv8mml.h;Drivers/CMSIS/Include/core_sc000.h;Drivers/CMSIS/Include/cmsis_version.h;Drivers/CMSIS/Include/core_cm0plus.h;Drivers/CMSIS/Include/cmsis_armclang.h;Drivers/CMSIS/Include/cmsis_iccarm.h;Drivers/CMSIS/Include/cmsis_compiler.h;Drivers/CMSIS/Include/cmsis_armcc.h;Drivers/CMSIS/Include/core_cm33.h;Drivers/CMSIS/Include/core_cm4.h;
+
+[PreviousUsedCubeIDEFiles]
+SourceFiles=Core/Src/main.c;Core/Src/stm32l0xx_it.c;Core/Src/stm32l0xx_hal_msp.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c;Core/Src/system_stm32l0xx.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c;Core/Src/system_stm32l0xx.c;Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/system_stm32l0xx.c;;
+HeaderPath=Drivers/STM32L0xx_HAL_Driver/Inc;Drivers/STM32L0xx_HAL_Driver/Inc/Legacy;Drivers/CMSIS/Device/ST/STM32L0xx/Include;Drivers/CMSIS/Include;Core/Inc;
+CDefines=USE_HAL_DRIVER;STM32L011xx;USE_HAL_DRIVER;USE_HAL_DRIVER;
+
+[PreviousGenFiles]
+AdvancedFolderStructure=true
+HeaderFileListSize=3
+HeaderFiles#0=/home/user/STM32CubeIDE/workspace_1.5.0/iaq_wired_sensor/Core/Inc/stm32l0xx_it.h
+HeaderFiles#1=/home/user/STM32CubeIDE/workspace_1.5.0/iaq_wired_sensor/Core/Inc/stm32l0xx_hal_conf.h
+HeaderFiles#2=/home/user/STM32CubeIDE/workspace_1.5.0/iaq_wired_sensor/Core/Inc/main.h
+HeaderFolderListSize=1
+HeaderPath#0=/home/user/STM32CubeIDE/workspace_1.5.0/iaq_wired_sensor/Core/Inc
+HeaderFiles=;
+SourceFileListSize=3
+SourceFiles#0=/home/user/STM32CubeIDE/workspace_1.5.0/iaq_wired_sensor/Core/Src/stm32l0xx_it.c
+SourceFiles#1=/home/user/STM32CubeIDE/workspace_1.5.0/iaq_wired_sensor/Core/Src/stm32l0xx_hal_msp.c
+SourceFiles#2=/home/user/STM32CubeIDE/workspace_1.5.0/iaq_wired_sensor/Core/Src/main.c
+SourceFolderListSize=1
+SourcePath#0=/home/user/STM32CubeIDE/workspace_1.5.0/iaq_wired_sensor/Core/Src
+SourceFiles=;
+
diff --git a/fw/.project b/fw/.project
new file mode 100644
index 0000000..6232ccb
--- /dev/null
+++ b/fw/.project
@@ -0,0 +1,33 @@
+
+
+ iaq_wired_sensor
+
+
+
+
+ org.eclipse.cdt.managedbuilder.core.genmakebuilder
+ clean,full,incremental,
+
+
+
+
+ org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder
+ full,incremental,
+
+
+
+
+
+ com.st.stm32cube.ide.mcu.MCUProjectNature
+ com.st.stm32cube.ide.mcu.MCUCubeProjectNature
+ org.eclipse.cdt.core.cnature
+ com.st.stm32cube.ide.mcu.MCUCubeIdeServicesRevAev2ProjectNature
+ com.st.stm32cube.ide.mcu.MCUAdvancedStructureProjectNature
+ com.st.stm32cube.ide.mcu.MCUEndUserDisabledTrustZoneProjectNature
+ com.st.stm32cube.ide.mcu.MCUSingleCpuProjectNature
+ com.st.stm32cube.ide.mcu.MCURootProjectNature
+ org.eclipse.cdt.managedbuilder.core.managedBuildNature
+ org.eclipse.cdt.managedbuilder.core.ScannerConfigNature
+
+
diff --git a/fw/.settings/language.settings.xml b/fw/.settings/language.settings.xml
new file mode 100644
index 0000000..87c8372
--- /dev/null
+++ b/fw/.settings/language.settings.xml
@@ -0,0 +1,27 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/fw/.settings/stm32cubeide.project.prefs b/fw/.settings/stm32cubeide.project.prefs
new file mode 100644
index 0000000..ae186d6
--- /dev/null
+++ b/fw/.settings/stm32cubeide.project.prefs
@@ -0,0 +1,3 @@
+8DF89ED150041C4CBC7CB9A9CAA90856=295E78E9D51884086204F31037537306
+DC22A860405A8BF2F2C095E5B6529F12=295E78E9D51884086204F31037537306
+eclipse.preferences.version=1
diff --git a/fw/Core/Inc/main.h b/fw/Core/Inc/main.h
new file mode 100644
index 0000000..85dd1dc
--- /dev/null
+++ b/fw/Core/Inc/main.h
@@ -0,0 +1,77 @@
+/* USER CODE BEGIN Header */
+/**
+ ******************************************************************************
+ * @file : main.h
+ * @brief : Header for main.c file.
+ * This file contains the common defines of the application.
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved. © Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved. © Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved. © Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved. © Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved. © Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved. © Copyright (c) 2020 STMicroelectronics.
+ * All rights reserved.
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+
+/* Variables */
+//#undef errno
+extern int errno;
+extern int __io_putchar(int ch) __attribute__((weak));
+extern int __io_getchar(void) __attribute__((weak));
+
+register char * stack_ptr asm("sp");
+
+char *__env[1] = { 0 };
+char **environ = __env;
+
+
+/* Functions */
+void initialise_monitor_handles()
+{
+}
+
+int _getpid(void)
+{
+ return 1;
+}
+
+int _kill(int pid, int sig)
+{
+ errno = EINVAL;
+ return -1;
+}
+
+void _exit (int status)
+{
+ _kill(status, -1);
+ while (1) {} /* Make sure we hang here */
+}
+
+__attribute__((weak)) int _read(int file, char *ptr, int len)
+{
+ int DataIdx;
+
+ for (DataIdx = 0; DataIdx < len; DataIdx++)
+ {
+ *ptr++ = __io_getchar();
+ }
+
+return len;
+}
+
+__attribute__((weak)) int _write(int file, char *ptr, int len)
+{
+ int DataIdx;
+
+ for (DataIdx = 0; DataIdx < len; DataIdx++)
+ {
+ __io_putchar(*ptr++);
+ }
+ return len;
+}
+
+int _close(int file)
+{
+ return -1;
+}
+
+
+int _fstat(int file, struct stat *st)
+{
+ st->st_mode = S_IFCHR;
+ return 0;
+}
+
+int _isatty(int file)
+{
+ return 1;
+}
+
+int _lseek(int file, int ptr, int dir)
+{
+ return 0;
+}
+
+int _open(char *path, int flags, ...)
+{
+ /* Pretend like we always fail */
+ return -1;
+}
+
+int _wait(int *status)
+{
+ errno = ECHILD;
+ return -1;
+}
+
+int _unlink(char *name)
+{
+ errno = ENOENT;
+ return -1;
+}
+
+int _times(struct tms *buf)
+{
+ return -1;
+}
+
+int _stat(char *file, struct stat *st)
+{
+ st->st_mode = S_IFCHR;
+ return 0;
+}
+
+int _link(char *old, char *new)
+{
+ errno = EMLINK;
+ return -1;
+}
+
+int _fork(void)
+{
+ errno = EAGAIN;
+ return -1;
+}
+
+int _execve(char *name, char **argv, char **env)
+{
+ errno = ENOMEM;
+ return -1;
+}
diff --git a/fw/Core/Src/sysmem.c b/fw/Core/Src/sysmem.c
new file mode 100644
index 0000000..d7cc52c
--- /dev/null
+++ b/fw/Core/Src/sysmem.c
@@ -0,0 +1,80 @@
+/**
+ ******************************************************************************
+ * @file sysmem.c
+ * @author Generated by STM32CubeIDE
+ * @brief STM32CubeIDE System Memory calls file
+ *
+ * For more information about which C functions
+ * need which of these lowlevel functions
+ * please consult the newlib libc manual
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2020 STMicroelectronics.
+ * All rights reserved.
+#include
+
+/**
+ * Pointer to the current high watermark of the heap usage
+ */
+static uint8_t *__sbrk_heap_end = NULL;
+
+/**
+ * @brief _sbrk() allocates memory to the newlib heap and is used by malloc
+ * and others from the C library
+ *
+ * @verbatim
+ * ############################################################################
+ * # .data # .bss # newlib heap # MSP stack #
+ * # # # # Reserved by _Min_Stack_Size #
+ * ############################################################################
+ * ^-- RAM start ^-- _end _estack, RAM end --^
+ * @endverbatim
+ *
+ * This implementation starts allocating at the '_end' linker symbol
+ * The '_Min_Stack_Size' linker symbol reserves a memory for the MSP stack
+ * The implementation considers '_estack' linker symbol to be RAM end
+ * NOTE: If the MSP stack, at any point during execution, grows larger than the
+ * reserved size, please increase the '_Min_Stack_Size'.
+ *
+ * @param incr Memory size
+ * @return Pointer to allocated memory
+ */
+void *_sbrk(ptrdiff_t incr)
+{
+ extern uint8_t _end; /* Symbol defined in the linker script */
+ extern uint8_t _estack; /* Symbol defined in the linker script */
+ extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */
+ const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size;
+ const uint8_t *max_heap = (uint8_t *)stack_limit;
+ uint8_t *prev_heap_end;
+
+ /* Initialize heap end at first call */
+ if (NULL == __sbrk_heap_end)
+ {
+ __sbrk_heap_end = &_end;
+ }
+
+ /* Protect heap from growing into the reserved MSP stack */
+ if (__sbrk_heap_end + incr > max_heap)
+ {
+ errno = ENOMEM;
+ return (void *)-1;
+ }
+
+ prev_heap_end = __sbrk_heap_end;
+ __sbrk_heap_end += incr;
+
+ return (void *)prev_heap_end;
+}
diff --git a/fw/Core/Src/system_stm32l0xx.c b/fw/Core/Src/system_stm32l0xx.c
new file mode 100644
index 0000000..9189ed8
--- /dev/null
+++ b/fw/Core/Src/system_stm32l0xx.c
@@ -0,0 +1,275 @@
+/**
+ ******************************************************************************
+ * @file system_stm32l0xx.c
+ * @author MCD Application Team
+ * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Source File.
+ *
+ * This file provides two functions and one global variable to be called from
+ * user application:
+ * - SystemInit(): This function is called at startup just after reset and
+ * before branch to main program. This call is made inside
+ * the "startup_stm32l0xx.s" file.
+ *
+ * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+ * by the user application to setup the SysTick
+ * timer or configure other parameters.
+ *
+ * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+ * be called whenever the core clock is changed
+ * during program execution.
+ *
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright(c) 2016 STMicroelectronics.
+ * All rights reserved. © Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved. :
+ 80000e8: 4b04 ldr r3, [pc, #16] ; (80000fc )
+ 80000ea: b510 push {r4, lr}
+ 80000ec: 2b00 cmp r3, #0
+ 80000ee: d003 beq.n 80000f8
+ 80000f0: 4903 ldr r1, [pc, #12] ; (8000100 )
+ 80000f2: 4804 ldr r0, [pc, #16] ; (8000104 )
+ 80000f4: e000 b.n 80000f8
+ 80000f6: bf00 nop
+ 80000f8: bd10 pop {r4, pc}
+ 80000fa: 46c0 nop ; (mov r8, r8)
+ 80000fc: 00000000 .word 0x00000000
+ 8000100: 20000010 .word 0x20000010
+ 8000104: 080027cc .word 0x080027cc
+
+08000108 <__udivsi3>:
+ 8000108: 2200 movs r2, #0
+ 800010a: 0843 lsrs r3, r0, #1
+ 800010c: 428b cmp r3, r1
+ 800010e: d374 bcc.n 80001fa <__udivsi3+0xf2>
+ 8000110: 0903 lsrs r3, r0, #4
+ 8000112: 428b cmp r3, r1
+ 8000114: d35f bcc.n 80001d6 <__udivsi3+0xce>
+ 8000116: 0a03 lsrs r3, r0, #8
+ 8000118: 428b cmp r3, r1
+ 800011a: d344 bcc.n 80001a6 <__udivsi3+0x9e>
+ 800011c: 0b03 lsrs r3, r0, #12
+ 800011e: 428b cmp r3, r1
+ 8000120: d328 bcc.n 8000174 <__udivsi3+0x6c>
+ 8000122: 0c03 lsrs r3, r0, #16
+ 8000124: 428b cmp r3, r1
+ 8000126: d30d bcc.n 8000144 <__udivsi3+0x3c>
+ 8000128: 22ff movs r2, #255 ; 0xff
+ 800012a: 0209 lsls r1, r1, #8
+ 800012c: ba12 rev r2, r2
+ 800012e: 0c03 lsrs r3, r0, #16
+ 8000130: 428b cmp r3, r1
+ 8000132: d302 bcc.n 800013a <__udivsi3+0x32>
+ 8000134: 1212 asrs r2, r2, #8
+ 8000136: 0209 lsls r1, r1, #8
+ 8000138: d065 beq.n 8000206 <__udivsi3+0xfe>
+ 800013a: 0b03 lsrs r3, r0, #12
+ 800013c: 428b cmp r3, r1
+ 800013e: d319 bcc.n 8000174 <__udivsi3+0x6c>
+ 8000140: e000 b.n 8000144 <__udivsi3+0x3c>
+ 8000142: 0a09 lsrs r1, r1, #8
+ 8000144: 0bc3 lsrs r3, r0, #15
+ 8000146: 428b cmp r3, r1
+ 8000148: d301 bcc.n 800014e <__udivsi3+0x46>
+ 800014a: 03cb lsls r3, r1, #15
+ 800014c: 1ac0 subs r0, r0, r3
+ 800014e: 4152 adcs r2, r2
+ 8000150: 0b83 lsrs r3, r0, #14
+ 8000152: 428b cmp r3, r1
+ 8000154: d301 bcc.n 800015a <__udivsi3+0x52>
+ 8000156: 038b lsls r3, r1, #14
+ 8000158: 1ac0 subs r0, r0, r3
+ 800015a: 4152 adcs r2, r2
+ 800015c: 0b43 lsrs r3, r0, #13
+ 800015e: 428b cmp r3, r1
+ 8000160: d301 bcc.n 8000166 <__udivsi3+0x5e>
+ 8000162: 034b lsls r3, r1, #13
+ 8000164: 1ac0 subs r0, r0, r3
+ 8000166: 4152 adcs r2, r2
+ 8000168: 0b03 lsrs r3, r0, #12
+ 800016a: 428b cmp r3, r1
+ 800016c: d301 bcc.n 8000172 <__udivsi3+0x6a>
+ 800016e: 030b lsls r3, r1, #12
+ 8000170: 1ac0 subs r0, r0, r3
+ 8000172: 4152 adcs r2, r2
+ 8000174: 0ac3 lsrs r3, r0, #11
+ 8000176: 428b cmp r3, r1
+ 8000178: d301 bcc.n 800017e <__udivsi3+0x76>
+ 800017a: 02cb lsls r3, r1, #11
+ 800017c: 1ac0 subs r0, r0, r3
+ 800017e: 4152 adcs r2, r2
+ 8000180: 0a83 lsrs r3, r0, #10
+ 8000182: 428b cmp r3, r1
+ 8000184: d301 bcc.n 800018a <__udivsi3+0x82>
+ 8000186: 028b lsls r3, r1, #10
+ 8000188: 1ac0 subs r0, r0, r3
+ 800018a: 4152 adcs r2, r2
+ 800018c: 0a43 lsrs r3, r0, #9
+ 800018e: 428b cmp r3, r1
+ 8000190: d301 bcc.n 8000196 <__udivsi3+0x8e>
+ 8000192: 024b lsls r3, r1, #9
+ 8000194: 1ac0 subs r0, r0, r3
+ 8000196: 4152 adcs r2, r2
+ 8000198: 0a03 lsrs r3, r0, #8
+ 800019a: 428b cmp r3, r1
+ 800019c: d301 bcc.n 80001a2 <__udivsi3+0x9a>
+ 800019e: 020b lsls r3, r1, #8
+ 80001a0: 1ac0 subs r0, r0, r3
+ 80001a2: 4152 adcs r2, r2
+ 80001a4: d2cd bcs.n 8000142 <__udivsi3+0x3a>
+ 80001a6: 09c3 lsrs r3, r0, #7
+ 80001a8: 428b cmp r3, r1
+ 80001aa: d301 bcc.n 80001b0 <__udivsi3+0xa8>
+ 80001ac: 01cb lsls r3, r1, #7
+ 80001ae: 1ac0 subs r0, r0, r3
+ 80001b0: 4152 adcs r2, r2
+ 80001b2: 0983 lsrs r3, r0, #6
+ 80001b4: 428b cmp r3, r1
+ 80001b6: d301 bcc.n 80001bc <__udivsi3+0xb4>
+ 80001b8: 018b lsls r3, r1, #6
+ 80001ba: 1ac0 subs r0, r0, r3
+ 80001bc: 4152 adcs r2, r2
+ 80001be: 0943 lsrs r3, r0, #5
+ 80001c0: 428b cmp r3, r1
+ 80001c2: d301 bcc.n 80001c8 <__udivsi3+0xc0>
+ 80001c4: 014b lsls r3, r1, #5
+ 80001c6: 1ac0 subs r0, r0, r3
+ 80001c8: 4152 adcs r2, r2
+ 80001ca: 0903 lsrs r3, r0, #4
+ 80001cc: 428b cmp r3, r1
+ 80001ce: d301 bcc.n 80001d4 <__udivsi3+0xcc>
+ 80001d0: 010b lsls r3, r1, #4
+ 80001d2: 1ac0 subs r0, r0, r3
+ 80001d4: 4152 adcs r2, r2
+ 80001d6: 08c3 lsrs r3, r0, #3
+ 80001d8: 428b cmp r3, r1
+ 80001da: d301 bcc.n 80001e0 <__udivsi3+0xd8>
+ 80001dc: 00cb lsls r3, r1, #3
+ 80001de: 1ac0 subs r0, r0, r3
+ 80001e0: 4152 adcs r2, r2
+ 80001e2: 0883 lsrs r3, r0, #2
+ 80001e4: 428b cmp r3, r1
+ 80001e6: d301 bcc.n 80001ec <__udivsi3+0xe4>
+ 80001e8: 008b lsls r3, r1, #2
+ 80001ea: 1ac0 subs r0, r0, r3
+ 80001ec: 4152 adcs r2, r2
+ 80001ee: 0843 lsrs r3, r0, #1
+ 80001f0: 428b cmp r3, r1
+ 80001f2: d301 bcc.n 80001f8 <__udivsi3+0xf0>
+ 80001f4: 004b lsls r3, r1, #1
+ 80001f6: 1ac0 subs r0, r0, r3
+ 80001f8: 4152 adcs r2, r2
+ 80001fa: 1a41 subs r1, r0, r1
+ 80001fc: d200 bcs.n 8000200 <__udivsi3+0xf8>
+ 80001fe: 4601 mov r1, r0
+ 8000200: 4152 adcs r2, r2
+ 8000202: 4610 mov r0, r2
+ 8000204: 4770 bx lr
+ 8000206: e7ff b.n 8000208 <__udivsi3+0x100>
+ 8000208: b501 push {r0, lr}
+ 800020a: 2000 movs r0, #0
+ 800020c: f000 f806 bl 800021c <__aeabi_idiv0>
+ 8000210: bd02 pop {r1, pc}
+ 8000212: 46c0 nop ; (mov r8, r8)
+
+08000214 <__aeabi_uidivmod>:
+ 8000214: 2900 cmp r1, #0
+ 8000216: d0f7 beq.n 8000208 <__udivsi3+0x100>
+ 8000218: e776 b.n 8000108 <__udivsi3>
+ 800021a: 4770 bx lr
+
+0800021c <__aeabi_idiv0>:
+ 800021c: 4770 bx lr
+ 800021e: 46c0 nop ; (mov r8, r8)
+
+08000220 <__aeabi_uldivmod>:
+ 8000220: 2b00 cmp r3, #0
+ 8000222: d111 bne.n 8000248 <__aeabi_uldivmod+0x28>
+ 8000224: 2a00 cmp r2, #0
+ 8000226: d10f bne.n 8000248 <__aeabi_uldivmod+0x28>
+ 8000228: 2900 cmp r1, #0
+ 800022a: d100 bne.n 800022e <__aeabi_uldivmod+0xe>
+ 800022c: 2800 cmp r0, #0
+ 800022e: d002 beq.n 8000236 <__aeabi_uldivmod+0x16>
+ 8000230: 2100 movs r1, #0
+ 8000232: 43c9 mvns r1, r1
+ 8000234: 1c08 adds r0, r1, #0
+ 8000236: b407 push {r0, r1, r2}
+ 8000238: 4802 ldr r0, [pc, #8] ; (8000244 <__aeabi_uldivmod+0x24>)
+ 800023a: a102 add r1, pc, #8 ; (adr r1, 8000244 <__aeabi_uldivmod+0x24>)
+ 800023c: 1840 adds r0, r0, r1
+ 800023e: 9002 str r0, [sp, #8]
+ 8000240: bd03 pop {r0, r1, pc}
+ 8000242: 46c0 nop ; (mov r8, r8)
+ 8000244: ffffffd9 .word 0xffffffd9
+ 8000248: b403 push {r0, r1}
+ 800024a: 4668 mov r0, sp
+ 800024c: b501 push {r0, lr}
+ 800024e: 9802 ldr r0, [sp, #8]
+ 8000250: f000 f830 bl 80002b4 <__udivmoddi4>
+ 8000254: 9b01 ldr r3, [sp, #4]
+ 8000256: 469e mov lr, r3
+ 8000258: b002 add sp, #8
+ 800025a: bc0c pop {r2, r3}
+ 800025c: 4770 bx lr
+ 800025e: 46c0 nop ; (mov r8, r8)
+
+08000260 <__aeabi_lmul>:
+ 8000260: b5f0 push {r4, r5, r6, r7, lr}
+ 8000262: 46ce mov lr, r9
+ 8000264: 4647 mov r7, r8
+ 8000266: 0415 lsls r5, r2, #16
+ 8000268: 0c2d lsrs r5, r5, #16
+ 800026a: 002e movs r6, r5
+ 800026c: b580 push {r7, lr}
+ 800026e: 0407 lsls r7, r0, #16
+ 8000270: 0c14 lsrs r4, r2, #16
+ 8000272: 0c3f lsrs r7, r7, #16
+ 8000274: 4699 mov r9, r3
+ 8000276: 0c03 lsrs r3, r0, #16
+ 8000278: 437e muls r6, r7
+ 800027a: 435d muls r5, r3
+ 800027c: 4367 muls r7, r4
+ 800027e: 4363 muls r3, r4
+ 8000280: 197f adds r7, r7, r5
+ 8000282: 0c34 lsrs r4, r6, #16
+ 8000284: 19e4 adds r4, r4, r7
+ 8000286: 469c mov ip, r3
+ 8000288: 42a5 cmp r5, r4
+ 800028a: d903 bls.n 8000294 <__aeabi_lmul+0x34>
+ 800028c: 2380 movs r3, #128 ; 0x80
+ 800028e: 025b lsls r3, r3, #9
+ 8000290: 4698 mov r8, r3
+ 8000292: 44c4 add ip, r8
+ 8000294: 464b mov r3, r9
+ 8000296: 4343 muls r3, r0
+ 8000298: 4351 muls r1, r2
+ 800029a: 0c25 lsrs r5, r4, #16
+ 800029c: 0436 lsls r6, r6, #16
+ 800029e: 4465 add r5, ip
+ 80002a0: 0c36 lsrs r6, r6, #16
+ 80002a2: 0424 lsls r4, r4, #16
+ 80002a4: 19a4 adds r4, r4, r6
+ 80002a6: 195b adds r3, r3, r5
+ 80002a8: 1859 adds r1, r3, r1
+ 80002aa: 0020 movs r0, r4
+ 80002ac: bc0c pop {r2, r3}
+ 80002ae: 4690 mov r8, r2
+ 80002b0: 4699 mov r9, r3
+ 80002b2: bdf0 pop {r4, r5, r6, r7, pc}
+
+080002b4 <__udivmoddi4>:
+ 80002b4: b5f0 push {r4, r5, r6, r7, lr}
+ 80002b6: 464f mov r7, r9
+ 80002b8: 4646 mov r6, r8
+ 80002ba: 46d6 mov lr, sl
+ 80002bc: b5c0 push {r6, r7, lr}
+ 80002be: 0004 movs r4, r0
+ 80002c0: b082 sub sp, #8
+ 80002c2: 000d movs r5, r1
+ 80002c4: 4691 mov r9, r2
+ 80002c6: 4698 mov r8, r3
+ 80002c8: 428b cmp r3, r1
+ 80002ca: d82f bhi.n 800032c <__udivmoddi4+0x78>
+ 80002cc: d02c beq.n 8000328 <__udivmoddi4+0x74>
+ 80002ce: 4641 mov r1, r8
+ 80002d0: 4648 mov r0, r9
+ 80002d2: f000 f8b1 bl 8000438 <__clzdi2>
+ 80002d6: 0029 movs r1, r5
+ 80002d8: 0006 movs r6, r0
+ 80002da: 0020 movs r0, r4
+ 80002dc: f000 f8ac bl 8000438 <__clzdi2>
+ 80002e0: 1a33 subs r3, r6, r0
+ 80002e2: 469c mov ip, r3
+ 80002e4: 3b20 subs r3, #32
+ 80002e6: 469a mov sl, r3
+ 80002e8: d500 bpl.n 80002ec <__udivmoddi4+0x38>
+ 80002ea: e076 b.n 80003da <__udivmoddi4+0x126>
+ 80002ec: 464b mov r3, r9
+ 80002ee: 4652 mov r2, sl
+ 80002f0: 4093 lsls r3, r2
+ 80002f2: 001f movs r7, r3
+ 80002f4: 464b mov r3, r9
+ 80002f6: 4662 mov r2, ip
+ 80002f8: 4093 lsls r3, r2
+ 80002fa: 001e movs r6, r3
+ 80002fc: 42af cmp r7, r5
+ 80002fe: d828 bhi.n 8000352 <__udivmoddi4+0x9e>
+ 8000300: d025 beq.n 800034e <__udivmoddi4+0x9a>
+ 8000302: 4653 mov r3, sl
+ 8000304: 1ba4 subs r4, r4, r6
+ 8000306: 41bd sbcs r5, r7
+ 8000308: 2b00 cmp r3, #0
+ 800030a: da00 bge.n 800030e <__udivmoddi4+0x5a>
+ 800030c: e07b b.n 8000406 <__udivmoddi4+0x152>
+ 800030e: 2200 movs r2, #0
+ 8000310: 2300 movs r3, #0
+ 8000312: 9200 str r2, [sp, #0]
+ 8000314: 9301 str r3, [sp, #4]
+ 8000316: 2301 movs r3, #1
+ 8000318: 4652 mov r2, sl
+ 800031a: 4093 lsls r3, r2
+ 800031c: 9301 str r3, [sp, #4]
+ 800031e: 2301 movs r3, #1
+ 8000320: 4662 mov r2, ip
+ 8000322: 4093 lsls r3, r2
+ 8000324: 9300 str r3, [sp, #0]
+ 8000326: e018 b.n 800035a <__udivmoddi4+0xa6>
+ 8000328: 4282 cmp r2, r0
+ 800032a: d9d0 bls.n 80002ce <__udivmoddi4+0x1a>
+ 800032c: 2200 movs r2, #0
+ 800032e: 2300 movs r3, #0
+ 8000330: 9200 str r2, [sp, #0]
+ 8000332: 9301 str r3, [sp, #4]
+ 8000334: 9b0a ldr r3, [sp, #40] ; 0x28
+ 8000336: 2b00 cmp r3, #0
+ 8000338: d001 beq.n 800033e <__udivmoddi4+0x8a>
+ 800033a: 601c str r4, [r3, #0]
+ 800033c: 605d str r5, [r3, #4]
+ 800033e: 9800 ldr r0, [sp, #0]
+ 8000340: 9901 ldr r1, [sp, #4]
+ 8000342: b002 add sp, #8
+ 8000344: bc1c pop {r2, r3, r4}
+ 8000346: 4690 mov r8, r2
+ 8000348: 4699 mov r9, r3
+ 800034a: 46a2 mov sl, r4
+ 800034c: bdf0 pop {r4, r5, r6, r7, pc}
+ 800034e: 42a3 cmp r3, r4
+ 8000350: d9d7 bls.n 8000302 <__udivmoddi4+0x4e>
+ 8000352: 2200 movs r2, #0
+ 8000354: 2300 movs r3, #0
+ 8000356: 9200 str r2, [sp, #0]
+ 8000358: 9301 str r3, [sp, #4]
+ 800035a: 4663 mov r3, ip
+ 800035c: 2b00 cmp r3, #0
+ 800035e: d0e9 beq.n 8000334 <__udivmoddi4+0x80>
+ 8000360: 07fb lsls r3, r7, #31
+ 8000362: 4698 mov r8, r3
+ 8000364: 4641 mov r1, r8
+ 8000366: 0872 lsrs r2, r6, #1
+ 8000368: 430a orrs r2, r1
+ 800036a: 087b lsrs r3, r7, #1
+ 800036c: 4666 mov r6, ip
+ 800036e: e00e b.n 800038e <__udivmoddi4+0xda>
+ 8000370: 42ab cmp r3, r5
+ 8000372: d101 bne.n 8000378 <__udivmoddi4+0xc4>
+ 8000374: 42a2 cmp r2, r4
+ 8000376: d80c bhi.n 8000392 <__udivmoddi4+0xde>
+ 8000378: 1aa4 subs r4, r4, r2
+ 800037a: 419d sbcs r5, r3
+ 800037c: 2001 movs r0, #1
+ 800037e: 1924 adds r4, r4, r4
+ 8000380: 416d adcs r5, r5
+ 8000382: 2100 movs r1, #0
+ 8000384: 3e01 subs r6, #1
+ 8000386: 1824 adds r4, r4, r0
+ 8000388: 414d adcs r5, r1
+ 800038a: 2e00 cmp r6, #0
+ 800038c: d006 beq.n 800039c <__udivmoddi4+0xe8>
+ 800038e: 42ab cmp r3, r5
+ 8000390: d9ee bls.n 8000370 <__udivmoddi4+0xbc>
+ 8000392: 3e01 subs r6, #1
+ 8000394: 1924 adds r4, r4, r4
+ 8000396: 416d adcs r5, r5
+ 8000398: 2e00 cmp r6, #0
+ 800039a: d1f8 bne.n 800038e <__udivmoddi4+0xda>
+ 800039c: 9800 ldr r0, [sp, #0]
+ 800039e: 9901 ldr r1, [sp, #4]
+ 80003a0: 4653 mov r3, sl
+ 80003a2: 1900 adds r0, r0, r4
+ 80003a4: 4169 adcs r1, r5
+ 80003a6: 2b00 cmp r3, #0
+ 80003a8: db23 blt.n 80003f2 <__udivmoddi4+0x13e>
+ 80003aa: 002b movs r3, r5
+ 80003ac: 4652 mov r2, sl
+ 80003ae: 40d3 lsrs r3, r2
+ 80003b0: 002a movs r2, r5
+ 80003b2: 4664 mov r4, ip
+ 80003b4: 40e2 lsrs r2, r4
+ 80003b6: 001c movs r4, r3
+ 80003b8: 4653 mov r3, sl
+ 80003ba: 0015 movs r5, r2
+ 80003bc: 2b00 cmp r3, #0
+ 80003be: db2d blt.n 800041c <__udivmoddi4+0x168>
+ 80003c0: 0026 movs r6, r4
+ 80003c2: 4657 mov r7, sl
+ 80003c4: 40be lsls r6, r7
+ 80003c6: 0033 movs r3, r6
+ 80003c8: 0026 movs r6, r4
+ 80003ca: 4667 mov r7, ip
+ 80003cc: 40be lsls r6, r7
+ 80003ce: 0032 movs r2, r6
+ 80003d0: 1a80 subs r0, r0, r2
+ 80003d2: 4199 sbcs r1, r3
+ 80003d4: 9000 str r0, [sp, #0]
+ 80003d6: 9101 str r1, [sp, #4]
+ 80003d8: e7ac b.n 8000334 <__udivmoddi4+0x80>
+ 80003da: 4662 mov r2, ip
+ 80003dc: 2320 movs r3, #32
+ 80003de: 1a9b subs r3, r3, r2
+ 80003e0: 464a mov r2, r9
+ 80003e2: 40da lsrs r2, r3
+ 80003e4: 4661 mov r1, ip
+ 80003e6: 0013 movs r3, r2
+ 80003e8: 4642 mov r2, r8
+ 80003ea: 408a lsls r2, r1
+ 80003ec: 0017 movs r7, r2
+ 80003ee: 431f orrs r7, r3
+ 80003f0: e780 b.n 80002f4 <__udivmoddi4+0x40>
+ 80003f2: 4662 mov r2, ip
+ 80003f4: 2320 movs r3, #32
+ 80003f6: 1a9b subs r3, r3, r2
+ 80003f8: 002a movs r2, r5
+ 80003fa: 4666 mov r6, ip
+ 80003fc: 409a lsls r2, r3
+ 80003fe: 0023 movs r3, r4
+ 8000400: 40f3 lsrs r3, r6
+ 8000402: 4313 orrs r3, r2
+ 8000404: e7d4 b.n 80003b0 <__udivmoddi4+0xfc>
+ 8000406: 4662 mov r2, ip
+ 8000408: 2320 movs r3, #32
+ 800040a: 2100 movs r1, #0
+ 800040c: 1a9b subs r3, r3, r2
+ 800040e: 2200 movs r2, #0
+ 8000410: 9100 str r1, [sp, #0]
+ 8000412: 9201 str r2, [sp, #4]
+ 8000414: 2201 movs r2, #1
+ 8000416: 40da lsrs r2, r3
+ 8000418: 9201 str r2, [sp, #4]
+ 800041a: e780 b.n 800031e <__udivmoddi4+0x6a>
+ 800041c: 2320 movs r3, #32
+ 800041e: 4662 mov r2, ip
+ 8000420: 0026 movs r6, r4
+ 8000422: 1a9b subs r3, r3, r2
+ 8000424: 40de lsrs r6, r3
+ 8000426: 002f movs r7, r5
+ 8000428: 46b0 mov r8, r6
+ 800042a: 4666 mov r6, ip
+ 800042c: 40b7 lsls r7, r6
+ 800042e: 4646 mov r6, r8
+ 8000430: 003b movs r3, r7
+ 8000432: 4333 orrs r3, r6
+ 8000434: e7c8 b.n 80003c8 <__udivmoddi4+0x114>
+ 8000436: 46c0 nop ; (mov r8, r8)
+
+08000438 <__clzdi2>:
+ 8000438: b510 push {r4, lr}
+ 800043a: 2900 cmp r1, #0
+ 800043c: d103 bne.n 8000446 <__clzdi2+0xe>
+ 800043e: f000 f807 bl 8000450 <__clzsi2>
+ 8000442: 3020 adds r0, #32
+ 8000444: e002 b.n 800044c <__clzdi2+0x14>
+ 8000446: 1c08 adds r0, r1, #0
+ 8000448: f000 f802 bl 8000450 <__clzsi2>
+ 800044c: bd10 pop {r4, pc}
+ 800044e: 46c0 nop ; (mov r8, r8)
+
+08000450 <__clzsi2>:
+ 8000450: 211c movs r1, #28
+ 8000452: 2301 movs r3, #1
+ 8000454: 041b lsls r3, r3, #16
+ 8000456: 4298 cmp r0, r3
+ 8000458: d301 bcc.n 800045e <__clzsi2+0xe>
+ 800045a: 0c00 lsrs r0, r0, #16
+ 800045c: 3910 subs r1, #16
+ 800045e: 0a1b lsrs r3, r3, #8
+ 8000460: 4298 cmp r0, r3
+ 8000462: d301 bcc.n 8000468 <__clzsi2+0x18>
+ 8000464: 0a00 lsrs r0, r0, #8
+ 8000466: 3908 subs r1, #8
+ 8000468: 091b lsrs r3, r3, #4
+ 800046a: 4298 cmp r0, r3
+ 800046c: d301 bcc.n 8000472 <__clzsi2+0x22>
+ 800046e: 0900 lsrs r0, r0, #4
+ 8000470: 3904 subs r1, #4
+ 8000472: a202 add r2, pc, #8 ; (adr r2, 800047c <__clzsi2+0x2c>)
+ 8000474: 5c10 ldrb r0, [r2, r0]
+ 8000476: 1840 adds r0, r0, r1
+ 8000478: 4770 bx lr
+ 800047a: 46c0 nop ; (mov r8, r8)
+ 800047c: 02020304 .word 0x02020304
+ 8000480: 01010101 .word 0x01010101
+ ...
+
+0800048c :
+/**
+ * @brief The application entry point.
+ * @retval int
+ */
+int main(void)
+{
+ 800048c: b580 push {r7, lr}
+ 800048e: af00 add r7, sp, #0
+ /* USER CODE END 1 */
+
+ /* MCU Configuration--------------------------------------------------------*/
+
+ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+ HAL_Init();
+ 8000490: f000 fa64 bl 800095c
+ /* USER CODE BEGIN Init */
+
+ /* USER CODE END Init */
+
+ /* Configure the system clock */
+ SystemClock_Config();
+ 8000494: f000 f850 bl 8000538
+ /* USER CODE BEGIN SysInit */
+
+ /* USER CODE END SysInit */
+
+ /* Initialize all configured peripherals */
+ MX_GPIO_Init();
+ 8000498: f000 f92c bl 80006f4
+ MX_I2C1_Init();
+ 800049c: f000 f8ba bl 8000614
+ MX_LPUART1_UART_Init();
+ 80004a0: f000 f8f8 bl 8000694
+ /* USER CODE BEGIN 2 */
+ /* Turn off all LEDs */
+ HAL_GPIO_WritePin(LED_R_GPIO_Port, LED_R_Pin, 1);
+ 80004a4: 23a0 movs r3, #160 ; 0xa0
+ 80004a6: 05db lsls r3, r3, #23
+ 80004a8: 2201 movs r2, #1
+ 80004aa: 2180 movs r1, #128 ; 0x80
+ 80004ac: 0018 movs r0, r3
+ 80004ae: f000 fd01 bl 8000eb4
+ HAL_GPIO_WritePin(LED_G_GPIO_Port, LED_G_Pin, 1);
+ 80004b2: 23a0 movs r3, #160 ; 0xa0
+ 80004b4: 05db lsls r3, r3, #23
+ 80004b6: 2201 movs r2, #1
+ 80004b8: 2140 movs r1, #64 ; 0x40
+ 80004ba: 0018 movs r0, r3
+ 80004bc: f000 fcfa bl 8000eb4
+ HAL_GPIO_WritePin(LED_B_GPIO_Port, LED_B_Pin, 1);
+ 80004c0: 23a0 movs r3, #160 ; 0xa0
+ 80004c2: 05db lsls r3, r3, #23
+ 80004c4: 2201 movs r2, #1
+ 80004c6: 2120 movs r1, #32
+ 80004c8: 0018 movs r0, r3
+ 80004ca: f000 fcf3 bl 8000eb4
+
+ /* Infinite loop */
+ /* USER CODE BEGIN WHILE */
+ while (1)
+ {
+ HAL_GPIO_TogglePin(LED_R_GPIO_Port, LED_R_Pin);
+ 80004ce: 23a0 movs r3, #160 ; 0xa0
+ 80004d0: 05db lsls r3, r3, #23
+ 80004d2: 2180 movs r1, #128 ; 0x80
+ 80004d4: 0018 movs r0, r3
+ 80004d6: f000 fd0a bl 8000eee
+ HAL_Delay(500);
+ 80004da: 23fa movs r3, #250 ; 0xfa
+ 80004dc: 005b lsls r3, r3, #1
+ 80004de: 0018 movs r0, r3
+ 80004e0: f000 faac bl 8000a3c
+ HAL_GPIO_TogglePin(LED_R_GPIO_Port, LED_R_Pin);
+ 80004e4: 23a0 movs r3, #160 ; 0xa0
+ 80004e6: 05db lsls r3, r3, #23
+ 80004e8: 2180 movs r1, #128 ; 0x80
+ 80004ea: 0018 movs r0, r3
+ 80004ec: f000 fcff bl 8000eee
+ HAL_GPIO_TogglePin(LED_G_GPIO_Port, LED_G_Pin);
+ 80004f0: 23a0 movs r3, #160 ; 0xa0
+ 80004f2: 05db lsls r3, r3, #23
+ 80004f4: 2140 movs r1, #64 ; 0x40
+ 80004f6: 0018 movs r0, r3
+ 80004f8: f000 fcf9 bl 8000eee
+ HAL_Delay(500);
+ 80004fc: 23fa movs r3, #250 ; 0xfa
+ 80004fe: 005b lsls r3, r3, #1
+ 8000500: 0018 movs r0, r3
+ 8000502: f000 fa9b bl 8000a3c
+ HAL_GPIO_TogglePin(LED_G_GPIO_Port, LED_G_Pin);
+ 8000506: 23a0 movs r3, #160 ; 0xa0
+ 8000508: 05db lsls r3, r3, #23
+ 800050a: 2140 movs r1, #64 ; 0x40
+ 800050c: 0018 movs r0, r3
+ 800050e: f000 fcee bl 8000eee
+ HAL_GPIO_TogglePin(LED_B_GPIO_Port, LED_B_Pin);
+ 8000512: 23a0 movs r3, #160 ; 0xa0
+ 8000514: 05db lsls r3, r3, #23
+ 8000516: 2120 movs r1, #32
+ 8000518: 0018 movs r0, r3
+ 800051a: f000 fce8 bl 8000eee
+ HAL_Delay(500);
+ 800051e: 23fa movs r3, #250 ; 0xfa
+ 8000520: 005b lsls r3, r3, #1
+ 8000522: 0018 movs r0, r3
+ 8000524: f000 fa8a bl 8000a3c
+ HAL_GPIO_TogglePin(LED_B_GPIO_Port, LED_B_Pin);
+ 8000528: 23a0 movs r3, #160 ; 0xa0
+ 800052a: 05db lsls r3, r3, #23
+ 800052c: 2120 movs r1, #32
+ 800052e: 0018 movs r0, r3
+ 8000530: f000 fcdd bl 8000eee
+ HAL_GPIO_TogglePin(LED_R_GPIO_Port, LED_R_Pin);
+ 8000534: e7cb b.n 80004ce
+ ...
+
+08000538 :
+/**
+ * @brief System Clock Configuration
+ * @retval None
+ */
+void SystemClock_Config(void)
+{
+ 8000538: b590 push {r4, r7, lr}
+ 800053a: b099 sub sp, #100 ; 0x64
+ 800053c: af00 add r7, sp, #0
+ RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+ 800053e: 242c movs r4, #44 ; 0x2c
+ 8000540: 193b adds r3, r7, r4
+ 8000542: 0018 movs r0, r3
+ 8000544: 2334 movs r3, #52 ; 0x34
+ 8000546: 001a movs r2, r3
+ 8000548: 2100 movs r1, #0
+ 800054a: f002 f937 bl 80027bc
+ RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+ 800054e: 2318 movs r3, #24
+ 8000550: 18fb adds r3, r7, r3
+ 8000552: 0018 movs r0, r3
+ 8000554: 2314 movs r3, #20
+ 8000556: 001a movs r2, r3
+ 8000558: 2100 movs r1, #0
+ 800055a: f002 f92f bl 80027bc
+ RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
+ 800055e: 003b movs r3, r7
+ 8000560: 0018 movs r0, r3
+ 8000562: 2318 movs r3, #24
+ 8000564: 001a movs r2, r3
+ 8000566: 2100 movs r1, #0
+ 8000568: f002 f928 bl 80027bc
+
+ /** Configure the main internal regulator output voltage
+ */
+ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+ 800056c: 4b27 ldr r3, [pc, #156] ; (800060c )
+ 800056e: 681b ldr r3, [r3, #0]
+ 8000570: 4a27 ldr r2, [pc, #156] ; (8000610 )
+ 8000572: 401a ands r2, r3
+ 8000574: 4b25 ldr r3, [pc, #148] ; (800060c )
+ 8000576: 2180 movs r1, #128 ; 0x80
+ 8000578: 0109 lsls r1, r1, #4
+ 800057a: 430a orrs r2, r1
+ 800057c: 601a str r2, [r3, #0]
+ /** Initializes the RCC Oscillators according to the specified parameters
+ * in the RCC_OscInitTypeDef structure.
+ */
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
+ 800057e: 0021 movs r1, r4
+ 8000580: 187b adds r3, r7, r1
+ 8000582: 2210 movs r2, #16
+ 8000584: 601a str r2, [r3, #0]
+ RCC_OscInitStruct.MSIState = RCC_MSI_ON;
+ 8000586: 187b adds r3, r7, r1
+ 8000588: 2201 movs r2, #1
+ 800058a: 619a str r2, [r3, #24]
+ RCC_OscInitStruct.MSICalibrationValue = 0;
+ 800058c: 187b adds r3, r7, r1
+ 800058e: 2200 movs r2, #0
+ 8000590: 61da str r2, [r3, #28]
+ RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_5;
+ 8000592: 187b adds r3, r7, r1
+ 8000594: 22a0 movs r2, #160 ; 0xa0
+ 8000596: 0212 lsls r2, r2, #8
+ 8000598: 621a str r2, [r3, #32]
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
+ 800059a: 187b adds r3, r7, r1
+ 800059c: 2200 movs r2, #0
+ 800059e: 625a str r2, [r3, #36] ; 0x24
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+ 80005a0: 187b adds r3, r7, r1
+ 80005a2: 0018 movs r0, r3
+ 80005a4: f000 fdec bl 8001180
+ 80005a8: 1e03 subs r3, r0, #0
+ 80005aa: d001 beq.n 80005b0
+ {
+ Error_Handler();
+ 80005ac: f000 f8d8 bl 8000760
+ }
+ /** Initializes the CPU, AHB and APB buses clocks
+ */
+ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+ 80005b0: 2118 movs r1, #24
+ 80005b2: 187b adds r3, r7, r1
+ 80005b4: 220f movs r2, #15
+ 80005b6: 601a str r2, [r3, #0]
+ |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI;
+ 80005b8: 187b adds r3, r7, r1
+ 80005ba: 2200 movs r2, #0
+ 80005bc: 605a str r2, [r3, #4]
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+ 80005be: 187b adds r3, r7, r1
+ 80005c0: 2200 movs r2, #0
+ 80005c2: 609a str r2, [r3, #8]
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+ 80005c4: 187b adds r3, r7, r1
+ 80005c6: 2200 movs r2, #0
+ 80005c8: 60da str r2, [r3, #12]
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+ 80005ca: 187b adds r3, r7, r1
+ 80005cc: 2200 movs r2, #0
+ 80005ce: 611a str r2, [r3, #16]
+
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK)
+ 80005d0: 187b adds r3, r7, r1
+ 80005d2: 2100 movs r1, #0
+ 80005d4: 0018 movs r0, r3
+ 80005d6: f001 f953 bl 8001880
+ 80005da: 1e03 subs r3, r0, #0
+ 80005dc: d001 beq.n 80005e2
+ {
+ Error_Handler();
+ 80005de: f000 f8bf bl 8000760
+ }
+ PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_LPUART1|RCC_PERIPHCLK_I2C1;
+ 80005e2: 003b movs r3, r7
+ 80005e4: 220c movs r2, #12
+ 80005e6: 601a str r2, [r3, #0]
+ PeriphClkInit.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_PCLK1;
+ 80005e8: 003b movs r3, r7
+ 80005ea: 2200 movs r2, #0
+ 80005ec: 60da str r2, [r3, #12]
+ PeriphClkInit.I2c1ClockSelection = RCC_I2C1CLKSOURCE_PCLK1;
+ 80005ee: 003b movs r3, r7
+ 80005f0: 2200 movs r2, #0
+ 80005f2: 611a str r2, [r3, #16]
+ if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
+ 80005f4: 003b movs r3, r7
+ 80005f6: 0018 movs r0, r3
+ 80005f8: f001 fb62 bl 8001cc0
+ 80005fc: 1e03 subs r3, r0, #0
+ 80005fe: d001 beq.n 8000604
+ {
+ Error_Handler();
+ 8000600: f000 f8ae bl 8000760
+ }
+}
+ 8000604: 46c0 nop ; (mov r8, r8)
+ 8000606: 46bd mov sp, r7
+ 8000608: b019 add sp, #100 ; 0x64
+ 800060a: bd90 pop {r4, r7, pc}
+ 800060c: 40007000 .word 0x40007000
+ 8000610: ffffe7ff .word 0xffffe7ff
+
+08000614 :
+ * @brief I2C1 Initialization Function
+ * @param None
+ * @retval None
+ */
+static void MX_I2C1_Init(void)
+{
+ 8000614: b580 push {r7, lr}
+ 8000616: af00 add r7, sp, #0
+ /* USER CODE END I2C1_Init 0 */
+
+ /* USER CODE BEGIN I2C1_Init 1 */
+
+ /* USER CODE END I2C1_Init 1 */
+ hi2c1.Instance = I2C1;
+ 8000618: 4b1c ldr r3, [pc, #112] ; (800068c )
+ 800061a: 4a1d ldr r2, [pc, #116] ; (8000690 )
+ 800061c: 601a str r2, [r3, #0]
+ hi2c1.Init.Timing = 0x00000708;
+ 800061e: 4b1b ldr r3, [pc, #108] ; (800068c )
+ 8000620: 22e1 movs r2, #225 ; 0xe1
+ 8000622: 00d2 lsls r2, r2, #3
+ 8000624: 605a str r2, [r3, #4]
+ hi2c1.Init.OwnAddress1 = 0;
+ 8000626: 4b19 ldr r3, [pc, #100] ; (800068c )
+ 8000628: 2200 movs r2, #0
+ 800062a: 609a str r2, [r3, #8]
+ hi2c1.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT;
+ 800062c: 4b17 ldr r3, [pc, #92] ; (800068c )
+ 800062e: 2201 movs r2, #1
+ 8000630: 60da str r2, [r3, #12]
+ hi2c1.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE;
+ 8000632: 4b16 ldr r3, [pc, #88] ; (800068c )
+ 8000634: 2200 movs r2, #0
+ 8000636: 611a str r2, [r3, #16]
+ hi2c1.Init.OwnAddress2 = 0;
+ 8000638: 4b14 ldr r3, [pc, #80] ; (800068c )
+ 800063a: 2200 movs r2, #0
+ 800063c: 615a str r2, [r3, #20]
+ hi2c1.Init.OwnAddress2Masks = I2C_OA2_NOMASK;
+ 800063e: 4b13 ldr r3, [pc, #76] ; (800068c )
+ 8000640: 2200 movs r2, #0
+ 8000642: 619a str r2, [r3, #24]
+ hi2c1.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE;
+ 8000644: 4b11 ldr r3, [pc, #68] ; (800068c )
+ 8000646: 2200 movs r2, #0
+ 8000648: 61da str r2, [r3, #28]
+ hi2c1.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE;
+ 800064a: 4b10 ldr r3, [pc, #64] ; (800068c )
+ 800064c: 2200 movs r2, #0
+ 800064e: 621a str r2, [r3, #32]
+ if (HAL_I2C_Init(&hi2c1) != HAL_OK)
+ 8000650: 4b0e ldr r3, [pc, #56] ; (800068c )
+ 8000652: 0018 movs r0, r3
+ 8000654: f000 fc66 bl 8000f24
+ 8000658: 1e03 subs r3, r0, #0
+ 800065a: d001 beq.n 8000660
+ {
+ Error_Handler();
+ 800065c: f000 f880 bl 8000760
+ }
+ /** Configure Analogue filter
+ */
+ if (HAL_I2CEx_ConfigAnalogFilter(&hi2c1, I2C_ANALOGFILTER_ENABLE) != HAL_OK)
+ 8000660: 4b0a ldr r3, [pc, #40] ; (800068c )
+ 8000662: 2100 movs r1, #0
+ 8000664: 0018 movs r0, r3
+ 8000666: f000 fcf3 bl 8001050
+ 800066a: 1e03 subs r3, r0, #0
+ 800066c: d001 beq.n 8000672
+ {
+ Error_Handler();
+ 800066e: f000 f877 bl 8000760
+ }
+ /** Configure Digital filter
+ */
+ if (HAL_I2CEx_ConfigDigitalFilter(&hi2c1, 0) != HAL_OK)
+ 8000672: 4b06 ldr r3, [pc, #24] ; (800068c )
+ 8000674: 2100 movs r1, #0
+ 8000676: 0018 movs r0, r3
+ 8000678: f000 fd36 bl 80010e8
+ 800067c: 1e03 subs r3, r0, #0
+ 800067e: d001 beq.n 8000684
+ {
+ Error_Handler();
+ 8000680: f000 f86e bl 8000760
+ }
+ /* USER CODE BEGIN I2C1_Init 2 */
+
+ /* USER CODE END I2C1_Init 2 */
+
+}
+ 8000684: 46c0 nop ; (mov r8, r8)
+ 8000686: 46bd mov sp, r7
+ 8000688: bd80 pop {r7, pc}
+ 800068a: 46c0 nop ; (mov r8, r8)
+ 800068c: 20000028 .word 0x20000028
+ 8000690: 40005400 .word 0x40005400
+
+08000694 :
+ * @brief LPUART1 Initialization Function
+ * @param None
+ * @retval None
+ */
+static void MX_LPUART1_UART_Init(void)
+{
+ 8000694: b580 push {r7, lr}
+ 8000696: af00 add r7, sp, #0
+ /* USER CODE END LPUART1_Init 0 */
+
+ /* USER CODE BEGIN LPUART1_Init 1 */
+
+ /* USER CODE END LPUART1_Init 1 */
+ hlpuart1.Instance = LPUART1;
+ 8000698: 4b13 ldr r3, [pc, #76] ; (80006e8 )
+ 800069a: 4a14 ldr r2, [pc, #80] ; (80006ec )
+ 800069c: 601a str r2, [r3, #0]
+ hlpuart1.Init.BaudRate = 209700;
+ 800069e: 4b12 ldr r3, [pc, #72] ; (80006e8 )
+ 80006a0: 4a13 ldr r2, [pc, #76] ; (80006f0 )
+ 80006a2: 605a str r2, [r3, #4]
+ hlpuart1.Init.WordLength = UART_WORDLENGTH_7B;
+ 80006a4: 4b10 ldr r3, [pc, #64] ; (80006e8 )
+ 80006a6: 2280 movs r2, #128 ; 0x80
+ 80006a8: 0552 lsls r2, r2, #21
+ 80006aa: 609a str r2, [r3, #8]
+ hlpuart1.Init.StopBits = UART_STOPBITS_1;
+ 80006ac: 4b0e ldr r3, [pc, #56] ; (80006e8 )
+ 80006ae: 2200 movs r2, #0
+ 80006b0: 60da str r2, [r3, #12]
+ hlpuart1.Init.Parity = UART_PARITY_NONE;
+ 80006b2: 4b0d ldr r3, [pc, #52] ; (80006e8 )
+ 80006b4: 2200 movs r2, #0
+ 80006b6: 611a str r2, [r3, #16]
+ hlpuart1.Init.Mode = UART_MODE_TX_RX;
+ 80006b8: 4b0b ldr r3, [pc, #44] ; (80006e8 )
+ 80006ba: 220c movs r2, #12
+ 80006bc: 615a str r2, [r3, #20]
+ hlpuart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
+ 80006be: 4b0a ldr r3, [pc, #40] ; (80006e8 )
+ 80006c0: 2200 movs r2, #0
+ 80006c2: 619a str r2, [r3, #24]
+ hlpuart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
+ 80006c4: 4b08 ldr r3, [pc, #32] ; (80006e8 )
+ 80006c6: 2200 movs r2, #0
+ 80006c8: 621a str r2, [r3, #32]
+ hlpuart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
+ 80006ca: 4b07 ldr r3, [pc, #28] ; (80006e8 )
+ 80006cc: 2200 movs r2, #0
+ 80006ce: 625a str r2, [r3, #36] ; 0x24
+ if (HAL_UART_Init(&hlpuart1) != HAL_OK)
+ 80006d0: 4b05 ldr r3, [pc, #20] ; (80006e8 )
+ 80006d2: 0018 movs r0, r3
+ 80006d4: f001 fc1c bl 8001f10
+ 80006d8: 1e03 subs r3, r0, #0
+ 80006da: d001 beq.n 80006e0
+ {
+ Error_Handler();
+ 80006dc: f000 f840 bl 8000760
+ }
+ /* USER CODE BEGIN LPUART1_Init 2 */
+
+ /* USER CODE END LPUART1_Init 2 */
+
+}
+ 80006e0: 46c0 nop ; (mov r8, r8)
+ 80006e2: 46bd mov sp, r7
+ 80006e4: bd80 pop {r7, pc}
+ 80006e6: 46c0 nop ; (mov r8, r8)
+ 80006e8: 20000074 .word 0x20000074
+ 80006ec: 40004800 .word 0x40004800
+ 80006f0: 00033324 .word 0x00033324
+
+080006f4 :
+ * @brief GPIO Initialization Function
+ * @param None
+ * @retval None
+ */
+static void MX_GPIO_Init(void)
+{
+ 80006f4: b580 push {r7, lr}
+ 80006f6: b086 sub sp, #24
+ 80006f8: af00 add r7, sp, #0
+ GPIO_InitTypeDef GPIO_InitStruct = {0};
+ 80006fa: 1d3b adds r3, r7, #4
+ 80006fc: 0018 movs r0, r3
+ 80006fe: 2314 movs r3, #20
+ 8000700: 001a movs r2, r3
+ 8000702: 2100 movs r1, #0
+ 8000704: f002 f85a bl 80027bc
+
+ /* GPIO Ports Clock Enable */
+ __HAL_RCC_GPIOA_CLK_ENABLE();
+ 8000708: 4b14 ldr r3, [pc, #80] ; (800075c )
+ 800070a: 6ada ldr r2, [r3, #44] ; 0x2c
+ 800070c: 4b13 ldr r3, [pc, #76] ; (800075c )
+ 800070e: 2101 movs r1, #1
+ 8000710: 430a orrs r2, r1
+ 8000712: 62da str r2, [r3, #44] ; 0x2c
+ 8000714: 4b11 ldr r3, [pc, #68] ; (800075c )
+ 8000716: 6adb ldr r3, [r3, #44] ; 0x2c
+ 8000718: 2201 movs r2, #1
+ 800071a: 4013 ands r3, r2
+ 800071c: 603b str r3, [r7, #0]
+ 800071e: 683b ldr r3, [r7, #0]
+
+ /*Configure GPIO pin Output Level */
+ HAL_GPIO_WritePin(GPIOA, LED_B_Pin|LED_G_Pin|LED_R_Pin, GPIO_PIN_SET);
+ 8000720: 23a0 movs r3, #160 ; 0xa0
+ 8000722: 05db lsls r3, r3, #23
+ 8000724: 2201 movs r2, #1
+ 8000726: 21e0 movs r1, #224 ; 0xe0
+ 8000728: 0018 movs r0, r3
+ 800072a: f000 fbc3 bl 8000eb4
+
+ /*Configure GPIO pins : LED_B_Pin LED_G_Pin LED_R_Pin */
+ GPIO_InitStruct.Pin = LED_B_Pin|LED_G_Pin|LED_R_Pin;
+ 800072e: 1d3b adds r3, r7, #4
+ 8000730: 22e0 movs r2, #224 ; 0xe0
+ 8000732: 601a str r2, [r3, #0]
+ GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+ 8000734: 1d3b adds r3, r7, #4
+ 8000736: 2201 movs r2, #1
+ 8000738: 605a str r2, [r3, #4]
+ GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 800073a: 1d3b adds r3, r7, #4
+ 800073c: 2200 movs r2, #0
+ 800073e: 609a str r2, [r3, #8]
+ GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+ 8000740: 1d3b adds r3, r7, #4
+ 8000742: 2200 movs r2, #0
+ 8000744: 60da str r2, [r3, #12]
+ HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+ 8000746: 1d3a adds r2, r7, #4
+ 8000748: 23a0 movs r3, #160 ; 0xa0
+ 800074a: 05db lsls r3, r3, #23
+ 800074c: 0011 movs r1, r2
+ 800074e: 0018 movs r0, r3
+ 8000750: f000 fa4a bl 8000be8
+
+}
+ 8000754: 46c0 nop ; (mov r8, r8)
+ 8000756: 46bd mov sp, r7
+ 8000758: b006 add sp, #24
+ 800075a: bd80 pop {r7, pc}
+ 800075c: 40021000 .word 0x40021000
+
+08000760 :
+/**
+ * @brief This function is executed in case of error occurrence.
+ * @retval None
+ */
+void Error_Handler(void)
+{
+ 8000760: b580 push {r7, lr}
+ 8000762: af00 add r7, sp, #0
+ \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __disable_irq(void)
+{
+ __ASM volatile ("cpsid i" : : : "memory");
+ 8000764: b672 cpsid i
+ /* USER CODE BEGIN Error_Handler_Debug */
+ /* User can add his own implementation to report the HAL error return state */
+ __disable_irq();
+ while (1)
+ 8000766: e7fe b.n 8000766
+
+08000768 :
+/* USER CODE END 0 */
+/**
+ * Initializes the Global MSP.
+ */
+void HAL_MspInit(void)
+{
+ 8000768: b580 push {r7, lr}
+ 800076a: af00 add r7, sp, #0
+ /* USER CODE BEGIN MspInit 0 */
+
+ /* USER CODE END MspInit 0 */
+
+ __HAL_RCC_SYSCFG_CLK_ENABLE();
+ 800076c: 4b07 ldr r3, [pc, #28] ; (800078c )
+ 800076e: 6b5a ldr r2, [r3, #52] ; 0x34
+ 8000770: 4b06 ldr r3, [pc, #24] ; (800078c )
+ 8000772: 2101 movs r1, #1
+ 8000774: 430a orrs r2, r1
+ 8000776: 635a str r2, [r3, #52] ; 0x34
+ __HAL_RCC_PWR_CLK_ENABLE();
+ 8000778: 4b04 ldr r3, [pc, #16] ; (800078c )
+ 800077a: 6b9a ldr r2, [r3, #56] ; 0x38
+ 800077c: 4b03 ldr r3, [pc, #12] ; (800078c )
+ 800077e: 2180 movs r1, #128 ; 0x80
+ 8000780: 0549 lsls r1, r1, #21
+ 8000782: 430a orrs r2, r1
+ 8000784: 639a str r2, [r3, #56] ; 0x38
+ /* System interrupt init*/
+
+ /* USER CODE BEGIN MspInit 1 */
+
+ /* USER CODE END MspInit 1 */
+}
+ 8000786: 46c0 nop ; (mov r8, r8)
+ 8000788: 46bd mov sp, r7
+ 800078a: bd80 pop {r7, pc}
+ 800078c: 40021000 .word 0x40021000
+
+08000790 :
+* This function configures the hardware resources used in this example
+* @param hi2c: I2C handle pointer
+* @retval None
+*/
+void HAL_I2C_MspInit(I2C_HandleTypeDef* hi2c)
+{
+ 8000790: b580 push {r7, lr}
+ 8000792: b088 sub sp, #32
+ 8000794: af00 add r7, sp, #0
+ 8000796: 6078 str r0, [r7, #4]
+ GPIO_InitTypeDef GPIO_InitStruct = {0};
+ 8000798: 230c movs r3, #12
+ 800079a: 18fb adds r3, r7, r3
+ 800079c: 0018 movs r0, r3
+ 800079e: 2314 movs r3, #20
+ 80007a0: 001a movs r2, r3
+ 80007a2: 2100 movs r1, #0
+ 80007a4: f002 f80a bl 80027bc
+ if(hi2c->Instance==I2C1)
+ 80007a8: 687b ldr r3, [r7, #4]
+ 80007aa: 681b ldr r3, [r3, #0]
+ 80007ac: 4a18 ldr r2, [pc, #96] ; (8000810 )
+ 80007ae: 4293 cmp r3, r2
+ 80007b0: d12a bne.n 8000808
+ {
+ /* USER CODE BEGIN I2C1_MspInit 0 */
+
+ /* USER CODE END I2C1_MspInit 0 */
+
+ __HAL_RCC_GPIOA_CLK_ENABLE();
+ 80007b2: 4b18 ldr r3, [pc, #96] ; (8000814 )
+ 80007b4: 6ada ldr r2, [r3, #44] ; 0x2c
+ 80007b6: 4b17 ldr r3, [pc, #92] ; (8000814 )
+ 80007b8: 2101 movs r1, #1
+ 80007ba: 430a orrs r2, r1
+ 80007bc: 62da str r2, [r3, #44] ; 0x2c
+ 80007be: 4b15 ldr r3, [pc, #84] ; (8000814 )
+ 80007c0: 6adb ldr r3, [r3, #44] ; 0x2c
+ 80007c2: 2201 movs r2, #1
+ 80007c4: 4013 ands r3, r2
+ 80007c6: 60bb str r3, [r7, #8]
+ 80007c8: 68bb ldr r3, [r7, #8]
+ /**I2C1 GPIO Configuration
+ PA9 ------> I2C1_SCL
+ PA10 ------> I2C1_SDA
+ */
+ GPIO_InitStruct.Pin = GPIO_PIN_9|GPIO_PIN_10;
+ 80007ca: 210c movs r1, #12
+ 80007cc: 187b adds r3, r7, r1
+ 80007ce: 22c0 movs r2, #192 ; 0xc0
+ 80007d0: 00d2 lsls r2, r2, #3
+ 80007d2: 601a str r2, [r3, #0]
+ GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
+ 80007d4: 187b adds r3, r7, r1
+ 80007d6: 2212 movs r2, #18
+ 80007d8: 605a str r2, [r3, #4]
+ GPIO_InitStruct.Pull = GPIO_PULLUP;
+ 80007da: 187b adds r3, r7, r1
+ 80007dc: 2201 movs r2, #1
+ 80007de: 609a str r2, [r3, #8]
+ GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+ 80007e0: 187b adds r3, r7, r1
+ 80007e2: 2203 movs r2, #3
+ 80007e4: 60da str r2, [r3, #12]
+ GPIO_InitStruct.Alternate = GPIO_AF1_I2C1;
+ 80007e6: 187b adds r3, r7, r1
+ 80007e8: 2201 movs r2, #1
+ 80007ea: 611a str r2, [r3, #16]
+ HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+ 80007ec: 187a adds r2, r7, r1
+ 80007ee: 23a0 movs r3, #160 ; 0xa0
+ 80007f0: 05db lsls r3, r3, #23
+ 80007f2: 0011 movs r1, r2
+ 80007f4: 0018 movs r0, r3
+ 80007f6: f000 f9f7 bl 8000be8
+
+ /* Peripheral clock enable */
+ __HAL_RCC_I2C1_CLK_ENABLE();
+ 80007fa: 4b06 ldr r3, [pc, #24] ; (8000814 )
+ 80007fc: 6b9a ldr r2, [r3, #56] ; 0x38
+ 80007fe: 4b05 ldr r3, [pc, #20] ; (8000814 )
+ 8000800: 2180 movs r1, #128 ; 0x80
+ 8000802: 0389 lsls r1, r1, #14
+ 8000804: 430a orrs r2, r1
+ 8000806: 639a str r2, [r3, #56] ; 0x38
+ /* USER CODE BEGIN I2C1_MspInit 1 */
+
+ /* USER CODE END I2C1_MspInit 1 */
+ }
+
+}
+ 8000808: 46c0 nop ; (mov r8, r8)
+ 800080a: 46bd mov sp, r7
+ 800080c: b008 add sp, #32
+ 800080e: bd80 pop {r7, pc}
+ 8000810: 40005400 .word 0x40005400
+ 8000814: 40021000 .word 0x40021000
+
+08000818 :
+* This function configures the hardware resources used in this example
+* @param huart: UART handle pointer
+* @retval None
+*/
+void HAL_UART_MspInit(UART_HandleTypeDef* huart)
+{
+ 8000818: b580 push {r7, lr}
+ 800081a: b088 sub sp, #32
+ 800081c: af00 add r7, sp, #0
+ 800081e: 6078 str r0, [r7, #4]
+ GPIO_InitTypeDef GPIO_InitStruct = {0};
+ 8000820: 230c movs r3, #12
+ 8000822: 18fb adds r3, r7, r3
+ 8000824: 0018 movs r0, r3
+ 8000826: 2314 movs r3, #20
+ 8000828: 001a movs r2, r3
+ 800082a: 2100 movs r1, #0
+ 800082c: f001 ffc6 bl 80027bc
+ if(huart->Instance==LPUART1)
+ 8000830: 687b ldr r3, [r7, #4]
+ 8000832: 681b ldr r3, [r3, #0]
+ 8000834: 4a18 ldr r2, [pc, #96] ; (8000898 )
+ 8000836: 4293 cmp r3, r2
+ 8000838: d129 bne.n 800088e
+ {
+ /* USER CODE BEGIN LPUART1_MspInit 0 */
+
+ /* USER CODE END LPUART1_MspInit 0 */
+ /* Peripheral clock enable */
+ __HAL_RCC_LPUART1_CLK_ENABLE();
+ 800083a: 4b18 ldr r3, [pc, #96] ; (800089c )
+ 800083c: 6b9a ldr r2, [r3, #56] ; 0x38
+ 800083e: 4b17 ldr r3, [pc, #92] ; (800089c )
+ 8000840: 2180 movs r1, #128 ; 0x80
+ 8000842: 02c9 lsls r1, r1, #11
+ 8000844: 430a orrs r2, r1
+ 8000846: 639a str r2, [r3, #56] ; 0x38
+
+ __HAL_RCC_GPIOA_CLK_ENABLE();
+ 8000848: 4b14 ldr r3, [pc, #80] ; (800089c )
+ 800084a: 6ada ldr r2, [r3, #44] ; 0x2c
+ 800084c: 4b13 ldr r3, [pc, #76] ; (800089c )
+ 800084e: 2101 movs r1, #1
+ 8000850: 430a orrs r2, r1
+ 8000852: 62da str r2, [r3, #44] ; 0x2c
+ 8000854: 4b11 ldr r3, [pc, #68] ; (800089c )
+ 8000856: 6adb ldr r3, [r3, #44] ; 0x2c
+ 8000858: 2201 movs r2, #1
+ 800085a: 4013 ands r3, r2
+ 800085c: 60bb str r3, [r7, #8]
+ 800085e: 68bb ldr r3, [r7, #8]
+ /**LPUART1 GPIO Configuration
+ PA0-CK_IN ------> LPUART1_RX
+ PA1 ------> LPUART1_TX
+ */
+ GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1;
+ 8000860: 210c movs r1, #12
+ 8000862: 187b adds r3, r7, r1
+ 8000864: 2203 movs r2, #3
+ 8000866: 601a str r2, [r3, #0]
+ GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+ 8000868: 187b adds r3, r7, r1
+ 800086a: 2202 movs r2, #2
+ 800086c: 605a str r2, [r3, #4]
+ GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 800086e: 187b adds r3, r7, r1
+ 8000870: 2200 movs r2, #0
+ 8000872: 609a str r2, [r3, #8]
+ GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+ 8000874: 187b adds r3, r7, r1
+ 8000876: 2203 movs r2, #3
+ 8000878: 60da str r2, [r3, #12]
+ GPIO_InitStruct.Alternate = GPIO_AF6_LPUART1;
+ 800087a: 187b adds r3, r7, r1
+ 800087c: 2206 movs r2, #6
+ 800087e: 611a str r2, [r3, #16]
+ HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+ 8000880: 187a adds r2, r7, r1
+ 8000882: 23a0 movs r3, #160 ; 0xa0
+ 8000884: 05db lsls r3, r3, #23
+ 8000886: 0011 movs r1, r2
+ 8000888: 0018 movs r0, r3
+ 800088a: f000 f9ad bl 8000be8
+ /* USER CODE BEGIN LPUART1_MspInit 1 */
+
+ /* USER CODE END LPUART1_MspInit 1 */
+ }
+
+}
+ 800088e: 46c0 nop ; (mov r8, r8)
+ 8000890: 46bd mov sp, r7
+ 8000892: b008 add sp, #32
+ 8000894: bd80 pop {r7, pc}
+ 8000896: 46c0 nop ; (mov r8, r8)
+ 8000898: 40004800 .word 0x40004800
+ 800089c: 40021000 .word 0x40021000
+
+080008a0 :
+/******************************************************************************/
+/**
+ * @brief This function handles Non maskable interrupt.
+ */
+void NMI_Handler(void)
+{
+ 80008a0: b580 push {r7, lr}
+ 80008a2: af00 add r7, sp, #0
+ /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
+
+ /* USER CODE END NonMaskableInt_IRQn 0 */
+ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
+ while (1)
+ 80008a4: e7fe b.n 80008a4
+
+080008a6 :
+
+/**
+ * @brief This function handles Hard fault interrupt.
+ */
+void HardFault_Handler(void)
+{
+ 80008a6: b580 push {r7, lr}
+ 80008a8: af00 add r7, sp, #0
+ /* USER CODE BEGIN HardFault_IRQn 0 */
+
+ /* USER CODE END HardFault_IRQn 0 */
+ while (1)
+ 80008aa: e7fe b.n 80008aa
+
+080008ac :
+
+/**
+ * @brief This function handles System service call via SWI instruction.
+ */
+void SVC_Handler(void)
+{
+ 80008ac: b580 push {r7, lr}
+ 80008ae: af00 add r7, sp, #0
+
+ /* USER CODE END SVC_IRQn 0 */
+ /* USER CODE BEGIN SVC_IRQn 1 */
+
+ /* USER CODE END SVC_IRQn 1 */
+}
+ 80008b0: 46c0 nop ; (mov r8, r8)
+ 80008b2: 46bd mov sp, r7
+ 80008b4: bd80 pop {r7, pc}
+
+080008b6 :
+
+/**
+ * @brief This function handles Pendable request for system service.
+ */
+void PendSV_Handler(void)
+{
+ 80008b6: b580 push {r7, lr}
+ 80008b8: af00 add r7, sp, #0
+
+ /* USER CODE END PendSV_IRQn 0 */
+ /* USER CODE BEGIN PendSV_IRQn 1 */
+
+ /* USER CODE END PendSV_IRQn 1 */
+}
+ 80008ba: 46c0 nop ; (mov r8, r8)
+ 80008bc: 46bd mov sp, r7
+ 80008be: bd80 pop {r7, pc}
+
+080008c0 :
+
+/**
+ * @brief This function handles System tick timer.
+ */
+void SysTick_Handler(void)
+{
+ 80008c0: b580 push {r7, lr}
+ 80008c2: af00 add r7, sp, #0
+ /* USER CODE BEGIN SysTick_IRQn 0 */
+
+ /* USER CODE END SysTick_IRQn 0 */
+ HAL_IncTick();
+ 80008c4: f000 f89e bl 8000a04
+ /* USER CODE BEGIN SysTick_IRQn 1 */
+
+ /* USER CODE END SysTick_IRQn 1 */
+}
+ 80008c8: 46c0 nop ; (mov r8, r8)
+ 80008ca: 46bd mov sp, r7
+ 80008cc: bd80 pop {r7, pc}
+
+080008ce :
+ * @brief Setup the microcontroller system.
+ * @param None
+ * @retval None
+ */
+void SystemInit (void)
+{
+ 80008ce: b580 push {r7, lr}
+ 80008d0: af00 add r7, sp, #0
+ /* Configure the Vector Table location add offset address ------------------*/
+#if defined (USER_VECT_TAB_ADDRESS)
+ SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+#endif /* USER_VECT_TAB_ADDRESS */
+}
+ 80008d2: 46c0 nop ; (mov r8, r8)
+ 80008d4: 46bd mov sp, r7
+ 80008d6: bd80 pop {r7, pc}
+
+080008d8 :
+
+ .section .text.Reset_Handler
+ .weak Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+ ldr r0, =_estack
+ 80008d8: 4813 ldr r0, [pc, #76] ; (8000928 )
+ mov sp, r0 /* set stack pointer */
+ 80008da: 4685 mov sp, r0
+
+/*Check if boot space corresponds to system memory*/
+
+ LDR R0,=0x00000004
+ 80008dc: 4813 ldr r0, [pc, #76] ; (800092c )
+ LDR R1, [R0]
+ 80008de: 6801 ldr r1, [r0, #0]
+ LSRS R1, R1, #24
+ 80008e0: 0e09 lsrs r1, r1, #24
+ LDR R2,=0x1F
+ 80008e2: 4a13 ldr r2, [pc, #76] ; (8000930 )
+ CMP R1, R2
+ 80008e4: 4291 cmp r1, r2
+ BNE ApplicationStart
+ 80008e6: d105 bne.n 80008f4
+
+ /*SYSCFG clock enable*/
+ LDR R0,=0x40021034
+ 80008e8: 4812 ldr r0, [pc, #72] ; (8000934 )
+ LDR R1,=0x00000001
+ 80008ea: 4913 ldr r1, [pc, #76] ; (8000938 )
+ STR R1, [R0]
+ 80008ec: 6001 str r1, [r0, #0]
+
+/*Set CFGR1 register with flash memory remap at address 0*/
+ LDR R0,=0x40010000
+ 80008ee: 4813 ldr r0, [pc, #76] ; (800093c )
+ LDR R1,=0x00000000
+ 80008f0: 4913 ldr r1, [pc, #76] ; (8000940 )
+ STR R1, [R0]
+ 80008f2: 6001 str r1, [r0, #0]
+
+080008f4 :
+
+ApplicationStart:
+/* Copy the data segment initializers from flash to SRAM */
+ ldr r0, =_sdata
+ 80008f4: 4813 ldr r0, [pc, #76] ; (8000944 )
+ ldr r1, =_edata
+ 80008f6: 4914 ldr r1, [pc, #80] ; (8000948 )
+ ldr r2, =_sidata
+ 80008f8: 4a14 ldr r2, [pc, #80] ; (800094c )
+ movs r3, #0
+ 80008fa: 2300 movs r3, #0
+ b LoopCopyDataInit
+ 80008fc: e002 b.n 8000904
+
+080008fe :
+
+CopyDataInit:
+ ldr r4, [r2, r3]
+ 80008fe: 58d4 ldr r4, [r2, r3]
+ str r4, [r0, r3]
+ 8000900: 50c4 str r4, [r0, r3]
+ adds r3, r3, #4
+ 8000902: 3304 adds r3, #4
+
+08000904 :
+
+LoopCopyDataInit:
+ adds r4, r0, r3
+ 8000904: 18c4 adds r4, r0, r3
+ cmp r4, r1
+ 8000906: 428c cmp r4, r1
+ bcc CopyDataInit
+ 8000908: d3f9 bcc.n 80008fe
+
+/* Zero fill the bss segment. */
+ ldr r2, =_sbss
+ 800090a: 4a11 ldr r2, [pc, #68] ; (8000950 )
+ ldr r4, =_ebss
+ 800090c: 4c11 ldr r4, [pc, #68] ; (8000954 )
+ movs r3, #0
+ 800090e: 2300 movs r3, #0
+ b LoopFillZerobss
+ 8000910: e001 b.n 8000916
+
+08000912 :
+
+FillZerobss:
+ str r3, [r2]
+ 8000912: 6013 str r3, [r2, #0]
+ adds r2, r2, #4
+ 8000914: 3204 adds r2, #4
+
+08000916 :
+
+LoopFillZerobss:
+ cmp r2, r4
+ 8000916: 42a2 cmp r2, r4
+ bcc FillZerobss
+ 8000918: d3fb bcc.n 8000912
+
+/* Call the clock system intitialization function.*/
+ bl SystemInit
+ 800091a: f7ff ffd8 bl 80008ce
+/* Call static constructors */
+ bl __libc_init_array
+ 800091e: f001 ff29 bl 8002774 <__libc_init_array>
+/* Call the application's entry point.*/
+ bl main
+ 8000922: f7ff fdb3 bl 800048c
+
+08000926 :
+
+LoopForever:
+ b LoopForever
+ 8000926: e7fe b.n 8000926
+ ldr r0, =_estack
+ 8000928: 20000800 .word 0x20000800
+ LDR R0,=0x00000004
+ 800092c: 00000004 .word 0x00000004
+ LDR R2,=0x1F
+ 8000930: 0000001f .word 0x0000001f
+ LDR R0,=0x40021034
+ 8000934: 40021034 .word 0x40021034
+ LDR R1,=0x00000001
+ 8000938: 00000001 .word 0x00000001
+ LDR R0,=0x40010000
+ 800093c: 40010000 .word 0x40010000
+ LDR R1,=0x00000000
+ 8000940: 00000000 .word 0x00000000
+ ldr r0, =_sdata
+ 8000944: 20000000 .word 0x20000000
+ ldr r1, =_edata
+ 8000948: 2000000c .word 0x2000000c
+ ldr r2, =_sidata
+ 800094c: 08002860 .word 0x08002860
+ ldr r2, =_sbss
+ 8000950: 2000000c .word 0x2000000c
+ ldr r4, =_ebss
+ 8000954: 200000fc .word 0x200000fc
+
+08000958 :
+ * @retval : None
+*/
+ .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+ b Infinite_Loop
+ 8000958: e7fe b.n 8000958
+ ...
+
+0800095c :
+ * In the default implementation,Systick is used as source of time base.
+ * the tick variable is incremented each 1ms in its ISR.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_Init(void)
+{
+ 800095c: b580 push {r7, lr}
+ 800095e: b082 sub sp, #8
+ 8000960: af00 add r7, sp, #0
+ HAL_StatusTypeDef status = HAL_OK;
+ 8000962: 1dfb adds r3, r7, #7
+ 8000964: 2200 movs r2, #0
+ 8000966: 701a strb r2, [r3, #0]
+#if (BUFFER_CACHE_DISABLE != 0)
+ __HAL_FLASH_BUFFER_CACHE_DISABLE();
+#endif /* BUFFER_CACHE_DISABLE */
+
+#if (PREREAD_ENABLE != 0)
+ __HAL_FLASH_PREREAD_BUFFER_ENABLE();
+ 8000968: 4b0b ldr r3, [pc, #44] ; (8000998 )
+ 800096a: 681a ldr r2, [r3, #0]
+ 800096c: 4b0a ldr r3, [pc, #40] ; (8000998 )
+ 800096e: 2140 movs r1, #64 ; 0x40
+ 8000970: 430a orrs r2, r1
+ 8000972: 601a str r2, [r3, #0]
+#if (PREFETCH_ENABLE != 0)
+ __HAL_FLASH_PREFETCH_BUFFER_ENABLE();
+#endif /* PREFETCH_ENABLE */
+
+ /* Use SysTick as time base source and configure 1ms tick (default clock after Reset is MSI) */
+ if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK)
+ 8000974: 2000 movs r0, #0
+ 8000976: f000 f811 bl 800099c
+ 800097a: 1e03 subs r3, r0, #0
+ 800097c: d003 beq.n 8000986
+ {
+ status = HAL_ERROR;
+ 800097e: 1dfb adds r3, r7, #7
+ 8000980: 2201 movs r2, #1
+ 8000982: 701a strb r2, [r3, #0]
+ 8000984: e001 b.n 800098a
+ }
+ else
+ {
+ /* Init the low level hardware */
+ HAL_MspInit();
+ 8000986: f7ff feef bl 8000768
+ }
+
+ /* Return function status */
+ return status;
+ 800098a: 1dfb adds r3, r7, #7
+ 800098c: 781b ldrb r3, [r3, #0]
+}
+ 800098e: 0018 movs r0, r3
+ 8000990: 46bd mov sp, r7
+ 8000992: b002 add sp, #8
+ 8000994: bd80 pop {r7, pc}
+ 8000996: 46c0 nop ; (mov r8, r8)
+ 8000998: 40022000 .word 0x40022000
+
+0800099c :
+ * implementation in user file.
+ * @param TickPriority Tick interrupt priority.
+ * @retval HAL status
+ */
+__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
+{
+ 800099c: b590 push {r4, r7, lr}
+ 800099e: b083 sub sp, #12
+ 80009a0: af00 add r7, sp, #0
+ 80009a2: 6078 str r0, [r7, #4]
+ /* Configure the SysTick to have interrupt in 1ms time basis*/
+ if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U)
+ 80009a4: 4b14 ldr r3, [pc, #80] ; (80009f8 )
+ 80009a6: 681c ldr r4, [r3, #0]
+ 80009a8: 4b14 ldr r3, [pc, #80] ; (80009fc )
+ 80009aa: 781b ldrb r3, [r3, #0]
+ 80009ac: 0019 movs r1, r3
+ 80009ae: 23fa movs r3, #250 ; 0xfa
+ 80009b0: 0098 lsls r0, r3, #2
+ 80009b2: f7ff fba9 bl 8000108 <__udivsi3>
+ 80009b6: 0003 movs r3, r0
+ 80009b8: 0019 movs r1, r3
+ 80009ba: 0020 movs r0, r4
+ 80009bc: f7ff fba4 bl 8000108 <__udivsi3>
+ 80009c0: 0003 movs r3, r0
+ 80009c2: 0018 movs r0, r3
+ 80009c4: f000 f903 bl 8000bce
+ 80009c8: 1e03 subs r3, r0, #0
+ 80009ca: d001 beq.n 80009d0
+ {
+ return HAL_ERROR;
+ 80009cc: 2301 movs r3, #1
+ 80009ce: e00f b.n 80009f0
+ }
+
+ /* Configure the SysTick IRQ priority */
+ if (TickPriority < (1UL << __NVIC_PRIO_BITS))
+ 80009d0: 687b ldr r3, [r7, #4]
+ 80009d2: 2b03 cmp r3, #3
+ 80009d4: d80b bhi.n 80009ee
+ {
+ HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
+ 80009d6: 6879 ldr r1, [r7, #4]
+ 80009d8: 2301 movs r3, #1
+ 80009da: 425b negs r3, r3
+ 80009dc: 2200 movs r2, #0
+ 80009de: 0018 movs r0, r3
+ 80009e0: f000 f8e0 bl 8000ba4
+ uwTickPrio = TickPriority;
+ 80009e4: 4b06 ldr r3, [pc, #24] ; (8000a00 )
+ 80009e6: 687a ldr r2, [r7, #4]
+ 80009e8: 601a str r2, [r3, #0]
+ {
+ return HAL_ERROR;
+ }
+
+ /* Return function status */
+ return HAL_OK;
+ 80009ea: 2300 movs r3, #0
+ 80009ec: e000 b.n 80009f0
+ return HAL_ERROR;
+ 80009ee: 2301 movs r3, #1
+}
+ 80009f0: 0018 movs r0, r3
+ 80009f2: 46bd mov sp, r7
+ 80009f4: b003 add sp, #12
+ 80009f6: bd90 pop {r4, r7, pc}
+ 80009f8: 20000000 .word 0x20000000
+ 80009fc: 20000008 .word 0x20000008
+ 8000a00: 20000004 .word 0x20000004
+
+08000a04 :
+ * @note This function is declared as __weak to be overwritten in case of other
+ * implementations in user file.
+ * @retval None
+ */
+__weak void HAL_IncTick(void)
+{
+ 8000a04: b580 push {r7, lr}
+ 8000a06: af00 add r7, sp, #0
+ uwTick += uwTickFreq;
+ 8000a08: 4b05 ldr r3, [pc, #20] ; (8000a20 )
+ 8000a0a: 781b ldrb r3, [r3, #0]
+ 8000a0c: 001a movs r2, r3
+ 8000a0e: 4b05 ldr r3, [pc, #20] ; (8000a24 )
+ 8000a10: 681b ldr r3, [r3, #0]
+ 8000a12: 18d2 adds r2, r2, r3
+ 8000a14: 4b03 ldr r3, [pc, #12] ; (8000a24 )
+ 8000a16: 601a str r2, [r3, #0]
+}
+ 8000a18: 46c0 nop ; (mov r8, r8)
+ 8000a1a: 46bd mov sp, r7
+ 8000a1c: bd80 pop {r7, pc}
+ 8000a1e: 46c0 nop ; (mov r8, r8)
+ 8000a20: 20000008 .word 0x20000008
+ 8000a24: 200000f8 .word 0x200000f8
+
+08000a28 :
+ * @note This function is declared as __weak to be overwritten in case of other
+ * implementations in user file.
+ * @retval tick value
+ */
+__weak uint32_t HAL_GetTick(void)
+{
+ 8000a28: b580 push {r7, lr}
+ 8000a2a: af00 add r7, sp, #0
+ return uwTick;
+ 8000a2c: 4b02 ldr r3, [pc, #8] ; (8000a38 )
+ 8000a2e: 681b ldr r3, [r3, #0]
+}
+ 8000a30: 0018 movs r0, r3
+ 8000a32: 46bd mov sp, r7
+ 8000a34: bd80 pop {r7, pc}
+ 8000a36: 46c0 nop ; (mov r8, r8)
+ 8000a38: 200000f8 .word 0x200000f8
+
+08000a3c :
+ * implementations in user file.
+ * @param Delay specifies the delay time length, in milliseconds.
+ * @retval None
+ */
+__weak void HAL_Delay(uint32_t Delay)
+{
+ 8000a3c: b580 push {r7, lr}
+ 8000a3e: b084 sub sp, #16
+ 8000a40: af00 add r7, sp, #0
+ 8000a42: 6078 str r0, [r7, #4]
+ uint32_t tickstart = HAL_GetTick();
+ 8000a44: f7ff fff0 bl 8000a28
+ 8000a48: 0003 movs r3, r0
+ 8000a4a: 60bb str r3, [r7, #8]
+ uint32_t wait = Delay;
+ 8000a4c: 687b ldr r3, [r7, #4]
+ 8000a4e: 60fb str r3, [r7, #12]
+
+ /* Add a freq to guarantee minimum wait */
+ if (wait < HAL_MAX_DELAY)
+ 8000a50: 68fb ldr r3, [r7, #12]
+ 8000a52: 3301 adds r3, #1
+ 8000a54: d005 beq.n 8000a62
+ {
+ wait += (uint32_t)(uwTickFreq);
+ 8000a56: 4b09 ldr r3, [pc, #36] ; (8000a7c )
+ 8000a58: 781b ldrb r3, [r3, #0]
+ 8000a5a: 001a movs r2, r3
+ 8000a5c: 68fb ldr r3, [r7, #12]
+ 8000a5e: 189b adds r3, r3, r2
+ 8000a60: 60fb str r3, [r7, #12]
+ }
+
+ while((HAL_GetTick() - tickstart) < wait)
+ 8000a62: 46c0 nop ; (mov r8, r8)
+ 8000a64: f7ff ffe0 bl 8000a28
+ 8000a68: 0002 movs r2, r0
+ 8000a6a: 68bb ldr r3, [r7, #8]
+ 8000a6c: 1ad3 subs r3, r2, r3
+ 8000a6e: 68fa ldr r2, [r7, #12]
+ 8000a70: 429a cmp r2, r3
+ 8000a72: d8f7 bhi.n 8000a64
+ {
+ }
+}
+ 8000a74: 46c0 nop ; (mov r8, r8)
+ 8000a76: 46bd mov sp, r7
+ 8000a78: b004 add sp, #16
+ 8000a7a: bd80 pop {r7, pc}
+ 8000a7c: 20000008 .word 0x20000008
+
+08000a80 <__NVIC_SetPriority>:
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ \note The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ 8000a80: b590 push {r4, r7, lr}
+ 8000a82: b083 sub sp, #12
+ 8000a84: af00 add r7, sp, #0
+ 8000a86: 0002 movs r2, r0
+ 8000a88: 6039 str r1, [r7, #0]
+ 8000a8a: 1dfb adds r3, r7, #7
+ 8000a8c: 701a strb r2, [r3, #0]
+ if ((int32_t)(IRQn) >= 0)
+ 8000a8e: 1dfb adds r3, r7, #7
+ 8000a90: 781b ldrb r3, [r3, #0]
+ 8000a92: 2b7f cmp r3, #127 ; 0x7f
+ 8000a94: d828 bhi.n 8000ae8 <__NVIC_SetPriority+0x68>
+ {
+ NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ 8000a96: 4a2f ldr r2, [pc, #188] ; (8000b54 <__NVIC_SetPriority+0xd4>)
+ 8000a98: 1dfb adds r3, r7, #7
+ 8000a9a: 781b ldrb r3, [r3, #0]
+ 8000a9c: b25b sxtb r3, r3
+ 8000a9e: 089b lsrs r3, r3, #2
+ 8000aa0: 33c0 adds r3, #192 ; 0xc0
+ 8000aa2: 009b lsls r3, r3, #2
+ 8000aa4: 589b ldr r3, [r3, r2]
+ 8000aa6: 1dfa adds r2, r7, #7
+ 8000aa8: 7812 ldrb r2, [r2, #0]
+ 8000aaa: 0011 movs r1, r2
+ 8000aac: 2203 movs r2, #3
+ 8000aae: 400a ands r2, r1
+ 8000ab0: 00d2 lsls r2, r2, #3
+ 8000ab2: 21ff movs r1, #255 ; 0xff
+ 8000ab4: 4091 lsls r1, r2
+ 8000ab6: 000a movs r2, r1
+ 8000ab8: 43d2 mvns r2, r2
+ 8000aba: 401a ands r2, r3
+ 8000abc: 0011 movs r1, r2
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ 8000abe: 683b ldr r3, [r7, #0]
+ 8000ac0: 019b lsls r3, r3, #6
+ 8000ac2: 22ff movs r2, #255 ; 0xff
+ 8000ac4: 401a ands r2, r3
+ 8000ac6: 1dfb adds r3, r7, #7
+ 8000ac8: 781b ldrb r3, [r3, #0]
+ 8000aca: 0018 movs r0, r3
+ 8000acc: 2303 movs r3, #3
+ 8000ace: 4003 ands r3, r0
+ 8000ad0: 00db lsls r3, r3, #3
+ 8000ad2: 409a lsls r2, r3
+ NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ 8000ad4: 481f ldr r0, [pc, #124] ; (8000b54 <__NVIC_SetPriority+0xd4>)
+ 8000ad6: 1dfb adds r3, r7, #7
+ 8000ad8: 781b ldrb r3, [r3, #0]
+ 8000ada: b25b sxtb r3, r3
+ 8000adc: 089b lsrs r3, r3, #2
+ 8000ade: 430a orrs r2, r1
+ 8000ae0: 33c0 adds r3, #192 ; 0xc0
+ 8000ae2: 009b lsls r3, r3, #2
+ 8000ae4: 501a str r2, [r3, r0]
+ else
+ {
+ SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
+}
+ 8000ae6: e031 b.n 8000b4c <__NVIC_SetPriority+0xcc>
+ SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ 8000ae8: 4a1b ldr r2, [pc, #108] ; (8000b58 <__NVIC_SetPriority+0xd8>)
+ 8000aea: 1dfb adds r3, r7, #7
+ 8000aec: 781b ldrb r3, [r3, #0]
+ 8000aee: 0019 movs r1, r3
+ 8000af0: 230f movs r3, #15
+ 8000af2: 400b ands r3, r1
+ 8000af4: 3b08 subs r3, #8
+ 8000af6: 089b lsrs r3, r3, #2
+ 8000af8: 3306 adds r3, #6
+ 8000afa: 009b lsls r3, r3, #2
+ 8000afc: 18d3 adds r3, r2, r3
+ 8000afe: 3304 adds r3, #4
+ 8000b00: 681b ldr r3, [r3, #0]
+ 8000b02: 1dfa adds r2, r7, #7
+ 8000b04: 7812 ldrb r2, [r2, #0]
+ 8000b06: 0011 movs r1, r2
+ 8000b08: 2203 movs r2, #3
+ 8000b0a: 400a ands r2, r1
+ 8000b0c: 00d2 lsls r2, r2, #3
+ 8000b0e: 21ff movs r1, #255 ; 0xff
+ 8000b10: 4091 lsls r1, r2
+ 8000b12: 000a movs r2, r1
+ 8000b14: 43d2 mvns r2, r2
+ 8000b16: 401a ands r2, r3
+ 8000b18: 0011 movs r1, r2
+ (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ 8000b1a: 683b ldr r3, [r7, #0]
+ 8000b1c: 019b lsls r3, r3, #6
+ 8000b1e: 22ff movs r2, #255 ; 0xff
+ 8000b20: 401a ands r2, r3
+ 8000b22: 1dfb adds r3, r7, #7
+ 8000b24: 781b ldrb r3, [r3, #0]
+ 8000b26: 0018 movs r0, r3
+ 8000b28: 2303 movs r3, #3
+ 8000b2a: 4003 ands r3, r0
+ 8000b2c: 00db lsls r3, r3, #3
+ 8000b2e: 409a lsls r2, r3
+ SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ 8000b30: 4809 ldr r0, [pc, #36] ; (8000b58 <__NVIC_SetPriority+0xd8>)
+ 8000b32: 1dfb adds r3, r7, #7
+ 8000b34: 781b ldrb r3, [r3, #0]
+ 8000b36: 001c movs r4, r3
+ 8000b38: 230f movs r3, #15
+ 8000b3a: 4023 ands r3, r4
+ 8000b3c: 3b08 subs r3, #8
+ 8000b3e: 089b lsrs r3, r3, #2
+ 8000b40: 430a orrs r2, r1
+ 8000b42: 3306 adds r3, #6
+ 8000b44: 009b lsls r3, r3, #2
+ 8000b46: 18c3 adds r3, r0, r3
+ 8000b48: 3304 adds r3, #4
+ 8000b4a: 601a str r2, [r3, #0]
+}
+ 8000b4c: 46c0 nop ; (mov r8, r8)
+ 8000b4e: 46bd mov sp, r7
+ 8000b50: b003 add sp, #12
+ 8000b52: bd90 pop {r4, r7, pc}
+ 8000b54: e000e100 .word 0xe000e100
+ 8000b58: e000ed00 .word 0xe000ed00
+
+08000b5c :
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device .h)
+ 8000b6a: 4293 cmp r3, r2
+ 8000b6c: d901 bls.n 8000b72
+ {
+ return (1UL); /* Reload value impossible */
+ 8000b6e: 2301 movs r3, #1
+ 8000b70: e010 b.n 8000b94
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ 8000b72: 4b0b ldr r3, [pc, #44] ; (8000ba0 )
+ 8000b74: 687a ldr r2, [r7, #4]
+ 8000b76: 3a01 subs r2, #1
+ 8000b78: 605a str r2, [r3, #4]
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ 8000b7a: 2301 movs r3, #1
+ 8000b7c: 425b negs r3, r3
+ 8000b7e: 2103 movs r1, #3
+ 8000b80: 0018 movs r0, r3
+ 8000b82: f7ff ff7d bl 8000a80 <__NVIC_SetPriority>
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ 8000b86: 4b06 ldr r3, [pc, #24] ; (8000ba0 )
+ 8000b88: 2200 movs r2, #0
+ 8000b8a: 609a str r2, [r3, #8]
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ 8000b8c: 4b04 ldr r3, [pc, #16] ; (8000ba0 )
+ 8000b8e: 2207 movs r2, #7
+ 8000b90: 601a str r2, [r3, #0]
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+ 8000b92: 2300 movs r3, #0
+}
+ 8000b94: 0018 movs r0, r3
+ 8000b96: 46bd mov sp, r7
+ 8000b98: b002 add sp, #8
+ 8000b9a: bd80 pop {r7, pc}
+ 8000b9c: 00ffffff .word 0x00ffffff
+ 8000ba0: e000e010 .word 0xe000e010
+
+08000ba4 :
+ * with stm32l0xx devices, this parameter is a dummy value and it is ignored, because
+ * no subpriority supported in Cortex M0+ based products.
+ * @retval None
+ */
+void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ 8000ba4: b580 push {r7, lr}
+ 8000ba6: b084 sub sp, #16
+ 8000ba8: af00 add r7, sp, #0
+ 8000baa: 60b9 str r1, [r7, #8]
+ 8000bac: 607a str r2, [r7, #4]
+ 8000bae: 210f movs r1, #15
+ 8000bb0: 187b adds r3, r7, r1
+ 8000bb2: 1c02 adds r2, r0, #0
+ 8000bb4: 701a strb r2, [r3, #0]
+ /* Check the parameters */
+ assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
+ NVIC_SetPriority(IRQn,PreemptPriority);
+ 8000bb6: 68ba ldr r2, [r7, #8]
+ 8000bb8: 187b adds r3, r7, r1
+ 8000bba: 781b ldrb r3, [r3, #0]
+ 8000bbc: b25b sxtb r3, r3
+ 8000bbe: 0011 movs r1, r2
+ 8000bc0: 0018 movs r0, r3
+ 8000bc2: f7ff ff5d bl 8000a80 <__NVIC_SetPriority>
+}
+ 8000bc6: 46c0 nop ; (mov r8, r8)
+ 8000bc8: 46bd mov sp, r7
+ 8000bca: b004 add sp, #16
+ 8000bcc: bd80 pop {r7, pc}
+
+08000bce :
+ * @param TicksNumb Specifies the ticks Number of ticks between two interrupts.
+ * @retval status: - 0 Function succeeded.
+ * - 1 Function failed.
+ */
+uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
+{
+ 8000bce: b580 push {r7, lr}
+ 8000bd0: b082 sub sp, #8
+ 8000bd2: af00 add r7, sp, #0
+ 8000bd4: 6078 str r0, [r7, #4]
+ return SysTick_Config(TicksNumb);
+ 8000bd6: 687b ldr r3, [r7, #4]
+ 8000bd8: 0018 movs r0, r3
+ 8000bda: f7ff ffbf bl 8000b5c
+ 8000bde: 0003 movs r3, r0
+}
+ 8000be0: 0018 movs r0, r3
+ 8000be2: 46bd mov sp, r7
+ 8000be4: b002 add sp, #8
+ 8000be6: bd80 pop {r7, pc}
+
+08000be8 :
+ * @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
+ * the configuration information for the specified GPIO peripheral.
+ * @retval None
+ */
+void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
+{
+ 8000be8: b580 push {r7, lr}
+ 8000bea: b086 sub sp, #24
+ 8000bec: af00 add r7, sp, #0
+ 8000bee: 6078 str r0, [r7, #4]
+ 8000bf0: 6039 str r1, [r7, #0]
+ uint32_t position = 0x00U;
+ 8000bf2: 2300 movs r3, #0
+ 8000bf4: 617b str r3, [r7, #20]
+ uint32_t iocurrent = 0x00U;
+ 8000bf6: 2300 movs r3, #0
+ 8000bf8: 60fb str r3, [r7, #12]
+ uint32_t temp = 0x00U;
+ 8000bfa: 2300 movs r3, #0
+ 8000bfc: 613b str r3, [r7, #16]
+ assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
+ assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
+ assert_param(IS_GPIO_PIN_AVAILABLE(GPIOx, (GPIO_Init->Pin)));
+
+ /* Configure the port pins */
+ while (((GPIO_Init->Pin) >> position) != 0)
+ 8000bfe: e143 b.n 8000e88
+ {
+ /* Get the IO position */
+ iocurrent = (GPIO_Init->Pin) & (1U << position);
+ 8000c00: 683b ldr r3, [r7, #0]
+ 8000c02: 681b ldr r3, [r3, #0]
+ 8000c04: 2101 movs r1, #1
+ 8000c06: 697a ldr r2, [r7, #20]
+ 8000c08: 4091 lsls r1, r2
+ 8000c0a: 000a movs r2, r1
+ 8000c0c: 4013 ands r3, r2
+ 8000c0e: 60fb str r3, [r7, #12]
+
+ if (iocurrent)
+ 8000c10: 68fb ldr r3, [r7, #12]
+ 8000c12: 2b00 cmp r3, #0
+ 8000c14: d100 bne.n 8000c18
+ 8000c16: e134 b.n 8000e82
+ {
+ /*--------------------- GPIO Mode Configuration ------------------------*/
+ /* In case of Output or Alternate function mode selection */
+ if ((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) ||
+ 8000c18: 683b ldr r3, [r7, #0]
+ 8000c1a: 685b ldr r3, [r3, #4]
+ 8000c1c: 2b01 cmp r3, #1
+ 8000c1e: d00b beq.n 8000c38
+ 8000c20: 683b ldr r3, [r7, #0]
+ 8000c22: 685b ldr r3, [r3, #4]
+ 8000c24: 2b02 cmp r3, #2
+ 8000c26: d007 beq.n 8000c38
+ (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
+ 8000c28: 683b ldr r3, [r7, #0]
+ 8000c2a: 685b ldr r3, [r3, #4]
+ if ((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) ||
+ 8000c2c: 2b11 cmp r3, #17
+ 8000c2e: d003 beq.n 8000c38
+ (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
+ 8000c30: 683b ldr r3, [r7, #0]
+ 8000c32: 685b ldr r3, [r3, #4]
+ 8000c34: 2b12 cmp r3, #18
+ 8000c36: d130 bne.n 8000c9a
+ {
+ /* Check the Speed parameter */
+ assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
+ /* Configure the IO Speed */
+ temp = GPIOx->OSPEEDR;
+ 8000c38: 687b ldr r3, [r7, #4]
+ 8000c3a: 689b ldr r3, [r3, #8]
+ 8000c3c: 613b str r3, [r7, #16]
+ temp &= ~(GPIO_OSPEEDER_OSPEED0 << (position * 2U));
+ 8000c3e: 697b ldr r3, [r7, #20]
+ 8000c40: 005b lsls r3, r3, #1
+ 8000c42: 2203 movs r2, #3
+ 8000c44: 409a lsls r2, r3
+ 8000c46: 0013 movs r3, r2
+ 8000c48: 43da mvns r2, r3
+ 8000c4a: 693b ldr r3, [r7, #16]
+ 8000c4c: 4013 ands r3, r2
+ 8000c4e: 613b str r3, [r7, #16]
+ temp |= (GPIO_Init->Speed << (position * 2U));
+ 8000c50: 683b ldr r3, [r7, #0]
+ 8000c52: 68da ldr r2, [r3, #12]
+ 8000c54: 697b ldr r3, [r7, #20]
+ 8000c56: 005b lsls r3, r3, #1
+ 8000c58: 409a lsls r2, r3
+ 8000c5a: 0013 movs r3, r2
+ 8000c5c: 693a ldr r2, [r7, #16]
+ 8000c5e: 4313 orrs r3, r2
+ 8000c60: 613b str r3, [r7, #16]
+ GPIOx->OSPEEDR = temp;
+ 8000c62: 687b ldr r3, [r7, #4]
+ 8000c64: 693a ldr r2, [r7, #16]
+ 8000c66: 609a str r2, [r3, #8]
+
+ /* Configure the IO Output Type */
+ temp = GPIOx->OTYPER;
+ 8000c68: 687b ldr r3, [r7, #4]
+ 8000c6a: 685b ldr r3, [r3, #4]
+ 8000c6c: 613b str r3, [r7, #16]
+ temp &= ~(GPIO_OTYPER_OT_0 << position) ;
+ 8000c6e: 2201 movs r2, #1
+ 8000c70: 697b ldr r3, [r7, #20]
+ 8000c72: 409a lsls r2, r3
+ 8000c74: 0013 movs r3, r2
+ 8000c76: 43da mvns r2, r3
+ 8000c78: 693b ldr r3, [r7, #16]
+ 8000c7a: 4013 ands r3, r2
+ 8000c7c: 613b str r3, [r7, #16]
+ temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4U) << position);
+ 8000c7e: 683b ldr r3, [r7, #0]
+ 8000c80: 685b ldr r3, [r3, #4]
+ 8000c82: 091b lsrs r3, r3, #4
+ 8000c84: 2201 movs r2, #1
+ 8000c86: 401a ands r2, r3
+ 8000c88: 697b ldr r3, [r7, #20]
+ 8000c8a: 409a lsls r2, r3
+ 8000c8c: 0013 movs r3, r2
+ 8000c8e: 693a ldr r2, [r7, #16]
+ 8000c90: 4313 orrs r3, r2
+ 8000c92: 613b str r3, [r7, #16]
+ GPIOx->OTYPER = temp;
+ 8000c94: 687b ldr r3, [r7, #4]
+ 8000c96: 693a ldr r2, [r7, #16]
+ 8000c98: 605a str r2, [r3, #4]
+ }
+
+ /* Activate the Pull-up or Pull down resistor for the current IO */
+ temp = GPIOx->PUPDR;
+ 8000c9a: 687b ldr r3, [r7, #4]
+ 8000c9c: 68db ldr r3, [r3, #12]
+ 8000c9e: 613b str r3, [r7, #16]
+ temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2U));
+ 8000ca0: 697b ldr r3, [r7, #20]
+ 8000ca2: 005b lsls r3, r3, #1
+ 8000ca4: 2203 movs r2, #3
+ 8000ca6: 409a lsls r2, r3
+ 8000ca8: 0013 movs r3, r2
+ 8000caa: 43da mvns r2, r3
+ 8000cac: 693b ldr r3, [r7, #16]
+ 8000cae: 4013 ands r3, r2
+ 8000cb0: 613b str r3, [r7, #16]
+ temp |= ((GPIO_Init->Pull) << (position * 2U));
+ 8000cb2: 683b ldr r3, [r7, #0]
+ 8000cb4: 689a ldr r2, [r3, #8]
+ 8000cb6: 697b ldr r3, [r7, #20]
+ 8000cb8: 005b lsls r3, r3, #1
+ 8000cba: 409a lsls r2, r3
+ 8000cbc: 0013 movs r3, r2
+ 8000cbe: 693a ldr r2, [r7, #16]
+ 8000cc0: 4313 orrs r3, r2
+ 8000cc2: 613b str r3, [r7, #16]
+ GPIOx->PUPDR = temp;
+ 8000cc4: 687b ldr r3, [r7, #4]
+ 8000cc6: 693a ldr r2, [r7, #16]
+ 8000cc8: 60da str r2, [r3, #12]
+
+ /* In case of Alternate function mode selection */
+ if ((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
+ 8000cca: 683b ldr r3, [r7, #0]
+ 8000ccc: 685b ldr r3, [r3, #4]
+ 8000cce: 2b02 cmp r3, #2
+ 8000cd0: d003 beq.n 8000cda
+ 8000cd2: 683b ldr r3, [r7, #0]
+ 8000cd4: 685b ldr r3, [r3, #4]
+ 8000cd6: 2b12 cmp r3, #18
+ 8000cd8: d123 bne.n 8000d22
+ /* Check the Alternate function parameters */
+ assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
+ assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
+
+ /* Configure Alternate function mapped with the current IO */
+ temp = GPIOx->AFR[position >> 3U];
+ 8000cda: 697b ldr r3, [r7, #20]
+ 8000cdc: 08da lsrs r2, r3, #3
+ 8000cde: 687b ldr r3, [r7, #4]
+ 8000ce0: 3208 adds r2, #8
+ 8000ce2: 0092 lsls r2, r2, #2
+ 8000ce4: 58d3 ldr r3, [r2, r3]
+ 8000ce6: 613b str r3, [r7, #16]
+ temp &= ~(0xFUL << ((uint32_t)(position & 0x07UL) * 4U));
+ 8000ce8: 697b ldr r3, [r7, #20]
+ 8000cea: 2207 movs r2, #7
+ 8000cec: 4013 ands r3, r2
+ 8000cee: 009b lsls r3, r3, #2
+ 8000cf0: 220f movs r2, #15
+ 8000cf2: 409a lsls r2, r3
+ 8000cf4: 0013 movs r3, r2
+ 8000cf6: 43da mvns r2, r3
+ 8000cf8: 693b ldr r3, [r7, #16]
+ 8000cfa: 4013 ands r3, r2
+ 8000cfc: 613b str r3, [r7, #16]
+ temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & (uint32_t)0x07U) * 4U));
+ 8000cfe: 683b ldr r3, [r7, #0]
+ 8000d00: 691a ldr r2, [r3, #16]
+ 8000d02: 697b ldr r3, [r7, #20]
+ 8000d04: 2107 movs r1, #7
+ 8000d06: 400b ands r3, r1
+ 8000d08: 009b lsls r3, r3, #2
+ 8000d0a: 409a lsls r2, r3
+ 8000d0c: 0013 movs r3, r2
+ 8000d0e: 693a ldr r2, [r7, #16]
+ 8000d10: 4313 orrs r3, r2
+ 8000d12: 613b str r3, [r7, #16]
+ GPIOx->AFR[position >> 3U] = temp;
+ 8000d14: 697b ldr r3, [r7, #20]
+ 8000d16: 08da lsrs r2, r3, #3
+ 8000d18: 687b ldr r3, [r7, #4]
+ 8000d1a: 3208 adds r2, #8
+ 8000d1c: 0092 lsls r2, r2, #2
+ 8000d1e: 6939 ldr r1, [r7, #16]
+ 8000d20: 50d1 str r1, [r2, r3]
+ }
+
+ /* Configure IO Direction mode (Input, Output, Alternate or Analog) */
+ temp = GPIOx->MODER;
+ 8000d22: 687b ldr r3, [r7, #4]
+ 8000d24: 681b ldr r3, [r3, #0]
+ 8000d26: 613b str r3, [r7, #16]
+ temp &= ~(GPIO_MODER_MODE0 << (position * 2U));
+ 8000d28: 697b ldr r3, [r7, #20]
+ 8000d2a: 005b lsls r3, r3, #1
+ 8000d2c: 2203 movs r2, #3
+ 8000d2e: 409a lsls r2, r3
+ 8000d30: 0013 movs r3, r2
+ 8000d32: 43da mvns r2, r3
+ 8000d34: 693b ldr r3, [r7, #16]
+ 8000d36: 4013 ands r3, r2
+ 8000d38: 613b str r3, [r7, #16]
+ temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U));
+ 8000d3a: 683b ldr r3, [r7, #0]
+ 8000d3c: 685b ldr r3, [r3, #4]
+ 8000d3e: 2203 movs r2, #3
+ 8000d40: 401a ands r2, r3
+ 8000d42: 697b ldr r3, [r7, #20]
+ 8000d44: 005b lsls r3, r3, #1
+ 8000d46: 409a lsls r2, r3
+ 8000d48: 0013 movs r3, r2
+ 8000d4a: 693a ldr r2, [r7, #16]
+ 8000d4c: 4313 orrs r3, r2
+ 8000d4e: 613b str r3, [r7, #16]
+ GPIOx->MODER = temp;
+ 8000d50: 687b ldr r3, [r7, #4]
+ 8000d52: 693a ldr r2, [r7, #16]
+ 8000d54: 601a str r2, [r3, #0]
+
+ /*--------------------- EXTI Mode Configuration ------------------------*/
+ /* Configure the External Interrupt or event for the current IO */
+ if ((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
+ 8000d56: 683b ldr r3, [r7, #0]
+ 8000d58: 685a ldr r2, [r3, #4]
+ 8000d5a: 2380 movs r3, #128 ; 0x80
+ 8000d5c: 055b lsls r3, r3, #21
+ 8000d5e: 4013 ands r3, r2
+ 8000d60: d100 bne.n 8000d64
+ 8000d62: e08e b.n 8000e82
+ {
+ /* Enable SYSCFG Clock */
+ __HAL_RCC_SYSCFG_CLK_ENABLE();
+ 8000d64: 4b4e ldr r3, [pc, #312] ; (8000ea0 )
+ 8000d66: 6b5a ldr r2, [r3, #52] ; 0x34
+ 8000d68: 4b4d ldr r3, [pc, #308] ; (8000ea0 )
+ 8000d6a: 2101 movs r1, #1
+ 8000d6c: 430a orrs r2, r1
+ 8000d6e: 635a str r2, [r3, #52] ; 0x34
+
+ temp = SYSCFG->EXTICR[position >> 2U];
+ 8000d70: 4a4c ldr r2, [pc, #304] ; (8000ea4 )
+ 8000d72: 697b ldr r3, [r7, #20]
+ 8000d74: 089b lsrs r3, r3, #2
+ 8000d76: 3302 adds r3, #2
+ 8000d78: 009b lsls r3, r3, #2
+ 8000d7a: 589b ldr r3, [r3, r2]
+ 8000d7c: 613b str r3, [r7, #16]
+ CLEAR_BIT(temp, (0x0FUL) << (4U * (position & 0x03U)));
+ 8000d7e: 697b ldr r3, [r7, #20]
+ 8000d80: 2203 movs r2, #3
+ 8000d82: 4013 ands r3, r2
+ 8000d84: 009b lsls r3, r3, #2
+ 8000d86: 220f movs r2, #15
+ 8000d88: 409a lsls r2, r3
+ 8000d8a: 0013 movs r3, r2
+ 8000d8c: 43da mvns r2, r3
+ 8000d8e: 693b ldr r3, [r7, #16]
+ 8000d90: 4013 ands r3, r2
+ 8000d92: 613b str r3, [r7, #16]
+ SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03U)));
+ 8000d94: 687a ldr r2, [r7, #4]
+ 8000d96: 23a0 movs r3, #160 ; 0xa0
+ 8000d98: 05db lsls r3, r3, #23
+ 8000d9a: 429a cmp r2, r3
+ 8000d9c: d00d beq.n 8000dba
+ 8000d9e: 687b ldr r3, [r7, #4]
+ 8000da0: 4a41 ldr r2, [pc, #260] ; (8000ea8 )
+ 8000da2: 4293 cmp r3, r2
+ 8000da4: d007 beq.n 8000db6
+ 8000da6: 687b ldr r3, [r7, #4]
+ 8000da8: 4a40 ldr r2, [pc, #256] ; (8000eac )
+ 8000daa: 4293 cmp r3, r2
+ 8000dac: d101 bne.n 8000db2
+ 8000dae: 2302 movs r3, #2
+ 8000db0: e004 b.n 8000dbc
+ 8000db2: 2306 movs r3, #6
+ 8000db4: e002 b.n 8000dbc
+ 8000db6: 2301 movs r3, #1
+ 8000db8: e000 b.n 8000dbc
+ 8000dba: 2300 movs r3, #0
+ 8000dbc: 697a ldr r2, [r7, #20]
+ 8000dbe: 2103 movs r1, #3
+ 8000dc0: 400a ands r2, r1
+ 8000dc2: 0092 lsls r2, r2, #2
+ 8000dc4: 4093 lsls r3, r2
+ 8000dc6: 693a ldr r2, [r7, #16]
+ 8000dc8: 4313 orrs r3, r2
+ 8000dca: 613b str r3, [r7, #16]
+ SYSCFG->EXTICR[position >> 2U] = temp;
+ 8000dcc: 4935 ldr r1, [pc, #212] ; (8000ea4 )
+ 8000dce: 697b ldr r3, [r7, #20]
+ 8000dd0: 089b lsrs r3, r3, #2
+ 8000dd2: 3302 adds r3, #2
+ 8000dd4: 009b lsls r3, r3, #2
+ 8000dd6: 693a ldr r2, [r7, #16]
+ 8000dd8: 505a str r2, [r3, r1]
+
+ /* Clear EXTI line configuration */
+ temp = EXTI->IMR;
+ 8000dda: 4b35 ldr r3, [pc, #212] ; (8000eb0 )
+ 8000ddc: 681b ldr r3, [r3, #0]
+ 8000dde: 613b str r3, [r7, #16]
+ temp &= ~((uint32_t)iocurrent);
+ 8000de0: 68fb ldr r3, [r7, #12]
+ 8000de2: 43da mvns r2, r3
+ 8000de4: 693b ldr r3, [r7, #16]
+ 8000de6: 4013 ands r3, r2
+ 8000de8: 613b str r3, [r7, #16]
+ if ((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
+ 8000dea: 683b ldr r3, [r7, #0]
+ 8000dec: 685a ldr r2, [r3, #4]
+ 8000dee: 2380 movs r3, #128 ; 0x80
+ 8000df0: 025b lsls r3, r3, #9
+ 8000df2: 4013 ands r3, r2
+ 8000df4: d003 beq.n 8000dfe
+ {
+ temp |= iocurrent;
+ 8000df6: 693a ldr r2, [r7, #16]
+ 8000df8: 68fb ldr r3, [r7, #12]
+ 8000dfa: 4313 orrs r3, r2
+ 8000dfc: 613b str r3, [r7, #16]
+ }
+ EXTI->IMR = temp;
+ 8000dfe: 4b2c ldr r3, [pc, #176] ; (8000eb0 )
+ 8000e00: 693a ldr r2, [r7, #16]
+ 8000e02: 601a str r2, [r3, #0]
+
+ temp = EXTI->EMR;
+ 8000e04: 4b2a ldr r3, [pc, #168] ; (8000eb0 )
+ 8000e06: 685b ldr r3, [r3, #4]
+ 8000e08: 613b str r3, [r7, #16]
+ temp &= ~((uint32_t)iocurrent);
+ 8000e0a: 68fb ldr r3, [r7, #12]
+ 8000e0c: 43da mvns r2, r3
+ 8000e0e: 693b ldr r3, [r7, #16]
+ 8000e10: 4013 ands r3, r2
+ 8000e12: 613b str r3, [r7, #16]
+ if ((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
+ 8000e14: 683b ldr r3, [r7, #0]
+ 8000e16: 685a ldr r2, [r3, #4]
+ 8000e18: 2380 movs r3, #128 ; 0x80
+ 8000e1a: 029b lsls r3, r3, #10
+ 8000e1c: 4013 ands r3, r2
+ 8000e1e: d003 beq.n 8000e28
+ {
+ temp |= iocurrent;
+ 8000e20: 693a ldr r2, [r7, #16]
+ 8000e22: 68fb ldr r3, [r7, #12]
+ 8000e24: 4313 orrs r3, r2
+ 8000e26: 613b str r3, [r7, #16]
+ }
+ EXTI->EMR = temp;
+ 8000e28: 4b21 ldr r3, [pc, #132] ; (8000eb0 )
+ 8000e2a: 693a ldr r2, [r7, #16]
+ 8000e2c: 605a str r2, [r3, #4]
+
+ /* Clear Rising Falling edge configuration */
+ temp = EXTI->RTSR;
+ 8000e2e: 4b20 ldr r3, [pc, #128] ; (8000eb0 )
+ 8000e30: 689b ldr r3, [r3, #8]
+ 8000e32: 613b str r3, [r7, #16]
+ temp &= ~((uint32_t)iocurrent);
+ 8000e34: 68fb ldr r3, [r7, #12]
+ 8000e36: 43da mvns r2, r3
+ 8000e38: 693b ldr r3, [r7, #16]
+ 8000e3a: 4013 ands r3, r2
+ 8000e3c: 613b str r3, [r7, #16]
+ if ((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
+ 8000e3e: 683b ldr r3, [r7, #0]
+ 8000e40: 685a ldr r2, [r3, #4]
+ 8000e42: 2380 movs r3, #128 ; 0x80
+ 8000e44: 035b lsls r3, r3, #13
+ 8000e46: 4013 ands r3, r2
+ 8000e48: d003 beq.n 8000e52
+ {
+ temp |= iocurrent;
+ 8000e4a: 693a ldr r2, [r7, #16]
+ 8000e4c: 68fb ldr r3, [r7, #12]
+ 8000e4e: 4313 orrs r3, r2
+ 8000e50: 613b str r3, [r7, #16]
+ }
+ EXTI->RTSR = temp;
+ 8000e52: 4b17 ldr r3, [pc, #92] ; (8000eb0 )
+ 8000e54: 693a ldr r2, [r7, #16]
+ 8000e56: 609a str r2, [r3, #8]
+
+ temp = EXTI->FTSR;
+ 8000e58: 4b15 ldr r3, [pc, #84] ; (8000eb0 )
+ 8000e5a: 68db ldr r3, [r3, #12]
+ 8000e5c: 613b str r3, [r7, #16]
+ temp &= ~((uint32_t)iocurrent);
+ 8000e5e: 68fb ldr r3, [r7, #12]
+ 8000e60: 43da mvns r2, r3
+ 8000e62: 693b ldr r3, [r7, #16]
+ 8000e64: 4013 ands r3, r2
+ 8000e66: 613b str r3, [r7, #16]
+ if ((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
+ 8000e68: 683b ldr r3, [r7, #0]
+ 8000e6a: 685a ldr r2, [r3, #4]
+ 8000e6c: 2380 movs r3, #128 ; 0x80
+ 8000e6e: 039b lsls r3, r3, #14
+ 8000e70: 4013 ands r3, r2
+ 8000e72: d003 beq.n 8000e7c
+ {
+ temp |= iocurrent;
+ 8000e74: 693a ldr r2, [r7, #16]
+ 8000e76: 68fb ldr r3, [r7, #12]
+ 8000e78: 4313 orrs r3, r2
+ 8000e7a: 613b str r3, [r7, #16]
+ }
+ EXTI->FTSR = temp;
+ 8000e7c: 4b0c ldr r3, [pc, #48] ; (8000eb0 )
+ 8000e7e: 693a ldr r2, [r7, #16]
+ 8000e80: 60da str r2, [r3, #12]
+ }
+ }
+ position++;
+ 8000e82: 697b ldr r3, [r7, #20]
+ 8000e84: 3301 adds r3, #1
+ 8000e86: 617b str r3, [r7, #20]
+ while (((GPIO_Init->Pin) >> position) != 0)
+ 8000e88: 683b ldr r3, [r7, #0]
+ 8000e8a: 681a ldr r2, [r3, #0]
+ 8000e8c: 697b ldr r3, [r7, #20]
+ 8000e8e: 40da lsrs r2, r3
+ 8000e90: 1e13 subs r3, r2, #0
+ 8000e92: d000 beq.n 8000e96
+ 8000e94: e6b4 b.n 8000c00
+ }
+}
+ 8000e96: 46c0 nop ; (mov r8, r8)
+ 8000e98: 46bd mov sp, r7
+ 8000e9a: b006 add sp, #24
+ 8000e9c: bd80 pop {r7, pc}
+ 8000e9e: 46c0 nop ; (mov r8, r8)
+ 8000ea0: 40021000 .word 0x40021000
+ 8000ea4: 40010000 .word 0x40010000
+ 8000ea8: 50000400 .word 0x50000400
+ 8000eac: 50000800 .word 0x50000800
+ 8000eb0: 40010400 .word 0x40010400
+
+08000eb4 :
+ * GPIO_PIN_RESET: to clear the port pin
+ * GPIO_PIN_SET: to set the port pin
+ * @retval None
+ */
+void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
+{
+ 8000eb4: b580 push {r7, lr}
+ 8000eb6: b082 sub sp, #8
+ 8000eb8: af00 add r7, sp, #0
+ 8000eba: 6078 str r0, [r7, #4]
+ 8000ebc: 0008 movs r0, r1
+ 8000ebe: 0011 movs r1, r2
+ 8000ec0: 1cbb adds r3, r7, #2
+ 8000ec2: 1c02 adds r2, r0, #0
+ 8000ec4: 801a strh r2, [r3, #0]
+ 8000ec6: 1c7b adds r3, r7, #1
+ 8000ec8: 1c0a adds r2, r1, #0
+ 8000eca: 701a strb r2, [r3, #0]
+ /* Check the parameters */
+ assert_param(IS_GPIO_PIN_AVAILABLE(GPIOx, GPIO_Pin));
+ assert_param(IS_GPIO_PIN_ACTION(PinState));
+
+ if (PinState != GPIO_PIN_RESET)
+ 8000ecc: 1c7b adds r3, r7, #1
+ 8000ece: 781b ldrb r3, [r3, #0]
+ 8000ed0: 2b00 cmp r3, #0
+ 8000ed2: d004 beq.n 8000ede
+ {
+ GPIOx->BSRR = GPIO_Pin;
+ 8000ed4: 1cbb adds r3, r7, #2
+ 8000ed6: 881a ldrh r2, [r3, #0]
+ 8000ed8: 687b ldr r3, [r7, #4]
+ 8000eda: 619a str r2, [r3, #24]
+ }
+ else
+ {
+ GPIOx->BRR = GPIO_Pin ;
+ }
+}
+ 8000edc: e003 b.n 8000ee6
+ GPIOx->BRR = GPIO_Pin ;
+ 8000ede: 1cbb adds r3, r7, #2
+ 8000ee0: 881a ldrh r2, [r3, #0]
+ 8000ee2: 687b ldr r3, [r7, #4]
+ 8000ee4: 629a str r2, [r3, #40] ; 0x28
+}
+ 8000ee6: 46c0 nop ; (mov r8, r8)
+ 8000ee8: 46bd mov sp, r7
+ 8000eea: b002 add sp, #8
+ 8000eec: bd80 pop {r7, pc}
+
+08000eee :
+ * All port bits are not necessarily available on all GPIOs.
+ * @param GPIO_Pin Specifies the pins to be toggled.
+ * @retval None
+ */
+void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
+{
+ 8000eee: b580 push {r7, lr}
+ 8000ef0: b084 sub sp, #16
+ 8000ef2: af00 add r7, sp, #0
+ 8000ef4: 6078 str r0, [r7, #4]
+ 8000ef6: 000a movs r2, r1
+ 8000ef8: 1cbb adds r3, r7, #2
+ 8000efa: 801a strh r2, [r3, #0]
+
+ /* Check the parameters */
+ assert_param(IS_GPIO_PIN_AVAILABLE(GPIOx, GPIO_Pin));
+
+ /* get current Ouput Data Register value */
+ odr = GPIOx->ODR;
+ 8000efc: 687b ldr r3, [r7, #4]
+ 8000efe: 695b ldr r3, [r3, #20]
+ 8000f00: 60fb str r3, [r7, #12]
+
+ /* Set selected pins that were at low level, and reset ones that were high */
+ GPIOx->BSRR = ((odr & GPIO_Pin) << GPIO_NUMBER) | (~odr & GPIO_Pin);
+ 8000f02: 1cbb adds r3, r7, #2
+ 8000f04: 881b ldrh r3, [r3, #0]
+ 8000f06: 68fa ldr r2, [r7, #12]
+ 8000f08: 4013 ands r3, r2
+ 8000f0a: 041a lsls r2, r3, #16
+ 8000f0c: 68fb ldr r3, [r7, #12]
+ 8000f0e: 43db mvns r3, r3
+ 8000f10: 1cb9 adds r1, r7, #2
+ 8000f12: 8809 ldrh r1, [r1, #0]
+ 8000f14: 400b ands r3, r1
+ 8000f16: 431a orrs r2, r3
+ 8000f18: 687b ldr r3, [r7, #4]
+ 8000f1a: 619a str r2, [r3, #24]
+}
+ 8000f1c: 46c0 nop ; (mov r8, r8)
+ 8000f1e: 46bd mov sp, r7
+ 8000f20: b004 add sp, #16
+ 8000f22: bd80 pop {r7, pc}
+
+08000f24 :
+ * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
+ * the configuration information for the specified I2C.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
+{
+ 8000f24: b580 push {r7, lr}
+ 8000f26: b082 sub sp, #8
+ 8000f28: af00 add r7, sp, #0
+ 8000f2a: 6078 str r0, [r7, #4]
+ /* Check the I2C handle allocation */
+ if (hi2c == NULL)
+ 8000f2c: 687b ldr r3, [r7, #4]
+ 8000f2e: 2b00 cmp r3, #0
+ 8000f30: d101 bne.n 8000f36
+ {
+ return HAL_ERROR;
+ 8000f32: 2301 movs r3, #1
+ 8000f34: e082 b.n 800103c
+ assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2));
+ assert_param(IS_I2C_OWN_ADDRESS2_MASK(hi2c->Init.OwnAddress2Masks));
+ assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode));
+ assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode));
+
+ if (hi2c->State == HAL_I2C_STATE_RESET)
+ 8000f36: 687b ldr r3, [r7, #4]
+ 8000f38: 2241 movs r2, #65 ; 0x41
+ 8000f3a: 5c9b ldrb r3, [r3, r2]
+ 8000f3c: b2db uxtb r3, r3
+ 8000f3e: 2b00 cmp r3, #0
+ 8000f40: d107 bne.n 8000f52
+ {
+ /* Allocate lock resource and initialize it */
+ hi2c->Lock = HAL_UNLOCKED;
+ 8000f42: 687b ldr r3, [r7, #4]
+ 8000f44: 2240 movs r2, #64 ; 0x40
+ 8000f46: 2100 movs r1, #0
+ 8000f48: 5499 strb r1, [r3, r2]
+
+ /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
+ hi2c->MspInitCallback(hi2c);
+#else
+ /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
+ HAL_I2C_MspInit(hi2c);
+ 8000f4a: 687b ldr r3, [r7, #4]
+ 8000f4c: 0018 movs r0, r3
+ 8000f4e: f7ff fc1f bl 8000790
+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
+ }
+
+ hi2c->State = HAL_I2C_STATE_BUSY;
+ 8000f52: 687b ldr r3, [r7, #4]
+ 8000f54: 2241 movs r2, #65 ; 0x41
+ 8000f56: 2124 movs r1, #36 ; 0x24
+ 8000f58: 5499 strb r1, [r3, r2]
+
+ /* Disable the selected I2C peripheral */
+ __HAL_I2C_DISABLE(hi2c);
+ 8000f5a: 687b ldr r3, [r7, #4]
+ 8000f5c: 681b ldr r3, [r3, #0]
+ 8000f5e: 681a ldr r2, [r3, #0]
+ 8000f60: 687b ldr r3, [r7, #4]
+ 8000f62: 681b ldr r3, [r3, #0]
+ 8000f64: 2101 movs r1, #1
+ 8000f66: 438a bics r2, r1
+ 8000f68: 601a str r2, [r3, #0]
+
+ /*---------------------------- I2Cx TIMINGR Configuration ------------------*/
+ /* Configure I2Cx: Frequency range */
+ hi2c->Instance->TIMINGR = hi2c->Init.Timing & TIMING_CLEAR_MASK;
+ 8000f6a: 687b ldr r3, [r7, #4]
+ 8000f6c: 685a ldr r2, [r3, #4]
+ 8000f6e: 687b ldr r3, [r7, #4]
+ 8000f70: 681b ldr r3, [r3, #0]
+ 8000f72: 4934 ldr r1, [pc, #208] ; (8001044 )
+ 8000f74: 400a ands r2, r1
+ 8000f76: 611a str r2, [r3, #16]
+
+ /*---------------------------- I2Cx OAR1 Configuration ---------------------*/
+ /* Disable Own Address1 before set the Own Address1 configuration */
+ hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN;
+ 8000f78: 687b ldr r3, [r7, #4]
+ 8000f7a: 681b ldr r3, [r3, #0]
+ 8000f7c: 689a ldr r2, [r3, #8]
+ 8000f7e: 687b ldr r3, [r7, #4]
+ 8000f80: 681b ldr r3, [r3, #0]
+ 8000f82: 4931 ldr r1, [pc, #196] ; (8001048 )
+ 8000f84: 400a ands r2, r1
+ 8000f86: 609a str r2, [r3, #8]
+
+ /* Configure I2Cx: Own Address1 and ack own address1 mode */
+ if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
+ 8000f88: 687b ldr r3, [r7, #4]
+ 8000f8a: 68db ldr r3, [r3, #12]
+ 8000f8c: 2b01 cmp r3, #1
+ 8000f8e: d108 bne.n 8000fa2
+ {
+ hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1);
+ 8000f90: 687b ldr r3, [r7, #4]
+ 8000f92: 689a ldr r2, [r3, #8]
+ 8000f94: 687b ldr r3, [r7, #4]
+ 8000f96: 681b ldr r3, [r3, #0]
+ 8000f98: 2180 movs r1, #128 ; 0x80
+ 8000f9a: 0209 lsls r1, r1, #8
+ 8000f9c: 430a orrs r2, r1
+ 8000f9e: 609a str r2, [r3, #8]
+ 8000fa0: e007 b.n 8000fb2
+ }
+ else /* I2C_ADDRESSINGMODE_10BIT */
+ {
+ hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hi2c->Init.OwnAddress1);
+ 8000fa2: 687b ldr r3, [r7, #4]
+ 8000fa4: 689a ldr r2, [r3, #8]
+ 8000fa6: 687b ldr r3, [r7, #4]
+ 8000fa8: 681b ldr r3, [r3, #0]
+ 8000faa: 2184 movs r1, #132 ; 0x84
+ 8000fac: 0209 lsls r1, r1, #8
+ 8000fae: 430a orrs r2, r1
+ 8000fb0: 609a str r2, [r3, #8]
+ }
+
+ /*---------------------------- I2Cx CR2 Configuration ----------------------*/
+ /* Configure I2Cx: Addressing Master mode */
+ if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
+ 8000fb2: 687b ldr r3, [r7, #4]
+ 8000fb4: 68db ldr r3, [r3, #12]
+ 8000fb6: 2b02 cmp r3, #2
+ 8000fb8: d104 bne.n 8000fc4
+ {
+ hi2c->Instance->CR2 = (I2C_CR2_ADD10);
+ 8000fba: 687b ldr r3, [r7, #4]
+ 8000fbc: 681b ldr r3, [r3, #0]
+ 8000fbe: 2280 movs r2, #128 ; 0x80
+ 8000fc0: 0112 lsls r2, r2, #4
+ 8000fc2: 605a str r2, [r3, #4]
+ }
+ /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */
+ hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK);
+ 8000fc4: 687b ldr r3, [r7, #4]
+ 8000fc6: 681b ldr r3, [r3, #0]
+ 8000fc8: 685a ldr r2, [r3, #4]
+ 8000fca: 687b ldr r3, [r7, #4]
+ 8000fcc: 681b ldr r3, [r3, #0]
+ 8000fce: 491f ldr r1, [pc, #124] ; (800104c