diff --git a/fw/.cproject b/fw/.cproject
index e5db677..6968ac3 100644
--- a/fw/.cproject
+++ b/fw/.cproject
@@ -47,7 +47,7 @@
-
+
@@ -219,7 +219,7 @@
-
+
diff --git a/fw/.settings/language.settings.xml b/fw/.settings/language.settings.xml
index 87c8372..3740b5b 100644
--- a/fw/.settings/language.settings.xml
+++ b/fw/.settings/language.settings.xml
@@ -1,27 +1,52 @@
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/fw/Core/Inc/led.h b/fw/Core/Inc/led.h
deleted file mode 100644
index 5ddc918..0000000
--- a/fw/Core/Inc/led.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- * led.h
- *
- * Created on: Jun 6, 2021
- * Author: user
- */
-
-#ifndef INC_LED_H_
-#define INC_LED_H_
-
-#include "stdint.h"
-#include "stm32l0xx_hal.h"
-#include "stm32l0xx_ll_gpio.h"
-
-/*
- * Context struct
- */
-
-typedef struct {
- GPIO_TypeDef *red_led_port;
- int red_led_pin;
- GPIO_TypeDef *green_led_port;
- int green_led_pin;
- GPIO_TypeDef *blue_led_port;
- int blue_led_pin;
-
-} led_context_t;
-
-/*
- * Externally defined variables
- */
-
-extern int led_pwm_max;
-extern int led_pwm_counter;
-extern int led_red_intensity;
-extern int led_green_intensity;
-extern int led_blue_intensity;
-
-/*
- * Function prototypes
- */
-
-void led_set_color(uint8_t red, uint8_t green, uint8_t blue);
-void led_off();
-void led_pwm_handler();
-void led_init(led_context_t *context, int pwm_freq, int pwm_handler_freq);
-
-#endif /* INC_LED_H_ */
diff --git a/fw/Core/Inc/main.h b/fw/Core/Inc/main.h
index 4720b03..8468db1 100644
--- a/fw/Core/Inc/main.h
+++ b/fw/Core/Inc/main.h
@@ -48,7 +48,6 @@ extern "C" {
/* Private includes ----------------------------------------------------------*/
/* USER CODE BEGIN Includes */
-#include "led.h"
/* USER CODE END Includes */
/* Exported types ------------------------------------------------------------*/
diff --git a/fw/Core/Src/led.c b/fw/Core/Src/led.c
deleted file mode 100644
index 051da44..0000000
--- a/fw/Core/Src/led.c
+++ /dev/null
@@ -1,121 +0,0 @@
-/*
- * led.c
- *
- * Created on: Jun 6, 2021
- * Author: user
- */
-
-#include "led.h"
-
-/*
- * Global variables
- */
-
-int led_pwm_max;
-int led_pwm_counter;
-int led_red_intensity;
-int led_green_intensity;
-int led_blue_intensity;
-int led_red_state;
-int led_green_state;
-int led_blue_state;
-led_context_t *led_context = NULL;
-
-/*
- * Functions
- */
-
-/*
- * led_set_color():
- * Set LED color
- * Arguments:
- * uint8_t red: red color intensity, possible values 0 ... 255
- * uint8_t green: green color intensity, possible values 0 ... 255
- * uint8_t blue: blue color intensity, possible values 0 ... 255
- * NOTE: if (color * led_pwm_max) < 255, LED will be off
- */
-void led_set_color(uint8_t red, uint8_t green, uint8_t blue)
-{
- led_red_intensity = (int)red * led_pwm_max / 255;
- led_green_intensity = (int)green * led_pwm_max / 255;
- led_blue_intensity = (int)blue * led_pwm_max / 255;
-}
-
-/*
- * led_off():
- * Set LED intensity to 0 for each color
- */
-void led_off()
-{
- led_red_intensity = 0;
- led_green_intensity = 0;
- led_blue_intensity = 0;
-}
-
-/*
- * led_pwm_handler():
- * handles switching LEDs on/off according to desired intensity;
- * should be regularly called in timer routine, preferably in SysTick_Handler()
- */
-void led_pwm_handler()
-{
- int new_red_state, new_green_state, new_blue_state;
-
- if (led_context == NULL) {
- // led_pwm_handler() may be called before led_init() was called;
- // this would result in a crash
- return;
- }
-
- new_red_state = led_pwm_counter >= led_red_intensity ? 1 : 0;
- new_green_state = led_pwm_counter >= led_green_intensity ? 1 : 0;
- new_blue_state = led_pwm_counter >= led_blue_intensity ? 1 : 0;
- // SysTick() is called at 1 kHz frequency, we don't want to call HAL_GPIO_WritePin() every time
- if (led_red_state != new_red_state) {
- LL_GPIO_TogglePin(led_context->red_led_port, led_context->red_led_pin);
- led_red_state = new_red_state;
- }
- if (led_green_state != new_green_state) {
- LL_GPIO_TogglePin(led_context->green_led_port, led_context->green_led_pin);
- led_green_state = new_green_state;
- }
- if (led_blue_state != new_blue_state) {
- LL_GPIO_TogglePin(led_context->blue_led_port, led_context->blue_led_pin);
- led_blue_state = new_blue_state;
- }
- if (++led_pwm_counter >= led_pwm_max) {
- led_pwm_counter = 0;
- }
-}
-
-/*
- * led_init():
- * Saves context and calculates max pwm value. Note that is PWM frequency is low (< 25 Hz),
- * flickering might be visible. If pwm_handler_freq is low (less than several kHz),
- * resolution of PWM will be limited
- * Arguments:
- * led_context_t *context:
- * Pointer to LED context struct, which contains port and pin for each LED
- * int pwm_freq:
- * Desired frequency of PWM in Hz (e.g. 25 Hz)
- * int pwm_handler_freq:
- * Frequency of led_pwm_handler() calls. Eequal to timer frequency if timer callback is used,
- * e.g. if led_pwm_handler() is called within SysTick_Handler(), then frequency is
- * HAL_TICK_FREQ_1KHZ
- */
-void led_init(led_context_t *context, int pwm_freq, int pwm_handler_freq)
-{
- // save context
- led_context = context;
- // Initial values
- led_red_intensity = 0;
- led_red_state = 1; // state is inverted (LEDs are sinking current into MCU)
- led_green_intensity = 0;
- led_green_state = 1;
- led_blue_intensity = 0;
- led_blue_state = 1;
- // calculate PWM counter overflow value (max value)
- // e.g. for 1 kHz handler freq and 25 Hz PWM freq, we only have
- // resolution of 40 steps for pwm
- led_pwm_max = pwm_handler_freq / pwm_freq;
-}
diff --git a/fw/Core/Src/main.c b/fw/Core/Src/main.c
index 8a499a2..4a0182b 100644
--- a/fw/Core/Src/main.c
+++ b/fw/Core/Src/main.c
@@ -99,22 +99,21 @@ int main(void)
LL_I2C_Enable(I2C1);
LL_LPUART_Enable(LPUART1);
/* LED PWM context */
- led_context_t led_context;
- led_context.red_led_port = LED_R_GPIO_Port;
- led_context.green_led_port = LED_G_GPIO_Port;
- led_context.blue_led_port = LED_B_GPIO_Port;
- led_context.red_led_pin = LED_R_Pin;
- led_context.green_led_pin = LED_G_Pin;
- led_context.blue_led_pin = LED_B_Pin;
- led_init(&led_context, 50, 1000);
- led_set_color(0, 20, 0);
+
/* USER CODE END 2 */
/* Infinite loop */
/* USER CODE BEGIN WHILE */
+ uint8_t uart_data_dummy = 0;
while (1)
{
+ LL_LPUART_SetDESignalPolarity(LPUART1, 1);
+ LL_LPUART_TransmitData8(LPUART1, uart_data_dummy);
+ uart_data_dummy++;
+
+ LL_mDelay(1000);
/* USER CODE END WHILE */
+
/* USER CODE BEGIN 3 */
}
/* USER CODE END 3 */
@@ -242,17 +241,15 @@ static void MX_LPUART1_UART_Init(void)
LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_LPUART1);
LL_IOP_GRP1_EnableClock(LL_IOP_GRP1_PERIPH_GPIOA);
- LL_IOP_GRP1_EnableClock(LL_IOP_GRP1_PERIPH_GPIOB);
/**LPUART1 GPIO Configuration
PA0-CK_IN ------> LPUART1_RX
PA1 ------> LPUART1_TX
- PB1 ------> LPUART1_DE
*/
GPIO_InitStruct.Pin = LL_GPIO_PIN_0;
GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE;
GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH;
GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;
- GPIO_InitStruct.Pull = LL_GPIO_PULL_NO;
+ GPIO_InitStruct.Pull = LL_GPIO_PULL_UP;
GPIO_InitStruct.Alternate = LL_GPIO_AF_6;
LL_GPIO_Init(GPIOA, &GPIO_InitStruct);
@@ -260,18 +257,10 @@ static void MX_LPUART1_UART_Init(void)
GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE;
GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH;
GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;
- GPIO_InitStruct.Pull = LL_GPIO_PULL_NO;
+ GPIO_InitStruct.Pull = LL_GPIO_PULL_UP;
GPIO_InitStruct.Alternate = LL_GPIO_AF_6;
LL_GPIO_Init(GPIOA, &GPIO_InitStruct);
- GPIO_InitStruct.Pin = LL_GPIO_PIN_1;
- GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE;
- GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH;
- GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;
- GPIO_InitStruct.Pull = LL_GPIO_PULL_NO;
- GPIO_InitStruct.Alternate = LL_GPIO_AF_4;
- LL_GPIO_Init(GPIOB, &GPIO_InitStruct);
-
/* LPUART1 DMA Init */
/* LPUART1_RX Init */
@@ -301,10 +290,6 @@ static void MX_LPUART1_UART_Init(void)
LPUART_InitStruct.TransferDirection = LL_LPUART_DIRECTION_TX_RX;
LPUART_InitStruct.HardwareFlowControl = LL_LPUART_HWCONTROL_NONE;
LL_LPUART_Init(LPUART1, &LPUART_InitStruct);
- LL_LPUART_EnableDEMode(LPUART1);
- LL_LPUART_SetDESignalPolarity(LPUART1, LL_LPUART_DE_POLARITY_HIGH);
- LL_LPUART_SetDEAssertionTime(LPUART1, 20);
- LL_LPUART_SetDEDeassertionTime(LPUART1, 20);
/* USER CODE BEGIN LPUART1_Init 2 */
/* USER CODE END LPUART1_Init 2 */
@@ -339,7 +324,6 @@ static void MX_GPIO_Init(void)
/* GPIO Ports Clock Enable */
LL_IOP_GRP1_EnableClock(LL_IOP_GRP1_PERIPH_GPIOA);
- LL_IOP_GRP1_EnableClock(LL_IOP_GRP1_PERIPH_GPIOB);
/**/
LL_GPIO_SetOutputPin(LED_B_GPIO_Port, LED_B_Pin);
diff --git a/fw/Core/Src/stm32l0xx_it.c b/fw/Core/Src/stm32l0xx_it.c
index 063906f..b44f078 100644
--- a/fw/Core/Src/stm32l0xx_it.c
+++ b/fw/Core/Src/stm32l0xx_it.c
@@ -23,7 +23,6 @@
#include "stm32l0xx_it.h"
/* Private includes ----------------------------------------------------------*/
/* USER CODE BEGIN Includes */
-#include "led.h"
/* USER CODE END Includes */
/* Private typedef -----------------------------------------------------------*/
@@ -131,7 +130,6 @@ void SysTick_Handler(void)
/* USER CODE END SysTick_IRQn 0 */
/* USER CODE BEGIN SysTick_IRQn 1 */
- led_pwm_handler();
/* USER CODE END SysTick_IRQn 1 */
}
diff --git a/fw/Debug/Core/Src/led.su b/fw/Debug/Core/Src/led.su
new file mode 100644
index 0000000..e69de29
diff --git a/fw/Debug/Core/Src/main.d b/fw/Debug/Core/Src/main.d
new file mode 100644
index 0000000..a36c859
--- /dev/null
+++ b/fw/Debug/Core/Src/main.d
@@ -0,0 +1,60 @@
+Core/Src/main.o: ../Core/Src/main.c ../Core/Inc/main.h \
+ ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h \
+ ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l011xx.h \
+ ../Drivers/CMSIS/Include/core_cm0plus.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h \
+ ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h \
+ ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h \
+ ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h \
+ ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_crs.h \
+ ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h \
+ ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h \
+ ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h \
+ ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h \
+ ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h \
+ ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h \
+ ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h
+
+../Core/Inc/main.h:
+
+../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h:
+
+../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h:
+
+../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l011xx.h:
+
+../Drivers/CMSIS/Include/core_cm0plus.h:
+
+../Drivers/CMSIS/Include/cmsis_version.h:
+
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+
+../Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h:
+
+../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h:
+
+../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h:
+
+../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h:
+
+../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_crs.h:
+
+../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h:
+
+../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h:
+
+../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h:
+
+../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h:
+
+../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h:
+
+../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h:
+
+../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h:
diff --git a/fw/Debug/Core/Src/main.o b/fw/Debug/Core/Src/main.o
new file mode 100644
index 0000000..988d811
Binary files /dev/null and b/fw/Debug/Core/Src/main.o differ
diff --git a/fw/Debug/Core/Src/main.su b/fw/Debug/Core/Src/main.su
new file mode 100644
index 0000000..d6f1927
--- /dev/null
+++ b/fw/Debug/Core/Src/main.su
@@ -0,0 +1,5 @@
+stm32l0xx_ll_bus.h:440:22:LL_APB1_GRP1_EnableClock 8 static
+stm32l0xx_ll_bus.h:987:22:LL_IOP_GRP1_EnableClock.constprop 8 static
+main.c:126:6:SystemClock_Config 8 static
+main.c:67:5:main 96 static
+main.c:371:6:Error_Handler 0 static,ignoring_inline_asm
diff --git a/fw/Debug/Core/Src/stm32l0xx_it.d b/fw/Debug/Core/Src/stm32l0xx_it.d
new file mode 100644
index 0000000..5e5bafa
--- /dev/null
+++ b/fw/Debug/Core/Src/stm32l0xx_it.d
@@ -0,0 +1,63 @@
+Core/Src/stm32l0xx_it.o: ../Core/Src/stm32l0xx_it.c ../Core/Inc/main.h \
+ ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h \
+ ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l011xx.h \
+ ../Drivers/CMSIS/Include/core_cm0plus.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h \
+ ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h \
+ ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h \
+ ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h \
+ ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_crs.h \
+ ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h \
+ ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h \
+ ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h \
+ ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h \
+ ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h \
+ ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h \
+ ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h \
+ ../Core/Inc/stm32l0xx_it.h
+
+../Core/Inc/main.h:
+
+../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h:
+
+../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h:
+
+../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l011xx.h:
+
+../Drivers/CMSIS/Include/core_cm0plus.h:
+
+../Drivers/CMSIS/Include/cmsis_version.h:
+
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+
+../Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h:
+
+../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h:
+
+../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h:
+
+../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h:
+
+../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_crs.h:
+
+../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h:
+
+../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h:
+
+../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h:
+
+../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h:
+
+../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h:
+
+../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h:
+
+../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h:
+
+../Core/Inc/stm32l0xx_it.h:
diff --git a/fw/Debug/Core/Src/stm32l0xx_it.o b/fw/Debug/Core/Src/stm32l0xx_it.o
new file mode 100644
index 0000000..4e0b80a
Binary files /dev/null and b/fw/Debug/Core/Src/stm32l0xx_it.o differ
diff --git a/fw/Debug/Core/Src/stm32l0xx_it.su b/fw/Debug/Core/Src/stm32l0xx_it.su
new file mode 100644
index 0000000..10bb9d0
--- /dev/null
+++ b/fw/Debug/Core/Src/stm32l0xx_it.su
@@ -0,0 +1,6 @@
+stm32l0xx_it.c:70:6:NMI_Handler 0 static
+stm32l0xx_it.c:85:6:HardFault_Handler 0 static
+stm32l0xx_it.c:100:6:SVC_Handler 0 static
+stm32l0xx_it.c:113:6:PendSV_Handler 0 static
+stm32l0xx_it.c:126:6:SysTick_Handler 0 static
+stm32l0xx_it.c:146:6:DMA1_Channel2_3_IRQHandler 0 static
diff --git a/fw/Debug/Core/Src/subdir.mk b/fw/Debug/Core/Src/subdir.mk
new file mode 100644
index 0000000..6c1e66f
--- /dev/null
+++ b/fw/Debug/Core/Src/subdir.mk
@@ -0,0 +1,40 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+# Toolchain: GNU Tools for STM32 (9-2020-q2-update)
+################################################################################
+
+# Add inputs and outputs from these tool invocations to the build variables
+C_SRCS += \
+../Core/Src/main.c \
+../Core/Src/stm32l0xx_it.c \
+../Core/Src/syscalls.c \
+../Core/Src/sysmem.c \
+../Core/Src/system_stm32l0xx.c
+
+OBJS += \
+./Core/Src/main.o \
+./Core/Src/stm32l0xx_it.o \
+./Core/Src/syscalls.o \
+./Core/Src/sysmem.o \
+./Core/Src/system_stm32l0xx.o
+
+C_DEPS += \
+./Core/Src/main.d \
+./Core/Src/stm32l0xx_it.d \
+./Core/Src/syscalls.d \
+./Core/Src/sysmem.d \
+./Core/Src/system_stm32l0xx.d
+
+
+# Each subdirectory must supply rules for building sources it contributes
+Core/Src/main.o: ../Core/Src/main.c Core/Src/subdir.mk
+ arm-none-eabi-gcc "$<" -mcpu=cortex-m0plus -std=gnu11 -g3 -DSTM32L011xx -DDEBUG -DUSE_FULL_LL_DRIVER '-DHSE_VALUE=8000000' '-DHSE_STARTUP_TIMEOUT=100' '-DLSE_STARTUP_TIMEOUT=5000' '-DLSE_VALUE=32768' '-DMSI_VALUE=2097000' '-DHSI_VALUE=16000000' '-DLSI_VALUE=37000' '-DVDD_VALUE=3300' '-DPREFETCH_ENABLE=0' '-DINSTRUCTION_CACHE_ENABLE=1' '-DDATA_CACHE_ENABLE=1' -c -I../Core/Inc -I../Drivers/STM32L0xx_HAL_Driver/Inc -I../Drivers/CMSIS/Device/ST/STM32L0xx/Include -I../Drivers/CMSIS/Include -Os -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Core/Src/main.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@"
+Core/Src/stm32l0xx_it.o: ../Core/Src/stm32l0xx_it.c Core/Src/subdir.mk
+ arm-none-eabi-gcc "$<" -mcpu=cortex-m0plus -std=gnu11 -g3 -DSTM32L011xx -DDEBUG -DUSE_FULL_LL_DRIVER '-DHSE_VALUE=8000000' '-DHSE_STARTUP_TIMEOUT=100' '-DLSE_STARTUP_TIMEOUT=5000' '-DLSE_VALUE=32768' '-DMSI_VALUE=2097000' '-DHSI_VALUE=16000000' '-DLSI_VALUE=37000' '-DVDD_VALUE=3300' '-DPREFETCH_ENABLE=0' '-DINSTRUCTION_CACHE_ENABLE=1' '-DDATA_CACHE_ENABLE=1' -c -I../Core/Inc -I../Drivers/STM32L0xx_HAL_Driver/Inc -I../Drivers/CMSIS/Device/ST/STM32L0xx/Include -I../Drivers/CMSIS/Include -Os -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Core/Src/stm32l0xx_it.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@"
+Core/Src/syscalls.o: ../Core/Src/syscalls.c Core/Src/subdir.mk
+ arm-none-eabi-gcc "$<" -mcpu=cortex-m0plus -std=gnu11 -g3 -DSTM32L011xx -DDEBUG -DUSE_FULL_LL_DRIVER '-DHSE_VALUE=8000000' '-DHSE_STARTUP_TIMEOUT=100' '-DLSE_STARTUP_TIMEOUT=5000' '-DLSE_VALUE=32768' '-DMSI_VALUE=2097000' '-DHSI_VALUE=16000000' '-DLSI_VALUE=37000' '-DVDD_VALUE=3300' '-DPREFETCH_ENABLE=0' '-DINSTRUCTION_CACHE_ENABLE=1' '-DDATA_CACHE_ENABLE=1' -c -I../Core/Inc -I../Drivers/STM32L0xx_HAL_Driver/Inc -I../Drivers/CMSIS/Device/ST/STM32L0xx/Include -I../Drivers/CMSIS/Include -Os -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Core/Src/syscalls.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@"
+Core/Src/sysmem.o: ../Core/Src/sysmem.c Core/Src/subdir.mk
+ arm-none-eabi-gcc "$<" -mcpu=cortex-m0plus -std=gnu11 -g3 -DSTM32L011xx -DDEBUG -DUSE_FULL_LL_DRIVER '-DHSE_VALUE=8000000' '-DHSE_STARTUP_TIMEOUT=100' '-DLSE_STARTUP_TIMEOUT=5000' '-DLSE_VALUE=32768' '-DMSI_VALUE=2097000' '-DHSI_VALUE=16000000' '-DLSI_VALUE=37000' '-DVDD_VALUE=3300' '-DPREFETCH_ENABLE=0' '-DINSTRUCTION_CACHE_ENABLE=1' '-DDATA_CACHE_ENABLE=1' -c -I../Core/Inc -I../Drivers/STM32L0xx_HAL_Driver/Inc -I../Drivers/CMSIS/Device/ST/STM32L0xx/Include -I../Drivers/CMSIS/Include -Os -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Core/Src/sysmem.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@"
+Core/Src/system_stm32l0xx.o: ../Core/Src/system_stm32l0xx.c Core/Src/subdir.mk
+ arm-none-eabi-gcc "$<" -mcpu=cortex-m0plus -std=gnu11 -g3 -DSTM32L011xx -DDEBUG -DUSE_FULL_LL_DRIVER '-DHSE_VALUE=8000000' '-DHSE_STARTUP_TIMEOUT=100' '-DLSE_STARTUP_TIMEOUT=5000' '-DLSE_VALUE=32768' '-DMSI_VALUE=2097000' '-DHSI_VALUE=16000000' '-DLSI_VALUE=37000' '-DVDD_VALUE=3300' '-DPREFETCH_ENABLE=0' '-DINSTRUCTION_CACHE_ENABLE=1' '-DDATA_CACHE_ENABLE=1' -c -I../Core/Inc -I../Drivers/STM32L0xx_HAL_Driver/Inc -I../Drivers/CMSIS/Device/ST/STM32L0xx/Include -I../Drivers/CMSIS/Include -Os -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Core/Src/system_stm32l0xx.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@"
+
diff --git a/fw/Debug/Core/Src/syscalls.d b/fw/Debug/Core/Src/syscalls.d
new file mode 100644
index 0000000..8667c70
--- /dev/null
+++ b/fw/Debug/Core/Src/syscalls.d
@@ -0,0 +1 @@
+Core/Src/syscalls.o: ../Core/Src/syscalls.c
diff --git a/fw/Debug/Core/Src/syscalls.o b/fw/Debug/Core/Src/syscalls.o
new file mode 100644
index 0000000..b0ef4b4
Binary files /dev/null and b/fw/Debug/Core/Src/syscalls.o differ
diff --git a/fw/Debug/Core/Src/syscalls.su b/fw/Debug/Core/Src/syscalls.su
new file mode 100644
index 0000000..c872039
--- /dev/null
+++ b/fw/Debug/Core/Src/syscalls.su
@@ -0,0 +1,18 @@
+syscalls.c:48:6:initialise_monitor_handles 0 static
+syscalls.c:52:5:_getpid 0 static
+syscalls.c:57:5:_kill 8 static
+syscalls.c:63:6:_exit 8 static
+syscalls.c:69:27:_read 16 static
+syscalls.c:81:27:_write 16 static
+syscalls.c:92:5:_close 0 static
+syscalls.c:98:5:_fstat 0 static
+syscalls.c:104:5:_isatty 0 static
+syscalls.c:109:5:_lseek 0 static
+syscalls.c:114:5:_open 0 static
+syscalls.c:120:5:_wait 8 static
+syscalls.c:126:5:_unlink 8 static
+syscalls.c:132:5:_times 0 static
+syscalls.c:137:5:_stat 0 static
+syscalls.c:143:5:_link 8 static
+syscalls.c:149:5:_fork 8 static
+syscalls.c:155:5:_execve 8 static
diff --git a/fw/Debug/Core/Src/sysmem.d b/fw/Debug/Core/Src/sysmem.d
new file mode 100644
index 0000000..74fecf9
--- /dev/null
+++ b/fw/Debug/Core/Src/sysmem.d
@@ -0,0 +1 @@
+Core/Src/sysmem.o: ../Core/Src/sysmem.c
diff --git a/fw/Debug/Core/Src/sysmem.o b/fw/Debug/Core/Src/sysmem.o
new file mode 100644
index 0000000..acba301
Binary files /dev/null and b/fw/Debug/Core/Src/sysmem.o differ
diff --git a/fw/Debug/Core/Src/sysmem.su b/fw/Debug/Core/Src/sysmem.su
new file mode 100644
index 0000000..c9ac5ce
--- /dev/null
+++ b/fw/Debug/Core/Src/sysmem.su
@@ -0,0 +1 @@
+sysmem.c:54:7:_sbrk 8 static
diff --git a/fw/Debug/Core/Src/system_stm32l0xx.d b/fw/Debug/Core/Src/system_stm32l0xx.d
new file mode 100644
index 0000000..92dd183
--- /dev/null
+++ b/fw/Debug/Core/Src/system_stm32l0xx.d
@@ -0,0 +1,22 @@
+Core/Src/system_stm32l0xx.o: ../Core/Src/system_stm32l0xx.c \
+ ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l011xx.h \
+ ../Drivers/CMSIS/Include/core_cm0plus.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h
+
+../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h:
+
+../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l011xx.h:
+
+../Drivers/CMSIS/Include/core_cm0plus.h:
+
+../Drivers/CMSIS/Include/cmsis_version.h:
+
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+
+../Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h:
diff --git a/fw/Debug/Core/Src/system_stm32l0xx.o b/fw/Debug/Core/Src/system_stm32l0xx.o
new file mode 100644
index 0000000..99fa31a
Binary files /dev/null and b/fw/Debug/Core/Src/system_stm32l0xx.o differ
diff --git a/fw/Debug/Core/Src/system_stm32l0xx.su b/fw/Debug/Core/Src/system_stm32l0xx.su
new file mode 100644
index 0000000..f548a45
--- /dev/null
+++ b/fw/Debug/Core/Src/system_stm32l0xx.su
@@ -0,0 +1,2 @@
+system_stm32l0xx.c:154:6:SystemInit 0 static
+system_stm32l0xx.c:200:6:SystemCoreClockUpdate 16 static
diff --git a/fw/Debug/Core/Startup/startup_stm32l011f4ux.d b/fw/Debug/Core/Startup/startup_stm32l011f4ux.d
new file mode 100644
index 0000000..7f6eea2
--- /dev/null
+++ b/fw/Debug/Core/Startup/startup_stm32l011f4ux.d
@@ -0,0 +1,2 @@
+Core/Startup/startup_stm32l011f4ux.o: \
+ ../Core/Startup/startup_stm32l011f4ux.s
diff --git a/fw/Debug/Core/Startup/startup_stm32l011f4ux.o b/fw/Debug/Core/Startup/startup_stm32l011f4ux.o
new file mode 100644
index 0000000..6e4550b
Binary files /dev/null and b/fw/Debug/Core/Startup/startup_stm32l011f4ux.o differ
diff --git a/fw/Debug/Core/Startup/subdir.mk b/fw/Debug/Core/Startup/subdir.mk
new file mode 100644
index 0000000..3fa16c8
--- /dev/null
+++ b/fw/Debug/Core/Startup/subdir.mk
@@ -0,0 +1,20 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+# Toolchain: GNU Tools for STM32 (9-2020-q2-update)
+################################################################################
+
+# Add inputs and outputs from these tool invocations to the build variables
+S_SRCS += \
+../Core/Startup/startup_stm32l011f4ux.s
+
+OBJS += \
+./Core/Startup/startup_stm32l011f4ux.o
+
+S_DEPS += \
+./Core/Startup/startup_stm32l011f4ux.d
+
+
+# Each subdirectory must supply rules for building sources it contributes
+Core/Startup/startup_stm32l011f4ux.o: ../Core/Startup/startup_stm32l011f4ux.s Core/Startup/subdir.mk
+ arm-none-eabi-gcc -mcpu=cortex-m0plus -g3 -c -x assembler-with-cpp -MMD -MP -MF"Core/Startup/startup_stm32l011f4ux.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" "$<"
+
diff --git a/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.d b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.d
new file mode 100644
index 0000000..737ad9a
--- /dev/null
+++ b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.d
@@ -0,0 +1,29 @@
+Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.o: \
+ ../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c \
+ ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h \
+ ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l011xx.h \
+ ../Drivers/CMSIS/Include/core_cm0plus.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h \
+ ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h
+
+../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h:
+
+../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h:
+
+../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l011xx.h:
+
+../Drivers/CMSIS/Include/core_cm0plus.h:
+
+../Drivers/CMSIS/Include/cmsis_version.h:
+
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+
+../Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h:
+
+../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h:
diff --git a/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.o b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.o
new file mode 100644
index 0000000..28b4bd9
Binary files /dev/null and b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.o differ
diff --git a/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.su b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.su
new file mode 100644
index 0000000..7e34b01
--- /dev/null
+++ b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.su
@@ -0,0 +1,3 @@
+stm32l0xx_ll_dma.c:150:13:LL_DMA_DeInit 16 static
+stm32l0xx_ll_dma.c:275:13:LL_DMA_Init 16 static
+stm32l0xx_ll_dma.c:343:6:LL_DMA_StructInit 0 static
diff --git a/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.d b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.d
new file mode 100644
index 0000000..2cc017f
--- /dev/null
+++ b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.d
@@ -0,0 +1,26 @@
+Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.o: \
+ ../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c \
+ ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h \
+ ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l011xx.h \
+ ../Drivers/CMSIS/Include/core_cm0plus.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h
+
+../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h:
+
+../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h:
+
+../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l011xx.h:
+
+../Drivers/CMSIS/Include/core_cm0plus.h:
+
+../Drivers/CMSIS/Include/cmsis_version.h:
+
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+
+../Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h:
diff --git a/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.o b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.o
new file mode 100644
index 0000000..bf76e61
Binary files /dev/null and b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.o differ
diff --git a/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.su b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.su
new file mode 100644
index 0000000..ca187b5
--- /dev/null
+++ b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.su
@@ -0,0 +1,3 @@
+stm32l0xx_ll_exti.c:80:10:LL_EXTI_DeInit 0 static
+stm32l0xx_ll_exti.c:105:10:LL_EXTI_Init 8 static
+stm32l0xx_ll_exti.c:186:6:LL_EXTI_StructInit 0 static
diff --git a/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.d b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.d
new file mode 100644
index 0000000..84a1bfe
--- /dev/null
+++ b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.d
@@ -0,0 +1,29 @@
+Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.o: \
+ ../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c \
+ ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h \
+ ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l011xx.h \
+ ../Drivers/CMSIS/Include/core_cm0plus.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h \
+ ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h
+
+../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h:
+
+../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h:
+
+../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l011xx.h:
+
+../Drivers/CMSIS/Include/core_cm0plus.h:
+
+../Drivers/CMSIS/Include/cmsis_version.h:
+
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+
+../Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h:
+
+../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h:
diff --git a/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.o b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.o
new file mode 100644
index 0000000..23f8214
Binary files /dev/null and b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.o differ
diff --git a/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.su b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.su
new file mode 100644
index 0000000..bc587a1
--- /dev/null
+++ b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.su
@@ -0,0 +1,3 @@
+stm32l0xx_ll_gpio.c:96:13:LL_GPIO_DeInit 0 static
+stm32l0xx_ll_gpio.c:157:13:LL_GPIO_Init 32 static
+stm32l0xx_ll_gpio.c:231:6:LL_GPIO_StructInit 0 static
diff --git a/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.d b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.d
new file mode 100644
index 0000000..94e870b
--- /dev/null
+++ b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.d
@@ -0,0 +1,29 @@
+Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.o: \
+ ../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c \
+ ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h \
+ ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l011xx.h \
+ ../Drivers/CMSIS/Include/core_cm0plus.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h \
+ ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h
+
+../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h:
+
+../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h:
+
+../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l011xx.h:
+
+../Drivers/CMSIS/Include/core_cm0plus.h:
+
+../Drivers/CMSIS/Include/cmsis_version.h:
+
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+
+../Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h:
+
+../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h:
diff --git a/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.o b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.o
new file mode 100644
index 0000000..b6f0046
Binary files /dev/null and b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.o differ
diff --git a/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.su b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.su
new file mode 100644
index 0000000..bfa06c8
--- /dev/null
+++ b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.su
@@ -0,0 +1,3 @@
+stm32l0xx_ll_i2c.c:87:13:LL_I2C_DeInit 0 static
+stm32l0xx_ll_i2c.c:139:13:LL_I2C_Init 12 static
+stm32l0xx_ll_i2c.c:207:6:LL_I2C_StructInit 0 static
diff --git a/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.d b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.d
new file mode 100644
index 0000000..45688ed
--- /dev/null
+++ b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.d
@@ -0,0 +1,32 @@
+Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.o: \
+ ../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c \
+ ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h \
+ ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l011xx.h \
+ ../Drivers/CMSIS/Include/core_cm0plus.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h \
+ ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h \
+ ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h
+
+../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h:
+
+../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h:
+
+../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l011xx.h:
+
+../Drivers/CMSIS/Include/core_cm0plus.h:
+
+../Drivers/CMSIS/Include/cmsis_version.h:
+
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+
+../Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h:
+
+../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h:
+
+../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h:
diff --git a/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.o b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.o
new file mode 100644
index 0000000..fabf774
Binary files /dev/null and b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.o differ
diff --git a/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.su b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.su
new file mode 100644
index 0000000..2af37eb
--- /dev/null
+++ b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.su
@@ -0,0 +1,3 @@
+stm32l0xx_ll_lpuart.c:117:13:LL_LPUART_DeInit 0 static
+stm32l0xx_ll_lpuart.c:155:13:LL_LPUART_Init 24 static
+stm32l0xx_ll_lpuart.c:232:6:LL_LPUART_StructInit 0 static
diff --git a/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_pwr.d b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_pwr.d
new file mode 100644
index 0000000..b22a85d
--- /dev/null
+++ b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_pwr.d
@@ -0,0 +1,29 @@
+Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_pwr.o: \
+ ../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_pwr.c \
+ ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h \
+ ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l011xx.h \
+ ../Drivers/CMSIS/Include/core_cm0plus.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h \
+ ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h
+
+../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h:
+
+../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h:
+
+../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l011xx.h:
+
+../Drivers/CMSIS/Include/core_cm0plus.h:
+
+../Drivers/CMSIS/Include/cmsis_version.h:
+
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+
+../Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h:
+
+../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h:
diff --git a/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_pwr.o b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_pwr.o
new file mode 100644
index 0000000..e423123
Binary files /dev/null and b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_pwr.o differ
diff --git a/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_pwr.su b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_pwr.su
new file mode 100644
index 0000000..68038bc
--- /dev/null
+++ b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_pwr.su
@@ -0,0 +1 @@
+stm32l0xx_ll_pwr.c:56:13:LL_PWR_DeInit 0 static
diff --git a/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.d b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.d
new file mode 100644
index 0000000..748ea46
--- /dev/null
+++ b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.d
@@ -0,0 +1,26 @@
+Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.o: \
+ ../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c \
+ ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h \
+ ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l011xx.h \
+ ../Drivers/CMSIS/Include/core_cm0plus.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h
+
+../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h:
+
+../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h:
+
+../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l011xx.h:
+
+../Drivers/CMSIS/Include/core_cm0plus.h:
+
+../Drivers/CMSIS/Include/cmsis_version.h:
+
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+
+../Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h:
diff --git a/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.o b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.o
new file mode 100644
index 0000000..1cd68e3
Binary files /dev/null and b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.o differ
diff --git a/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.su b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.su
new file mode 100644
index 0000000..0819a7b
--- /dev/null
+++ b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.su
@@ -0,0 +1,13 @@
+stm32l0xx_ll_rcc.h:802:26:LL_RCC_HSI_IsReady 0 static
+stm32l0xx_ll_rcc.h:2097:26:LL_RCC_IsActiveFlag_HSIDIV 0 static
+stm32l0xx_ll_rcc.c:112:13:LL_RCC_DeInit 16 static,ignoring_inline_asm
+stm32l0xx_ll_rcc.c:622:10:RCC_GetHCLKClockFreq 0 static
+stm32l0xx_ll_rcc.c:633:10:RCC_GetPCLK1ClockFreq 0 static
+stm32l0xx_ll_rcc.c:644:10:RCC_GetPCLK2ClockFreq 0 static
+stm32l0xx_ll_rcc.c:654:10:RCC_PLL_GetFreqDomain_SYS 8 static
+stm32l0xx_ll_rcc.c:579:10:RCC_GetSystemClockFreq 8 static
+stm32l0xx_ll_rcc.c:222:6:LL_RCC_GetSystemClocksFreq 8 static
+stm32l0xx_ll_rcc.c:247:10:LL_RCC_GetUSARTClockFreq 8 static
+stm32l0xx_ll_rcc.c:344:10:LL_RCC_GetI2CClockFreq 8 static
+stm32l0xx_ll_rcc.c:423:10:LL_RCC_GetLPUARTClockFreq 8 static
+stm32l0xx_ll_rcc.c:474:10:LL_RCC_GetLPTIMClockFreq 8 static
diff --git a/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.d b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.d
new file mode 100644
index 0000000..577cc36
--- /dev/null
+++ b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.d
@@ -0,0 +1,35 @@
+Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.o: \
+ ../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c \
+ ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h \
+ ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l011xx.h \
+ ../Drivers/CMSIS/Include/core_cm0plus.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h \
+ ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h \
+ ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h \
+ ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h
+
+../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h:
+
+../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h:
+
+../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l011xx.h:
+
+../Drivers/CMSIS/Include/core_cm0plus.h:
+
+../Drivers/CMSIS/Include/cmsis_version.h:
+
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+
+../Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h:
+
+../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h:
+
+../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h:
+
+../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h:
diff --git a/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.o b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.o
new file mode 100644
index 0000000..07a2e90
Binary files /dev/null and b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.o differ
diff --git a/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.su b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.su
new file mode 100644
index 0000000..ab2a69f
--- /dev/null
+++ b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.su
@@ -0,0 +1,7 @@
+stm32l0xx_ll_utils.c:147:6:LL_Init1msTick 8 static
+stm32l0xx_ll_utils.c:163:6:LL_mDelay 8 static
+stm32l0xx_ll_utils.c:225:6:LL_SetSystemCoreClock 0 static
+stm32l0xx_ll_utils.c:239:13:LL_SetFlashLatency 8 static
+stm32l0xx_ll_utils.c:521:20:UTILS_EnablePLLAndSwitchSystem 16 static
+stm32l0xx_ll_utils.c:338:13:LL_PLL_ConfigSystemClock_HSI 24 static
+stm32l0xx_ll_utils.c:397:13:LL_PLL_ConfigSystemClock_HSE 24 static
diff --git a/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/subdir.mk b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/subdir.mk
new file mode 100644
index 0000000..40b8c42
--- /dev/null
+++ b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/subdir.mk
@@ -0,0 +1,55 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+# Toolchain: GNU Tools for STM32 (9-2020-q2-update)
+################################################################################
+
+# Add inputs and outputs from these tool invocations to the build variables
+C_SRCS += \
+../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c \
+../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c \
+../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c \
+../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c \
+../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c \
+../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_pwr.c \
+../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c \
+../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c
+
+OBJS += \
+./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.o \
+./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.o \
+./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.o \
+./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.o \
+./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.o \
+./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_pwr.o \
+./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.o \
+./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.o
+
+C_DEPS += \
+./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.d \
+./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.d \
+./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.d \
+./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.d \
+./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.d \
+./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_pwr.d \
+./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.d \
+./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.d
+
+
+# Each subdirectory must supply rules for building sources it contributes
+Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.o: ../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c Drivers/STM32L0xx_HAL_Driver/Src/subdir.mk
+ arm-none-eabi-gcc "$<" -mcpu=cortex-m0plus -std=gnu11 -g3 -DSTM32L011xx -DDEBUG -DUSE_FULL_LL_DRIVER '-DHSE_VALUE=8000000' '-DHSE_STARTUP_TIMEOUT=100' '-DLSE_STARTUP_TIMEOUT=5000' '-DLSE_VALUE=32768' '-DMSI_VALUE=2097000' '-DHSI_VALUE=16000000' '-DLSI_VALUE=37000' '-DVDD_VALUE=3300' '-DPREFETCH_ENABLE=0' '-DINSTRUCTION_CACHE_ENABLE=1' '-DDATA_CACHE_ENABLE=1' -c -I../Core/Inc -I../Drivers/STM32L0xx_HAL_Driver/Inc -I../Drivers/CMSIS/Device/ST/STM32L0xx/Include -I../Drivers/CMSIS/Include -Os -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@"
+Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.o: ../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c Drivers/STM32L0xx_HAL_Driver/Src/subdir.mk
+ arm-none-eabi-gcc "$<" -mcpu=cortex-m0plus -std=gnu11 -g3 -DSTM32L011xx -DDEBUG -DUSE_FULL_LL_DRIVER '-DHSE_VALUE=8000000' '-DHSE_STARTUP_TIMEOUT=100' '-DLSE_STARTUP_TIMEOUT=5000' '-DLSE_VALUE=32768' '-DMSI_VALUE=2097000' '-DHSI_VALUE=16000000' '-DLSI_VALUE=37000' '-DVDD_VALUE=3300' '-DPREFETCH_ENABLE=0' '-DINSTRUCTION_CACHE_ENABLE=1' '-DDATA_CACHE_ENABLE=1' -c -I../Core/Inc -I../Drivers/STM32L0xx_HAL_Driver/Inc -I../Drivers/CMSIS/Device/ST/STM32L0xx/Include -I../Drivers/CMSIS/Include -Os -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@"
+Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.o: ../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c Drivers/STM32L0xx_HAL_Driver/Src/subdir.mk
+ arm-none-eabi-gcc "$<" -mcpu=cortex-m0plus -std=gnu11 -g3 -DSTM32L011xx -DDEBUG -DUSE_FULL_LL_DRIVER '-DHSE_VALUE=8000000' '-DHSE_STARTUP_TIMEOUT=100' '-DLSE_STARTUP_TIMEOUT=5000' '-DLSE_VALUE=32768' '-DMSI_VALUE=2097000' '-DHSI_VALUE=16000000' '-DLSI_VALUE=37000' '-DVDD_VALUE=3300' '-DPREFETCH_ENABLE=0' '-DINSTRUCTION_CACHE_ENABLE=1' '-DDATA_CACHE_ENABLE=1' -c -I../Core/Inc -I../Drivers/STM32L0xx_HAL_Driver/Inc -I../Drivers/CMSIS/Device/ST/STM32L0xx/Include -I../Drivers/CMSIS/Include -Os -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@"
+Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.o: ../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c Drivers/STM32L0xx_HAL_Driver/Src/subdir.mk
+ arm-none-eabi-gcc "$<" -mcpu=cortex-m0plus -std=gnu11 -g3 -DSTM32L011xx -DDEBUG -DUSE_FULL_LL_DRIVER '-DHSE_VALUE=8000000' '-DHSE_STARTUP_TIMEOUT=100' '-DLSE_STARTUP_TIMEOUT=5000' '-DLSE_VALUE=32768' '-DMSI_VALUE=2097000' '-DHSI_VALUE=16000000' '-DLSI_VALUE=37000' '-DVDD_VALUE=3300' '-DPREFETCH_ENABLE=0' '-DINSTRUCTION_CACHE_ENABLE=1' '-DDATA_CACHE_ENABLE=1' -c -I../Core/Inc -I../Drivers/STM32L0xx_HAL_Driver/Inc -I../Drivers/CMSIS/Device/ST/STM32L0xx/Include -I../Drivers/CMSIS/Include -Os -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@"
+Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.o: ../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c Drivers/STM32L0xx_HAL_Driver/Src/subdir.mk
+ arm-none-eabi-gcc "$<" -mcpu=cortex-m0plus -std=gnu11 -g3 -DSTM32L011xx -DDEBUG -DUSE_FULL_LL_DRIVER '-DHSE_VALUE=8000000' '-DHSE_STARTUP_TIMEOUT=100' '-DLSE_STARTUP_TIMEOUT=5000' '-DLSE_VALUE=32768' '-DMSI_VALUE=2097000' '-DHSI_VALUE=16000000' '-DLSI_VALUE=37000' '-DVDD_VALUE=3300' '-DPREFETCH_ENABLE=0' '-DINSTRUCTION_CACHE_ENABLE=1' '-DDATA_CACHE_ENABLE=1' -c -I../Core/Inc -I../Drivers/STM32L0xx_HAL_Driver/Inc -I../Drivers/CMSIS/Device/ST/STM32L0xx/Include -I../Drivers/CMSIS/Include -Os -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@"
+Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_pwr.o: ../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_pwr.c Drivers/STM32L0xx_HAL_Driver/Src/subdir.mk
+ arm-none-eabi-gcc "$<" -mcpu=cortex-m0plus -std=gnu11 -g3 -DSTM32L011xx -DDEBUG -DUSE_FULL_LL_DRIVER '-DHSE_VALUE=8000000' '-DHSE_STARTUP_TIMEOUT=100' '-DLSE_STARTUP_TIMEOUT=5000' '-DLSE_VALUE=32768' '-DMSI_VALUE=2097000' '-DHSI_VALUE=16000000' '-DLSI_VALUE=37000' '-DVDD_VALUE=3300' '-DPREFETCH_ENABLE=0' '-DINSTRUCTION_CACHE_ENABLE=1' '-DDATA_CACHE_ENABLE=1' -c -I../Core/Inc -I../Drivers/STM32L0xx_HAL_Driver/Inc -I../Drivers/CMSIS/Device/ST/STM32L0xx/Include -I../Drivers/CMSIS/Include -Os -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_pwr.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@"
+Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.o: ../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c Drivers/STM32L0xx_HAL_Driver/Src/subdir.mk
+ arm-none-eabi-gcc "$<" -mcpu=cortex-m0plus -std=gnu11 -g3 -DSTM32L011xx -DDEBUG -DUSE_FULL_LL_DRIVER '-DHSE_VALUE=8000000' '-DHSE_STARTUP_TIMEOUT=100' '-DLSE_STARTUP_TIMEOUT=5000' '-DLSE_VALUE=32768' '-DMSI_VALUE=2097000' '-DHSI_VALUE=16000000' '-DLSI_VALUE=37000' '-DVDD_VALUE=3300' '-DPREFETCH_ENABLE=0' '-DINSTRUCTION_CACHE_ENABLE=1' '-DDATA_CACHE_ENABLE=1' -c -I../Core/Inc -I../Drivers/STM32L0xx_HAL_Driver/Inc -I../Drivers/CMSIS/Device/ST/STM32L0xx/Include -I../Drivers/CMSIS/Include -Os -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@"
+Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.o: ../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c Drivers/STM32L0xx_HAL_Driver/Src/subdir.mk
+ arm-none-eabi-gcc "$<" -mcpu=cortex-m0plus -std=gnu11 -g3 -DSTM32L011xx -DDEBUG -DUSE_FULL_LL_DRIVER '-DHSE_VALUE=8000000' '-DHSE_STARTUP_TIMEOUT=100' '-DLSE_STARTUP_TIMEOUT=5000' '-DLSE_VALUE=32768' '-DMSI_VALUE=2097000' '-DHSI_VALUE=16000000' '-DLSI_VALUE=37000' '-DVDD_VALUE=3300' '-DPREFETCH_ENABLE=0' '-DINSTRUCTION_CACHE_ENABLE=1' '-DDATA_CACHE_ENABLE=1' -c -I../Core/Inc -I../Drivers/STM32L0xx_HAL_Driver/Inc -I../Drivers/CMSIS/Device/ST/STM32L0xx/Include -I../Drivers/CMSIS/Include -Os -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@"
+
diff --git a/fw/Debug/iaq_wired_sensor.bin b/fw/Debug/iaq_wired_sensor.bin
new file mode 100755
index 0000000..fc28ce9
Binary files /dev/null and b/fw/Debug/iaq_wired_sensor.bin differ
diff --git a/fw/Debug/iaq_wired_sensor.elf b/fw/Debug/iaq_wired_sensor.elf
new file mode 100755
index 0000000..b2a3214
Binary files /dev/null and b/fw/Debug/iaq_wired_sensor.elf differ
diff --git a/fw/Debug/iaq_wired_sensor.list b/fw/Debug/iaq_wired_sensor.list
new file mode 100644
index 0000000..ae7f4f3
--- /dev/null
+++ b/fw/Debug/iaq_wired_sensor.list
@@ -0,0 +1,2140 @@
+
+iaq_wired_sensor.elf: file format elf32-littlearm
+
+Sections:
+Idx Name Size VMA LMA File off Algn
+ 0 .isr_vector 000000c0 08000000 08000000 00010000 2**0
+ CONTENTS, ALLOC, LOAD, READONLY, DATA
+ 1 .text 00000b50 080000c0 080000c0 000100c0 2**2
+ CONTENTS, ALLOC, LOAD, READONLY, CODE
+ 2 .rodata 00000024 08000c10 08000c10 00010c10 2**0
+ CONTENTS, ALLOC, LOAD, READONLY, DATA
+ 3 .ARM.extab 00000000 08000c34 08000c34 00020004 2**0
+ CONTENTS
+ 4 .ARM 00000008 08000c34 08000c34 00010c34 2**2
+ CONTENTS, ALLOC, LOAD, READONLY, DATA
+ 5 .preinit_array 00000000 08000c3c 08000c3c 00020004 2**0
+ CONTENTS, ALLOC, LOAD, DATA
+ 6 .init_array 00000004 08000c3c 08000c3c 00010c3c 2**2
+ CONTENTS, ALLOC, LOAD, DATA
+ 7 .fini_array 00000004 08000c40 08000c40 00010c40 2**2
+ CONTENTS, ALLOC, LOAD, DATA
+ 8 .data 00000004 20000000 08000c44 00020000 2**2
+ CONTENTS, ALLOC, LOAD, DATA
+ 9 .bss 0000001c 20000004 08000c48 00020004 2**2
+ ALLOC
+ 10 ._user_heap_stack 00000600 20000020 08000c48 00020020 2**0
+ ALLOC
+ 11 .ARM.attributes 00000028 00000000 00000000 00020004 2**0
+ CONTENTS, READONLY
+ 12 .debug_info 00004bf4 00000000 00000000 0002002c 2**0
+ CONTENTS, READONLY, DEBUGGING, OCTETS
+ 13 .debug_abbrev 00001294 00000000 00000000 00024c20 2**0
+ CONTENTS, READONLY, DEBUGGING, OCTETS
+ 14 .debug_loc 000019f8 00000000 00000000 00025eb4 2**0
+ CONTENTS, READONLY, DEBUGGING, OCTETS
+ 15 .debug_aranges 00000220 00000000 00000000 000278b0 2**3
+ CONTENTS, READONLY, DEBUGGING, OCTETS
+ 16 .debug_ranges 000009b8 00000000 00000000 00027ad0 2**3
+ CONTENTS, READONLY, DEBUGGING, OCTETS
+ 17 .debug_macro 0000b1c4 00000000 00000000 00028488 2**0
+ CONTENTS, READONLY, DEBUGGING, OCTETS
+ 18 .debug_line 000042de 00000000 00000000 0003364c 2**0
+ CONTENTS, READONLY, DEBUGGING, OCTETS
+ 19 .debug_str 000391e8 00000000 00000000 0003792a 2**0
+ CONTENTS, READONLY, DEBUGGING, OCTETS
+ 20 .comment 00000053 00000000 00000000 00070b12 2**0
+ CONTENTS, READONLY
+ 21 .debug_frame 000004a8 00000000 00000000 00070b68 2**2
+ CONTENTS, READONLY, DEBUGGING, OCTETS
+
+Disassembly of section .text:
+
+080000c0 <__do_global_dtors_aux>:
+ 80000c0: b510 push {r4, lr}
+ 80000c2: 4c06 ldr r4, [pc, #24] ; (80000dc <__do_global_dtors_aux+0x1c>)
+ 80000c4: 7823 ldrb r3, [r4, #0]
+ 80000c6: 2b00 cmp r3, #0
+ 80000c8: d107 bne.n 80000da <__do_global_dtors_aux+0x1a>
+ 80000ca: 4b05 ldr r3, [pc, #20] ; (80000e0 <__do_global_dtors_aux+0x20>)
+ 80000cc: 2b00 cmp r3, #0
+ 80000ce: d002 beq.n 80000d6 <__do_global_dtors_aux+0x16>
+ 80000d0: 4804 ldr r0, [pc, #16] ; (80000e4 <__do_global_dtors_aux+0x24>)
+ 80000d2: e000 b.n 80000d6 <__do_global_dtors_aux+0x16>
+ 80000d4: bf00 nop
+ 80000d6: 2301 movs r3, #1
+ 80000d8: 7023 strb r3, [r4, #0]
+ 80000da: bd10 pop {r4, pc}
+ 80000dc: 20000004 .word 0x20000004
+ 80000e0: 00000000 .word 0x00000000
+ 80000e4: 08000bf8 .word 0x08000bf8
+
+080000e8 :
+ 80000e8: 4b04 ldr r3, [pc, #16] ; (80000fc )
+ 80000ea: b510 push {r4, lr}
+ 80000ec: 2b00 cmp r3, #0
+ 80000ee: d003 beq.n 80000f8
+ 80000f0: 4903 ldr r1, [pc, #12] ; (8000100 )
+ 80000f2: 4804 ldr r0, [pc, #16] ; (8000104 )
+ 80000f4: e000 b.n 80000f8
+ 80000f6: bf00 nop
+ 80000f8: bd10 pop {r4, pc}
+ 80000fa: 46c0 nop ; (mov r8, r8)
+ 80000fc: 00000000 .word 0x00000000
+ 8000100: 20000008 .word 0x20000008
+ 8000104: 08000bf8 .word 0x08000bf8
+
+08000108 <__udivsi3>:
+ 8000108: 2200 movs r2, #0
+ 800010a: 0843 lsrs r3, r0, #1
+ 800010c: 428b cmp r3, r1
+ 800010e: d374 bcc.n 80001fa <__udivsi3+0xf2>
+ 8000110: 0903 lsrs r3, r0, #4
+ 8000112: 428b cmp r3, r1
+ 8000114: d35f bcc.n 80001d6 <__udivsi3+0xce>
+ 8000116: 0a03 lsrs r3, r0, #8
+ 8000118: 428b cmp r3, r1
+ 800011a: d344 bcc.n 80001a6 <__udivsi3+0x9e>
+ 800011c: 0b03 lsrs r3, r0, #12
+ 800011e: 428b cmp r3, r1
+ 8000120: d328 bcc.n 8000174 <__udivsi3+0x6c>
+ 8000122: 0c03 lsrs r3, r0, #16
+ 8000124: 428b cmp r3, r1
+ 8000126: d30d bcc.n 8000144 <__udivsi3+0x3c>
+ 8000128: 22ff movs r2, #255 ; 0xff
+ 800012a: 0209 lsls r1, r1, #8
+ 800012c: ba12 rev r2, r2
+ 800012e: 0c03 lsrs r3, r0, #16
+ 8000130: 428b cmp r3, r1
+ 8000132: d302 bcc.n 800013a <__udivsi3+0x32>
+ 8000134: 1212 asrs r2, r2, #8
+ 8000136: 0209 lsls r1, r1, #8
+ 8000138: d065 beq.n 8000206 <__udivsi3+0xfe>
+ 800013a: 0b03 lsrs r3, r0, #12
+ 800013c: 428b cmp r3, r1
+ 800013e: d319 bcc.n 8000174 <__udivsi3+0x6c>
+ 8000140: e000 b.n 8000144 <__udivsi3+0x3c>
+ 8000142: 0a09 lsrs r1, r1, #8
+ 8000144: 0bc3 lsrs r3, r0, #15
+ 8000146: 428b cmp r3, r1
+ 8000148: d301 bcc.n 800014e <__udivsi3+0x46>
+ 800014a: 03cb lsls r3, r1, #15
+ 800014c: 1ac0 subs r0, r0, r3
+ 800014e: 4152 adcs r2, r2
+ 8000150: 0b83 lsrs r3, r0, #14
+ 8000152: 428b cmp r3, r1
+ 8000154: d301 bcc.n 800015a <__udivsi3+0x52>
+ 8000156: 038b lsls r3, r1, #14
+ 8000158: 1ac0 subs r0, r0, r3
+ 800015a: 4152 adcs r2, r2
+ 800015c: 0b43 lsrs r3, r0, #13
+ 800015e: 428b cmp r3, r1
+ 8000160: d301 bcc.n 8000166 <__udivsi3+0x5e>
+ 8000162: 034b lsls r3, r1, #13
+ 8000164: 1ac0 subs r0, r0, r3
+ 8000166: 4152 adcs r2, r2
+ 8000168: 0b03 lsrs r3, r0, #12
+ 800016a: 428b cmp r3, r1
+ 800016c: d301 bcc.n 8000172 <__udivsi3+0x6a>
+ 800016e: 030b lsls r3, r1, #12
+ 8000170: 1ac0 subs r0, r0, r3
+ 8000172: 4152 adcs r2, r2
+ 8000174: 0ac3 lsrs r3, r0, #11
+ 8000176: 428b cmp r3, r1
+ 8000178: d301 bcc.n 800017e <__udivsi3+0x76>
+ 800017a: 02cb lsls r3, r1, #11
+ 800017c: 1ac0 subs r0, r0, r3
+ 800017e: 4152 adcs r2, r2
+ 8000180: 0a83 lsrs r3, r0, #10
+ 8000182: 428b cmp r3, r1
+ 8000184: d301 bcc.n 800018a <__udivsi3+0x82>
+ 8000186: 028b lsls r3, r1, #10
+ 8000188: 1ac0 subs r0, r0, r3
+ 800018a: 4152 adcs r2, r2
+ 800018c: 0a43 lsrs r3, r0, #9
+ 800018e: 428b cmp r3, r1
+ 8000190: d301 bcc.n 8000196 <__udivsi3+0x8e>
+ 8000192: 024b lsls r3, r1, #9
+ 8000194: 1ac0 subs r0, r0, r3
+ 8000196: 4152 adcs r2, r2
+ 8000198: 0a03 lsrs r3, r0, #8
+ 800019a: 428b cmp r3, r1
+ 800019c: d301 bcc.n 80001a2 <__udivsi3+0x9a>
+ 800019e: 020b lsls r3, r1, #8
+ 80001a0: 1ac0 subs r0, r0, r3
+ 80001a2: 4152 adcs r2, r2
+ 80001a4: d2cd bcs.n 8000142 <__udivsi3+0x3a>
+ 80001a6: 09c3 lsrs r3, r0, #7
+ 80001a8: 428b cmp r3, r1
+ 80001aa: d301 bcc.n 80001b0 <__udivsi3+0xa8>
+ 80001ac: 01cb lsls r3, r1, #7
+ 80001ae: 1ac0 subs r0, r0, r3
+ 80001b0: 4152 adcs r2, r2
+ 80001b2: 0983 lsrs r3, r0, #6
+ 80001b4: 428b cmp r3, r1
+ 80001b6: d301 bcc.n 80001bc <__udivsi3+0xb4>
+ 80001b8: 018b lsls r3, r1, #6
+ 80001ba: 1ac0 subs r0, r0, r3
+ 80001bc: 4152 adcs r2, r2
+ 80001be: 0943 lsrs r3, r0, #5
+ 80001c0: 428b cmp r3, r1
+ 80001c2: d301 bcc.n 80001c8 <__udivsi3+0xc0>
+ 80001c4: 014b lsls r3, r1, #5
+ 80001c6: 1ac0 subs r0, r0, r3
+ 80001c8: 4152 adcs r2, r2
+ 80001ca: 0903 lsrs r3, r0, #4
+ 80001cc: 428b cmp r3, r1
+ 80001ce: d301 bcc.n 80001d4 <__udivsi3+0xcc>
+ 80001d0: 010b lsls r3, r1, #4
+ 80001d2: 1ac0 subs r0, r0, r3
+ 80001d4: 4152 adcs r2, r2
+ 80001d6: 08c3 lsrs r3, r0, #3
+ 80001d8: 428b cmp r3, r1
+ 80001da: d301 bcc.n 80001e0 <__udivsi3+0xd8>
+ 80001dc: 00cb lsls r3, r1, #3
+ 80001de: 1ac0 subs r0, r0, r3
+ 80001e0: 4152 adcs r2, r2
+ 80001e2: 0883 lsrs r3, r0, #2
+ 80001e4: 428b cmp r3, r1
+ 80001e6: d301 bcc.n 80001ec <__udivsi3+0xe4>
+ 80001e8: 008b lsls r3, r1, #2
+ 80001ea: 1ac0 subs r0, r0, r3
+ 80001ec: 4152 adcs r2, r2
+ 80001ee: 0843 lsrs r3, r0, #1
+ 80001f0: 428b cmp r3, r1
+ 80001f2: d301 bcc.n 80001f8 <__udivsi3+0xf0>
+ 80001f4: 004b lsls r3, r1, #1
+ 80001f6: 1ac0 subs r0, r0, r3
+ 80001f8: 4152 adcs r2, r2
+ 80001fa: 1a41 subs r1, r0, r1
+ 80001fc: d200 bcs.n 8000200 <__udivsi3+0xf8>
+ 80001fe: 4601 mov r1, r0
+ 8000200: 4152 adcs r2, r2
+ 8000202: 4610 mov r0, r2
+ 8000204: 4770 bx lr
+ 8000206: e7ff b.n 8000208 <__udivsi3+0x100>
+ 8000208: b501 push {r0, lr}
+ 800020a: 2000 movs r0, #0
+ 800020c: f000 f806 bl 800021c <__aeabi_idiv0>
+ 8000210: bd02 pop {r1, pc}
+ 8000212: 46c0 nop ; (mov r8, r8)
+
+08000214 <__aeabi_uidivmod>:
+ 8000214: 2900 cmp r1, #0
+ 8000216: d0f7 beq.n 8000208 <__udivsi3+0x100>
+ 8000218: e776 b.n 8000108 <__udivsi3>
+ 800021a: 4770 bx lr
+
+0800021c <__aeabi_idiv0>:
+ 800021c: 4770 bx lr
+ 800021e: 46c0 nop ; (mov r8, r8)
+
+08000220 <__aeabi_uldivmod>:
+ 8000220: 2b00 cmp r3, #0
+ 8000222: d111 bne.n 8000248 <__aeabi_uldivmod+0x28>
+ 8000224: 2a00 cmp r2, #0
+ 8000226: d10f bne.n 8000248 <__aeabi_uldivmod+0x28>
+ 8000228: 2900 cmp r1, #0
+ 800022a: d100 bne.n 800022e <__aeabi_uldivmod+0xe>
+ 800022c: 2800 cmp r0, #0
+ 800022e: d002 beq.n 8000236 <__aeabi_uldivmod+0x16>
+ 8000230: 2100 movs r1, #0
+ 8000232: 43c9 mvns r1, r1
+ 8000234: 1c08 adds r0, r1, #0
+ 8000236: b407 push {r0, r1, r2}
+ 8000238: 4802 ldr r0, [pc, #8] ; (8000244 <__aeabi_uldivmod+0x24>)
+ 800023a: a102 add r1, pc, #8 ; (adr r1, 8000244 <__aeabi_uldivmod+0x24>)
+ 800023c: 1840 adds r0, r0, r1
+ 800023e: 9002 str r0, [sp, #8]
+ 8000240: bd03 pop {r0, r1, pc}
+ 8000242: 46c0 nop ; (mov r8, r8)
+ 8000244: ffffffd9 .word 0xffffffd9
+ 8000248: b403 push {r0, r1}
+ 800024a: 4668 mov r0, sp
+ 800024c: b501 push {r0, lr}
+ 800024e: 9802 ldr r0, [sp, #8]
+ 8000250: f000 f806 bl 8000260 <__udivmoddi4>
+ 8000254: 9b01 ldr r3, [sp, #4]
+ 8000256: 469e mov lr, r3
+ 8000258: b002 add sp, #8
+ 800025a: bc0c pop {r2, r3}
+ 800025c: 4770 bx lr
+ 800025e: 46c0 nop ; (mov r8, r8)
+
+08000260 <__udivmoddi4>:
+ 8000260: b5f0 push {r4, r5, r6, r7, lr}
+ 8000262: 4657 mov r7, sl
+ 8000264: 464e mov r6, r9
+ 8000266: 4645 mov r5, r8
+ 8000268: 46de mov lr, fp
+ 800026a: b5e0 push {r5, r6, r7, lr}
+ 800026c: 0004 movs r4, r0
+ 800026e: 000d movs r5, r1
+ 8000270: 4692 mov sl, r2
+ 8000272: 4699 mov r9, r3
+ 8000274: b083 sub sp, #12
+ 8000276: 428b cmp r3, r1
+ 8000278: d830 bhi.n 80002dc <__udivmoddi4+0x7c>
+ 800027a: d02d beq.n 80002d8 <__udivmoddi4+0x78>
+ 800027c: 4649 mov r1, r9
+ 800027e: 4650 mov r0, sl
+ 8000280: f000 f8ba bl 80003f8 <__clzdi2>
+ 8000284: 0029 movs r1, r5
+ 8000286: 0006 movs r6, r0
+ 8000288: 0020 movs r0, r4
+ 800028a: f000 f8b5 bl 80003f8 <__clzdi2>
+ 800028e: 1a33 subs r3, r6, r0
+ 8000290: 4698 mov r8, r3
+ 8000292: 3b20 subs r3, #32
+ 8000294: 469b mov fp, r3
+ 8000296: d433 bmi.n 8000300 <__udivmoddi4+0xa0>
+ 8000298: 465a mov r2, fp
+ 800029a: 4653 mov r3, sl
+ 800029c: 4093 lsls r3, r2
+ 800029e: 4642 mov r2, r8
+ 80002a0: 001f movs r7, r3
+ 80002a2: 4653 mov r3, sl
+ 80002a4: 4093 lsls r3, r2
+ 80002a6: 001e movs r6, r3
+ 80002a8: 42af cmp r7, r5
+ 80002aa: d83a bhi.n 8000322 <__udivmoddi4+0xc2>
+ 80002ac: 42af cmp r7, r5
+ 80002ae: d100 bne.n 80002b2 <__udivmoddi4+0x52>
+ 80002b0: e078 b.n 80003a4 <__udivmoddi4+0x144>
+ 80002b2: 465b mov r3, fp
+ 80002b4: 1ba4 subs r4, r4, r6
+ 80002b6: 41bd sbcs r5, r7
+ 80002b8: 2b00 cmp r3, #0
+ 80002ba: da00 bge.n 80002be <__udivmoddi4+0x5e>
+ 80002bc: e075 b.n 80003aa <__udivmoddi4+0x14a>
+ 80002be: 2200 movs r2, #0
+ 80002c0: 2300 movs r3, #0
+ 80002c2: 9200 str r2, [sp, #0]
+ 80002c4: 9301 str r3, [sp, #4]
+ 80002c6: 2301 movs r3, #1
+ 80002c8: 465a mov r2, fp
+ 80002ca: 4093 lsls r3, r2
+ 80002cc: 9301 str r3, [sp, #4]
+ 80002ce: 2301 movs r3, #1
+ 80002d0: 4642 mov r2, r8
+ 80002d2: 4093 lsls r3, r2
+ 80002d4: 9300 str r3, [sp, #0]
+ 80002d6: e028 b.n 800032a <__udivmoddi4+0xca>
+ 80002d8: 4282 cmp r2, r0
+ 80002da: d9cf bls.n 800027c <__udivmoddi4+0x1c>
+ 80002dc: 2200 movs r2, #0
+ 80002de: 2300 movs r3, #0
+ 80002e0: 9200 str r2, [sp, #0]
+ 80002e2: 9301 str r3, [sp, #4]
+ 80002e4: 9b0c ldr r3, [sp, #48] ; 0x30
+ 80002e6: 2b00 cmp r3, #0
+ 80002e8: d001 beq.n 80002ee <__udivmoddi4+0x8e>
+ 80002ea: 601c str r4, [r3, #0]
+ 80002ec: 605d str r5, [r3, #4]
+ 80002ee: 9800 ldr r0, [sp, #0]
+ 80002f0: 9901 ldr r1, [sp, #4]
+ 80002f2: b003 add sp, #12
+ 80002f4: bcf0 pop {r4, r5, r6, r7}
+ 80002f6: 46bb mov fp, r7
+ 80002f8: 46b2 mov sl, r6
+ 80002fa: 46a9 mov r9, r5
+ 80002fc: 46a0 mov r8, r4
+ 80002fe: bdf0 pop {r4, r5, r6, r7, pc}
+ 8000300: 4642 mov r2, r8
+ 8000302: 2320 movs r3, #32
+ 8000304: 1a9b subs r3, r3, r2
+ 8000306: 4652 mov r2, sl
+ 8000308: 40da lsrs r2, r3
+ 800030a: 4641 mov r1, r8
+ 800030c: 0013 movs r3, r2
+ 800030e: 464a mov r2, r9
+ 8000310: 408a lsls r2, r1
+ 8000312: 0017 movs r7, r2
+ 8000314: 4642 mov r2, r8
+ 8000316: 431f orrs r7, r3
+ 8000318: 4653 mov r3, sl
+ 800031a: 4093 lsls r3, r2
+ 800031c: 001e movs r6, r3
+ 800031e: 42af cmp r7, r5
+ 8000320: d9c4 bls.n 80002ac <__udivmoddi4+0x4c>
+ 8000322: 2200 movs r2, #0
+ 8000324: 2300 movs r3, #0
+ 8000326: 9200 str r2, [sp, #0]
+ 8000328: 9301 str r3, [sp, #4]
+ 800032a: 4643 mov r3, r8
+ 800032c: 2b00 cmp r3, #0
+ 800032e: d0d9 beq.n 80002e4 <__udivmoddi4+0x84>
+ 8000330: 07fb lsls r3, r7, #31
+ 8000332: 0872 lsrs r2, r6, #1
+ 8000334: 431a orrs r2, r3
+ 8000336: 4646 mov r6, r8
+ 8000338: 087b lsrs r3, r7, #1
+ 800033a: e00e b.n 800035a <__udivmoddi4+0xfa>
+ 800033c: 42ab cmp r3, r5
+ 800033e: d101 bne.n 8000344 <__udivmoddi4+0xe4>
+ 8000340: 42a2 cmp r2, r4
+ 8000342: d80c bhi.n 800035e <__udivmoddi4+0xfe>
+ 8000344: 1aa4 subs r4, r4, r2
+ 8000346: 419d sbcs r5, r3
+ 8000348: 2001 movs r0, #1
+ 800034a: 1924 adds r4, r4, r4
+ 800034c: 416d adcs r5, r5
+ 800034e: 2100 movs r1, #0
+ 8000350: 3e01 subs r6, #1
+ 8000352: 1824 adds r4, r4, r0
+ 8000354: 414d adcs r5, r1
+ 8000356: 2e00 cmp r6, #0
+ 8000358: d006 beq.n 8000368 <__udivmoddi4+0x108>
+ 800035a: 42ab cmp r3, r5
+ 800035c: d9ee bls.n 800033c <__udivmoddi4+0xdc>
+ 800035e: 3e01 subs r6, #1
+ 8000360: 1924 adds r4, r4, r4
+ 8000362: 416d adcs r5, r5
+ 8000364: 2e00 cmp r6, #0
+ 8000366: d1f8 bne.n 800035a <__udivmoddi4+0xfa>
+ 8000368: 9800 ldr r0, [sp, #0]
+ 800036a: 9901 ldr r1, [sp, #4]
+ 800036c: 465b mov r3, fp
+ 800036e: 1900 adds r0, r0, r4
+ 8000370: 4169 adcs r1, r5
+ 8000372: 2b00 cmp r3, #0
+ 8000374: db24 blt.n 80003c0 <__udivmoddi4+0x160>
+ 8000376: 002b movs r3, r5
+ 8000378: 465a mov r2, fp
+ 800037a: 4644 mov r4, r8
+ 800037c: 40d3 lsrs r3, r2
+ 800037e: 002a movs r2, r5
+ 8000380: 40e2 lsrs r2, r4
+ 8000382: 001c movs r4, r3
+ 8000384: 465b mov r3, fp
+ 8000386: 0015 movs r5, r2
+ 8000388: 2b00 cmp r3, #0
+ 800038a: db2a blt.n 80003e2 <__udivmoddi4+0x182>
+ 800038c: 0026 movs r6, r4
+ 800038e: 409e lsls r6, r3
+ 8000390: 0033 movs r3, r6
+ 8000392: 0026 movs r6, r4
+ 8000394: 4647 mov r7, r8
+ 8000396: 40be lsls r6, r7
+ 8000398: 0032 movs r2, r6
+ 800039a: 1a80 subs r0, r0, r2
+ 800039c: 4199 sbcs r1, r3
+ 800039e: 9000 str r0, [sp, #0]
+ 80003a0: 9101 str r1, [sp, #4]
+ 80003a2: e79f b.n 80002e4 <__udivmoddi4+0x84>
+ 80003a4: 42a3 cmp r3, r4
+ 80003a6: d8bc bhi.n 8000322 <__udivmoddi4+0xc2>
+ 80003a8: e783 b.n 80002b2 <__udivmoddi4+0x52>
+ 80003aa: 4642 mov r2, r8
+ 80003ac: 2320 movs r3, #32
+ 80003ae: 2100 movs r1, #0
+ 80003b0: 1a9b subs r3, r3, r2
+ 80003b2: 2200 movs r2, #0
+ 80003b4: 9100 str r1, [sp, #0]
+ 80003b6: 9201 str r2, [sp, #4]
+ 80003b8: 2201 movs r2, #1
+ 80003ba: 40da lsrs r2, r3
+ 80003bc: 9201 str r2, [sp, #4]
+ 80003be: e786 b.n 80002ce <__udivmoddi4+0x6e>
+ 80003c0: 4642 mov r2, r8
+ 80003c2: 2320 movs r3, #32
+ 80003c4: 1a9b subs r3, r3, r2
+ 80003c6: 002a movs r2, r5
+ 80003c8: 4646 mov r6, r8
+ 80003ca: 409a lsls r2, r3
+ 80003cc: 0023 movs r3, r4
+ 80003ce: 40f3 lsrs r3, r6
+ 80003d0: 4644 mov r4, r8
+ 80003d2: 4313 orrs r3, r2
+ 80003d4: 002a movs r2, r5
+ 80003d6: 40e2 lsrs r2, r4
+ 80003d8: 001c movs r4, r3
+ 80003da: 465b mov r3, fp
+ 80003dc: 0015 movs r5, r2
+ 80003de: 2b00 cmp r3, #0
+ 80003e0: dad4 bge.n 800038c <__udivmoddi4+0x12c>
+ 80003e2: 4642 mov r2, r8
+ 80003e4: 002f movs r7, r5
+ 80003e6: 2320 movs r3, #32
+ 80003e8: 0026 movs r6, r4
+ 80003ea: 4097 lsls r7, r2
+ 80003ec: 1a9b subs r3, r3, r2
+ 80003ee: 40de lsrs r6, r3
+ 80003f0: 003b movs r3, r7
+ 80003f2: 4333 orrs r3, r6
+ 80003f4: e7cd b.n 8000392 <__udivmoddi4+0x132>
+ 80003f6: 46c0 nop ; (mov r8, r8)
+
+080003f8 <__clzdi2>:
+ 80003f8: b510 push {r4, lr}
+ 80003fa: 2900 cmp r1, #0
+ 80003fc: d103 bne.n 8000406 <__clzdi2+0xe>
+ 80003fe: f000 f807 bl 8000410 <__clzsi2>
+ 8000402: 3020 adds r0, #32
+ 8000404: e002 b.n 800040c <__clzdi2+0x14>
+ 8000406: 1c08 adds r0, r1, #0
+ 8000408: f000 f802 bl 8000410 <__clzsi2>
+ 800040c: bd10 pop {r4, pc}
+ 800040e: 46c0 nop ; (mov r8, r8)
+
+08000410 <__clzsi2>:
+ 8000410: 211c movs r1, #28
+ 8000412: 2301 movs r3, #1
+ 8000414: 041b lsls r3, r3, #16
+ 8000416: 4298 cmp r0, r3
+ 8000418: d301 bcc.n 800041e <__clzsi2+0xe>
+ 800041a: 0c00 lsrs r0, r0, #16
+ 800041c: 3910 subs r1, #16
+ 800041e: 0a1b lsrs r3, r3, #8
+ 8000420: 4298 cmp r0, r3
+ 8000422: d301 bcc.n 8000428 <__clzsi2+0x18>
+ 8000424: 0a00 lsrs r0, r0, #8
+ 8000426: 3908 subs r1, #8
+ 8000428: 091b lsrs r3, r3, #4
+ 800042a: 4298 cmp r0, r3
+ 800042c: d301 bcc.n 8000432 <__clzsi2+0x22>
+ 800042e: 0900 lsrs r0, r0, #4
+ 8000430: 3904 subs r1, #4
+ 8000432: a202 add r2, pc, #8 ; (adr r2, 800043c <__clzsi2+0x2c>)
+ 8000434: 5c10 ldrb r0, [r2, r0]
+ 8000436: 1840 adds r0, r0, r1
+ 8000438: 4770 bx lr
+ 800043a: 46c0 nop ; (mov r8, r8)
+ 800043c: 02020304 .word 0x02020304
+ 8000440: 01010101 .word 0x01010101
+ ...
+
+0800044c :
+ * @retval None
+*/
+__STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs)
+{
+ __IO uint32_t tmpreg;
+ SET_BIT(RCC->APB1ENR, Periphs);
+ 800044c: 4b05 ldr r3, [pc, #20] ; (8000464 )
+{
+ 800044e: b082 sub sp, #8
+ SET_BIT(RCC->APB1ENR, Periphs);
+ 8000450: 6b9a ldr r2, [r3, #56] ; 0x38
+ 8000452: 4302 orrs r2, r0
+ 8000454: 639a str r2, [r3, #56] ; 0x38
+ /* Delay after an RCC peripheral clock enabling */
+ tmpreg = READ_BIT(RCC->APB1ENR, Periphs);
+ 8000456: 6b9b ldr r3, [r3, #56] ; 0x38
+ 8000458: 4018 ands r0, r3
+ 800045a: 9001 str r0, [sp, #4]
+ (void)tmpreg;
+ 800045c: 9b01 ldr r3, [sp, #4]
+}
+ 800045e: b002 add sp, #8
+ 8000460: 4770 bx lr
+ 8000462: 46c0 nop ; (mov r8, r8)
+ 8000464: 40021000 .word 0x40021000
+
+08000468 :
+ * @retval None
+*/
+__STATIC_INLINE void LL_IOP_GRP1_EnableClock(uint32_t Periphs)
+{
+ __IO uint32_t tmpreg;
+ SET_BIT(RCC->IOPENR, Periphs);
+ 8000468: 2001 movs r0, #1
+ 800046a: 4a05 ldr r2, [pc, #20] ; (8000480 )
+__STATIC_INLINE void LL_IOP_GRP1_EnableClock(uint32_t Periphs)
+ 800046c: b082 sub sp, #8
+ SET_BIT(RCC->IOPENR, Periphs);
+ 800046e: 6ad1 ldr r1, [r2, #44] ; 0x2c
+ 8000470: 4301 orrs r1, r0
+ 8000472: 62d1 str r1, [r2, #44] ; 0x2c
+ /* Delay after an RCC peripheral clock enabling */
+ tmpreg = READ_BIT(RCC->IOPENR, Periphs);
+ 8000474: 6ad3 ldr r3, [r2, #44] ; 0x2c
+ 8000476: 4003 ands r3, r0
+ 8000478: 9301 str r3, [sp, #4]
+ (void)tmpreg;
+ 800047a: 9b01 ldr r3, [sp, #4]
+}
+ 800047c: b002 add sp, #8
+ 800047e: 4770 bx lr
+ 8000480: 40021000 .word 0x40021000
+
+08000484 :
+ * @arg @ref LL_FLASH_LATENCY_1
+ * @retval None
+ */
+__STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency)
+{
+ MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency);
+ 8000484: 2201 movs r2, #1
+ 8000486: 4b24 ldr r3, [pc, #144] ; (8000518 )
+/**
+ * @brief System Clock Configuration
+ * @retval None
+ */
+void SystemClock_Config(void)
+{
+ 8000488: b510 push {r4, lr}
+ 800048a: 6819 ldr r1, [r3, #0]
+ 800048c: 4391 bics r1, r2
+ 800048e: 6019 str r1, [r3, #0]
+ * @arg @ref LL_FLASH_LATENCY_0
+ * @arg @ref LL_FLASH_LATENCY_1
+ */
+__STATIC_INLINE uint32_t LL_FLASH_GetLatency(void)
+{
+ return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY));
+ 8000490: 6819 ldr r1, [r3, #0]
+ LL_FLASH_SetLatency(LL_FLASH_LATENCY_0);
+ while(LL_FLASH_GetLatency()!= LL_FLASH_LATENCY_0)
+ 8000492: 4211 tst r1, r2
+ 8000494: d1fc bne.n 8000490
+ * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE3
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_SetRegulVoltageScaling(uint32_t VoltageScaling)
+{
+ MODIFY_REG(PWR->CR, PWR_CR_VOS, VoltageScaling);
+ 8000496: 4921 ldr r1, [pc, #132] ; (800051c )
+ 8000498: 4a21 ldr r2, [pc, #132] ; (8000520 )
+ 800049a: 680b ldr r3, [r1, #0]
+ * @rmtoll CR MSION LL_RCC_MSI_Enable
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_MSI_Enable(void)
+{
+ SET_BIT(RCC->CR, RCC_CR_MSION);
+ 800049c: 4c21 ldr r4, [pc, #132] ; (8000524 )
+ 800049e: 401a ands r2, r3
+ 80004a0: 2380 movs r3, #128 ; 0x80
+ 80004a2: 011b lsls r3, r3, #4
+ 80004a4: 4313 orrs r3, r2
+ 80004a6: 600b str r3, [r1, #0]
+ 80004a8: 2380 movs r3, #128 ; 0x80
+ 80004aa: 6822 ldr r2, [r4, #0]
+ 80004ac: 005b lsls r3, r3, #1
+ 80004ae: 4313 orrs r3, r2
+ 80004b0: 6023 str r3, [r4, #0]
+ * @rmtoll CR MSIRDY LL_RCC_MSI_IsReady
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_MSI_IsReady(void)
+{
+ return ((READ_BIT(RCC->CR, RCC_CR_MSIRDY) == RCC_CR_MSIRDY) ? 1UL : 0UL);
+ 80004b2: 2380 movs r3, #128 ; 0x80
+ 80004b4: 009b lsls r3, r3, #2
+ 80004b6: 6822 ldr r2, [r4, #0]
+ 80004b8: 421a tst r2, r3
+ 80004ba: d0fc beq.n 80004b6
+ * @arg @ref LL_RCC_MSIRANGE_6
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_MSI_SetRange(uint32_t Range)
+{
+ MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSIRANGE, Range);
+ 80004bc: 6863 ldr r3, [r4, #4]
+ 80004be: 4a1a ldr r2, [pc, #104] ; (8000528 )
+ 80004c0: 401a ands r2, r3
+ 80004c2: 23a0 movs r3, #160 ; 0xa0
+ 80004c4: 021b lsls r3, r3, #8
+ 80004c6: 4313 orrs r3, r2
+ * @arg @ref LL_RCC_SYSCLK_DIV_512
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler)
+{
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler);
+ 80004c8: 22f0 movs r2, #240 ; 0xf0
+ MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSIRANGE, Range);
+ 80004ca: 6063 str r3, [r4, #4]
+ MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSITRIM, Value << RCC_ICSCR_MSITRIM_Pos);
+ 80004cc: 6863 ldr r3, [r4, #4]
+ 80004ce: 021b lsls r3, r3, #8
+ 80004d0: 0a1b lsrs r3, r3, #8
+ 80004d2: 6063 str r3, [r4, #4]
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler);
+ 80004d4: 68e3 ldr r3, [r4, #12]
+ 80004d6: 4393 bics r3, r2
+ 80004d8: 60e3 str r3, [r4, #12]
+ * @arg @ref LL_RCC_APB1_DIV_16
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)
+{
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, Prescaler);
+ 80004da: 68e3 ldr r3, [r4, #12]
+ 80004dc: 4a13 ldr r2, [pc, #76] ; (800052c )
+ 80004de: 4013 ands r3, r2
+ 80004e0: 60e3 str r3, [r4, #12]
+ * @arg @ref LL_RCC_APB2_DIV_16
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler)
+{
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler);
+ 80004e2: 68e3 ldr r3, [r4, #12]
+ 80004e4: 4a12 ldr r2, [pc, #72] ; (8000530 )
+ 80004e6: 4013 ands r3, r2
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source);
+ 80004e8: 2203 movs r2, #3
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler);
+ 80004ea: 60e3 str r3, [r4, #12]
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source);
+ 80004ec: 68e3 ldr r3, [r4, #12]
+ 80004ee: 4393 bics r3, r2
+ 80004f0: 60e3 str r3, [r4, #12]
+ return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS));
+ 80004f2: 230c movs r3, #12
+ 80004f4: 68e2 ldr r2, [r4, #12]
+ LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_1);
+ LL_RCC_SetAPB2Prescaler(LL_RCC_APB2_DIV_1);
+ LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_MSI);
+
+ /* Wait till System clock is ready */
+ while(LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_MSI)
+ 80004f6: 421a tst r2, r3
+ 80004f8: d1fc bne.n 80004f4
+ {
+
+ }
+
+ LL_Init1msTick(2097000);
+ 80004fa: 480e ldr r0, [pc, #56] ; (8000534 )
+ 80004fc: f000 fb24 bl 8000b48
+
+ LL_SetSystemCoreClock(2097000);
+ 8000500: 480c ldr r0, [pc, #48] ; (8000534 )
+ 8000502: f000 fb47 bl 8000b94
+ * @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetLPUARTClockSource(uint32_t LPUARTxSource)
+{
+ MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART1SEL, LPUARTxSource);
+ 8000506: 6ce3 ldr r3, [r4, #76] ; 0x4c
+ 8000508: 4a0b ldr r2, [pc, #44] ; (8000538 )
+ 800050a: 4013 ands r3, r2
+ 800050c: 64e3 str r3, [r4, #76] ; 0x4c
+ * (*) value not defined in all devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetI2CClockSource(uint32_t I2CxSource)
+{
+ MODIFY_REG(RCC->CCIPR, ((I2CxSource >> 4U) & 0x000FF000U), ((I2CxSource << 4U) & 0x000FF000U));
+ 800050e: 6ce3 ldr r3, [r4, #76] ; 0x4c
+ 8000510: 4a0a ldr r2, [pc, #40] ; (800053c )
+ 8000512: 4013 ands r3, r2
+ 8000514: 64e3 str r3, [r4, #76] ; 0x4c
+ LL_RCC_SetLPUARTClockSource(LL_RCC_LPUART1_CLKSOURCE_PCLK1);
+ LL_RCC_SetI2CClockSource(LL_RCC_I2C1_CLKSOURCE_PCLK1);
+}
+ 8000516: bd10 pop {r4, pc}
+ 8000518: 40022000 .word 0x40022000
+ 800051c: 40007000 .word 0x40007000
+ 8000520: ffffe7ff .word 0xffffe7ff
+ 8000524: 40021000 .word 0x40021000
+ 8000528: ffff1fff .word 0xffff1fff
+ 800052c: fffff8ff .word 0xfffff8ff
+ 8000530: ffffc7ff .word 0xffffc7ff
+ 8000534: 001fff68 .word 0x001fff68
+ 8000538: fffff3ff .word 0xfffff3ff
+ 800053c: ffffcfff .word 0xffffcfff
+
+08000540 :
+{
+ 8000540: b5f0 push {r4, r5, r6, r7, lr}
+ SET_BIT(RCC->APB2ENR, Periphs);
+ 8000542: 2701 movs r7, #1
+ LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR);
+ 8000544: 2080 movs r0, #128 ; 0x80
+ 8000546: 4e8c ldr r6, [pc, #560] ; (8000778 )
+{
+ 8000548: b093 sub sp, #76 ; 0x4c
+ 800054a: 6b73 ldr r3, [r6, #52] ; 0x34
+ LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR);
+ 800054c: 0540 lsls r0, r0, #21
+ 800054e: 433b orrs r3, r7
+ 8000550: 6373 str r3, [r6, #52] ; 0x34
+ tmpreg = READ_BIT(RCC->APB2ENR, Periphs);
+ 8000552: 6b73 ldr r3, [r6, #52] ; 0x34
+ * @arg @ref LL_GPIO_PIN_ALL
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_SetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
+{
+ WRITE_REG(GPIOx->BSRR, PinMask);
+ 8000554: 25a0 movs r5, #160 ; 0xa0
+ 8000556: 403b ands r3, r7
+ 8000558: 9303 str r3, [sp, #12]
+ (void)tmpreg;
+ 800055a: 9b03 ldr r3, [sp, #12]
+ 800055c: f7ff ff76 bl 800044c
+ SystemClock_Config();
+ 8000560: f7ff ff90 bl 8000484
+ * @param None
+ * @retval None
+ */
+static void MX_GPIO_Init(void)
+{
+ LL_GPIO_InitTypeDef GPIO_InitStruct = {0};
+ 8000564: 2218 movs r2, #24
+ 8000566: 2100 movs r1, #0
+ 8000568: a80b add r0, sp, #44 ; 0x2c
+ 800056a: f000 fb3d bl 8000be8
+
+ /* GPIO Ports Clock Enable */
+ LL_IOP_GRP1_EnableClock(LL_IOP_GRP1_PERIPH_GPIOA);
+ 800056e: f7ff ff7b bl 8000468
+ 8000572: 2320 movs r3, #32
+ 8000574: 2240 movs r2, #64 ; 0x40
+ 8000576: 2180 movs r1, #128 ; 0x80
+ LL_GPIO_SetOutputPin(LED_R_GPIO_Port, LED_R_Pin);
+
+ /**/
+ GPIO_InitStruct.Pin = LED_B_Pin;
+ GPIO_InitStruct.Mode = LL_GPIO_MODE_OUTPUT;
+ GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_LOW;
+ 8000578: 2400 movs r4, #0
+ 800057a: 05ed lsls r5, r5, #23
+ GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;
+ GPIO_InitStruct.Pull = LL_GPIO_PULL_NO;
+ LL_GPIO_Init(LED_B_GPIO_Port, &GPIO_InitStruct);
+ 800057c: a80b add r0, sp, #44 ; 0x2c
+ 800057e: 61ab str r3, [r5, #24]
+ 8000580: 61aa str r2, [r5, #24]
+ 8000582: 61a9 str r1, [r5, #24]
+ 8000584: 0001 movs r1, r0
+ 8000586: 0028 movs r0, r5
+ GPIO_InitStruct.Pin = LED_B_Pin;
+ 8000588: 930b str r3, [sp, #44] ; 0x2c
+ GPIO_InitStruct.Mode = LL_GPIO_MODE_OUTPUT;
+ 800058a: 970c str r7, [sp, #48] ; 0x30
+ GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_LOW;
+ 800058c: 940d str r4, [sp, #52] ; 0x34
+ GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;
+ 800058e: 940e str r4, [sp, #56] ; 0x38
+ GPIO_InitStruct.Pull = LL_GPIO_PULL_NO;
+ 8000590: 940f str r4, [sp, #60] ; 0x3c
+ LL_GPIO_Init(LED_B_GPIO_Port, &GPIO_InitStruct);
+ 8000592: f000 f95a bl 800084a
+
+ /**/
+ GPIO_InitStruct.Pin = LED_G_Pin;
+ 8000596: 2040 movs r0, #64 ; 0x40
+ GPIO_InitStruct.Mode = LL_GPIO_MODE_OUTPUT;
+ GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_LOW;
+ GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;
+ GPIO_InitStruct.Pull = LL_GPIO_PULL_NO;
+ LL_GPIO_Init(LED_G_GPIO_Port, &GPIO_InitStruct);
+ 8000598: aa0b add r2, sp, #44 ; 0x2c
+ 800059a: 0011 movs r1, r2
+ GPIO_InitStruct.Pin = LED_G_Pin;
+ 800059c: 900b str r0, [sp, #44] ; 0x2c
+ LL_GPIO_Init(LED_G_GPIO_Port, &GPIO_InitStruct);
+ 800059e: 0028 movs r0, r5
+ GPIO_InitStruct.Mode = LL_GPIO_MODE_OUTPUT;
+ 80005a0: 970c str r7, [sp, #48] ; 0x30
+ GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_LOW;
+ 80005a2: 940d str r4, [sp, #52] ; 0x34
+ GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;
+ 80005a4: 940e str r4, [sp, #56] ; 0x38
+ GPIO_InitStruct.Pull = LL_GPIO_PULL_NO;
+ 80005a6: 940f str r4, [sp, #60] ; 0x3c
+ LL_GPIO_Init(LED_G_GPIO_Port, &GPIO_InitStruct);
+ 80005a8: f000 f94f bl 800084a
+
+ /**/
+ GPIO_InitStruct.Pin = LED_R_Pin;
+ 80005ac: 2280 movs r2, #128 ; 0x80
+ 80005ae: 920b str r2, [sp, #44] ; 0x2c
+ GPIO_InitStruct.Mode = LL_GPIO_MODE_OUTPUT;
+ GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_LOW;
+ GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;
+ GPIO_InitStruct.Pull = LL_GPIO_PULL_NO;
+ LL_GPIO_Init(LED_R_GPIO_Port, &GPIO_InitStruct);
+ 80005b0: aa0b add r2, sp, #44 ; 0x2c
+ 80005b2: 0011 movs r1, r2
+ 80005b4: 0028 movs r0, r5
+ GPIO_InitStruct.Mode = LL_GPIO_MODE_OUTPUT;
+ 80005b6: 970c str r7, [sp, #48] ; 0x30
+ GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_LOW;
+ 80005b8: 940d str r4, [sp, #52] ; 0x34
+ GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;
+ 80005ba: 940e str r4, [sp, #56] ; 0x38
+ GPIO_InitStruct.Pull = LL_GPIO_PULL_NO;
+ 80005bc: 940f str r4, [sp, #60] ; 0x3c
+ LL_GPIO_Init(LED_R_GPIO_Port, &GPIO_InitStruct);
+ 80005be: f000 f944 bl 800084a
+ SET_BIT(RCC->AHBENR, Periphs);
+ 80005c2: 6b33 ldr r3, [r6, #48] ; 0x30
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ 80005c4: 21c2 movs r1, #194 ; 0xc2
+ 80005c6: 433b orrs r3, r7
+ 80005c8: 6333 str r3, [r6, #48] ; 0x30
+ tmpreg = READ_BIT(RCC->AHBENR, Periphs);
+ 80005ca: 6b33 ldr r3, [r6, #48] ; 0x30
+ NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ 80005cc: 2680 movs r6, #128 ; 0x80
+ 80005ce: 403b ands r3, r7
+ 80005d0: 9304 str r3, [sp, #16]
+ (void)tmpreg;
+ 80005d2: 9b04 ldr r3, [sp, #16]
+ NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ 80005d4: 4b69 ldr r3, [pc, #420] ; (800077c )
+ 80005d6: 0089 lsls r1, r1, #2
+ 80005d8: 585a ldr r2, [r3, r1]
+ 80005da: 4869 ldr r0, [pc, #420] ; (8000780 )
+ NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ 80005dc: 00f6 lsls r6, r6, #3
+ NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ 80005de: 4002 ands r2, r0
+ 80005e0: 505a str r2, [r3, r1]
+ LL_I2C_InitTypeDef I2C_InitStruct = {0};
+ 80005e2: a80b add r0, sp, #44 ; 0x2c
+ NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ 80005e4: 601e str r6, [r3, #0]
+ 80005e6: 221c movs r2, #28
+ 80005e8: 0021 movs r1, r4
+ 80005ea: f000 fafd bl 8000be8
+ LL_GPIO_InitTypeDef GPIO_InitStruct = {0};
+ 80005ee: 2218 movs r2, #24
+ 80005f0: 0021 movs r1, r4
+ 80005f2: a805 add r0, sp, #20
+ 80005f4: f000 faf8 bl 8000be8
+ LL_IOP_GRP1_EnableClock(LL_IOP_GRP1_PERIPH_GPIOA);
+ 80005f8: f7ff ff36 bl 8000468
+ GPIO_InitStruct.Pin = LL_GPIO_PIN_9;
+ 80005fc: 2380 movs r3, #128 ; 0x80
+ GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH;
+ 80005fe: 2003 movs r0, #3
+ GPIO_InitStruct.Pin = LL_GPIO_PIN_9;
+ 8000600: 009b lsls r3, r3, #2
+ LL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+ 8000602: aa05 add r2, sp, #20
+ GPIO_InitStruct.Pin = LL_GPIO_PIN_9;
+ 8000604: 9305 str r3, [sp, #20]
+ GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE;
+ 8000606: 3bff subs r3, #255 ; 0xff
+ LL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+ 8000608: 0011 movs r1, r2
+ GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE;
+ 800060a: 3bff subs r3, #255 ; 0xff
+ GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH;
+ 800060c: 9007 str r0, [sp, #28]
+ LL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+ 800060e: 0028 movs r0, r5
+ GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE;
+ 8000610: 9306 str r3, [sp, #24]
+ GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_OPENDRAIN;
+ 8000612: 9708 str r7, [sp, #32]
+ GPIO_InitStruct.Pull = LL_GPIO_PULL_UP;
+ 8000614: 9709 str r7, [sp, #36] ; 0x24
+ GPIO_InitStruct.Alternate = LL_GPIO_AF_1;
+ 8000616: 970a str r7, [sp, #40] ; 0x28
+ LL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+ 8000618: f000 f917 bl 800084a
+ GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH;
+ 800061c: 2003 movs r0, #3
+ GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE;
+ 800061e: 2302 movs r3, #2
+ GPIO_InitStruct.Pin = LL_GPIO_PIN_10;
+ 8000620: 9605 str r6, [sp, #20]
+ LL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+ 8000622: ae05 add r6, sp, #20
+ 8000624: 0031 movs r1, r6
+ GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH;
+ 8000626: 9007 str r0, [sp, #28]
+ LL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+ 8000628: 0028 movs r0, r5
+ GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE;
+ 800062a: 9306 str r3, [sp, #24]
+ GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_OPENDRAIN;
+ 800062c: 9708 str r7, [sp, #32]
+ GPIO_InitStruct.Pull = LL_GPIO_PULL_UP;
+ 800062e: 9709 str r7, [sp, #36] ; 0x24
+ GPIO_InitStruct.Alternate = LL_GPIO_AF_1;
+ 8000630: 970a str r7, [sp, #40] ; 0x28
+ LL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+ 8000632: f000 f90a bl 800084a
+ LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_I2C1);
+ 8000636: 2080 movs r0, #128 ; 0x80
+ 8000638: 0380 lsls r0, r0, #14
+ 800063a: f7ff ff07 bl 800044c
+ * @param I2Cx I2C Instance.
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_EnableAutoEndMode(I2C_TypeDef *I2Cx)
+{
+ SET_BIT(I2Cx->CR2, I2C_CR2_AUTOEND);
+ 800063e: 2380 movs r3, #128 ; 0x80
+ 8000640: 4e50 ldr r6, [pc, #320] ; (8000784 )
+ 8000642: 049b lsls r3, r3, #18
+ 8000644: 6872 ldr r2, [r6, #4]
+ LL_I2C_Init(I2C1, &I2C_InitStruct);
+ 8000646: 0030 movs r0, r6
+ 8000648: 4313 orrs r3, r2
+ 800064a: 6073 str r3, [r6, #4]
+ CLEAR_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN);
+ 800064c: 68f3 ldr r3, [r6, #12]
+ 800064e: 4a4e ldr r2, [pc, #312] ; (8000788 )
+ 8000650: 4013 ands r3, r2
+ 8000652: 60f3 str r3, [r6, #12]
+ CLEAR_BIT(I2Cx->CR1, I2C_CR1_GCEN);
+ 8000654: 6833 ldr r3, [r6, #0]
+ 8000656: 4a4d ldr r2, [pc, #308] ; (800078c )
+ 8000658: 4013 ands r3, r2
+ 800065a: 6033 str r3, [r6, #0]
+ CLEAR_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH);
+ 800065c: 6833 ldr r3, [r6, #0]
+ 800065e: 4a4c ldr r2, [pc, #304] ; (8000790 )
+ 8000660: 4013 ands r3, r2
+ 8000662: 6033 str r3, [r6, #0]
+ I2C_InitStruct.Timing = 0x00000708;
+ 8000664: 23e1 movs r3, #225 ; 0xe1
+ LL_I2C_Init(I2C1, &I2C_InitStruct);
+ 8000666: aa0b add r2, sp, #44 ; 0x2c
+ 8000668: 0011 movs r1, r2
+ I2C_InitStruct.Timing = 0x00000708;
+ 800066a: 00db lsls r3, r3, #3
+ 800066c: 930c str r3, [sp, #48] ; 0x30
+ I2C_InitStruct.PeripheralMode = LL_I2C_MODE_I2C;
+ 800066e: 940b str r4, [sp, #44] ; 0x2c
+ I2C_InitStruct.AnalogFilter = LL_I2C_ANALOGFILTER_ENABLE;
+ 8000670: 940d str r4, [sp, #52] ; 0x34
+ I2C_InitStruct.DigitalFilter = 0;
+ 8000672: 940e str r4, [sp, #56] ; 0x38
+ I2C_InitStruct.OwnAddress1 = 0;
+ 8000674: 940f str r4, [sp, #60] ; 0x3c
+ I2C_InitStruct.TypeAcknowledge = LL_I2C_ACK;
+ 8000676: 9410 str r4, [sp, #64] ; 0x40
+ I2C_InitStruct.OwnAddrSize = LL_I2C_OWNADDRESS1_7BIT;
+ 8000678: 9411 str r4, [sp, #68] ; 0x44
+ LL_I2C_Init(I2C1, &I2C_InitStruct);
+ 800067a: f000 f937 bl 80008ec
+ MODIFY_REG(I2Cx->OAR2, I2C_OAR2_OA2 | I2C_OAR2_OA2MSK, OwnAddress2 | OwnAddrMask);
+ 800067e: 68f3 ldr r3, [r6, #12]
+ 8000680: 4a44 ldr r2, [pc, #272] ; (8000794 )
+ LL_LPUART_InitTypeDef LPUART_InitStruct = {0};
+ 8000682: 0021 movs r1, r4
+ 8000684: 4013 ands r3, r2
+ 8000686: 60f3 str r3, [r6, #12]
+ 8000688: 2218 movs r2, #24
+ 800068a: a805 add r0, sp, #20
+ 800068c: f000 faac bl 8000be8
+ LL_GPIO_InitTypeDef GPIO_InitStruct = {0};
+ 8000690: 2218 movs r2, #24
+ 8000692: 0021 movs r1, r4
+ 8000694: a80b add r0, sp, #44 ; 0x2c
+ 8000696: f000 faa7 bl 8000be8
+ LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_LPUART1);
+ 800069a: 2080 movs r0, #128 ; 0x80
+ 800069c: 02c0 lsls r0, r0, #11
+ 800069e: f7ff fed5 bl 800044c
+ LL_IOP_GRP1_EnableClock(LL_IOP_GRP1_PERIPH_GPIOA);
+ 80006a2: f7ff fee1 bl 8000468
+ GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH;
+ 80006a6: 2003 movs r0, #3
+ GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE;
+ 80006a8: 2302 movs r3, #2
+ GPIO_InitStruct.Alternate = LL_GPIO_AF_6;
+ 80006aa: 2206 movs r2, #6
+ GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH;
+ 80006ac: 900d str r0, [sp, #52] ; 0x34
+ LL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+ 80006ae: a90b add r1, sp, #44 ; 0x2c
+ 80006b0: 0028 movs r0, r5
+ GPIO_InitStruct.Pin = LL_GPIO_PIN_0;
+ 80006b2: 970b str r7, [sp, #44] ; 0x2c
+ GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE;
+ 80006b4: 930c str r3, [sp, #48] ; 0x30
+ GPIO_InitStruct.Pull = LL_GPIO_PULL_UP;
+ 80006b6: 970f str r7, [sp, #60] ; 0x3c
+ GPIO_InitStruct.Alternate = LL_GPIO_AF_6;
+ 80006b8: 9210 str r2, [sp, #64] ; 0x40
+ GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;
+ 80006ba: 940e str r4, [sp, #56] ; 0x38
+ LL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+ 80006bc: f000 f8c5 bl 800084a
+ GPIO_InitStruct.Alternate = LL_GPIO_AF_6;
+ 80006c0: 2206 movs r2, #6
+ GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH;
+ 80006c2: 2003 movs r0, #3
+ GPIO_InitStruct.Pin = LL_GPIO_PIN_1;
+ 80006c4: 2302 movs r3, #2
+ GPIO_InitStruct.Alternate = LL_GPIO_AF_6;
+ 80006c6: 9210 str r2, [sp, #64] ; 0x40
+ LL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+ 80006c8: aa0b add r2, sp, #44 ; 0x2c
+ 80006ca: 0011 movs r1, r2
+ GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH;
+ 80006cc: 900d str r0, [sp, #52] ; 0x34
+ LL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+ 80006ce: 0028 movs r0, r5
+ GPIO_InitStruct.Pin = LL_GPIO_PIN_1;
+ 80006d0: 930b str r3, [sp, #44] ; 0x2c
+ GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE;
+ 80006d2: 930c str r3, [sp, #48] ; 0x30
+ GPIO_InitStruct.Pull = LL_GPIO_PULL_UP;
+ 80006d4: 970f str r7, [sp, #60] ; 0x3c
+ GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;
+ 80006d6: 940e str r4, [sp, #56] ; 0x38
+ LL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+ 80006d8: f000 f8b7 bl 800084a
+ * @arg @ref LL_DMA_REQUEST_15
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Request)
+{
+ MODIFY_REG(((DMA_Request_TypeDef *)((uint32_t)((uint32_t)DMAx + DMA_CSELR_OFFSET)))->CSELR,
+ 80006dc: 492e ldr r1, [pc, #184] ; (8000798 )
+ 80006de: 4a2f ldr r2, [pc, #188] ; (800079c )
+ 80006e0: 680b ldr r3, [r1, #0]
+ MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PINC,
+ 80006e2: 2040 movs r0, #64 ; 0x40
+ MODIFY_REG(((DMA_Request_TypeDef *)((uint32_t)((uint32_t)DMAx + DMA_CSELR_OFFSET)))->CSELR,
+ 80006e4: 401a ands r2, r3
+ 80006e6: 23a0 movs r3, #160 ; 0xa0
+ 80006e8: 00db lsls r3, r3, #3
+ 80006ea: 4313 orrs r3, r2
+ 80006ec: 600b str r3, [r1, #0]
+ MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
+ 80006ee: 4b2c ldr r3, [pc, #176] ; (80007a0 )
+ 80006f0: 492c ldr r1, [pc, #176] ; (80007a4 )
+ 80006f2: 681a ldr r2, [r3, #0]
+ LL_LPUART_Init(LPUART1, &LPUART_InitStruct);
+ 80006f4: 4d2c ldr r5, [pc, #176] ; (80007a8 )
+ 80006f6: 400a ands r2, r1
+ 80006f8: 601a str r2, [r3, #0]
+ MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PL,
+ 80006fa: 681a ldr r2, [r3, #0]
+ 80006fc: 492b ldr r1, [pc, #172] ; (80007ac )
+ 80006fe: 4011 ands r1, r2
+ 8000700: 2280 movs r2, #128 ; 0x80
+ 8000702: 0152 lsls r2, r2, #5
+ 8000704: 430a orrs r2, r1
+ MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_CIRC,
+ 8000706: 2120 movs r1, #32
+ MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PL,
+ 8000708: 601a str r2, [r3, #0]
+ MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_CIRC,
+ 800070a: 681a ldr r2, [r3, #0]
+ 800070c: 438a bics r2, r1
+ 800070e: 430a orrs r2, r1
+ 8000710: 601a str r2, [r3, #0]
+ MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PINC,
+ 8000712: 681a ldr r2, [r3, #0]
+ MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MINC,
+ 8000714: 3160 adds r1, #96 ; 0x60
+ MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PINC,
+ 8000716: 4382 bics r2, r0
+ 8000718: 601a str r2, [r3, #0]
+ MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MINC,
+ 800071a: 681a ldr r2, [r3, #0]
+ 800071c: 0028 movs r0, r5
+ 800071e: 438a bics r2, r1
+ 8000720: 430a orrs r2, r1
+ 8000722: 601a str r2, [r3, #0]
+ MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PSIZE,
+ 8000724: 681a ldr r2, [r3, #0]
+ 8000726: 4922 ldr r1, [pc, #136] ; (80007b0 )
+ 8000728: 400a ands r2, r1
+ 800072a: 601a str r2, [r3, #0]
+ MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MSIZE,
+ 800072c: 681a ldr r2, [r3, #0]
+ 800072e: 4921 ldr r1, [pc, #132] ; (80007b4 )
+ 8000730: 400a ands r2, r1
+ 8000732: 601a str r2, [r3, #0]
+ LPUART_InitStruct.BaudRate = 115200;
+ 8000734: 23e1 movs r3, #225 ; 0xe1
+ 8000736: 025b lsls r3, r3, #9
+ 8000738: 9305 str r3, [sp, #20]
+ LPUART_InitStruct.TransferDirection = LL_LPUART_DIRECTION_TX_RX;
+ 800073a: 230c movs r3, #12
+ LL_LPUART_Init(LPUART1, &LPUART_InitStruct);
+ 800073c: a905 add r1, sp, #20
+ LPUART_InitStruct.TransferDirection = LL_LPUART_DIRECTION_TX_RX;
+ 800073e: 9309 str r3, [sp, #36] ; 0x24
+ LPUART_InitStruct.DataWidth = LL_LPUART_DATAWIDTH_8B;
+ 8000740: 9406 str r4, [sp, #24]
+ LPUART_InitStruct.StopBits = LL_LPUART_STOPBITS_1;
+ 8000742: 9407 str r4, [sp, #28]
+ LPUART_InitStruct.Parity = LL_LPUART_PARITY_NONE;
+ 8000744: 9408 str r4, [sp, #32]
+ LPUART_InitStruct.HardwareFlowControl = LL_LPUART_HWCONTROL_NONE;
+ 8000746: 940a str r4, [sp, #40] ; 0x28
+ LL_LPUART_Init(LPUART1, &LPUART_InitStruct);
+ 8000748: f000 f90a bl 8000960
+ SET_BIT(I2Cx->CR1, I2C_CR1_PE);
+ 800074c: 6833 ldr r3, [r6, #0]
+ 800074e: 433b orrs r3, r7
+ 8000750: 6033 str r3, [r6, #0]
+ * @param LPUARTx LPUART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_Enable(USART_TypeDef *LPUARTx)
+{
+ SET_BIT(LPUARTx->CR1, USART_CR1_UE);
+ 8000752: 682b ldr r3, [r5, #0]
+ 8000754: 4e0c ldr r6, [pc, #48] ; (8000788 )
+ 8000756: 433b orrs r3, r7
+ 8000758: 602b str r3, [r5, #0]
+ * @arg @ref LL_LPUART_DE_POLARITY_LOW
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_SetDESignalPolarity(USART_TypeDef *LPUARTx, uint32_t Polarity)
+{
+ MODIFY_REG(LPUARTx->CR3, USART_CR3_DEP, Polarity);
+ 800075a: 9701 str r7, [sp, #4]
+ LL_mDelay(1000);
+ 800075c: 27fa movs r7, #250 ; 0xfa
+ 800075e: 00bf lsls r7, r7, #2
+ 8000760: 68ab ldr r3, [r5, #8]
+ 8000762: 9a01 ldr r2, [sp, #4]
+ 8000764: 4033 ands r3, r6
+ 8000766: 4313 orrs r3, r2
+ 8000768: 60ab str r3, [r5, #8]
+ 800076a: 0038 movs r0, r7
+ * @param Value between Min_Data=0x00 and Max_Data=0xFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_TransmitData8(USART_TypeDef *LPUARTx, uint8_t Value)
+{
+ LPUARTx->TDR = Value;
+ 800076c: 62ac str r4, [r5, #40] ; 0x28
+ uart_data_dummy++;
+ 800076e: 3401 adds r4, #1
+ 8000770: b2e4 uxtb r4, r4
+ LL_mDelay(1000);
+ 8000772: f000 f9f9 bl 8000b68
+ while (1)
+ 8000776: e7f3 b.n 8000760
+ 8000778: 40021000 .word 0x40021000
+ 800077c: e000e100 .word 0xe000e100
+ 8000780: ff00ffff .word 0xff00ffff
+ 8000784: 40005400 .word 0x40005400
+ 8000788: ffff7fff .word 0xffff7fff
+ 800078c: fff7ffff .word 0xfff7ffff
+ 8000790: fffdffff .word 0xfffdffff
+ 8000794: fffff801 .word 0xfffff801
+ 8000798: 400200a8 .word 0x400200a8
+ 800079c: fffff0ff .word 0xfffff0ff
+ 80007a0: 40020030 .word 0x40020030
+ 80007a4: ffffbfef .word 0xffffbfef
+ 80007a8: 40004800 .word 0x40004800
+ 80007ac: ffffcfff .word 0xffffcfff
+ 80007b0: fffffcff .word 0xfffffcff
+ 80007b4: fffff3ff .word 0xfffff3ff
+
+080007b8 :
+{
+ /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
+
+ /* USER CODE END NonMaskableInt_IRQn 0 */
+ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
+ while (1)
+ 80007b8: e7fe b.n 80007b8
+
+080007ba :
+void HardFault_Handler(void)
+{
+ /* USER CODE BEGIN HardFault_IRQn 0 */
+
+ /* USER CODE END HardFault_IRQn 0 */
+ while (1)
+ 80007ba: e7fe b.n 80007ba
+
+080007bc :
+
+ /* USER CODE END SVC_IRQn 0 */
+ /* USER CODE BEGIN SVC_IRQn 1 */
+
+ /* USER CODE END SVC_IRQn 1 */
+}
+ 80007bc: 4770 bx lr
+
+080007be :
+ 80007be: 4770 bx lr
+
+080007c0 :
+ 80007c0: 4770 bx lr
+
+080007c2 :
+ 80007c2: 4770 bx lr
+
+080007c4 :
+{
+ /* Configure the Vector Table location add offset address ------------------*/
+#if defined (USER_VECT_TAB_ADDRESS)
+ SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+#endif /* USER_VECT_TAB_ADDRESS */
+}
+ 80007c4: 4770 bx lr
+ ...
+
+080007c8 :
+
+ .section .text.Reset_Handler
+ .weak Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+ ldr r0, =_estack
+ 80007c8: 4813 ldr r0, [pc, #76] ; (8000818 )
+ mov sp, r0 /* set stack pointer */
+ 80007ca: 4685 mov sp, r0
+
+/*Check if boot space corresponds to system memory*/
+
+ LDR R0,=0x00000004
+ 80007cc: 4813 ldr r0, [pc, #76] ; (800081c )
+ LDR R1, [R0]
+ 80007ce: 6801 ldr r1, [r0, #0]
+ LSRS R1, R1, #24
+ 80007d0: 0e09 lsrs r1, r1, #24
+ LDR R2,=0x1F
+ 80007d2: 4a13 ldr r2, [pc, #76] ; (8000820 )
+ CMP R1, R2
+ 80007d4: 4291 cmp r1, r2
+ BNE ApplicationStart
+ 80007d6: d105 bne.n 80007e4
+
+ /*SYSCFG clock enable*/
+ LDR R0,=0x40021034
+ 80007d8: 4812 ldr r0, [pc, #72] ; (8000824 )
+ LDR R1,=0x00000001
+ 80007da: 4913 ldr r1, [pc, #76] ; (8000828 )
+ STR R1, [R0]
+ 80007dc: 6001 str r1, [r0, #0]
+
+/*Set CFGR1 register with flash memory remap at address 0*/
+ LDR R0,=0x40010000
+ 80007de: 4813 ldr r0, [pc, #76] ; (800082c )
+ LDR R1,=0x00000000
+ 80007e0: 4913 ldr r1, [pc, #76] ; (8000830 )
+ STR R1, [R0]
+ 80007e2: 6001 str r1, [r0, #0]
+
+080007e4 :
+
+ApplicationStart:
+/* Copy the data segment initializers from flash to SRAM */
+ ldr r0, =_sdata
+ 80007e4: 4813 ldr r0, [pc, #76] ; (8000834 )
+ ldr r1, =_edata
+ 80007e6: 4914 ldr r1, [pc, #80] ; (8000838 )
+ ldr r2, =_sidata
+ 80007e8: 4a14 ldr r2, [pc, #80] ; (800083c )
+ movs r3, #0
+ 80007ea: 2300 movs r3, #0
+ b LoopCopyDataInit
+ 80007ec: e002 b.n 80007f4
+
+080007ee :
+
+CopyDataInit:
+ ldr r4, [r2, r3]
+ 80007ee: 58d4 ldr r4, [r2, r3]
+ str r4, [r0, r3]
+ 80007f0: 50c4 str r4, [r0, r3]
+ adds r3, r3, #4
+ 80007f2: 3304 adds r3, #4
+
+080007f4 :
+
+LoopCopyDataInit:
+ adds r4, r0, r3
+ 80007f4: 18c4 adds r4, r0, r3
+ cmp r4, r1
+ 80007f6: 428c cmp r4, r1
+ bcc CopyDataInit
+ 80007f8: d3f9 bcc.n 80007ee
+
+/* Zero fill the bss segment. */
+ ldr r2, =_sbss
+ 80007fa: 4a11 ldr r2, [pc, #68] ; (8000840 )
+ ldr r4, =_ebss
+ 80007fc: 4c11 ldr r4, [pc, #68] ; (8000844 )
+ movs r3, #0
+ 80007fe: 2300 movs r3, #0
+ b LoopFillZerobss
+ 8000800: e001 b.n 8000806
+
+08000802 :
+
+FillZerobss:
+ str r3, [r2]
+ 8000802: 6013 str r3, [r2, #0]
+ adds r2, r2, #4
+ 8000804: 3204 adds r2, #4
+
+08000806 :
+
+LoopFillZerobss:
+ cmp r2, r4
+ 8000806: 42a2 cmp r2, r4
+ bcc FillZerobss
+ 8000808: d3fb bcc.n 8000802
+
+/* Call the clock system intitialization function.*/
+ bl SystemInit
+ 800080a: f7ff ffdb bl 80007c4
+/* Call static constructors */
+ bl __libc_init_array
+ 800080e: f000 f9c7 bl 8000ba0 <__libc_init_array>
+/* Call the application's entry point.*/
+ bl main
+ 8000812: f7ff fe95 bl 8000540
+
+08000816 :
+
+LoopForever:
+ b LoopForever
+ 8000816: e7fe b.n 8000816
+ ldr r0, =_estack
+ 8000818: 20000800 .word 0x20000800
+ LDR R0,=0x00000004
+ 800081c: 00000004 .word 0x00000004
+ LDR R2,=0x1F
+ 8000820: 0000001f .word 0x0000001f
+ LDR R0,=0x40021034
+ 8000824: 40021034 .word 0x40021034
+ LDR R1,=0x00000001
+ 8000828: 00000001 .word 0x00000001
+ LDR R0,=0x40010000
+ 800082c: 40010000 .word 0x40010000
+ LDR R1,=0x00000000
+ 8000830: 00000000 .word 0x00000000
+ ldr r0, =_sdata
+ 8000834: 20000000 .word 0x20000000
+ ldr r1, =_edata
+ 8000838: 20000004 .word 0x20000004
+ ldr r2, =_sidata
+ 800083c: 08000c44 .word 0x08000c44
+ ldr r2, =_sbss
+ 8000840: 20000004 .word 0x20000004
+ ldr r4, =_ebss
+ 8000844: 20000020 .word 0x20000020
+
+08000848 :
+ * @retval : None
+*/
+ .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+ b Infinite_Loop
+ 8000848: e7fe b.n 8000848
+
+0800084a :
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: GPIO registers are initialized according to GPIO_InitStruct content
+ * - ERROR: Not applicable
+ */
+ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct)
+{
+ 800084a: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr}
+ uint32_t pinpos = 0x00000000U;
+ 800084c: 2300 movs r3, #0
+{
+ 800084e: 0002 movs r2, r0
+ /* ------------------------- Configure the port pins ---------------- */
+ /* Initialize pinpos on first pin set */
+ /* pinpos = 0; useless as already done in default initialization */
+
+ /* Configure the port pins */
+ while (((GPIO_InitStruct->Pin) >> pinpos) != 0x00000000U)
+ 8000850: 680c ldr r4, [r1, #0]
+ }
+
+ /* Pin Mode configuration */
+ LL_GPIO_SetPinMode(GPIOx, currentpin, GPIO_InitStruct->Mode);
+ }
+ pinpos++;
+ 8000852: 9300 str r3, [sp, #0]
+ while (((GPIO_InitStruct->Pin) >> pinpos) != 0x00000000U)
+ 8000854: 0020 movs r0, r4
+ 8000856: 9b00 ldr r3, [sp, #0]
+ 8000858: 40d8 lsrs r0, r3
+ 800085a: d100 bne.n 800085e
+ }
+
+
+ return (SUCCESS);
+}
+ 800085c: bdfe pop {r1, r2, r3, r4, r5, r6, r7, pc}
+ currentpin = (GPIO_InitStruct->Pin) & (0x00000001U << pinpos);
+ 800085e: 2001 movs r0, #1
+ 8000860: 9b00 ldr r3, [sp, #0]
+ 8000862: 4098 lsls r0, r3
+ 8000864: 0023 movs r3, r4
+ 8000866: 4003 ands r3, r0
+ if (currentpin)
+ 8000868: 4204 tst r4, r0
+ 800086a: d031 beq.n 80008d0
+ if ((GPIO_InitStruct->Mode == LL_GPIO_MODE_OUTPUT) || (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE))
+ 800086c: 6848 ldr r0, [r1, #4]
+ 800086e: 2503 movs r5, #3
+ 8000870: 9001 str r0, [sp, #4]
+ 8000872: 0018 movs r0, r3
+ 8000874: 4358 muls r0, r3
+ 8000876: 4345 muls r5, r0
+ 8000878: 9e01 ldr r6, [sp, #4]
+ 800087a: 43ed mvns r5, r5
+ 800087c: 1e77 subs r7, r6, #1
+ 800087e: 2f01 cmp r7, #1
+ 8000880: d80b bhi.n 800089a
+ MODIFY_REG(GPIOx->OSPEEDR, ((Pin * Pin) * GPIO_OSPEEDER_OSPEED0), ((Pin * Pin) * Speed));
+ 8000882: 688f ldr r7, [r1, #8]
+ 8000884: 6896 ldr r6, [r2, #8]
+ 8000886: 4347 muls r7, r0
+ 8000888: 402e ands r6, r5
+ 800088a: 4337 orrs r7, r6
+ 800088c: 6097 str r7, [r2, #8]
+ MODIFY_REG(GPIOx->OTYPER, PinMask, (PinMask * OutputType));
+ 800088e: 6857 ldr r7, [r2, #4]
+ 8000890: 68ce ldr r6, [r1, #12]
+ 8000892: 43a7 bics r7, r4
+ 8000894: 4374 muls r4, r6
+ 8000896: 433c orrs r4, r7
+ 8000898: 6054 str r4, [r2, #4]
+ MODIFY_REG(GPIOx->PUPDR, ((Pin * Pin) * GPIO_PUPDR_PUPD0), ((Pin * Pin) * Pull));
+ 800089a: 690c ldr r4, [r1, #16]
+ 800089c: 68d7 ldr r7, [r2, #12]
+ 800089e: 4344 muls r4, r0
+ 80008a0: 402f ands r7, r5
+ 80008a2: 433c orrs r4, r7
+ 80008a4: 60d4 str r4, [r2, #12]
+ if (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE)
+ 80008a6: 9c01 ldr r4, [sp, #4]
+ 80008a8: 2c02 cmp r4, #2
+ 80008aa: d10b bne.n 80008c4
+ if (currentpin < LL_GPIO_PIN_8)
+ 80008ac: 694f ldr r7, [r1, #20]
+ 80008ae: 2bff cmp r3, #255 ; 0xff
+ 80008b0: d811 bhi.n 80008d6
+ MODIFY_REG(GPIOx->AFR[0], ((((Pin * Pin) * Pin) * Pin) * GPIO_AFRL_AFSEL0),
+ 80008b2: 0003 movs r3, r0
+ 80008b4: 260f movs r6, #15
+ 80008b6: 4343 muls r3, r0
+ 80008b8: 435e muls r6, r3
+ 80008ba: 437b muls r3, r7
+ 80008bc: 6a14 ldr r4, [r2, #32]
+ 80008be: 43b4 bics r4, r6
+ 80008c0: 431c orrs r4, r3
+ 80008c2: 6214 str r4, [r2, #32]
+ MODIFY_REG(GPIOx->MODER, ((Pin * Pin) * GPIO_MODER_MODE0), ((Pin * Pin) * Mode));
+ 80008c4: 6813 ldr r3, [r2, #0]
+ 80008c6: 401d ands r5, r3
+ 80008c8: 9b01 ldr r3, [sp, #4]
+ 80008ca: 4358 muls r0, r3
+ 80008cc: 4305 orrs r5, r0
+ 80008ce: 6015 str r5, [r2, #0]
+ pinpos++;
+ 80008d0: 9b00 ldr r3, [sp, #0]
+ 80008d2: 3301 adds r3, #1
+ 80008d4: e7bc b.n 8000850
+ MODIFY_REG(GPIOx->AFR[1], (((((Pin >> 8U) * (Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U)) * GPIO_AFRH_AFSEL8),
+ 80008d6: 260f movs r6, #15
+ 80008d8: 0a1b lsrs r3, r3, #8
+ 80008da: 435b muls r3, r3
+ 80008dc: 435b muls r3, r3
+ 80008de: 435e muls r6, r3
+ 80008e0: 437b muls r3, r7
+ 80008e2: 6a54 ldr r4, [r2, #36] ; 0x24
+ 80008e4: 43b4 bics r4, r6
+ 80008e6: 431c orrs r4, r3
+ 80008e8: 6254 str r4, [r2, #36] ; 0x24
+}
+ 80008ea: e7eb b.n 80008c4
+
+080008ec :
+ CLEAR_BIT(I2Cx->CR1, I2C_CR1_PE);
+ 80008ec: 2201 movs r2, #1
+ 80008ee: 6803 ldr r3, [r0, #0]
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: I2C registers are initialized
+ * - ERROR: Not applicable
+ */
+ErrorStatus LL_I2C_Init(I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct)
+{
+ 80008f0: b530 push {r4, r5, lr}
+ 80008f2: 4393 bics r3, r2
+ 80008f4: 6003 str r3, [r0, #0]
+ MODIFY_REG(I2Cx->CR1, I2C_CR1_ANFOFF | I2C_CR1_DNF, AnalogFilter | (DigitalFilter << I2C_CR1_DNF_Pos));
+ 80008f6: 68cb ldr r3, [r1, #12]
+ 80008f8: 688d ldr r5, [r1, #8]
+ 80008fa: 021b lsls r3, r3, #8
+ 80008fc: 6804 ldr r4, [r0, #0]
+ 80008fe: 432b orrs r3, r5
+ 8000900: 4d14 ldr r5, [pc, #80] ; (8000954 )
+ 8000902: 402c ands r4, r5
+ 8000904: 4323 orrs r3, r4
+ 8000906: 6003 str r3, [r0, #0]
+ WRITE_REG(I2Cx->TIMINGR, Timing);
+ 8000908: 684b ldr r3, [r1, #4]
+ * Disable, Configure and Enable I2Cx device own address 1 with parameters :
+ * - OwnAddress1: I2C_OAR1_OA1[9:0] bits
+ * - OwnAddrSize: I2C_OAR1_OA1MODE bit
+ */
+ LL_I2C_DisableOwnAddress1(I2Cx);
+ LL_I2C_SetOwnAddress1(I2Cx, I2C_InitStruct->OwnAddress1, I2C_InitStruct->OwnAddrSize);
+ 800090a: 690d ldr r5, [r1, #16]
+ 800090c: 6103 str r3, [r0, #16]
+ SET_BIT(I2Cx->CR1, I2C_CR1_PE);
+ 800090e: 6803 ldr r3, [r0, #0]
+ 8000910: 431a orrs r2, r3
+ 8000912: 6002 str r2, [r0, #0]
+ CLEAR_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN);
+ 8000914: 6882 ldr r2, [r0, #8]
+ 8000916: 4b10 ldr r3, [pc, #64] ; (8000958 )
+ 8000918: 401a ands r2, r3
+ 800091a: 6082 str r2, [r0, #8]
+ MODIFY_REG(I2Cx->OAR1, I2C_OAR1_OA1 | I2C_OAR1_OA1MODE, OwnAddress1 | OwnAddrSize);
+ 800091c: 6884 ldr r4, [r0, #8]
+ 800091e: 698a ldr r2, [r1, #24]
+ 8000920: 0ae4 lsrs r4, r4, #11
+ 8000922: 02e4 lsls r4, r4, #11
+ 8000924: 432a orrs r2, r5
+ 8000926: 4322 orrs r2, r4
+ 8000928: 6082 str r2, [r0, #8]
+
+ /* OwnAdress1 == 0 is reserved for General Call address */
+ if (I2C_InitStruct->OwnAddress1 != 0U)
+ 800092a: 001c movs r4, r3
+ 800092c: 2d00 cmp r5, #0
+ 800092e: d004 beq.n 800093a
+ SET_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN);
+ 8000930: 2380 movs r3, #128 ; 0x80
+ 8000932: 6882 ldr r2, [r0, #8]
+ 8000934: 021b lsls r3, r3, #8
+ 8000936: 4313 orrs r3, r2
+ 8000938: 6083 str r3, [r0, #8]
+ MODIFY_REG(I2Cx->CR1, I2C_CR1_SMBHEN | I2C_CR1_SMBDEN, PeripheralMode);
+ 800093a: 6802 ldr r2, [r0, #0]
+ 800093c: 4b07 ldr r3, [pc, #28] ; (800095c )
+ 800093e: 401a ands r2, r3
+ 8000940: 680b ldr r3, [r1, #0]
+ 8000942: 431a orrs r2, r3
+ 8000944: 6002 str r2, [r0, #0]
+ * @arg @ref LL_I2C_NACK
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_AcknowledgeNextData(I2C_TypeDef *I2Cx, uint32_t TypeAcknowledge)
+{
+ MODIFY_REG(I2Cx->CR2, I2C_CR2_NACK, TypeAcknowledge);
+ 8000946: 6843 ldr r3, [r0, #4]
+ 8000948: 694a ldr r2, [r1, #20]
+ 800094a: 4023 ands r3, r4
+ 800094c: 4313 orrs r3, r2
+ 800094e: 6043 str r3, [r0, #4]
+ * - TypeAcknowledge: I2C_CR2_NACK bit
+ */
+ LL_I2C_AcknowledgeNextData(I2Cx, I2C_InitStruct->TypeAcknowledge);
+
+ return SUCCESS;
+}
+ 8000950: 2000 movs r0, #0
+ 8000952: bd30 pop {r4, r5, pc}
+ 8000954: ffffe0ff .word 0xffffe0ff
+ 8000958: ffff7fff .word 0xffff7fff
+ 800095c: ffcfffff .word 0xffcfffff
+
+08000960 :
+ return ((READ_BIT(LPUARTx->CR1, USART_CR1_UE) == (USART_CR1_UE)) ? 1UL : 0UL);
+ 8000960: 6802 ldr r2, [r0, #0]
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: LPUART registers are initialized according to LPUART_InitStruct content
+ * - ERROR: Problem occurred during LPUART Registers initialization
+ */
+ErrorStatus LL_LPUART_Init(USART_TypeDef *LPUARTx, LL_LPUART_InitTypeDef *LPUART_InitStruct)
+{
+ 8000962: b5f8 push {r3, r4, r5, r6, r7, lr}
+ 8000964: 2301 movs r3, #1
+ 8000966: 0015 movs r5, r2
+ 8000968: 0004 movs r4, r0
+ 800096a: 000e movs r6, r1
+ 800096c: 401d ands r5, r3
+ assert_param(IS_LL_LPUART_DIRECTION(LPUART_InitStruct->TransferDirection));
+ assert_param(IS_LL_LPUART_HWCONTROL(LPUART_InitStruct->HardwareFlowControl));
+
+ /* LPUART needs to be in disabled state, in order to be able to configure some bits in
+ CRx registers. Otherwise (LPUART not in Disabled state) => return ERROR */
+ if (LL_LPUART_IsEnabled(LPUARTx) == 0U)
+ 800096e: 421a tst r2, r3
+ 8000970: d001 beq.n 8000976
+ ErrorStatus status = ERROR;
+ 8000972: 2001 movs r0, #1
+ }
+
+ }
+
+ return (status);
+}
+ 8000974: bdf8 pop {r3, r4, r5, r6, r7, pc}
+ MODIFY_REG(LPUARTx->CR1,
+ 8000976: 684b ldr r3, [r1, #4]
+ 8000978: 68c9 ldr r1, [r1, #12]
+ 800097a: 6802 ldr r2, [r0, #0]
+ 800097c: 430b orrs r3, r1
+ 800097e: 6931 ldr r1, [r6, #16]
+ 8000980: 430b orrs r3, r1
+ 8000982: 4913 ldr r1, [pc, #76] ; (80009d0 )
+ 8000984: 400a ands r2, r1
+ 8000986: 4313 orrs r3, r2
+ 8000988: 6003 str r3, [r0, #0]
+ MODIFY_REG(LPUARTx->CR2, USART_CR2_STOP, StopBits);
+ 800098a: 6843 ldr r3, [r0, #4]
+ 800098c: 4a11 ldr r2, [pc, #68] ; (80009d4 )
+ 800098e: 4013 ands r3, r2
+ 8000990: 68b2 ldr r2, [r6, #8]
+ 8000992: 4313 orrs r3, r2
+ 8000994: 6043 str r3, [r0, #4]
+ MODIFY_REG(LPUARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE, HardwareFlowControl);
+ 8000996: 6883 ldr r3, [r0, #8]
+ 8000998: 4a0f ldr r2, [pc, #60] ; (80009d8 )
+ 800099a: 4013 ands r3, r2
+ 800099c: 6972 ldr r2, [r6, #20]
+ 800099e: 4313 orrs r3, r2
+ 80009a0: 6083 str r3, [r0, #8]
+ periphclk = LL_RCC_GetLPUARTClockFreq(LL_RCC_LPUART1_CLKSOURCE);
+ 80009a2: 20c0 movs r0, #192 ; 0xc0
+ 80009a4: 0100 lsls r0, r0, #4
+ 80009a6: f000 f899 bl 8000adc
+ if ((periphclk != LL_RCC_PERIPH_FREQUENCY_NO)
+ 80009aa: 2800 cmp r0, #0
+ 80009ac: d0e1 beq.n 8000972
+ && (LPUART_InitStruct->BaudRate != 0U))
+ 80009ae: 6832 ldr r2, [r6, #0]
+ 80009b0: 2a00 cmp r2, #0
+ 80009b2: d0de beq.n 8000972
+ LPUARTx->BRR = __LL_LPUART_DIV(PeriphClk, BaudRate);
+ 80009b4: 0029 movs r1, r5
+ 80009b6: 0e07 lsrs r7, r0, #24
+ 80009b8: 0206 lsls r6, r0, #8
+ 80009ba: 0850 lsrs r0, r2, #1
+ 80009bc: 1980 adds r0, r0, r6
+ 80009be: 4179 adcs r1, r7
+ 80009c0: 002b movs r3, r5
+ 80009c2: f7ff fc2d bl 8000220 <__aeabi_uldivmod>
+ 80009c6: 0300 lsls r0, r0, #12
+ 80009c8: 0b00 lsrs r0, r0, #12
+ 80009ca: 60e0 str r0, [r4, #12]
+ status = SUCCESS;
+ 80009cc: 0028 movs r0, r5
+}
+ 80009ce: e7d1 b.n 8000974
+ 80009d0: efffe9f3 .word 0xefffe9f3
+ 80009d4: ffffcfff .word 0xffffcfff
+ 80009d8: fffffcff .word 0xfffffcff
+
+080009dc :
+ return ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) == RCC_CR_HSIRDY) ? 1UL : 0UL);
+ 80009dc: 4b02 ldr r3, [pc, #8] ; (80009e8 )
+ 80009de: 6818 ldr r0, [r3, #0]
+ 80009e0: 0740 lsls r0, r0, #29
+ 80009e2: 0fc0 lsrs r0, r0, #31
+}
+ 80009e4: 4770 bx lr
+ 80009e6: 46c0 nop ; (mov r8, r8)
+ 80009e8: 40021000 .word 0x40021000
+
+080009ec :
+ * @rmtoll CR HSIDIVF LL_RCC_IsActiveFlag_HSIDIV
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIDIV(void)
+{
+ return ((READ_BIT(RCC->CR, RCC_CR_HSIDIVF) == RCC_CR_HSIDIVF) ? 1UL : 0UL);
+ 80009ec: 4b02 ldr r3, [pc, #8] ; (80009f8 )
+ 80009ee: 6818 ldr r0, [r3, #0]
+ 80009f0: 06c0 lsls r0, r0, #27
+ 80009f2: 0fc0 lsrs r0, r0, #31
+}
+ 80009f4: 4770 bx lr
+ 80009f6: 46c0 nop ; (mov r8, r8)
+ 80009f8: 40021000 .word 0x40021000
+
+080009fc :
+ return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE));
+ 80009fc: 4b03 ldr r3, [pc, #12] ; (8000a0c )
+ * @retval HCLK clock frequency (in Hz)
+ */
+uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency)
+{
+ /* HCLK clock frequency */
+ return __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, LL_RCC_GetAHBPrescaler());
+ 80009fe: 4a04 ldr r2, [pc, #16] ; (8000a10 )
+ 8000a00: 68db ldr r3, [r3, #12]
+ 8000a02: 061b lsls r3, r3, #24
+ 8000a04: 0f1b lsrs r3, r3, #28
+ 8000a06: 5cd3 ldrb r3, [r2, r3]
+ 8000a08: 40d8 lsrs r0, r3
+}
+ 8000a0a: 4770 bx lr
+ 8000a0c: 40021000 .word 0x40021000
+ 8000a10: 08000c10 .word 0x08000c10
+
+08000a14 :
+ return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1));
+ 8000a14: 4b03 ldr r3, [pc, #12] ; (8000a24 )
+ * @retval PCLK1 clock frequency (in Hz)
+ */
+uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency)
+{
+ /* PCLK1 clock frequency */
+ return __LL_RCC_CALC_PCLK1_FREQ(HCLK_Frequency, LL_RCC_GetAPB1Prescaler());
+ 8000a16: 4a04 ldr r2, [pc, #16] ; (8000a28 )
+ 8000a18: 68db ldr r3, [r3, #12]
+ 8000a1a: 055b lsls r3, r3, #21
+ 8000a1c: 0f5b lsrs r3, r3, #29
+ 8000a1e: 5cd3 ldrb r3, [r2, r3]
+ 8000a20: 40d8 lsrs r0, r3
+}
+ 8000a22: 4770 bx lr
+ 8000a24: 40021000 .word 0x40021000
+ 8000a28: 08000c20 .word 0x08000c20
+
+08000a2c :
+/**
+ * @brief Return PLL clock frequency used for system domain
+ * @retval PLL clock frequency (in Hz)
+ */
+uint32_t RCC_PLL_GetFreqDomain_SYS(void)
+{
+ 8000a2c: b510 push {r4, lr}
+ return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC));
+ 8000a2e: 4c0e ldr r4, [pc, #56] ; (8000a68 )
+ 8000a30: 68e3 ldr r3, [r4, #12]
+ /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL divider) * PLL Multiplicator */
+
+ /* Get PLL source */
+ pllsource = LL_RCC_PLL_GetMainSource();
+
+ switch (pllsource)
+ 8000a32: 03db lsls r3, r3, #15
+ 8000a34: d415 bmi.n 8000a62
+ {
+ case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
+ if (LL_RCC_IsActiveFlag_HSIDIV() != 0U)
+ 8000a36: f7ff ffd9 bl 80009ec
+ {
+ pllinputfreq = (HSI_VALUE >> 2U);
+ }
+ else
+ {
+ pllinputfreq = HSI_VALUE;
+ 8000a3a: 1e43 subs r3, r0, #1
+ 8000a3c: 4198 sbcs r0, r3
+ 8000a3e: 4b0b ldr r3, [pc, #44] ; (8000a6c )
+ 8000a40: 4240 negs r0, r0
+ 8000a42: 4018 ands r0, r3
+ 8000a44: 4b0a ldr r3, [pc, #40] ; (8000a70 )
+ 8000a46: 18c0 adds r0, r0, r3
+ return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLMUL));
+ 8000a48: 68e3 ldr r3, [r4, #12]
+
+ default: /* HSE used as PLL clock source */
+ pllinputfreq = HSE_VALUE;
+ break;
+ }
+ return __LL_RCC_CALC_PLLCLK_FREQ(pllinputfreq, LL_RCC_PLL_GetMultiplicator(), LL_RCC_PLL_GetDivider());
+ 8000a4a: 4a0a ldr r2, [pc, #40] ; (8000a74 )
+ return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLDIV));
+ 8000a4c: 68e1 ldr r1, [r4, #12]
+ 8000a4e: 029b lsls r3, r3, #10
+ 8000a50: 0f1b lsrs r3, r3, #28
+ 8000a52: 5cd3 ldrb r3, [r2, r3]
+ 8000a54: 0209 lsls r1, r1, #8
+ 8000a56: 0f89 lsrs r1, r1, #30
+ 8000a58: 4358 muls r0, r3
+ 8000a5a: 3101 adds r1, #1
+ 8000a5c: f7ff fb54 bl 8000108 <__udivsi3>
+}
+ 8000a60: bd10 pop {r4, pc}
+ pllinputfreq = HSE_VALUE;
+ 8000a62: 4805 ldr r0, [pc, #20] ; (8000a78 )
+ 8000a64: e7f0 b.n 8000a48
+ 8000a66: 46c0 nop ; (mov r8, r8)
+ 8000a68: 40021000 .word 0x40021000
+ 8000a6c: ff48e500 .word 0xff48e500
+ 8000a70: 00f42400 .word 0x00f42400
+ 8000a74: 08000c28 .word 0x08000c28
+ 8000a78: 007a1200 .word 0x007a1200
+
+08000a7c :
+ return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS));
+ 8000a7c: 210c movs r1, #12
+ 8000a7e: 4a13 ldr r2, [pc, #76] ; (8000acc )
+{
+ 8000a80: b510 push {r4, lr}
+ 8000a82: 68d3 ldr r3, [r2, #12]
+ 8000a84: 400b ands r3, r1
+ 8000a86: 0011 movs r1, r2
+ switch (LL_RCC_GetSysClkSource())
+ 8000a88: 2b08 cmp r3, #8
+ 8000a8a: d01d beq.n 8000ac8
+ 8000a8c: d805 bhi.n 8000a9a
+ 8000a8e: 2b00 cmp r3, #0
+ 8000a90: d008 beq.n 8000aa4
+ 8000a92: 2b04 cmp r3, #4
+ 8000a94: d00e beq.n 8000ab4
+ return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_MSIRANGE));
+ 8000a96: 684b ldr r3, [r1, #4]
+ 8000a98: e005 b.n 8000aa6
+ 8000a9a: 2b0c cmp r3, #12
+ 8000a9c: d1fb bne.n 8000a96
+ frequency = RCC_PLL_GetFreqDomain_SYS();
+ 8000a9e: f7ff ffc5 bl 8000a2c
+ break;
+ 8000aa2: e010 b.n 8000ac6
+ 8000aa4: 6853 ldr r3, [r2, #4]
+ frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_GetRange());
+ 8000aa6: 2080 movs r0, #128 ; 0x80
+ 8000aa8: 041b lsls r3, r3, #16
+ 8000aaa: 0f5b lsrs r3, r3, #29
+ 8000aac: 3301 adds r3, #1
+ 8000aae: 0200 lsls r0, r0, #8
+ 8000ab0: 4098 lsls r0, r3
+ return frequency;
+ 8000ab2: e008 b.n 8000ac6
+ if (LL_RCC_IsActiveFlag_HSIDIV() != 0U)
+ 8000ab4: f7ff ff9a bl 80009ec
+ frequency = HSI_VALUE;
+ 8000ab8: 1e43 subs r3, r0, #1
+ 8000aba: 4198 sbcs r0, r3
+ 8000abc: 4b04 ldr r3, [pc, #16] ; (8000ad0 )
+ 8000abe: 4240 negs r0, r0
+ 8000ac0: 4018 ands r0, r3
+ 8000ac2: 4b04 ldr r3, [pc, #16] ; (8000ad4 )
+ 8000ac4: 18c0 adds r0, r0, r3
+}
+ 8000ac6: bd10 pop {r4, pc}
+ switch (LL_RCC_GetSysClkSource())
+ 8000ac8: 4803 ldr r0, [pc, #12] ; (8000ad8 )
+ 8000aca: e7fc b.n 8000ac6
+ 8000acc: 40021000 .word 0x40021000
+ 8000ad0: ff48e500 .word 0xff48e500
+ 8000ad4: 00f42400 .word 0x00f42400
+ 8000ad8: 007a1200 .word 0x007a1200
+
+08000adc :
+ return (uint32_t)(READ_BIT(RCC->CCIPR, LPUARTx));
+ 8000adc: 4a17 ldr r2, [pc, #92] ; (8000b3c )
+{
+ 8000ade: b510 push {r4, lr}
+ 8000ae0: 6cd3 ldr r3, [r2, #76] ; 0x4c
+ 8000ae2: 4018 ands r0, r3
+ switch (LL_RCC_GetLPUARTClockSource(LPUARTxSource))
+ 8000ae4: 2380 movs r3, #128 ; 0x80
+ 8000ae6: 011b lsls r3, r3, #4
+ 8000ae8: 4298 cmp r0, r3
+ 8000aea: d00a beq.n 8000b02
+ 8000aec: 23c0 movs r3, #192 ; 0xc0
+ 8000aee: 011b lsls r3, r3, #4
+ 8000af0: 4298 cmp r0, r3
+ 8000af2: d014 beq.n 8000b1e
+ 8000af4: 2380 movs r3, #128 ; 0x80
+ 8000af6: 00db lsls r3, r3, #3
+ 8000af8: 4298 cmp r0, r3
+ 8000afa: d115 bne.n 8000b28
+ lpuart_frequency = RCC_GetSystemClockFreq();
+ 8000afc: f7ff ffbe bl 8000a7c
+}
+ 8000b00: bd10 pop {r4, pc}
+ if (LL_RCC_HSI_IsReady() != 0U)
+ 8000b02: f7ff ff6b bl 80009dc
+ 8000b06: 2800 cmp r0, #0
+ 8000b08: d00c beq.n 8000b24
+ if (LL_RCC_IsActiveFlag_HSIDIV() != 0U)
+ 8000b0a: f7ff ff6f bl 80009ec
+ lpuart_frequency = HSI_VALUE;
+ 8000b0e: 1e43 subs r3, r0, #1
+ 8000b10: 4198 sbcs r0, r3
+ 8000b12: 4b0b ldr r3, [pc, #44] ; (8000b40 )
+ 8000b14: 4240 negs r0, r0
+ 8000b16: 4018 ands r0, r3
+ 8000b18: 4b0a ldr r3, [pc, #40] ; (8000b44 )
+ 8000b1a: 18c0 adds r0, r0, r3
+ 8000b1c: e7f0 b.n 8000b00
+ return ((READ_BIT(RCC->CSR, RCC_CSR_LSERDY) == RCC_CSR_LSERDY) ? 1UL : 0UL);
+ 8000b1e: 6d13 ldr r3, [r2, #80] ; 0x50
+ 8000b20: 059b lsls r3, r3, #22
+ 8000b22: d408 bmi.n 8000b36
+ uint32_t lpuart_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+ 8000b24: 2000 movs r0, #0
+ 8000b26: e7eb b.n 8000b00
+ lpuart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
+ 8000b28: f7ff ffa8 bl 8000a7c
+ 8000b2c: f7ff ff66 bl 80009fc
+ 8000b30: f7ff ff70 bl 8000a14
+ break;
+ 8000b34: e7e4 b.n 8000b00
+ lpuart_frequency = LSE_VALUE;
+ 8000b36: 2080 movs r0, #128 ; 0x80
+ 8000b38: 0200 lsls r0, r0, #8
+ return lpuart_frequency;
+ 8000b3a: e7e1 b.n 8000b00
+ 8000b3c: 40021000 .word 0x40021000
+ 8000b40: ff48e500 .word 0xff48e500
+ 8000b44: 00f42400 .word 0x00f42400
+
+08000b48 :
+ * @retval None
+ */
+__STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks)
+{
+ /* Configure the SysTick to have interrupt in 1ms time base */
+ SysTick->LOAD = (uint32_t)((HCLKFrequency / Ticks) - 1UL); /* set reload register */
+ 8000b48: 21fa movs r1, #250 ; 0xfa
+ * @param HCLKFrequency HCLK frequency in Hz
+ * @note HCLK frequency can be calculated thanks to RCC helper macro or function @ref LL_RCC_GetSystemClocksFreq
+ * @retval None
+ */
+void LL_Init1msTick(uint32_t HCLKFrequency)
+{
+ 8000b4a: b510 push {r4, lr}
+ 8000b4c: 0089 lsls r1, r1, #2
+ 8000b4e: f7ff fadb bl 8000108 <__udivsi3>
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ 8000b52: 2200 movs r2, #0
+ SysTick->LOAD = (uint32_t)((HCLKFrequency / Ticks) - 1UL); /* set reload register */
+ 8000b54: 4b03 ldr r3, [pc, #12] ; (8000b64 )
+ 8000b56: 3801 subs r0, #1
+ 8000b58: 6058 str r0, [r3, #4]
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ 8000b5a: 609a str r2, [r3, #8]
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ 8000b5c: 3205 adds r2, #5
+ 8000b5e: 601a str r2, [r3, #0]
+ /* Use frequency provided in argument */
+ LL_InitTick(HCLKFrequency, 1000U);
+}
+ 8000b60: bd10 pop {r4, pc}
+ 8000b62: 46c0 nop ; (mov r8, r8)
+ 8000b64: e000e010 .word 0xe000e010
+
+08000b68 :
+ * @param Delay specifies the delay time length, in milliseconds.
+ * @retval None
+ */
+void LL_mDelay(uint32_t Delay)
+{
+ __IO uint32_t tmp = SysTick->CTRL; /* Clear the COUNTFLAG first */
+ 8000b68: 4b09 ldr r3, [pc, #36] ; (8000b90 )
+{
+ 8000b6a: b082 sub sp, #8
+ __IO uint32_t tmp = SysTick->CTRL; /* Clear the COUNTFLAG first */
+ 8000b6c: 681a ldr r2, [r3, #0]
+ 8000b6e: 9201 str r2, [sp, #4]
+ /* Add this code to indicate that local variable is not used */
+ ((void)tmp);
+ 8000b70: 9a01 ldr r2, [sp, #4]
+
+ /* Add a period to guaranty minimum wait */
+ if (Delay < LL_MAX_DELAY)
+ {
+ Delay++;
+ 8000b72: 1c42 adds r2, r0, #1
+ 8000b74: 1e51 subs r1, r2, #1
+ 8000b76: 418a sbcs r2, r1
+ 8000b78: 1880 adds r0, r0, r2
+ }
+
+ while (Delay)
+ {
+ if ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) != 0U)
+ 8000b7a: 2280 movs r2, #128 ; 0x80
+ 8000b7c: 0252 lsls r2, r2, #9
+ while (Delay)
+ 8000b7e: 2800 cmp r0, #0
+ 8000b80: d101 bne.n 8000b86
+ {
+ Delay--;
+ }
+ }
+}
+ 8000b82: b002 add sp, #8
+ 8000b84: 4770 bx lr
+ if ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) != 0U)
+ 8000b86: 6819 ldr r1, [r3, #0]
+ 8000b88: 4211 tst r1, r2
+ 8000b8a: d0f8 beq.n 8000b7e
+ Delay--;
+ 8000b8c: 3801 subs r0, #1
+ 8000b8e: e7f6 b.n 8000b7e
+ 8000b90: e000e010 .word 0xe000e010
+
+08000b94 :
+ * @retval None
+ */
+void LL_SetSystemCoreClock(uint32_t HCLKFrequency)
+{
+ /* HCLK clock frequency */
+ SystemCoreClock = HCLKFrequency;
+ 8000b94: 4b01 ldr r3, [pc, #4] ; (8000b9c )
+ 8000b96: 6018 str r0, [r3, #0]
+}
+ 8000b98: 4770 bx lr
+ 8000b9a: 46c0 nop ; (mov r8, r8)
+ 8000b9c: 20000000 .word 0x20000000
+
+08000ba0 <__libc_init_array>:
+ 8000ba0: b570 push {r4, r5, r6, lr}
+ 8000ba2: 2600 movs r6, #0
+ 8000ba4: 4d0c ldr r5, [pc, #48] ; (8000bd8 <__libc_init_array+0x38>)
+ 8000ba6: 4c0d ldr r4, [pc, #52] ; (8000bdc <__libc_init_array+0x3c>)
+ 8000ba8: 1b64 subs r4, r4, r5
+ 8000baa: 10a4 asrs r4, r4, #2
+ 8000bac: 42a6 cmp r6, r4
+ 8000bae: d109 bne.n 8000bc4 <__libc_init_array+0x24>
+ 8000bb0: 2600 movs r6, #0
+ 8000bb2: f000 f821 bl 8000bf8 <_init>
+ 8000bb6: 4d0a ldr r5, [pc, #40] ; (8000be0 <__libc_init_array+0x40>)
+ 8000bb8: 4c0a ldr r4, [pc, #40] ; (8000be4 <__libc_init_array+0x44>)
+ 8000bba: 1b64 subs r4, r4, r5
+ 8000bbc: 10a4 asrs r4, r4, #2
+ 8000bbe: 42a6 cmp r6, r4
+ 8000bc0: d105 bne.n 8000bce <__libc_init_array+0x2e>
+ 8000bc2: bd70 pop {r4, r5, r6, pc}
+ 8000bc4: 00b3 lsls r3, r6, #2
+ 8000bc6: 58eb ldr r3, [r5, r3]
+ 8000bc8: 4798 blx r3
+ 8000bca: 3601 adds r6, #1
+ 8000bcc: e7ee b.n 8000bac <__libc_init_array+0xc>
+ 8000bce: 00b3 lsls r3, r6, #2
+ 8000bd0: 58eb ldr r3, [r5, r3]
+ 8000bd2: 4798 blx r3
+ 8000bd4: 3601 adds r6, #1
+ 8000bd6: e7f2 b.n 8000bbe <__libc_init_array+0x1e>
+ 8000bd8: 08000c3c .word 0x08000c3c
+ 8000bdc: 08000c3c .word 0x08000c3c
+ 8000be0: 08000c3c .word 0x08000c3c
+ 8000be4: 08000c40 .word 0x08000c40
+
+08000be8 :
+ 8000be8: 0003 movs r3, r0
+ 8000bea: 1882 adds r2, r0, r2
+ 8000bec: 4293 cmp r3, r2
+ 8000bee: d100 bne.n 8000bf2
+ 8000bf0: 4770 bx lr
+ 8000bf2: 7019 strb r1, [r3, #0]
+ 8000bf4: 3301 adds r3, #1
+ 8000bf6: e7f9 b.n 8000bec
+
+08000bf8 <_init>:
+ 8000bf8: b5f8 push {r3, r4, r5, r6, r7, lr}
+ 8000bfa: 46c0 nop ; (mov r8, r8)
+ 8000bfc: bcf8 pop {r3, r4, r5, r6, r7}
+ 8000bfe: bc08 pop {r3}
+ 8000c00: 469e mov lr, r3
+ 8000c02: 4770 bx lr
+
+08000c04 <_fini>:
+ 8000c04: b5f8 push {r3, r4, r5, r6, r7, lr}
+ 8000c06: 46c0 nop ; (mov r8, r8)
+ 8000c08: bcf8 pop {r3, r4, r5, r6, r7}
+ 8000c0a: bc08 pop {r3}
+ 8000c0c: 469e mov lr, r3
+ 8000c0e: 4770 bx lr
diff --git a/fw/Debug/iaq_wired_sensor.map b/fw/Debug/iaq_wired_sensor.map
new file mode 100644
index 0000000..21a21e3
--- /dev/null
+++ b/fw/Debug/iaq_wired_sensor.map
@@ -0,0 +1,1345 @@
+Archive member included to satisfy reference by file (symbol)
+
+/opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-errno.o)
+ Core/Src/syscalls.o (__errno)
+/opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-exit.o)
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+
+Memory Configuration
+
+Name Origin Length Attributes
+RAM 0x0000000020000000 0x0000000000000800 xrw
+FLASH 0x0000000008000000 0x0000000000004000 xr
+*default* 0x0000000000000000 0xffffffffffffffff
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+Linker script and memory map
+
+LOAD /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crti.o
+LOAD /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crtbegin.o
+LOAD /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/crt0.o
+LOAD Core/Src/main.o
+LOAD Core/Src/stm32l0xx_it.o
+LOAD Core/Src/syscalls.o
+LOAD Core/Src/sysmem.o
+LOAD Core/Src/system_stm32l0xx.o
+LOAD Core/Startup/startup_stm32l011f4ux.o
+LOAD Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.o
+LOAD Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.o
+LOAD Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.o
+LOAD Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.o
+LOAD Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.o
+LOAD Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_pwr.o
+LOAD Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.o
+LOAD Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.o
+START GROUP
+LOAD /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a
+LOAD /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libm.a
+END GROUP
+START GROUP
+LOAD /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a
+LOAD /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a
+END GROUP
+START GROUP
+LOAD /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a
+LOAD /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a
+LOAD /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libnosys.a
+END GROUP
+START GROUP
+LOAD /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a
+LOAD /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a
+LOAD /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libnosys.a
+END GROUP
+LOAD /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crtend.o
+LOAD /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crtn.o
+ 0x0000000020000800 _estack = (ORIGIN (RAM) + LENGTH (RAM))
+ 0x0000000000000200 _Min_Heap_Size = 0x200
+ 0x0000000000000400 _Min_Stack_Size = 0x400
+
+.isr_vector 0x0000000008000000 0xc0
+ 0x0000000008000000 . = ALIGN (0x4)
+ *(.isr_vector)
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+ 0x0000000008000000 g_pfnVectors
+ 0x00000000080000c0 . = ALIGN (0x4)
+
+.text 0x00000000080000c0 0xb50
+ 0x00000000080000c0 . = ALIGN (0x4)
+ *(.text)
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+ .text 0x0000000008000108 0x114 /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_udivsi3.o)
+ 0x0000000008000108 __udivsi3
+ 0x0000000008000108 __aeabi_uidiv
+ 0x0000000008000214 __aeabi_uidivmod
+ .text 0x000000000800021c 0x4 /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_dvmd_tls.o)
+ 0x000000000800021c __aeabi_ldiv0
+ 0x000000000800021c __aeabi_idiv0
+ .text 0x0000000008000220 0x40 /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_aeabi_uldivmod.o)
+ 0x0000000008000220 __aeabi_uldivmod
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+ 0x0000000008000260 __udivmoddi4
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+ 0x00000000080003f8 __clzdi2
+ .text 0x0000000008000410 0x3c /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_clzsi2.o)
+ 0x0000000008000410 __clzsi2
+ *(.text*)
+ .text.LL_APB1_GRP1_EnableClock
+ 0x000000000800044c 0x1c Core/Src/main.o
+ .text.LL_IOP_GRP1_EnableClock.constprop.0
+ 0x0000000008000468 0x1c Core/Src/main.o
+ .text.SystemClock_Config
+ 0x0000000008000484 0xbc Core/Src/main.o
+ 0x0000000008000484 SystemClock_Config
+ .text.startup.main
+ 0x0000000008000540 0x278 Core/Src/main.o
+ 0x0000000008000540 main
+ .text.NMI_Handler
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+ 0x00000000080007b8 NMI_Handler
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+ 0x00000000080007ba HardFault_Handler
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+ 0x00000000080007bc SVC_Handler
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+ 0x00000000080007be PendSV_Handler
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+ 0x00000000080007c0 SysTick_Handler
+ .text.DMA1_Channel2_3_IRQHandler
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+ 0x00000000080007c2 DMA1_Channel2_3_IRQHandler
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+ 0x00000000080007c4 SystemInit
+ *fill* 0x00000000080007c6 0x2
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+ 0x000000000800084a 0xa2 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.o
+ 0x000000000800084a LL_GPIO_Init
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+ 0x00000000080008ec LL_I2C_Init
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+ 0x0000000008000960 0x7c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.o
+ 0x0000000008000960 LL_LPUART_Init
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+ .text.LL_RCC_IsActiveFlag_HSIDIV
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+ 0x00000000080009fc RCC_GetHCLKClockFreq
+ .text.RCC_GetPCLK1ClockFreq
+ 0x0000000008000a14 0x18 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.o
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+ .debug_macro 0x0000000000001545 0x7b9c Core/Src/main.o
+ .debug_macro 0x00000000000090e1 0x3c Core/Src/main.o
+ .debug_macro 0x000000000000911d 0x27f Core/Src/main.o
+ .debug_macro 0x000000000000939c 0x246 Core/Src/main.o
+ .debug_macro 0x00000000000095e2 0x229 Core/Src/main.o
+ .debug_macro 0x000000000000980b 0x3b4 Core/Src/main.o
+ .debug_macro 0x0000000000009bbf 0xa7 Core/Src/main.o
+ .debug_macro 0x0000000000009c66 0x13d Core/Src/main.o
+ .debug_macro 0x0000000000009da3 0x109 Core/Src/main.o
+ .debug_macro 0x0000000000009eac 0x16 Core/Src/main.o
+ .debug_macro 0x0000000000009ec2 0x2a Core/Src/main.o
+ .debug_macro 0x0000000000009eec 0xdb Core/Src/main.o
+ .debug_macro 0x0000000000009fc7 0x12d Core/Src/main.o
+ .debug_macro 0x000000000000a0f4 0x46 Core/Src/main.o
+ .debug_macro 0x000000000000a13a 0x146 Core/Src/stm32l0xx_it.o
+ .debug_macro 0x000000000000a280 0xba Core/Src/system_stm32l0xx.o
+ .debug_macro 0x000000000000a33a 0xfc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.o
+ .debug_macro 0x000000000000a436 0x127 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.o
+ .debug_macro 0x000000000000a55d 0xfc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.o
+ .debug_macro 0x000000000000a659 0x240 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.o
+ .debug_macro 0x000000000000a899 0x111 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.o
+ .debug_macro 0x000000000000a9aa 0x223 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.o
+ .debug_macro 0x000000000000abcd 0xe7 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.o
+ .debug_macro 0x000000000000acb4 0x3ae Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.o
+ .debug_macro 0x000000000000b062 0x162 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.o
+
+.debug_line 0x0000000000000000 0x42de
+ .debug_line 0x0000000000000000 0xda6 Core/Src/main.o
+ .debug_line 0x0000000000000da6 0x5d8 Core/Src/stm32l0xx_it.o
+ .debug_line 0x000000000000137e 0x534 Core/Src/system_stm32l0xx.o
+ .debug_line 0x00000000000018b2 0x9b Core/Startup/startup_stm32l011f4ux.o
+ .debug_line 0x000000000000194d 0x681 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.o
+ .debug_line 0x0000000000001fce 0x643 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.o
+ .debug_line 0x0000000000002611 0x62c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.o
+ .debug_line 0x0000000000002c3d 0xb31 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.o
+ .debug_line 0x000000000000376e 0xb70 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.o
+
+.debug_str 0x0000000000000000 0x391e8
+ .debug_str 0x0000000000000000 0x37067 Core/Src/main.o
+ 0x3736e (size before relaxing)
+ .debug_str 0x0000000000037067 0x91 Core/Src/stm32l0xx_it.o
+ 0x369b1 (size before relaxing)
+ .debug_str 0x00000000000370f8 0x61 Core/Src/system_stm32l0xx.o
+ 0x3045a (size before relaxing)
+ .debug_str 0x0000000000037159 0x36 Core/Startup/startup_stm32l011f4ux.o
+ 0x92 (size before relaxing)
+ .debug_str 0x000000000003718f 0x578 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.o
+ 0x3157a (size before relaxing)
+ .debug_str 0x0000000000037707 0x3e1 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.o
+ 0x31cef (size before relaxing)
+ .debug_str 0x0000000000037ae8 0x521 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.o
+ 0x33365 (size before relaxing)
+ .debug_str 0x0000000000038009 0x4f5 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.o
+ 0x3226f (size before relaxing)
+ .debug_str 0x00000000000384fe 0xcea Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.o
+ 0x33996 (size before relaxing)
+
+.comment 0x0000000000000000 0x53
+ .comment 0x0000000000000000 0x53 Core/Src/main.o
+ 0x54 (size before relaxing)
+ .comment 0x0000000000000053 0x54 Core/Src/stm32l0xx_it.o
+ .comment 0x0000000000000053 0x54 Core/Src/system_stm32l0xx.o
+ .comment 0x0000000000000053 0x54 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.o
+ .comment 0x0000000000000053 0x54 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.o
+ .comment 0x0000000000000053 0x54 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.o
+ .comment 0x0000000000000053 0x54 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.o
+ .comment 0x0000000000000053 0x54 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.o
+
+.debug_frame 0x0000000000000000 0x4a8
+ .debug_frame 0x0000000000000000 0x80 Core/Src/main.o
+ .debug_frame 0x0000000000000080 0x70 Core/Src/stm32l0xx_it.o
+ .debug_frame 0x00000000000000f0 0x3c Core/Src/system_stm32l0xx.o
+ .debug_frame 0x000000000000012c 0x54 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.o
+ .debug_frame 0x0000000000000180 0x4c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.o
+ .debug_frame 0x00000000000001cc 0x50 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.o
+ .debug_frame 0x000000000000021c 0x124 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.o
+ .debug_frame 0x0000000000000340 0xc0 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.o
+ .debug_frame 0x0000000000000400 0x2c /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-init.o)
+ .debug_frame 0x000000000000042c 0x20 /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-memset.o)
+ .debug_frame 0x000000000000044c 0x20 /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_udivsi3.o)
+ .debug_frame 0x000000000000046c 0x3c /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_udivmoddi4.o)
diff --git a/fw/Debug/makefile b/fw/Debug/makefile
new file mode 100644
index 0000000..7d54beb
--- /dev/null
+++ b/fw/Debug/makefile
@@ -0,0 +1,101 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+# Toolchain: GNU Tools for STM32 (9-2020-q2-update)
+################################################################################
+
+-include ../makefile.init
+
+RM := rm -rf
+
+# All of the sources participating in the build are defined here
+-include sources.mk
+-include Drivers/STM32L0xx_HAL_Driver/Src/subdir.mk
+-include Core/Startup/subdir.mk
+-include Core/Src/subdir.mk
+-include subdir.mk
+-include objects.mk
+
+ifneq ($(MAKECMDGOALS),clean)
+ifneq ($(strip $(S_DEPS)),)
+-include $(S_DEPS)
+endif
+ifneq ($(strip $(S_UPPER_DEPS)),)
+-include $(S_UPPER_DEPS)
+endif
+ifneq ($(strip $(C_DEPS)),)
+-include $(C_DEPS)
+endif
+endif
+
+-include ../makefile.defs
+
+OPTIONAL_TOOL_DEPS := \
+$(wildcard ../makefile.defs) \
+$(wildcard ../makefile.init) \
+$(wildcard ../makefile.targets) \
+
+
+BUILD_ARTIFACT_NAME := iaq_wired_sensor
+BUILD_ARTIFACT_EXTENSION := elf
+BUILD_ARTIFACT_PREFIX :=
+BUILD_ARTIFACT := $(BUILD_ARTIFACT_PREFIX)$(BUILD_ARTIFACT_NAME).$(BUILD_ARTIFACT_EXTENSION)
+
+# Add inputs and outputs from these tool invocations to the build variables
+EXECUTABLES += \
+iaq_wired_sensor.elf \
+
+SIZE_OUTPUT += \
+default.size.stdout \
+
+OBJDUMP_LIST += \
+iaq_wired_sensor.list \
+
+OBJCOPY_BIN += \
+iaq_wired_sensor.bin \
+
+
+# All Target
+all: main-build
+
+# Main-build Target
+main-build: iaq_wired_sensor.elf secondary-outputs
+
+# Tool invocations
+iaq_wired_sensor.elf: $(OBJS) $(USER_OBJS) /home/david/Personal/Projects/HDIoT/Smart_Household/Wired_Sensors/iaq_wired_sensor/fw/STM32L011F4UX_FLASH.ld makefile objects.list $(OPTIONAL_TOOL_DEPS)
+ arm-none-eabi-gcc -o "iaq_wired_sensor.elf" @"objects.list" $(USER_OBJS) $(LIBS) -mcpu=cortex-m0plus -T"/home/david/Personal/Projects/HDIoT/Smart_Household/Wired_Sensors/iaq_wired_sensor/fw/STM32L011F4UX_FLASH.ld" --specs=nosys.specs -Wl,-Map="iaq_wired_sensor.map" -Wl,--gc-sections -static --specs=nano.specs -mfloat-abi=soft -mthumb -Wl,--start-group -lc -lm -Wl,--end-group
+ @echo 'Finished building target: $@'
+ @echo ' '
+
+default.size.stdout: $(EXECUTABLES) makefile objects.list $(OPTIONAL_TOOL_DEPS)
+ arm-none-eabi-size $(EXECUTABLES)
+ @echo 'Finished building: $@'
+ @echo ' '
+
+iaq_wired_sensor.list: $(EXECUTABLES) makefile objects.list $(OPTIONAL_TOOL_DEPS)
+ arm-none-eabi-objdump -h -S $(EXECUTABLES) > "iaq_wired_sensor.list"
+ @echo 'Finished building: $@'
+ @echo ' '
+
+iaq_wired_sensor.bin: $(EXECUTABLES) makefile objects.list $(OPTIONAL_TOOL_DEPS)
+ arm-none-eabi-objcopy -O binary $(EXECUTABLES) "iaq_wired_sensor.bin"
+ @echo 'Finished building: $@'
+ @echo ' '
+
+# Other Targets
+clean:
+ -$(RM) *
+ -@echo ' '
+
+secondary-outputs: $(SIZE_OUTPUT) $(OBJDUMP_LIST) $(OBJCOPY_BIN)
+
+fail-specified-linker-script-missing:
+ @echo 'Error: Cannot find the specified linker script. Check the linker settings in the build configuration.'
+ @exit 2
+
+warn-no-linker-script-specified:
+ @echo 'Warning: No linker script specified. Check the linker settings in the build configuration.'
+
+.PHONY: all clean dependents fail-specified-linker-script-missing warn-no-linker-script-specified
+.SECONDARY:
+
+-include ../makefile.targets
diff --git a/fw/Debug/objects.list b/fw/Debug/objects.list
new file mode 100644
index 0000000..fd3a2ee
--- /dev/null
+++ b/fw/Debug/objects.list
@@ -0,0 +1,14 @@
+"Core/Src/main.o"
+"Core/Src/stm32l0xx_it.o"
+"Core/Src/syscalls.o"
+"Core/Src/sysmem.o"
+"Core/Src/system_stm32l0xx.o"
+"Core/Startup/startup_stm32l011f4ux.o"
+"Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.o"
+"Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.o"
+"Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.o"
+"Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.o"
+"Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.o"
+"Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_pwr.o"
+"Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.o"
+"Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.o"
diff --git a/fw/Debug/objects.mk b/fw/Debug/objects.mk
new file mode 100644
index 0000000..e12976d
--- /dev/null
+++ b/fw/Debug/objects.mk
@@ -0,0 +1,9 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+# Toolchain: GNU Tools for STM32 (9-2020-q2-update)
+################################################################################
+
+USER_OBJS :=
+
+LIBS :=
+
diff --git a/fw/Debug/sources.mk b/fw/Debug/sources.mk
new file mode 100644
index 0000000..a511ac3
--- /dev/null
+++ b/fw/Debug/sources.mk
@@ -0,0 +1,26 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+# Toolchain: GNU Tools for STM32 (9-2020-q2-update)
+################################################################################
+
+ELF_SRCS :=
+OBJ_SRCS :=
+S_SRCS :=
+C_SRCS :=
+S_UPPER_SRCS :=
+O_SRCS :=
+SIZE_OUTPUT :=
+OBJDUMP_LIST :=
+EXECUTABLES :=
+OBJS :=
+S_DEPS :=
+S_UPPER_DEPS :=
+C_DEPS :=
+OBJCOPY_BIN :=
+
+# Every subdirectory with source files must be described here
+SUBDIRS := \
+Core/Src \
+Core/Startup \
+Drivers/STM32L0xx_HAL_Driver/Src \
+
diff --git a/fw/iaq_wired_sensor.ioc b/fw/iaq_wired_sensor.ioc
index 9947a1c..5978da7 100644
--- a/fw/iaq_wired_sensor.ioc
+++ b/fw/iaq_wired_sensor.ioc
@@ -3,11 +3,12 @@ Mcu.Family=STM32L0
PA6.GPIOParameters=PinState,GPIO_Label
RCC.MSI_VALUE=2097000
ProjectManager.MainLocation=Core/Src
+PA0-CK_IN.GPIOParameters=GPIO_PuPd
ProjectManager.ProjectFileName=iaq_wired_sensor.ioc
ProjectManager.KeepUserCode=true
PA10.Mode=I2C
Mcu.UserName=STM32L011F4Ux
-Mcu.PinsNb=11
+Mcu.PinsNb=10
ProjectManager.NoMain=false
PA0-CK_IN.Mode=Asynchronous
RCC.LPUARTFreq_Value=2097000
@@ -25,22 +26,19 @@ Dma.LPUART1_RX.0.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDat
NVIC.SVC_IRQn=true\:0\:0\:false\:false\:true\:false\:false
ProjectManager.DeletePrevious=true
PA5.PinState=GPIO_PIN_SET
-LPUART1.UART_DEDeassertionTime=20
Dma.LPUART1_RX.0.Instance=DMA1_Channel3
-LPUART1.IPParameters=BaudRate,SwapParam,OneBitSampling,UART_DEAssertionTime,UART_DEDeassertionTime,UART_DEPolarity,WordLength
+LPUART1.IPParameters=BaudRate,SwapParam,OneBitSampling,WordLength
PinOutPanel.RotationAngle=0
RCC.FamilyName=M
ProjectManager.StackSize=0x400
Dma.LPUART1_RX.0.PeriphInc=DMA_PINC_DISABLE
RCC.WatchDogFreq_Value=37000
-LPUART1.UART_DEAssertionTime=20
PA13.Signal=SYS_SWDIO
Mcu.IP4=RCC
RCC.HSI16_VALUE=16000000
Mcu.IP5=SYS
Mcu.IP2=LPUART1
Mcu.IP3=NVIC
-LPUART1.UART_DEPolarity=UART_DE_POLARITY_HIGH
LPUART1.OneBitSampling=UART_ONE_BIT_SAMPLE_ENABLE
Mcu.IP0=DMA
PA9.Mode=I2C
@@ -53,12 +51,14 @@ Mcu.IPNb=6
ProjectManager.PreviousToolchain=
RCC.APB2TimFreq_Value=2097000
PA9.Signal=I2C1_SCL
-Mcu.Pin6=PA9
-Mcu.Pin7=PA10
+Mcu.Pin6=PA10
+Mcu.Pin7=PA13
ProjectManager.RegisterCallBack=
-Mcu.Pin8=PA13
-Mcu.Pin9=PA14
+Mcu.Pin8=PA14
+Mcu.Pin9=VP_SYS_VS_Systick
+PA0-CK_IN.GPIO_PuPd=GPIO_PULLUP
RCC.LSE_VALUE=32768
+PA1.GPIO_PuPd=GPIO_PULLUP
PA1.Signal=LPUART1_TX
RCC.AHBFreq_Value=2097000
Mcu.Pin0=PA0-CK_IN
@@ -67,7 +67,7 @@ GPIO.groupedBy=Group By Peripherals
Mcu.Pin2=PA5
Mcu.Pin3=PA6
Mcu.Pin4=PA7
-Mcu.Pin5=PB1
+Mcu.Pin5=PA9
Dma.LPUART1_RX.0.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
PA5.Signal=GPIO_Output
ProjectManager.ProjectBuild=false
@@ -82,6 +82,7 @@ PA0-CK_IN.Signal=LPUART1_RX
MxDb.Version=DB.6.0.10
RCC.APB2Freq_Value=2097000
PA1.Mode=Asynchronous
+PA1.GPIOParameters=GPIO_PuPd
ProjectManager.BackupPrevious=false
MxCube.Version=6.1.0
RCC.I2C1Freq_Value=2097000
@@ -106,7 +107,6 @@ ProjectManager.UnderRoot=true
ProjectManager.CoupleFile=false
RCC.SYSCLKFreq_VALUE=2097000
Mcu.Package=UFQFPN20
-PB1.Signal=LPUART1_DE
PA6.Signal=GPIO_Output
PA7.GPIO_Label=LED_R
Dma.LPUART1_RX.0.Mode=DMA_CIRCULAR
@@ -124,11 +124,9 @@ PA10.Signal=I2C1_SDA
PA14.Signal=SYS_SWCLK
ProjectManager.HeapSize=0x200
NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
-PB1.Mode=Hardware Flow Control (RS485)
PA5.GPIOParameters=PinState,GPIO_Label
ProjectManager.ComputerToolchain=false
RCC.HSI_VALUE=16000000
-Mcu.Pin10=VP_SYS_VS_Systick
NVIC.DMA1_Channel2_3_IRQn=true\:0\:0\:false\:false\:true\:false\:true
RCC.APB1TimFreq_Value=2097000
RCC.PWRFreq_Value=2097000