diff --git a/PCB/Project_Outputs/GERBERS/iaq_wired_sensor-GERBERS.zip b/PCB/Project_Outputs/GERBERS/iaq_wired_sensor-GERBERS.zip new file mode 100755 index 0000000..325fcfd Binary files /dev/null and b/PCB/Project_Outputs/GERBERS/iaq_wired_sensor-GERBERS.zip differ diff --git a/PCB/bom/wired_iaq_sensor_digikey_bom.csv b/PCB/bom/wired_iaq_sensor_digikey_bom.csv new file mode 100755 index 0000000..31d15fd --- /dev/null +++ b/PCB/bom/wired_iaq_sensor_digikey_bom.csv @@ -0,0 +1,27 @@ +Digikey,Quantity +587-5853-1-ND,1 +445-175218-1-ND,4 +587-3238-1-ND,3 +490-10700-1-ND,5 +18-AQ12-02HTGCT-ND,1 +1727-3854-1-ND,1 +31-SD24-7CT-ND,1 +507-2156-1-ND,1 +507-1794-1-ND,1 +S9461-ND,1 +455-1696-1-ND,1 +587-2891-1-ND,1 +587-5935-1-ND,1 +516-3906-1-ND,1 +1727-1287-1-ND,1 +YAG5275CT-ND,1 +YAG3164CT-ND,1 +311-100KJRCT-ND,2 +311-10KJRCT-ND,4 +311-1KLBCT-ND,3 +311-120JRCT-ND,1 +MAX15062CATA+TCT-ND,2 +497-17478-1-ND,1 +1649-SHT40-AD1B-R2CT-ND,1 +1649-SCD40-D-R2CT-ND,1 +296-THVD1450DRBRCT-ND,1 diff --git a/PCB/iaq_wired_sensor-rescue.dcm b/PCB/iaq_wired_sensor-rescue.dcm new file mode 100644 index 0000000..5f3ed79 --- /dev/null +++ b/PCB/iaq_wired_sensor-rescue.dcm @@ -0,0 +1,3 @@ +EESchema-DOCLIB Version 2.0 +# +#End Doc Library diff --git a/PCB/iaq_wired_sensor-rescue.lib b/PCB/iaq_wired_sensor-rescue.lib new file mode 100644 index 0000000..faa0ad8 --- /dev/null +++ b/PCB/iaq_wired_sensor-rescue.lib @@ -0,0 +1,889 @@ +EESchema-LIBRARY Version 2.4 +#encoding utf-8 +# +# +3V3-HD_Power_Symbols +# +DEF +3V3-HD_Power_Symbols #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -150 50 H I C CNN +F1 "+3V3-HD_Power_Symbols" 0 140 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 2 0 1 0 -30 50 0 100 N +P 2 0 1 0 0 0 0 100 N +P 2 0 1 0 0 100 30 50 N +X +3V3 1 0 0 0 U 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# +5V-HD_Power_Symbols +# +DEF +5V-HD_Power_Symbols #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -150 50 H I C CNN +F1 "+5V-HD_Power_Symbols" 0 140 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 2 0 1 0 -30 50 0 100 N +P 2 0 1 0 0 0 0 100 N +P 2 0 1 0 0 100 30 50 N +X +5V 1 0 0 0 U 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# 0686F0500-01-HD_Other +# +DEF 0686F0500-01-HD_Other F 0 40 Y Y 1 F N +F0 "F" 0 200 50 H V C CNN +F1 "0686F0500-01-HD_Other" 0 -100 50 H V C CNN +F2 "HD_Other:F0603" 0 -200 50 H I C CNN +F3 "" 0 200 50 H I C CNN +F4 "2834860" 0 -700 50 H I C CNN "Farnell" +F5 "C1F-500" 0 -800 50 H I C CNN "TME" +F6 "530-0686F0500-01" 0 -600 50 H I C CNN "Mouser" +F7 "507-2156-1-ND" 0 -500 50 H I C CNN "Digikey" +F8 "Bel Fuse Inc." 0 -300 50 H I C CNN "Manufacturer" +F9 "0686F0500-01" 0 -400 50 H I C CNN "Code" +F10 "Eaton - Electronics Division" 1050 -300 50 H I C CNN "Alt_Manufacturer" +F11 "CC06FA500MA-TR" 1100 -400 50 H I C CNN "Alt_Code" +DRAW +S 100 -30 -100 30 1 1 10 N +P 2 1 1 0 -100 0 100 0 N +X ~ 1 -150 0 50 R 50 50 1 1 P +X ~ 2 150 0 50 L 50 50 1 1 P +ENDDRAW +ENDDEF +# +# 0ZCJ0010FF2E-HD_Other +# +DEF 0ZCJ0010FF2E-HD_Other F 0 40 Y Y 1 F N +F0 "F" 0 200 50 H V C CNN +F1 "0ZCJ0010FF2E-HD_Other" 0 -100 50 H V C CNN +F2 "HD_Other:F1206" 0 -200 50 H I C CNN +F3 "" 0 200 50 H I C CNN +F4 "Bel Fuse Inc." 0 -300 50 H I C CNN "Manufacturer" +F5 "0ZCJ0010FF2E" 0 -400 50 H I C CNN "Code" +F6 "Eaton - Electronics Division" 1050 -300 50 H I C CNN "Alt_Manufacturer" +F7 "PTS120660V010" 1100 -400 50 H I C CNN "Alt_Code" +F8 "507-1794-1-ND" 0 -500 50 H I C CNN "Digikey" +F9 "530-0ZCJ0010FF2E" 0 -600 50 H I C CNN "Mouser" +F10 "2834880" 0 -700 50 H I C CNN "Farnell" +F11 " 0ZCJ0010FF2E" 0 -800 50 H I C CNN "TME" +DRAW +S 100 -30 -100 30 1 1 10 N +P 2 1 1 0 -100 0 100 0 N +X ~ 1 -150 0 50 R 50 50 1 1 P +X ~ 2 150 0 50 L 50 50 1 1 P +ENDDRAW +ENDDEF +# +# AQ12-02HTG-HD_Diodes +# +DEF AQ12-02HTG-HD_Diodes D 0 40 Y N 1 F N +F0 "D" 250 100 50 H V C CNN +F1 "AQ12-02HTG-HD_Diodes" 475 0 50 H V C CNN +F2 "HD_SOT:SOT-23" 0 -300 50 H I C CNN +F3 "" -50 600 50 H I C CNN +F4 "Littelfuse Inc." 0 -400 50 H I C CNN "Manufacturer" +F5 "AQ12-02HTG" 0 -500 50 H I C CNN "Code" +F6 "Bourns" 1000 -400 50 H I C CNN "Alt_Manufacturer" +F7 "CDSOT23-SM712" 950 -500 50 H I C CNN "Alt_Code" +F8 "18-AQ12-02HTGCT-ND" 0 -600 50 H I C CNN "Digikey" +F9 "576-AQ12-02HTG" 0 -700 50 H I C CNN "Mouser" +F10 "X" 0 -800 50 H I C CNN "Farnell" +F11 "X" 0 -900 50 H I C CNN "TME" +DRAW +S -200 150 200 -100 1 1 0 f +P 4 0 1 0 -50 100 -150 100 -100 50 -50 100 F +P 2 1 1 0 -100 100 -100 150 N +P 2 1 1 0 0 -100 0 -50 N +P 2 1 1 0 100 100 100 150 N +P 4 1 1 0 -150 0 -50 0 -100 50 -150 0 F +P 4 1 1 0 -150 60 -140 50 -60 50 -50 40 N +P 4 1 1 0 -100 0 -100 -50 100 -50 100 0 N +P 4 1 1 0 50 0 150 0 100 50 50 0 F +P 4 1 1 0 50 60 60 50 140 50 150 40 N +P 4 1 1 0 150 100 50 100 100 50 150 100 F +X 1 1 -100 250 100 D 50 50 1 1 I +X 2 2 100 250 100 D 50 50 1 1 I +X 3 3 0 -200 100 U 50 50 1 1 I +ENDDRAW +ENDDEF +# +# ASMB-KTF0-0A306-HD_Diodes +# +DEF ASMB-KTF0-0A306-HD_Diodes LD 0 40 Y N 1 F N +F0 "LD" 0 400 50 H V C CNN +F1 "ASMB-KTF0-0A306-HD_Diodes" 0 -350 50 H V C CNN +F2 "HD_Diodes:LED_ASMB-KTF0-0A306" 0 -450 50 H I C CNN +F3 "" 0 -1000 50 H I C CNN +F4 "Broadcom Limited" 0 -550 50 H I C CNN "Manufacturer" +F5 "ASMB-KTF0-0A306" 0 -650 50 H I C CNN "Code" +F6 "516-3906-1-ND" 0 -750 50 H I C CNN "Digikey" +F7 "630-ASMB-KTF0-0A306" 0 -850 50 H I C CNN "Mouser" +F8 "2858363" 0 -950 50 H I C CNN "Farnell" +F9 "X" 0 -1050 50 H I C CNN "TME" +DRAW +T 0 0 -100 50 0 0 0 BLUE Normal 0 C C +T 0 0 100 50 0 0 0 GREEN Normal 0 C C +T 0 0 300 50 0 0 0 RED Normal 0 C C +S -200 350 200 -300 0 0 0 f +P 2 0 1 0 -200 -200 -50 -200 N +P 2 0 1 0 -200 0 -50 0 N +P 2 0 1 0 -200 200 -50 200 N +P 2 0 1 0 150 0 50 0 N +P 3 0 1 0 50 200 150 200 150 0 N +P 4 0 1 0 50 -200 150 -200 150 0 200 0 N +P 2 1 1 0 -50 -200 50 -200 N +P 2 1 1 8 -50 -150 -50 -250 N +P 2 1 1 0 -50 0 50 0 N +P 2 1 1 8 -50 50 -50 -50 N +P 2 1 1 0 -50 200 50 200 N +P 2 1 1 8 -50 250 -50 150 N +P 4 1 1 8 50 -150 50 -250 -50 -200 50 -150 N +P 4 1 1 8 50 50 50 -50 -50 0 50 50 N +P 4 1 1 8 50 250 50 150 -50 200 50 250 N +P 5 1 1 0 -120 -170 -180 -110 -150 -110 -180 -110 -180 -140 N +P 5 1 1 0 -120 30 -180 90 -150 90 -180 90 -180 60 N +P 5 1 1 0 -120 230 -180 290 -150 290 -180 290 -180 260 N +P 5 1 1 0 -70 -170 -130 -110 -100 -110 -130 -110 -130 -140 N +P 5 1 1 0 -70 30 -130 90 -100 90 -130 90 -130 60 N +P 5 1 1 0 -70 230 -130 290 -100 290 -130 290 -130 260 N +X A 1 300 0 100 L 50 50 1 1 P +X K 2 -300 200 100 R 50 50 1 1 P +X K 3 -300 0 100 R 50 50 1 1 P +X K 4 -300 -200 100 R 50 50 1 1 P +ENDDRAW +ENDDEF +# +# C0402_100nF_50V_X7R-HD_Capacitors +# +DEF C0402_100nF_50V_X7R-HD_Capacitors C 0 40 N N 1 F N +F0 "C" 200 150 50 H V C CNN +F1 "C0402_100nF_50V_X7R-HD_Capacitors" 0 -200 50 H I C CNN +F2 "HD_Capacitors:C0402" 0 -300 50 H I C CNN +F3 "" 0 0 50 H I C CNN +F4 "100nF" 250 50 50 H V C CNN "Capacitance" +F5 "50V" 200 -50 50 H V C CNN "Voltage" +F6 "X7R" 0 0 50 H I C CNN "Dielectric" +F7 "Murata Electronics" 0 -400 50 H I C CNN "Manufacturer" +F8 "GRM155R71H104KE14D" 0 -500 50 H I C CNN "Code" +F9 "490-10700-1-ND" 0 -600 50 H I C CNN "Digikey" +F10 "81-GRM155R71H104KE4D" 0 -700 50 H I C CNN "Mouser" +F11 "2611912" 0 -800 50 H I C CNN "Farnell" +F12 "GRM155R71H104KE14D" 0 -900 50 H I C CNN "TME" +F13 "TDK Corporation" 900 -400 50 H I C CNN "Alt_Manufacturer" +F14 "C1005X7R1H104K050BB" 900 -500 50 H I C CNN "Alt_Code" +DRAW +P 2 1 1 20 -80 -30 80 -30 N +P 2 1 1 20 -80 30 80 30 N +X ~ 1 0 150 110 D 50 50 1 1 P +X ~ 2 0 -150 110 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# C0402_1uF_35V_X5R-HD_Capacitors +# +DEF C0402_1uF_35V_X5R-HD_Capacitors C 0 40 N N 1 F N +F0 "C" 200 150 50 H V C CNN +F1 "C0402_1uF_35V_X5R-HD_Capacitors" 0 -200 50 H I C CNN +F2 "HD_Capacitors:C0402" 0 -300 50 H I C CNN +F3 "" 0 0 50 H I C CNN +F4 "1uF" 200 50 50 H V C CNN "Capacitance" +F5 "35V" 200 -50 50 H V C CNN "Voltage" +F6 "X5R" 0 0 50 H I C CNN "Dielectric" +F7 "TDK Corporation" 0 -400 50 H I C CNN "Manufacturer" +F8 "C1005X5R1V105K050BE" 0 -500 50 H I C CNN "Code" +F9 "445-175218-1-ND" 0 -600 50 H I C CNN "Digikey" +F10 "810-C1005X5R1V105K" 0 -700 50 H I C CNN "Mouser" +F11 "3416060" 0 -800 50 H I C CNN "Farnell" +F12 "X" 0 -900 50 H I C CNN "TME" +F13 "Kyocera International Inc. Electronic Components" 900 -400 50 H I C CNN "Alt_Manufacturer" +F14 "CM05X5R105K35AH" 900 -500 50 H I C CNN "Alt_Code" +DRAW +P 2 1 1 20 -80 -30 80 -30 N +P 2 1 1 20 -80 30 80 30 N +X ~ 1 0 150 110 D 50 50 1 1 P +X ~ 2 0 -150 110 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# C0603_10uF_16V_X5R-HD_Capacitors +# +DEF C0603_10uF_16V_X5R-HD_Capacitors C 0 40 N N 1 F N +F0 "C" 200 150 50 H V C CNN +F1 "C0603_10uF_16V_X5R-HD_Capacitors" 0 -200 50 H I C CNN +F2 "HD_Capacitors:C0603" 0 -300 50 H I C CNN +F3 "" 0 0 50 H I C CNN +F4 "10uF" 200 50 50 H V C CNN "Capacitance" +F5 "16V" 200 -50 50 H V C CNN "Voltage" +F6 "X5R" 0 0 50 H I C CNN "Dielectric" +F7 "Taiyo Yuden" 0 -400 50 H I C CNN "Manufacturer" +F8 "EMK107BBJ106MA-T" 0 -500 50 H I C CNN "Code" +F9 "587-3238-1-ND" 0 -600 50 H I C CNN "Digikey" +F10 "963-EMK107BBJ106MA-T" 0 -700 50 H I C CNN "Mouser" +F11 "2779064" 0 -800 50 H I C CNN "Farnell" +F12 "CL10A106MO8NQNC" 0 -900 50 H I C CNN "TME" +F13 "Murata Electronics" 950 -400 50 H I C CNN "Alt_Manufacturer" +F14 "GRM188R61C106MA73D" 950 -500 50 H I C CNN "Alt_Code" +DRAW +P 2 1 1 20 -80 -30 80 -30 N +P 2 1 1 20 -80 30 80 30 N +X ~ 1 0 150 110 D 50 50 1 1 P +X ~ 2 0 -150 110 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# C1210_22uF_35V_X5R-HD_Capacitors +# +DEF C1210_22uF_35V_X5R-HD_Capacitors C 0 40 N N 1 F N +F0 "C" 200 150 50 H V C CNN +F1 "C1210_22uF_35V_X5R-HD_Capacitors" 0 -200 50 H I C CNN +F2 "HD_Capacitors:C1210" 0 -300 50 H I C CNN +F3 "" 0 0 50 H I C CNN +F4 "22uF" 200 50 50 H V C CNN "Capacitance" +F5 "35V" 200 -50 50 H V C CNN "Voltage" +F6 "X5R" 0 0 50 H I C CNN "Dielectric" +F7 "Taiyo Yuden" 0 -400 50 H I C CNN "Manufacturer" +F8 "GMK325BJ226MM-P" 0 -500 50 H I C CNN "Code" +F9 "587-5853-1-ND" 0 -600 50 H I C CNN "Digikey" +F10 "963-GMK325BJ226MM-P" 0 -700 50 H I C CNN "Mouser" +F11 "X" 0 -800 50 H I C CNN "Farnell" +F12 "X" 0 -900 50 H I C CNN "TME" +F13 "Taiyo Yuden" 950 -400 50 H I C CNN "Alt_Manufacturer" +F14 "GMK325BJ226MM-T" 950 -500 50 H I C CNN "Alt_Code" +DRAW +P 2 1 1 20 -80 -30 80 -30 N +P 2 1 1 20 -80 30 80 30 N +X ~ 1 0 150 110 D 50 50 1 1 P +X ~ 2 0 -150 110 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# GND-HD_Power_Symbols +# +DEF GND-HD_Power_Symbols #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "GND-HD_Power_Symbols" 0 -150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 2 0 1 0 -25 -75 25 -75 N +P 2 0 1 0 -5 -100 5 -100 N +P 2 0 1 0 0 -50 0 0 N +P 2 0 1 0 50 -50 -50 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# JST_ZH5_Side_Entry_S5B-ZR-SM4A-TF-HD_Connectors +# +DEF JST_ZH5_Side_Entry_S5B-ZR-SM4A-TF-HD_Connectors J 0 1 Y N 1 F N +F0 "J" 50 300 50 H V C CNN +F1 "JST_ZH5_Side_Entry_S5B-ZR-SM4A-TF-HD_Connectors" 50 -300 50 H V C CNN +F2 "HD_Connectors:JST_ZH_5PIN_S5B-ZR-SM4A-TF" 50 -400 50 H I C CNN +F3 "" -450 -300 50 H I C CNN +F4 "455-1696-1-ND" 50 -500 50 H I C CNN "Digikey" +F5 "X" 50 -600 50 H I C CNN "Mouser" +F6 "2399336" 50 -700 50 H I C CNN "Farnell" +F7 "S5B-ZR-SM4A-TF" 50 -800 50 H I C CNN "TME" +DRAW +S 0 250 100 -250 0 1 0 f +X MH 0 200 -200 100 L 50 50 1 1 I +X 1 1 -100 200 100 R 50 50 1 1 B +X 2 2 -100 100 100 R 50 50 1 1 B +X 3 3 -100 0 100 R 50 50 1 1 I +X 4 4 -100 -100 100 R 50 50 1 1 I +X 5 5 -100 -200 100 R 50 50 1 1 I +ENDDRAW +ENDDEF +# +# MAX15062C-HD_PMICs +# +DEF MAX15062C-HD_PMICs U 0 40 Y Y 1 F N +F0 "U" -350 300 50 H V C CNN +F1 "MAX15062C-HD_PMICs" 100 300 50 H V C CNN +F2 "HD_DFN_QFN:TDFN-8-1EP_2x2mm_P0.5mm" 0 -450 50 H I C CNN +F3 "" -150 300 50 H I C CNN +F4 "Maxim Integrated" 0 -550 50 H I C CNN "Manufacturer" +F5 "MAX15062CATA+T" 0 -650 50 H I C CNN "Code" +F6 "MAX15062CATA+TCT-ND" 0 -750 50 H I C CNN "Digikey" +F7 "700-MAX15062CATA+T" 0 -850 50 H I C CNN "Mouser" +F8 "X" 0 -1050 50 H I C CNN "TME" +F9 "2516652" 0 -950 50 H I C CNN "Farnell" +DRAW +S -450 250 450 -250 0 1 0 f +X VIN 1 -550 200 100 R 50 50 1 1 I +X EN/UVLO 2 -550 100 100 R 50 50 1 1 I +X VCC 3 -550 -200 100 R 50 50 1 1 I +X FB/VOUT 4 550 100 100 L 50 50 1 1 I +X MODE 5 -550 -100 100 R 50 50 1 1 I +X nRST 6 -550 0 100 R 50 50 1 1 I +X GND 7 0 -350 100 U 50 50 1 1 I +X LX 8 550 200 100 L 50 50 1 1 w +ENDDRAW +ENDDEF +# +# NRS4018T330MDGJ-HD_Inductors +# +DEF NRS4018T330MDGJ-HD_Inductors L 0 40 N N 1 F N +F0 "L" 0 200 50 H V C CNN +F1 "NRS4018T330MDGJ-HD_Inductors" 0 -50 50 H V C CNN +F2 "HD_Inductors:L_NR40xx" 0 -150 50 H I C CNN +F3 "" 0 350 50 H I C CNN +F4 "33uH" 0 100 50 H V C CNN "Inductance" +F5 "550mA" 250 100 50 H I C CNN "Current Rating" +F6 "Taiyo Yuden" 0 -250 50 H I C CNN "Manufacturer" +F7 "NRS4018T330MDGJ" 0 -350 50 H I C CNN "Code" +F8 "587-2891-1-ND" 0 -450 50 H I C CNN "Digikey" +F9 "963-NRS4018T330MDGJ" 0 -550 50 H I C CNN "Mouser" +F10 "X" 0 -650 50 H I C CNN "Farnell" +F11 "X" 0 -750 50 H I C CNN "TME" +DRAW +A -75 0 25 1 1799 1 1 0 N -50 0 -100 0 +A -25 0 25 1 1799 1 1 0 N 0 0 -50 0 +A 25 0 25 1 1799 1 1 0 N 50 0 0 0 +A 75 0 25 1 1799 1 1 0 N 100 0 50 0 +X 1 1 -150 0 50 R 50 50 1 1 P +X 2 2 150 0 50 L 50 50 1 1 P +ENDDRAW +ENDDEF +# +# NRS4018T470MDGJ-HD_Inductors +# +DEF NRS4018T470MDGJ-HD_Inductors L 0 40 N N 1 F N +F0 "L" 0 200 50 H V C CNN +F1 "NRS4018T470MDGJ-HD_Inductors" 0 -50 50 H V C CNN +F2 "HD_Inductors:L_NR40xx" 0 -150 50 H I C CNN +F3 "" 0 350 50 H I C CNN +F4 "47uH" 0 100 50 H V C CNN "Inductance" +F5 "440mA" 250 100 50 H I C CNN "Current Rating" +F6 "Taiyo Yuden" 0 -250 50 H I C CNN "Manufacturer" +F7 "NRS4018T470MDGJ" 0 -350 50 H I C CNN "Code" +F8 "587-5935-1-ND" 0 -450 50 H I C CNN "Digikey" +F9 "963-NRS4018T470MDGJ" 0 -550 50 H I C CNN "Mouser" +F10 "X" 0 -650 50 H I C CNN "Farnell" +F11 "X" 0 -750 50 H I C CNN "TME" +DRAW +A -75 0 25 1 1799 1 1 0 N -50 0 -100 0 +A -25 0 25 1 1799 1 1 0 N 0 0 -50 0 +A 25 0 25 1 1799 1 1 0 N 50 0 0 0 +A 75 0 25 1 1799 1 1 0 N 100 0 50 0 +X 1 1 -150 0 50 R 50 50 1 1 P +X 2 2 150 0 50 L 50 50 1 1 P +ENDDRAW +ENDDEF +# +# NX3020NAKV,115-HD_Transistors +# +DEF NX3020NAKV,115-HD_Transistors Q 0 40 Y Y 2 L N +F0 "Q" -250 250 50 H V C CNN +F1 "NX3020NAKV,115-HD_Transistors" -100 -200 50 H V C CNN +F2 "HD_SOT:SOT−563-6" 0 -350 50 H I C CNN +F3 "" 0 -350 50 H I C CNN +F4 "Nexperia USA Inc." 0 -450 50 H I C CNN "Manufacturer" +F5 "NX3020NAKV,115" 0 -550 50 H I C CNN "Code" +F6 "ON Semiconductor" 950 -450 50 H I C CNN "Alt_Manufacturer" +F7 "FDY3000NZCT-ND" 950 -550 50 H I C CNN "Alt_Code" +F8 "1727-1287-1-ND" 0 -650 50 H I C CNN "Digikey" +F9 "771-NX3020NAKV115" 0 -750 50 H I C CNN "Mouser" +F10 "2311182" 0 -850 50 H I C CNN "Farnell" +F11 "X" 0 -950 50 H I C CNN "TME" +DRAW +S -300 200 300 -150 1 1 0 f +S -300 200 300 -150 2 1 0 f +P 2 1 1 0 -120 10 -110 10 N +P 2 1 1 0 -120 15 -110 15 N +P 2 1 1 0 -115 0 -130 -20 N +P 2 1 1 0 -115 0 -130 20 N +P 2 1 1 0 -115 0 -100 -20 N +P 2 1 1 0 -115 0 -100 20 N +P 2 1 1 0 -115 100 -115 -100 N +P 2 1 1 0 -110 -15 -120 -15 N +P 2 1 1 0 -110 -10 -120 -10 N +P 2 1 1 0 -75 0 75 0 N +P 2 1 1 0 -50 20 -50 100 N +P 2 1 1 0 -50 100 -300 100 N +P 2 1 1 0 -50 100 0 100 N +P 2 1 1 0 -10 135 -10 140 N +P 2 1 1 0 -10 165 -10 140 N +P 2 1 1 0 0 -50 0 -10 N +P 2 1 1 0 0 -10 0 0 N +P 2 1 1 0 0 20 -15 40 N +P 2 1 1 0 0 50 0 20 N +P 2 1 1 0 0 100 0 50 N +P 2 1 1 0 50 25 50 20 N +P 3 1 1 0 -300 -100 0 -100 0 -50 N +P 3 1 1 0 -130 20 -105 20 -100 20 N +P 3 1 1 0 -100 -20 -125 -20 -130 -20 N +P 3 1 1 0 -65 20 -40 20 -35 20 N +P 3 1 1 0 -15 20 10 20 15 20 N +P 3 1 1 0 -15 40 15 40 0 20 N +P 3 1 1 0 -10 40 -10 35 -5 35 N +P 3 1 1 0 -5 35 10 35 10 40 N +P 3 1 1 0 -5 140 -5 155 -5 160 N +P 3 1 1 0 35 20 60 20 65 20 N +P 3 1 1 0 50 25 50 100 300 100 N +P 4 1 1 0 -125 20 -125 15 -105 20 -105 15 N +P 4 1 1 0 -115 100 -115 150 115 150 115 100 N +P 4 1 1 0 -105 -20 -105 -15 -125 -20 -125 -15 N +P 4 1 1 0 -10 160 -10 140 5 150 -10 160 N +P 4 1 1 0 -5 35 5 35 0 30 -5 35 N +P 4 1 1 0 15 150 -15 170 -15 130 15 150 N +P 4 1 1 0 15 150 15 170 15 150 15 130 N +P 5 1 1 0 -145 -10 -135 0 -115 0 -95 0 -85 10 N +P 2 2 1 0 -120 10 -110 10 N +P 2 2 1 0 -120 15 -110 15 N +P 2 2 1 0 -115 0 -130 -20 N +P 2 2 1 0 -115 0 -130 20 N +P 2 2 1 0 -115 0 -100 -20 N +P 2 2 1 0 -115 0 -100 20 N +P 2 2 1 0 -115 100 -115 -100 N +P 2 2 1 0 -110 -15 -120 -15 N +P 2 2 1 0 -110 -10 -120 -10 N +P 2 2 1 0 -75 0 75 0 N +P 2 2 1 0 -50 20 -50 100 N +P 2 2 1 0 -50 100 -300 100 N +P 2 2 1 0 -10 135 -10 140 N +P 2 2 1 0 -10 165 -10 140 N +P 2 2 1 0 0 -50 0 -10 N +P 2 2 1 0 0 -10 0 0 N +P 2 2 1 0 0 20 -15 40 N +P 2 2 1 0 0 50 0 20 N +P 2 2 1 0 0 100 -50 100 N +P 2 2 1 0 0 100 0 50 N +P 2 2 1 0 50 20 50 100 N +P 2 2 1 0 300 100 50 100 N +P 3 2 1 0 -300 -100 0 -100 0 -50 N +P 3 2 1 0 -130 20 -105 20 -100 20 N +P 3 2 1 0 -100 -20 -125 -20 -130 -20 N +P 3 2 1 0 -65 20 -40 20 -35 20 N +P 3 2 1 0 -15 20 10 20 15 20 N +P 3 2 1 0 -15 40 15 40 0 20 N +P 3 2 1 0 -10 40 -10 35 -5 35 N +P 3 2 1 0 -5 35 10 35 10 40 N +P 3 2 1 0 -5 140 -5 155 -5 160 N +P 3 2 1 0 35 20 60 20 65 20 N +P 4 2 1 0 -125 20 -125 15 -105 20 -105 15 N +P 4 2 1 0 -115 100 -115 150 115 150 115 100 N +P 4 2 1 0 -105 -20 -105 -15 -125 -20 -125 -15 N +P 4 2 1 0 -10 160 -10 140 5 150 -10 160 N +P 4 2 1 0 -5 35 5 35 0 30 -5 35 N +P 4 2 1 0 15 150 -15 170 -15 130 15 150 N +P 4 2 1 0 15 150 15 170 15 150 15 130 N +P 5 2 1 0 -145 -10 -135 0 -115 0 -95 0 -85 10 N +X S1 1 -400 100 100 R 50 50 1 1 B +X G1 2 -400 -100 100 R 50 50 1 1 B +X D1 6 400 100 100 L 50 50 1 1 B +X D2 3 400 100 100 L 50 50 2 1 B +X S2 4 -400 100 100 R 50 50 2 1 B +X G2 5 -400 -100 100 R 50 50 2 1 B +ENDDRAW +ENDDEF +# +# PMEG2005EJ115-HD_Diodes +# +DEF PMEG2005EJ115-HD_Diodes D 0 40 N N 1 F N +F0 "D" 0 100 50 H V C CNN +F1 "PMEG2005EJ115-HD_Diodes" 0 -100 50 H V C CNN +F2 "HD_Diodes:D_SOD-323F" 0 -200 50 H I C CNN +F3 "" 0 -300 50 H I C CNN +F4 "Nexperia" 0 -300 50 H I C CNN "Manufacturer" +F5 " 771-PMEG2005EJ115" 0 -400 50 H I C CNN "Code" +F6 "1727-3854-1-ND" 0 -500 50 H I C CNN "Digikey" +F7 "771-PMEG2005EJ115" 0 -600 50 H I C CNN "Mouser" +F8 "1757760" 0 -700 50 H I C CNN "Farnell" +F9 "PMEG2005EJ.115" 0 -800 50 H I C CNN "TME" +$FPLIST + TO-???* + *_Diode_* + *SingleDiode* + D_* +$ENDFPLIST +DRAW +P 2 1 1 0 50 0 -50 0 N +P 4 1 1 8 50 50 50 -50 -50 0 50 50 N +P 6 1 1 8 -75 25 -75 50 -50 50 -50 -50 -25 -50 -25 -25 N +X K 1 -150 0 100 R 50 50 1 1 P +X A 2 150 0 100 L 50 50 1 1 P +ENDDRAW +ENDDEF +# +# R0402_100k_5%_1d16W-HD_Resistors +# +DEF R0402_100k_5%_1d16W-HD_Resistors R 0 40 N N 1 F N +F0 "R" 100 50 50 H V C CNN +F1 "R0402_100k_5%_1d16W-HD_Resistors" 0 -200 50 H I C CNN +F2 "HD_Resistors:R0402" 0 -300 50 H I C CNN +F3 "" 0 0 50 H I C CNN +F4 "100k" 150 -50 50 H V C CNN "Resistance" +F5 "1/16W" 300 50 50 H I C CNN "Power" +F6 "5%" 300 -50 50 H I C CNN "Precision" +F7 "Yageo" 0 -400 50 H I C CNN "Manufacturer" +F8 "RC0402JR-07100KL" 0 -500 50 H I C CNN "Code" +F9 "Stackpole Electronics Inc" 800 -400 50 H I C CNN "Alt_Manufacturer" +F10 "RMCF0402FT100K" 800 -500 50 H I C CNN "Alt_Code" +F11 "311-100KJRCT-ND" 0 -600 50 H I C CNN "Digikey" +F12 "603-RC0402JR-07100KL" 0 -700 50 H I C CNN "Mouser" +F13 "9233008" 0 -800 50 H I C CNN "Farnell" +F14 "RC0402JR-07100KL" 0 -900 50 H I C CNN "TME" +DRAW +S -40 -100 40 100 1 1 10 N +X ~ 1 0 150 50 D 50 50 1 1 P +X ~ 2 0 -150 50 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# R0402_10k_5%_1d16W-HD_Resistors +# +DEF R0402_10k_5%_1d16W-HD_Resistors R 0 40 N N 1 F N +F0 "R" 100 50 50 H V C CNN +F1 "R0402_10k_5%_1d16W-HD_Resistors" 0 -200 50 H I C CNN +F2 "HD_Resistors:R0402" 0 -300 50 H I C CNN +F3 "" 0 0 50 H I C CNN +F4 "10k" 150 -50 50 H V C CNN "Resistance" +F5 "1/16W" 300 50 50 H I C CNN "Power" +F6 "5%" 300 -50 50 H I C CNN "Precision" +F7 "Yageo" 0 -400 50 H I C CNN "Manufacturer" +F8 "RC0402JR-0710KL" 0 -500 50 H I C CNN "Code" +F9 "Stackpole Electronics Inc" 800 -400 50 H I C CNN "Alt_Manufacturer" +F10 "RMCF0402JT10K0" 800 -500 50 H I C CNN "Alt_Code" +F11 "311-10KJRCT-ND" 0 -600 50 H I C CNN "Digikey" +F12 "603-RC0402JR-0710KL" 0 -700 50 H I C CNN "Mouser" +F13 "*" 0 -800 50 H I C CNN "Farnell" +F14 "SMD0402-10K" 0 -900 50 H I C CNN "TME" +DRAW +S -40 -100 40 100 1 1 10 N +X ~ 1 0 150 50 D 50 50 1 1 P +X ~ 2 0 -150 50 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# R0402_120R_1%_1d16W-HD_Resistors +# +DEF R0402_120R_1%_1d16W-HD_Resistors R 0 40 N N 1 F N +F0 "R" 100 50 50 H V C CNN +F1 "R0402_120R_1%_1d16W-HD_Resistors" 0 -200 50 H I C CNN +F2 "HD_Resistors:R0402" 0 -300 50 H I C CNN +F3 "" 0 0 50 H I C CNN +F4 "120R" 150 -50 50 H V C CNN "Resistance" +F5 "1/16W" 300 50 50 H I C CNN "Power" +F6 "1%" 300 -50 50 H I C CNN "Precision" +F7 "Yageo" 0 -400 50 H I C CNN "Manufacturer" +F8 "RC0402JR-07120RL" 0 -500 50 H I C CNN "Code" +F9 "Stackpole Electronics Inc" 800 -400 50 H I C CNN "Alt_Manufacturer" +F10 "RMCF0402JT120R" 800 -500 50 H I C CNN "Alt_Code" +F11 "311-120JRCT-ND" 0 -600 50 H I C CNN "Digikey" +F12 "603-RC0402JR-07120RL" 0 -700 50 H I C CNN "Mouser" +F13 "9232656" 0 -800 50 H I C CNN "Farnell" +F14 "RC0402FR-07120RL" 0 -900 50 H I C CNN "TME" +DRAW +S -40 -100 40 100 1 1 10 N +X ~ 1 0 150 50 D 50 50 1 1 P +X ~ 2 0 -150 50 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# R0402_1k_1%_1d16W-HD_Resistors +# +DEF R0402_1k_1%_1d16W-HD_Resistors R 0 40 N N 1 F N +F0 "R" 100 50 50 H V C CNN +F1 "R0402_1k_1%_1d16W-HD_Resistors" 0 -200 50 H I C CNN +F2 "HD_Resistors:R0402" 0 -300 50 H I C CNN +F3 "" 0 0 50 H I C CNN +F4 "1k" 100 -50 50 H V C CNN "Resistance" +F5 "1/16W" 300 50 50 H I C CNN "Power" +F6 "1%" 300 -50 50 H I C CNN "Precision" +F7 "Yageo" 0 -400 50 H I C CNN "Manufacturer" +F8 "AC0402FR-071KL" 0 -500 50 H I C CNN "Code" +F9 "TE Connectivity Passive Product" 800 -400 50 H I C CNN "Alt_Manufacturer" +F10 "CRGCQ0402F1K0" 800 -500 50 H I C CNN "Alt_Code" +F11 "311-1KLBCT-ND" 0 -600 50 H I C CNN "Digikey" +F12 "603-RC0402JR-131KL" 0 -700 50 H I C CNN "Mouser" +F13 "3495181" 0 -800 50 H I C CNN "Farnell" +F14 "SMD0402-1K" 0 -900 50 H I C CNN "TME" +DRAW +S -40 -100 40 100 1 1 10 N +X ~ 1 0 150 50 D 50 50 1 1 P +X ~ 2 0 -150 50 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# R0402_267k_1%_1d16W-HD_Resistors +# +DEF R0402_267k_1%_1d16W-HD_Resistors R 0 40 N N 1 F N +F0 "R" 100 50 50 H V C CNN +F1 "R0402_267k_1%_1d16W-HD_Resistors" 0 -200 50 H I C CNN +F2 "HD_Resistors:R0402" 0 -300 50 H I C CNN +F3 "" 0 0 50 H I C CNN +F4 "267k" 150 -50 50 H V C CNN "Resistance" +F5 "1/16W" 300 50 50 H I C CNN "Power" +F6 "1%" 300 -50 50 H I C CNN "Precision" +F7 "Yageo" 0 -400 50 H I C CNN "Manufacturer" +F8 "AC0402FR-07267KL" 0 -500 50 H I C CNN "Code" +F9 "Stackpole Electronics Inc" 800 -400 50 H I C CNN "Alt_Manufacturer" +F10 "RMCF0402FT267KCT-ND" 800 -500 50 H I C CNN "Alt_Code" +F11 "YAG5275CT-ND" 0 -600 50 H I C CNN "Digikey" +F12 "603-AC0402FR-07267KL " 0 -700 50 H I C CNN "Mouser" +F13 "2140969" 0 -800 50 H I C CNN "Farnell" +F14 "X" 0 -900 50 H I C CNN "TME" +DRAW +S -40 -100 40 100 1 1 10 N +X ~ 1 0 150 50 D 50 50 1 1 P +X ~ 2 0 -150 50 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# R0402_453k_1%_1d16W-HD_Resistors +# +DEF R0402_453k_1%_1d16W-HD_Resistors R 0 40 N N 1 F N +F0 "R" 100 50 50 H V C CNN +F1 "R0402_453k_1%_1d16W-HD_Resistors" 0 -200 50 H I C CNN +F2 "HD_Resistors:R0402" 0 -300 50 H I C CNN +F3 "" 0 0 50 H I C CNN +F4 "453k" 150 -50 50 H V C CNN "Resistance" +F5 "1/16W" 300 50 50 H I C CNN "Power" +F6 "1%" 300 -50 50 H I C CNN "Precision" +F7 "Yageo" 0 -400 50 H I C CNN "Manufacturer" +F8 "RC0402FR-07453KL" 0 -500 50 H I C CNN "Code" +F9 "Stackpole Electronics Inc" 800 -400 50 H I C CNN "Alt_Manufacturer" +F10 "RMCF0402FT453K" 800 -500 50 H I C CNN "Alt_Code" +F11 "YAG3164CT-ND" 0 -600 50 H I C CNN "Digikey" +F12 "603-RC0402FR-07453KL" 0 -700 50 H I C CNN "Mouser" +F13 "2140999" 0 -800 50 H I C CNN "Farnell" +F14 "RC0402FR-07453KL" 0 -900 50 H I C CNN "TME" +DRAW +S -40 -100 40 100 1 1 10 N +X ~ 1 0 150 50 D 50 50 1 1 P +X ~ 2 0 -150 50 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# SCD40-D-R2-HD_Sensors +# +DEF SCD40-D-R2-HD_Sensors U 0 40 Y Y 1 F N +F0 "U" 0 350 50 H V C CNN +F1 "SCD40-D-R2-HD_Sensors" 0 250 50 H V C CNN +F2 "HD_Sensors:SCD4x" 0 -250 50 H I C CNN +F3 "" 0 50 50 H I C CNN +F4 "Sensirion AG" 0 -350 50 H I C CNN "Manufacturer" +F5 "SCD40-D-R2" 0 -450 50 H I C CNN "Code" +F6 "1649-SCD40-D-R2CT-ND" 0 -550 50 H I C CNN "Digikey" +F7 "X" 0 -650 50 H I C CNN "Mouser" +F8 "X" 0 -750 50 H I C CNN "Farnell" +F9 "X" 0 -850 50 H I C CNN "TME" +DRAW +S 250 200 -250 -200 0 1 0 f +X VSS 0 -350 -150 100 R 50 50 1 1 W N +X DNC 1 -50 150 100 R 50 50 1 1 N N +X SDA 10 350 50 100 L 50 50 1 1 B +X DNC 11 -200 150 100 R 50 50 1 1 N N +X DNC 12 -200 100 100 R 50 50 1 1 N N +X DNC 13 -200 50 100 R 50 50 1 1 N N +X DNC 14 -50 50 100 R 50 50 1 1 N N +X DNC 15 -200 0 100 R 50 50 1 1 N N +X DNC 16 -50 0 100 R 50 50 1 1 N N +X DNC 17 -200 -50 100 R 50 50 1 1 N N +X DNC 18 -50 -50 100 R 50 50 1 1 N N +X VDDH 19 -350 50 100 R 50 50 1 1 W +X DNC 2 -200 -100 100 R 50 50 1 1 N N +X VSS 20 -350 -150 100 R 50 50 1 1 W N +X DNC 3 -50 -100 100 R 50 50 1 1 N N +X DNC 4 -200 -150 100 R 50 50 1 1 N N +X DNC 5 -50 -150 100 R 50 50 1 1 N N +X VSS 6 -350 -150 100 R 50 50 1 1 W +X VDD 7 -350 150 100 R 50 50 1 1 W +X DNC 8 -50 100 100 R 50 50 1 1 N N +X SCL 9 350 -50 100 L 50 50 1 1 B +ENDDRAW +ENDDEF +# +# SD24-7-HD_Diodes +# +DEF SD24-7-HD_Diodes D 0 40 N N 1 F N +F0 "D" 0 100 50 H V C CNN +F1 "SD24-7-HD_Diodes" 0 -100 50 H V C CNN +F2 "HD_Diodes:D_SOD-323" 0 -200 50 H I C CNN +F3 "" 0 -300 50 H I C CNN +F4 "Diodes Incorporated" 0 -300 50 H I C CNN "Manufacturer" +F5 "SD24-7" 0 -400 50 H I C CNN "Code" +F6 "31-SD24-7CT-ND" 0 -500 50 H I C CNN "Digikey" +F7 "621-SD24-7" 0 -600 50 H I C CNN "Mouser" +F8 "X" 0 -700 50 H I C CNN "Farnell" +F9 "X" 0 -800 50 H I C CNN "TME" +$FPLIST + TO-???* + *_Diode_* + *SingleDiode* + D_* +$ENDFPLIST +DRAW +P 2 1 1 0 50 0 -50 0 N +P 4 1 1 0 -75 50 -50 25 -50 -25 -25 -50 N +P 4 1 1 8 50 50 50 -50 -50 0 50 50 N +X K 1 -150 0 100 R 50 50 1 1 P +X A 2 150 0 100 L 50 50 1 1 P +ENDDRAW +ENDDEF +# +# SHT40-AD1B-R2-HD_Sensors +# +DEF SHT40-AD1B-R2-HD_Sensors U 0 40 Y Y 1 F N +F0 "U" 0 350 50 H V C CNN +F1 "SHT40-AD1B-R2-HD_Sensors" 0 250 50 H V C CNN +F2 "HD_Sensors:SHT4x" 0 -250 50 H I C CNN +F3 "" 0 50 50 H I C CNN +F4 "Sensirion AG" 0 -350 50 H I C CNN "Manufacturer" +F5 "SHT40-AD1B-R2" 0 -450 50 H I C CNN "Code" +F6 "1649-SHT40-AD1B-R2CT-ND" 0 -550 50 H I C CNN "Digikey" +F7 "403-SHT40-AD1B-R2" 0 -650 50 H I C CNN "Mouser" +F8 "3586476" 0 -750 50 H I C CNN "Farnell" +F9 "SHT40-AD1B-R2" 0 -850 50 H I C CNN "TME" +DRAW +S 250 200 -250 -200 0 1 0 f +X SDA 1 350 50 100 L 50 50 1 1 B +X SCL 2 350 -50 100 L 50 50 1 1 B +X VDD 3 -350 150 100 R 50 50 1 1 W +X VSS 4 -350 -150 100 R 50 50 1 1 W +ENDDRAW +ENDDEF +# +# STM32L011F4U6TR-HD_MCUs +# +DEF STM32L011F4U6TR-HD_MCUs U 0 40 Y Y 1 F N +F0 "U" -300 600 50 H V C CNN +F1 "STM32L011F4U6TR-HD_MCUs" 450 600 50 H V C CNN +F2 "HD_DFN_QFN:ST_UFQFPN-20_3x3mm_P0.5mm" 0 -750 50 H I C CNN +F3 "" -50 800 50 H I C CNN +F4 "STMicroelectronics" 0 -850 50 H I C CNN "Manufacturer" +F5 "STM32L011F4U6TR" 0 -950 50 H I C CNN "Code" +F6 "497-17478-1-ND" 0 -1050 50 H I C CNN "Digikey" +F7 "511-STM32L011F4U6TR" 0 -1150 50 H I C CNN "Mouser" +F8 "2851005" 0 -1250 50 H I C CNN "Farnell" +F9 "STM32L011F4U6TR" 0 -1350 50 H I C CNN "TME" +DRAW +S -350 -550 350 550 1 1 10 f +X PC14 1 -450 150 100 R 50 50 1 1 B +X PA7 10 450 -50 100 L 50 50 1 1 B +X PB1 11 -450 -150 100 R 50 50 1 1 B +X VSS 12 -50 -650 100 U 50 50 1 1 W +X VDD 13 -50 650 100 D 50 50 1 1 W +X PA9 14 450 -150 100 L 50 50 1 1 B +X PA10 15 450 -250 100 L 50 50 1 1 B +X PA13 16 450 -350 100 L 50 50 1 1 B +X PA14 17 450 -450 100 L 50 50 1 1 B +X PB6 18 -450 -250 100 R 50 50 1 1 B +X PB7 19 -450 -350 100 R 50 50 1 1 B +X PC15 2 -450 50 100 R 50 50 1 1 B +X PB9 20 -450 -450 100 R 50 50 1 1 B +X NRST 3 -450 450 100 R 50 50 1 1 I +X VDDA 4 50 650 100 D 50 50 1 1 W +X PA0 5 450 450 100 L 50 50 1 1 B +X PA1 6 450 350 100 L 50 50 1 1 B +X PA4 7 450 250 100 L 50 50 1 1 B +X PA5 8 450 150 100 L 50 50 1 1 B +X PA6 9 450 50 100 L 50 50 1 1 B +ENDDRAW +ENDDEF +# +# SWD_Connector-HD_Connectors +# +DEF SWD_Connector-HD_Connectors SWD 0 1 Y Y 1 F N +F0 "SWD" 100 300 50 H V C CNN +F1 "SWD_Connector-HD_Connectors" 50 -300 50 H V C CNN +F2 "HD_Connectors:SWD_Connector_for_PogoHeader" 50 -400 50 H I C CNN +F3 "" -450 -300 50 H I C CNN +F4 "X" 50 -600 50 H I C CNN "Mouser" +F5 "X" 50 -700 50 H I C CNN "Farnell" +F6 "X" 50 -800 50 H I C CNN "TME" +F7 "X" 50 -500 50 H I C CNN "Digikey" +DRAW +S 0 250 250 -250 0 1 0 f +X 3V3 1 -100 200 100 R 50 50 1 1 B +X GND 2 -100 100 100 R 50 50 1 1 B +X SWDIO 3 -100 0 100 R 50 50 1 1 I +X SWCLK 4 -100 -100 100 R 50 50 1 1 I +X NRST 5 -100 -200 100 R 50 50 1 1 I +ENDDRAW +ENDDEF +# +# Sullins_SWR204-NRTN-D02-RA-GA-HD_Connectors +# +DEF Sullins_SWR204-NRTN-D02-RA-GA-HD_Connectors J 0 40 Y N 1 F N +F0 "J" 50 250 50 H V C CNN +F1 "Sullins_SWR204-NRTN-D02-RA-GA-HD_Connectors" 50 350 50 H I C CNN +F2 "HD_Connectors:Sullins_SWR204-NRTN-D02-RA-GA" 0 -250 50 H I C CNN +F3 "" 0 0 50 H I C CNN +F4 "Sullins Connector Solutions" 0 -350 50 H I C CNN "Manufacturer" +F5 "SWR204-NRTN-D02-RA-GA" 0 -450 50 H I C CNN "Code" +F6 "S9461-ND" 0 -550 50 H I C CNN "Digikey" +F7 "X" 0 -650 50 H I C CNN "Mouser" +F8 "X" 0 -750 50 H I C CNN "Farnell" +F9 "X" 0 -850 50 H I C CNN "TME" +DRAW +S 0 200 100 -200 0 1 0 f +X 1 1 -100 150 100 R 50 50 1 1 I +X 2 2 -100 50 100 R 50 50 1 1 I +X 3 3 -100 -50 100 R 50 50 1 1 I +X 4 4 -100 -150 100 R 50 50 1 1 I +ENDDRAW +ENDDEF +# +# THVD1450DRBR-HD_Communication +# +DEF THVD1450DRBR-HD_Communication U 0 40 Y Y 1 F N +F0 "U" -250 450 50 H V C CNN +F1 "THVD1450DRBR-HD_Communication" 350 450 50 H V C CNN +F2 "HD_SON:Texas_VSON8" 0 -650 50 H I C CNN +F3 "" 0 450 50 H I C CNN +F4 "Texas Instruments" 0 -750 50 H I C CNN "Manufacturer" +F5 "THVD1450DRBR" 0 -850 50 H I C CNN "Code" +F6 "296-THVD1450DRBRCT-ND" 0 -950 50 H I C CNN "Digikey" +F7 "595-THVD1450DRBR" 0 -1050 50 H I C CNN "Mouser" +F8 "X" 0 -1150 50 H I C CNN "Farnell" +F9 "X" 0 -1250 50 H I C CNN "TME" +DRAW +C -12 -145 14 1 1 10 F +C -1 59 14 1 1 10 F +C 65 75 14 1 1 10 F +S -300 400 300 -500 1 1 10 f +S 50 125 50 125 1 1 0 N +P 2 1 1 10 -160 -200 -75 -200 N +P 2 1 1 10 -160 100 -50 100 N +P 2 1 1 10 -50 -126 -50 -136 N +P 2 1 1 10 -25 -200 210 -200 N +P 3 1 1 10 -160 -100 -50 -100 -50 -125 N +P 3 1 1 10 0 50 0 0 -160 0 N +P 3 1 1 10 50 125 150 125 150 -200 N +P 3 1 1 10 100 75 100 -150 0 -150 N +P 4 1 1 10 -75 -125 -75 -225 25 -175 -75 -125 N +P 4 1 1 10 -50 100 50 150 50 50 -50 100 N +P 4 1 1 10 75 75 175 75 175 100 210 100 N +X ePAD 0 0 -600 100 U 50 50 1 1 I N +X RO 1 -400 100 100 R 50 50 1 1 O +X ~RE 2 -400 0 100 R 50 50 1 1 I +X DE 3 -400 -100 100 R 50 50 1 1 I +X DI 4 -400 -200 100 R 50 50 1 1 I +X GND 5 0 -600 100 U 50 50 1 1 W +X A 6 400 -200 100 L 50 50 1 1 B +X B 7 400 100 100 L 50 50 1 1 B +X VCC 8 0 500 100 D 50 50 1 1 W +ENDDRAW +ENDDEF +# +# VCC-HD_Power_Symbols +# +DEF VCC-HD_Power_Symbols #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -150 50 H I C CNN +F1 "VCC-HD_Power_Symbols" 0 150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 2 0 1 0 -30 50 0 100 N +P 2 0 1 0 0 0 0 100 N +P 2 0 1 0 0 100 30 50 N +X VCC 1 0 0 0 U 50 50 1 1 W N +ENDDRAW +ENDDEF +# +#End Library diff --git a/PCB/iaq_wired_sensor.csv b/PCB/iaq_wired_sensor.csv new file mode 100755 index 0000000..f592998 --- /dev/null +++ b/PCB/iaq_wired_sensor.csv @@ -0,0 +1,27 @@ +Reference,Quantity,Value,Manufacturer,Code,Description,Cmp name,Footprint,Mouser,Digikey +"C1, ",1,C1210_22uF_35V_X5R,Taiyo Yuden,GMK325BJ226MM-P,,C1210_22uF_35V_X5R,HD_Capacitors:C1210,963-GMK325BJ226MM-P,587-5853-1-ND +"C21, C22, C11, C12, ",4,C0402_1uF_35V_X5R,TDK Corporation,C1005X5R1V105K050BE,,C0402_1uF_35V_X5R,HD_Capacitors:C0402,810-C1005X5R1V105K,445-175218-1-ND +"C23, C13, C31, ",3,C0603_10uF_16V_X5R,Taiyo Yuden,EMK107BBJ106MA-T,,C0603_10uF_16V_X5R,HD_Capacitors:C0603,963-EMK107BBJ106MA-T,587-3238-1-ND +"C41, C51, C61, C33, C32, ",5,C0402_100nF_50V_X7R,Murata Electronics,GRM155R71H104KE14D,,C0402_100nF_50V_X7R,HD_Capacitors:C0402,81-GRM155R71H104KE4D,490-10700-1-ND +"D1, ",1,AQ12-02HTG,Littelfuse Inc.,AQ12-02HTG,,AQ12-02HTG,HD_SOT:SOT-23,576-AQ12-02HTG,18-AQ12-02HTGCT-ND +"D2, ",1,PMEG2005EJ115,Nexperia, 771-PMEG2005EJ115,,PMEG2005EJ115,HD_Diodes:D_SOD-323F,771-PMEG2005EJ115,1727-3854-1-ND +"D3, ",1,SD24-7,Diodes Incorporated,SD24-7,,SD24-7,HD_Diodes:D_SOD-323,621-SD24-7,31-SD24-7CT-ND +"F1, ",1,0686F0500-01,Bel Fuse Inc.,0686F0500-01,,0686F0500-01,HD_Other:F0603,530-0686F0500-01,507-2156-1-ND +"F2, ",1,0ZCJ0010FF2E,Bel Fuse Inc.,0ZCJ0010FF2E,,0ZCJ0010FF2E,HD_Other:F1206,530-0ZCJ0010FF2E,507-1794-1-ND +"J1, ",1,Sullins_SWR204-NRTN-D02-RA-GA,Sullins Connector Solutions,SWR204-NRTN-D02-RA-GA,,Sullins_SWR204-NRTN-D02-RA-GA,HD_Connectors:Sullins_SWR204-NRTN-D02-RA-GA,X,S9461-ND +"J2, ",1,JST_ZH5_Side_Entry_S5B-ZR-SM4A-TF,,,,JST_ZH5_Side_Entry_S5B-ZR-SM4A-TF,HD_Connectors:JST_ZH_5PIN_S5B-ZR-SM4A-TF,X,455-1696-1-ND +"L11, ",1,NRS4018T330MDGJ,Taiyo Yuden,NRS4018T330MDGJ,,NRS4018T330MDGJ,HD_Inductors:L_NR40xx,963-NRS4018T330MDGJ,587-2891-1-ND +"L21, ",1,NRS4018T470MDGJ,Taiyo Yuden,NRS4018T470MDGJ,,NRS4018T470MDGJ,HD_Inductors:L_NR40xx,963-NRS4018T470MDGJ,587-5935-1-ND +"LD1, ",1,ASMB-KTF0-0A306,Broadcom Limited,ASMB-KTF0-0A306,,ASMB-KTF0-0A306,HD_Diodes:LED_ASMB-KTF0-0A306,630-ASMB-KTF0-0A306,516-3906-1-ND +"Q1, ",1,"NX3020NAKV,115",Nexperia USA Inc.,"NX3020NAKV,115",,"NX3020NAKV,115",HD_SOT:SOT−563-6,771-NX3020NAKV115,1727-1287-1-ND +"R11, ",1,R0402_267k_1%_1d16W,Yageo,AC0402FR-07267KL,,R0402_267k_1%_1d16W,HD_Resistors:R0402,603-AC0402FR-07267KL ,YAG5275CT-ND +"R21, ",1,R0402_453k_1%_1d16W,Yageo,RC0402FR-07453KL,,R0402_453k_1%_1d16W,HD_Resistors:R0402,603-RC0402FR-07453KL,YAG3164CT-ND +"R22, R12, ",2,R0402_100k_5%_1d16W,Yageo,RC0402JR-07100KL,,R0402_100k_5%_1d16W,HD_Resistors:R0402,603-RC0402JR-07100KL,311-100KJRCT-ND +"R32, R31, R42, R41, ",4,R0402_10k_5%_1d16W,Yageo,RC0402JR-0710KL,,R0402_10k_5%_1d16W,HD_Resistors:R0402,603-RC0402JR-0710KL,311-10KJRCT-ND +"R34, R33, R35, ",3,R0402_1k_1%_1d16W,Yageo,AC0402FR-071KL,,R0402_1k_1%_1d16W,HD_Resistors:R0402,603-RC0402JR-131KL,311-1KLBCT-ND +"R61, ",1,R0402_120R_1%_1d16W,Yageo,RC0402JR-07120RL,,R0402_120R_1%_1d16W,HD_Resistors:R0402,603-RC0402JR-07120RL,311-120JRCT-ND +"U2, U1, ",2,MAX15062C,Maxim Integrated,MAX15062CATA+T,,MAX15062C,HD_DFN_QFN:TDFN-8-1EP_2x2mm_P0.5mm,700-MAX15062CATA+T,MAX15062CATA+TCT-ND +"U3, ",1,STM32L011F4U6TR,STMicroelectronics,STM32L011F4U6TR,,STM32L011F4U6TR,HD_DFN_QFN:ST_UFQFPN-20_3x3mm_P0.5mm,511-STM32L011F4U6TR,497-17478-1-ND +"U4, ",1,SHT40-AD1B-R2,Sensirion AG,SHT40-AD1B-R2,,SHT40-AD1B-R2,HD_Sensors:SHT4x,403-SHT40-AD1B-R2,1649-SHT40-AD1B-R2CT-ND +"U5, ",1,SCD40-D-R2,Sensirion AG,SCD40-D-R2,,SCD40-D-R2,HD_Sensors:SCD4x,X,1649-SCD40-D-R2CT-ND +"U6, ",1,THVD1450DRBR,Texas Instruments,THVD1450DRBR,,THVD1450DRBR,HD_SON:Texas_VSON8,595-THVD1450DRBR,296-THVD1450DRBRCT-ND diff --git a/PCB/sym-lib-table b/PCB/sym-lib-table new file mode 100644 index 0000000..fa8c0e2 --- /dev/null +++ b/PCB/sym-lib-table @@ -0,0 +1,3 @@ +(sym_lib_table + (lib (name iaq_wired_sensor-rescue)(type Legacy)(uri ${KIPRJMOD}/iaq_wired_sensor-rescue.lib)(options "")(descr "")) +) diff --git a/fw/.cproject b/fw/.cproject index 8fd8e0b..a34ddb9 100644 --- a/fw/.cproject +++ b/fw/.cproject @@ -1,172 +1,360 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fw/.mxproject b/fw/.mxproject index 4092066..95a213c 100644 --- a/fw/.mxproject +++ b/fw/.mxproject @@ -1,25 +1,26 @@ [PreviousLibFiles] -LibFiles=Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h;Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma_ex.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_exti.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h;Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma_ex.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_exti.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h;Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l011xx.h;Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h;Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h;Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/system_stm32l0xx.c;Drivers/CMSIS/Include/core_cm0.h;Drivers/CMSIS/Include/core_armv8mbl.h;Drivers/CMSIS/Include/core_cm1.h;Drivers/CMSIS/Include/cmsis_gcc.h;Drivers/CMSIS/Include/mpu_armv8.h;Drivers/CMSIS/Include/core_cm3.h;Drivers/CMSIS/Include/core_sc300.h;Drivers/CMSIS/Include/core_cm23.h;Drivers/CMSIS/Include/core_cm7.h;Drivers/CMSIS/Include/tz_context.h;Drivers/CMSIS/Include/mpu_armv7.h;Drivers/CMSIS/Include/core_armv8mml.h;Drivers/CMSIS/Include/core_sc000.h;Drivers/CMSIS/Include/cmsis_version.h;Drivers/CMSIS/Include/core_cm0plus.h;Drivers/CMSIS/Include/cmsis_armclang.h;Drivers/CMSIS/Include/cmsis_iccarm.h;Drivers/CMSIS/Include/cmsis_compiler.h;Drivers/CMSIS/Include/cmsis_armcc.h;Drivers/CMSIS/Include/core_cm33.h;Drivers/CMSIS/Include/core_cm4.h; +LibFiles=Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h;Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma_ex.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_exti.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_crs.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h;Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma_ex.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_exti.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_crs.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_tim_ex.h;Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l011xx.h;Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h;Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h;Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/system_stm32l0xx.c;Drivers/CMSIS/Include/core_cm4.h;Drivers/CMSIS/Include/tz_context.h;Drivers/CMSIS/Include/cmsis_compiler.h;Drivers/CMSIS/Include/mpu_armv7.h;Drivers/CMSIS/Include/core_cm7.h;Drivers/CMSIS/Include/core_cm0.h;Drivers/CMSIS/Include/cmsis_armcc.h;Drivers/CMSIS/Include/core_cm23.h;Drivers/CMSIS/Include/core_sc000.h;Drivers/CMSIS/Include/cmsis_version.h;Drivers/CMSIS/Include/core_cm1.h;Drivers/CMSIS/Include/core_cm0plus.h;Drivers/CMSIS/Include/cmsis_armclang.h;Drivers/CMSIS/Include/cmsis_iccarm.h;Drivers/CMSIS/Include/cmsis_gcc.h;Drivers/CMSIS/Include/core_sc300.h;Drivers/CMSIS/Include/core_cm3.h;Drivers/CMSIS/Include/mpu_armv8.h;Drivers/CMSIS/Include/core_cm33.h;Drivers/CMSIS/Include/core_armv8mml.h;Drivers/CMSIS/Include/core_armv8mbl.h; [PreviousUsedCubeIDEFiles] -SourceFiles=Core/Src/main.c;Core/Src/stm32l0xx_it.c;Core/Src/stm32l0xx_hal_msp.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c;Core/Src/system_stm32l0xx.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c;Core/Src/system_stm32l0xx.c;Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/system_stm32l0xx.c;; +SourceFiles=Core/Src/main.c;Core/Src/stm32l0xx_it.c;Core/Src/stm32l0xx_hal_msp.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c;Core/Src/system_stm32l0xx.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c;Core/Src/system_stm32l0xx.c;Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/system_stm32l0xx.c;; HeaderPath=Drivers/STM32L0xx_HAL_Driver/Inc;Drivers/STM32L0xx_HAL_Driver/Inc/Legacy;Drivers/CMSIS/Device/ST/STM32L0xx/Include;Drivers/CMSIS/Include;Core/Inc; -CDefines=USE_HAL_DRIVER;STM32L011xx;USE_HAL_DRIVER;USE_HAL_DRIVER; +CDefines=USE_FULL_LL_DRIVER;USE_HAL_DRIVER;STM32L011xx;USE_FULL_LL_DRIVER;USE_HAL_DRIVER;USE_HAL_DRIVER; [PreviousGenFiles] AdvancedFolderStructure=true -HeaderFileListSize=3 -HeaderFiles#0=/home/user/HDIoT/iaq_wired_sensor/fw/Core/Inc/stm32l0xx_it.h -HeaderFiles#1=/home/user/HDIoT/iaq_wired_sensor/fw/Core/Inc/stm32l0xx_hal_conf.h -HeaderFiles#2=/home/user/HDIoT/iaq_wired_sensor/fw/Core/Inc/main.h +HeaderFileListSize=4 +HeaderFiles#0=/home/david/Personal/Projects/HDIoT/Smart_Household/Wired_Sensors/iaq_wired_sensor/fw/Core/Inc/stm32l0xx_it.h +HeaderFiles#1=/home/david/Personal/Projects/HDIoT/Smart_Household/Wired_Sensors/iaq_wired_sensor/fw/Core/Inc/stm32_assert.h +HeaderFiles#2=/home/david/Personal/Projects/HDIoT/Smart_Household/Wired_Sensors/iaq_wired_sensor/fw/Core/Inc/stm32l0xx_hal_conf.h +HeaderFiles#3=/home/david/Personal/Projects/HDIoT/Smart_Household/Wired_Sensors/iaq_wired_sensor/fw/Core/Inc/main.h HeaderFolderListSize=1 -HeaderPath#0=/home/user/HDIoT/iaq_wired_sensor/fw/Core/Inc +HeaderPath#0=/home/david/Personal/Projects/HDIoT/Smart_Household/Wired_Sensors/iaq_wired_sensor/fw/Core/Inc HeaderFiles=; SourceFileListSize=3 -SourceFiles#0=/home/user/HDIoT/iaq_wired_sensor/fw/Core/Src/stm32l0xx_it.c -SourceFiles#1=/home/user/HDIoT/iaq_wired_sensor/fw/Core/Src/stm32l0xx_hal_msp.c -SourceFiles#2=/home/user/HDIoT/iaq_wired_sensor/fw/Core/Src/main.c +SourceFiles#0=/home/david/Personal/Projects/HDIoT/Smart_Household/Wired_Sensors/iaq_wired_sensor/fw/Core/Src/stm32l0xx_it.c +SourceFiles#1=/home/david/Personal/Projects/HDIoT/Smart_Household/Wired_Sensors/iaq_wired_sensor/fw/Core/Src/stm32l0xx_hal_msp.c +SourceFiles#2=/home/david/Personal/Projects/HDIoT/Smart_Household/Wired_Sensors/iaq_wired_sensor/fw/Core/Src/main.c SourceFolderListSize=1 -SourcePath#0=/home/user/HDIoT/iaq_wired_sensor/fw/Core/Src +SourcePath#0=/home/david/Personal/Projects/HDIoT/Smart_Household/Wired_Sensors/iaq_wired_sensor/fw/Core/Src SourceFiles=; diff --git a/fw/.settings/language.settings.xml b/fw/.settings/language.settings.xml index 87c8372..3740b5b 100644 --- a/fw/.settings/language.settings.xml +++ b/fw/.settings/language.settings.xml @@ -1,27 +1,52 @@ - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fw/Core/Inc/led.h b/fw/Core/Inc/led.h deleted file mode 100644 index 08a95ee..0000000 --- a/fw/Core/Inc/led.h +++ /dev/null @@ -1,47 +0,0 @@ -/* - * led.h - * - * Created on: Jun 6, 2021 - * Author: user - */ - -#ifndef INC_LED_H_ -#define INC_LED_H_ - -#include "stdint.h" -#include "stm32l0xx_hal.h" - -/* - * Context struct - */ - -typedef struct { - GPIO_TypeDef *red_led_port; - int red_led_pin; - GPIO_TypeDef *green_led_port; - int green_led_pin; - GPIO_TypeDef *blue_led_port; - int blue_led_pin; - -} led_context_t; - -/* - * Externally defined variables - */ - -extern int led_pwm_max; -extern int led_pwm_counter; -extern int led_red_intensity; -extern int led_green_intensity; -extern int led_blue_intensity; - -/* - * Function prototypes - */ - -void led_set_color(float red, float green, float blue); -void led_off(); -void led_pwm_handler(); -void led_init(led_context_t *context, int pwm_freq, int pwm_handler_freq); - -#endif /* INC_LED_H_ */ diff --git a/fw/Core/Inc/main.h b/fw/Core/Inc/main.h index f4efcd0..716c334 100644 --- a/fw/Core/Inc/main.h +++ b/fw/Core/Inc/main.h @@ -29,10 +29,21 @@ extern "C" { /* Includes ------------------------------------------------------------------*/ #include "stm32l0xx_hal.h" +#include "stm32l0xx_ll_dma.h" +#include "stm32l0xx.h" +#include "stm32l0xx_ll_i2c.h" +#include "stm32l0xx_ll_lpuart.h" +#include "stm32l0xx_ll_rcc.h" +#include "stm32l0xx_ll_system.h" +#include "stm32l0xx_ll_gpio.h" +#include "stm32l0xx_ll_exti.h" +#include "stm32l0xx_ll_bus.h" +#include "stm32l0xx_ll_cortex.h" +#include "stm32l0xx_ll_utils.h" +#include "stm32l0xx_ll_pwr.h" /* Private includes ----------------------------------------------------------*/ /* USER CODE BEGIN Includes */ -#include "led.h" /* USER CODE END Includes */ /* Exported types ------------------------------------------------------------*/ @@ -58,11 +69,11 @@ void Error_Handler(void); /* USER CODE END EFP */ /* Private defines -----------------------------------------------------------*/ -#define LED_B_Pin GPIO_PIN_5 +#define LED_B_Pin LL_GPIO_PIN_5 #define LED_B_GPIO_Port GPIOA -#define LED_G_Pin GPIO_PIN_6 +#define LED_G_Pin LL_GPIO_PIN_6 #define LED_G_GPIO_Port GPIOA -#define LED_R_Pin GPIO_PIN_7 +#define LED_R_Pin LL_GPIO_PIN_7 #define LED_R_GPIO_Port GPIOA /* USER CODE BEGIN Private defines */ diff --git a/fw/Core/Inc/stm32_assert.h b/fw/Core/Inc/stm32_assert.h new file mode 100644 index 0000000..ca09699 --- /dev/null +++ b/fw/Core/Inc/stm32_assert.h @@ -0,0 +1,53 @@ +/** + ****************************************************************************** + * @file stm32_assert.h + * @brief STM32 assert file. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2018 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32_ASSERT_H +#define __STM32_ASSERT_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Includes ------------------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32_ASSERT_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/fw/Core/Inc/stm32l0xx_hal_conf.h b/fw/Core/Inc/stm32l0xx_hal_conf.h index 5252f0f..30c4584 100644 --- a/fw/Core/Inc/stm32l0xx_hal_conf.h +++ b/fw/Core/Inc/stm32l0xx_hal_conf.h @@ -52,7 +52,7 @@ /*#define HAL_SPI_MODULE_ENABLED */ /*#define HAL_TIM_MODULE_ENABLED */ /*#define HAL_TSC_MODULE_ENABLED */ -#define HAL_UART_MODULE_ENABLED +/*#define HAL_UART_MODULE_ENABLED */ /*#define HAL_USART_MODULE_ENABLED */ /*#define HAL_IRDA_MODULE_ENABLED */ /*#define HAL_SMARTCARD_MODULE_ENABLED */ diff --git a/fw/Core/Inc/stm32l0xx_it.h b/fw/Core/Inc/stm32l0xx_it.h index 77cb7bd..5212081 100644 --- a/fw/Core/Inc/stm32l0xx_it.h +++ b/fw/Core/Inc/stm32l0xx_it.h @@ -52,6 +52,7 @@ void HardFault_Handler(void); void SVC_Handler(void); void PendSV_Handler(void); void SysTick_Handler(void); +void DMA1_Channel2_3_IRQHandler(void); /* USER CODE BEGIN EFP */ /* USER CODE END EFP */ diff --git a/fw/Core/Src/led.c b/fw/Core/Src/led.c deleted file mode 100644 index 2ca35fc..0000000 --- a/fw/Core/Src/led.c +++ /dev/null @@ -1,120 +0,0 @@ -/* - * led.c - * - * Created on: Jun 6, 2021 - * Author: user - */ - -#include "led.h" - -/* - * Global variables - */ - -int led_pwm_max; -int led_pwm_counter; -int led_red_intensity; -int led_green_intensity; -int led_blue_intensity; -int led_red_state; -int led_green_state; -int led_blue_state; -led_context_t *led_context = NULL; - -/* - * Functions - */ - -/* - * led_set_color(): - * Set LED color - * Arguments: - * float red: red color intensity, possible values 0.0 ... 1.0 - * float green: green color intensity, possible values 0.0 ... 1.0 - * float blue: blue color intensity, possible values 0.0 ... 1.0 - */ -void led_set_color(float red, float green, float blue) -{ - led_red_intensity = red * led_pwm_max; - led_green_intensity = green * led_pwm_max; - led_blue_intensity = blue * led_pwm_max; -} - -/* - * led_off(): - * Set LED intensity to 0 for each color - */ -void led_off() -{ - led_red_intensity = 0; - led_green_intensity = 0; - led_blue_intensity = 0; -} - -/* - * led_pwm_handler(): - * handles switching LEDs on/off according to desired intensity; - * should be regularly called in timer routine, preferably in SysTick_Handler() - */ -void led_pwm_handler() -{ - int new_red_state, new_green_state, new_blue_state; - - if (led_context == NULL) { - // led_pwm_handler() may be called before led_init() was called; - // this would result in a crash - return; - } - - new_red_state = led_pwm_counter >= led_red_intensity ? 1 : 0; - new_green_state = led_pwm_counter >= led_green_intensity ? 1 : 0; - new_blue_state = led_pwm_counter >= led_blue_intensity ? 1 : 0; - // SysTick() is called at 1 kHz frequency, we don't want to call HAL_GPIO_WritePin() every time - if (led_red_state != new_red_state) { - HAL_GPIO_WritePin(led_context->red_led_port, led_context->red_led_pin, new_red_state); - led_red_state = new_red_state; - } - if (led_green_state != new_green_state) { - HAL_GPIO_WritePin(led_context->green_led_port, led_context->green_led_pin, new_green_state); - led_green_state = new_green_state; - } - if (led_blue_state != new_blue_state) { - HAL_GPIO_WritePin(led_context->blue_led_port, led_context->blue_led_pin, new_blue_state); - led_blue_state = new_blue_state; - } - if (++led_pwm_counter >= led_pwm_max) { - led_pwm_counter = 0; - } -} - -/* - * led_init(): - * Saves context and calculates max pwm value. Note that is PWM frequency is low (< 25 Hz), - * flickering might be visible. If pwm_handler_freq is low (less than several kHz), - * resolution of PWM will be limited - * Arguments: - * led_context_t *context: - * Pointer to LED context struct, which contains port and pin for each LED - * int pwm_freq: - * Desired frequency of PWM in Hz (e.g. 25 Hz) - * int pwm_handler_freq: - * Frequency of led_pwm_handler() calls. Eequal to timer frequency if timer callback is used, - * e.g. if led_pwm_handler() is called within SysTick_Handler(), then frequency is - * HAL_TICK_FREQ_1KHZ - */ -void led_init(led_context_t *context, int pwm_freq, int pwm_handler_freq) -{ - // save context - led_context = context; - // Initial values - led_red_intensity = 0; - led_red_state = 1; // state is inverted (LEDs are sinking current into MCU) - led_green_intensity = 0; - led_green_state = 1; - led_blue_intensity = 0; - led_blue_state = 1; - // calculate PWM counter overflow value (max value) - // e.g. for 1 kHz handler freq and 25 Hz PWM freq, we only have - // resolution of 40 steps for pwm - led_pwm_max = pwm_handler_freq / pwm_freq; -} diff --git a/fw/Core/Src/main.c b/fw/Core/Src/main.c index 328294b..3b9e698 100644 --- a/fw/Core/Src/main.c +++ b/fw/Core/Src/main.c @@ -40,9 +40,6 @@ /* USER CODE END PM */ /* Private variables ---------------------------------------------------------*/ -I2C_HandleTypeDef hi2c1; - -UART_HandleTypeDef hlpuart1; /* USER CODE BEGIN PV */ @@ -51,6 +48,7 @@ UART_HandleTypeDef hlpuart1; /* Private function prototypes -----------------------------------------------*/ void SystemClock_Config(void); static void MX_GPIO_Init(void); +static void MX_DMA_Init(void); static void MX_I2C1_Init(void); static void MX_LPUART1_UART_Init(void); /* USER CODE BEGIN PFP */ @@ -90,41 +88,33 @@ int main(void) /* Initialize all configured peripherals */ MX_GPIO_Init(); + MX_DMA_Init(); MX_I2C1_Init(); MX_LPUART1_UART_Init(); /* USER CODE BEGIN 2 */ - /* Create LED context */ - led_context_t led_context; - led_context.red_led_port = LED_R_GPIO_Port; - led_context.red_led_pin = LED_R_Pin; - led_context.green_led_port = LED_G_GPIO_Port; - led_context.green_led_pin = LED_G_Pin; - led_context.blue_led_port = LED_B_GPIO_Port; - led_context.blue_led_pin = LED_B_Pin; - // TODO tady je neco spatne, jako by SysTick nemel 1 kHz? - // TODO premerit osciloskopem frekvenci spinani led - led_init(&led_context, 50, 1000); - /* Turn off all LEDs */ - led_off(); /* USER CODE END 2 */ /* Infinite loop */ /* USER CODE BEGIN WHILE */ - // LED PWM test - int counter = 0; - float R = 0.0, G = 0.0, B = 0.0; + LL_LPUART_Enable(LPUART1); + uint8_t i = 0; while (1) { - if (counter % 1000 == 0) { - R += 0.035; - G += 0.015; - B += 0.005; - if (R > 1.0) R = 0; - if (G > 1.0) G = 0; - if (B > 1.0) B = 0; - led_set_color(R, G, B); + LL_GPIO_TogglePin(LED_R_GPIO_Port, LED_R_Pin); + LL_GPIO_TogglePin(LED_G_GPIO_Port, LED_G_Pin); + LL_GPIO_TogglePin(LED_B_GPIO_Port, LED_B_Pin); + + /* Wait for TXE flag to be raised */ + while (!LL_LPUART_IsActiveFlag_TXE(LPUART1)) + { } - counter++; + + /* Write character in Transmit Data register. + TXE flag is cleared by writing data in TDR register */ + LL_LPUART_TransmitData8(LPUART1, i); + i++; + + HAL_Delay(1000); /* USER CODE END WHILE */ /* USER CODE BEGIN 3 */ @@ -191,34 +181,52 @@ static void MX_I2C1_Init(void) /* USER CODE END I2C1_Init 0 */ + LL_I2C_InitTypeDef I2C_InitStruct = {0}; + + LL_GPIO_InitTypeDef GPIO_InitStruct = {0}; + + LL_IOP_GRP1_EnableClock(LL_IOP_GRP1_PERIPH_GPIOA); + /**I2C1 GPIO Configuration + PA9 ------> I2C1_SCL + PA10 ------> I2C1_SDA + */ + GPIO_InitStruct.Pin = LL_GPIO_PIN_9; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; + GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_OPENDRAIN; + GPIO_InitStruct.Pull = LL_GPIO_PULL_UP; + GPIO_InitStruct.Alternate = LL_GPIO_AF_1; + LL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = LL_GPIO_PIN_10; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; + GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_OPENDRAIN; + GPIO_InitStruct.Pull = LL_GPIO_PULL_UP; + GPIO_InitStruct.Alternate = LL_GPIO_AF_1; + LL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /* Peripheral clock enable */ + LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_I2C1); + /* USER CODE BEGIN I2C1_Init 1 */ /* USER CODE END I2C1_Init 1 */ - hi2c1.Instance = I2C1; - hi2c1.Init.Timing = 0x00000708; - hi2c1.Init.OwnAddress1 = 0; - hi2c1.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT; - hi2c1.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE; - hi2c1.Init.OwnAddress2 = 0; - hi2c1.Init.OwnAddress2Masks = I2C_OA2_NOMASK; - hi2c1.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE; - hi2c1.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE; - if (HAL_I2C_Init(&hi2c1) != HAL_OK) - { - Error_Handler(); - } - /** Configure Analogue filter + /** I2C Initialization */ - if (HAL_I2CEx_ConfigAnalogFilter(&hi2c1, I2C_ANALOGFILTER_ENABLE) != HAL_OK) - { - Error_Handler(); - } - /** Configure Digital filter - */ - if (HAL_I2CEx_ConfigDigitalFilter(&hi2c1, 0) != HAL_OK) - { - Error_Handler(); - } + LL_I2C_EnableAutoEndMode(I2C1); + LL_I2C_DisableOwnAddress2(I2C1); + LL_I2C_DisableGeneralCall(I2C1); + LL_I2C_EnableClockStretching(I2C1); + I2C_InitStruct.PeripheralMode = LL_I2C_MODE_I2C; + I2C_InitStruct.Timing = 0x00000708; + I2C_InitStruct.AnalogFilter = LL_I2C_ANALOGFILTER_ENABLE; + I2C_InitStruct.DigitalFilter = 0; + I2C_InitStruct.OwnAddress1 = 0; + I2C_InitStruct.TypeAcknowledge = LL_I2C_ACK; + I2C_InitStruct.OwnAddrSize = LL_I2C_OWNADDRESS1_7BIT; + LL_I2C_Init(I2C1, &I2C_InitStruct); + LL_I2C_SetOwnAddress2(I2C1, 0, LL_I2C_OWNADDRESS2_NOMASK); /* USER CODE BEGIN I2C1_Init 2 */ /* USER CODE END I2C1_Init 2 */ @@ -237,28 +245,100 @@ static void MX_LPUART1_UART_Init(void) /* USER CODE END LPUART1_Init 0 */ + LL_LPUART_InitTypeDef LPUART_InitStruct = {0}; + + LL_GPIO_InitTypeDef GPIO_InitStruct = {0}; + + /* Peripheral clock enable */ + LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_LPUART1); + + LL_IOP_GRP1_EnableClock(LL_IOP_GRP1_PERIPH_GPIOA); + LL_IOP_GRP1_EnableClock(LL_IOP_GRP1_PERIPH_GPIOB); + /**LPUART1 GPIO Configuration + PA0-CK_IN ------> LPUART1_RX + PA1 ------> LPUART1_TX + PB1 ------> LPUART1_DE + */ + GPIO_InitStruct.Pin = LL_GPIO_PIN_0; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; + GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + GPIO_InitStruct.Alternate = LL_GPIO_AF_6; + LL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = LL_GPIO_PIN_1; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; + GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + GPIO_InitStruct.Alternate = LL_GPIO_AF_6; + LL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = LL_GPIO_PIN_1; + GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; + GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + GPIO_InitStruct.Alternate = LL_GPIO_AF_4; + LL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /* LPUART1 DMA Init */ + + /* LPUART1_RX Init */ + LL_DMA_SetPeriphRequest(DMA1, LL_DMA_CHANNEL_3, LL_DMA_REQUEST_5); + + LL_DMA_SetDataTransferDirection(DMA1, LL_DMA_CHANNEL_3, LL_DMA_DIRECTION_PERIPH_TO_MEMORY); + + LL_DMA_SetChannelPriorityLevel(DMA1, LL_DMA_CHANNEL_3, LL_DMA_PRIORITY_MEDIUM); + + LL_DMA_SetMode(DMA1, LL_DMA_CHANNEL_3, LL_DMA_MODE_CIRCULAR); + + LL_DMA_SetPeriphIncMode(DMA1, LL_DMA_CHANNEL_3, LL_DMA_PERIPH_NOINCREMENT); + + LL_DMA_SetMemoryIncMode(DMA1, LL_DMA_CHANNEL_3, LL_DMA_MEMORY_INCREMENT); + + LL_DMA_SetPeriphSize(DMA1, LL_DMA_CHANNEL_3, LL_DMA_PDATAALIGN_BYTE); + + LL_DMA_SetMemorySize(DMA1, LL_DMA_CHANNEL_3, LL_DMA_MDATAALIGN_BYTE); + /* USER CODE BEGIN LPUART1_Init 1 */ /* USER CODE END LPUART1_Init 1 */ - hlpuart1.Instance = LPUART1; - hlpuart1.Init.BaudRate = 209700; - hlpuart1.Init.WordLength = UART_WORDLENGTH_7B; - hlpuart1.Init.StopBits = UART_STOPBITS_1; - hlpuart1.Init.Parity = UART_PARITY_NONE; - hlpuart1.Init.Mode = UART_MODE_TX_RX; - hlpuart1.Init.HwFlowCtl = UART_HWCONTROL_NONE; - hlpuart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; - hlpuart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; - if (HAL_UART_Init(&hlpuart1) != HAL_OK) - { - Error_Handler(); - } + LPUART_InitStruct.BaudRate = 115200; + LPUART_InitStruct.DataWidth = LL_LPUART_DATAWIDTH_8B; + LPUART_InitStruct.StopBits = LL_LPUART_STOPBITS_1; + LPUART_InitStruct.Parity = LL_LPUART_PARITY_NONE; + LPUART_InitStruct.TransferDirection = LL_LPUART_DIRECTION_TX_RX; + LPUART_InitStruct.HardwareFlowControl = LL_LPUART_HWCONTROL_NONE; + LL_LPUART_Init(LPUART1, &LPUART_InitStruct); + LL_LPUART_EnableDEMode(LPUART1); + LL_LPUART_SetDESignalPolarity(LPUART1, LL_LPUART_DE_POLARITY_HIGH); + LL_LPUART_SetDEAssertionTime(LPUART1, 20); + LL_LPUART_SetDEDeassertionTime(LPUART1, 20); /* USER CODE BEGIN LPUART1_Init 2 */ /* USER CODE END LPUART1_Init 2 */ } +/** + * Enable DMA controller clock + */ +static void MX_DMA_Init(void) +{ + + /* Init with LL driver */ + /* DMA controller clock enable */ + LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_DMA1); + + /* DMA interrupt init */ + /* DMA1_Channel2_3_IRQn interrupt configuration */ + NVIC_SetPriority(DMA1_Channel2_3_IRQn, 0); + NVIC_EnableIRQ(DMA1_Channel2_3_IRQn); + +} + /** * @brief GPIO Initialization Function * @param None @@ -266,20 +346,44 @@ static void MX_LPUART1_UART_Init(void) */ static void MX_GPIO_Init(void) { - GPIO_InitTypeDef GPIO_InitStruct = {0}; + LL_GPIO_InitTypeDef GPIO_InitStruct = {0}; /* GPIO Ports Clock Enable */ - __HAL_RCC_GPIOA_CLK_ENABLE(); + LL_IOP_GRP1_EnableClock(LL_IOP_GRP1_PERIPH_GPIOA); + LL_IOP_GRP1_EnableClock(LL_IOP_GRP1_PERIPH_GPIOB); - /*Configure GPIO pin Output Level */ - HAL_GPIO_WritePin(GPIOA, LED_B_Pin|LED_G_Pin|LED_R_Pin, GPIO_PIN_SET); + /**/ + LL_GPIO_SetOutputPin(LED_B_GPIO_Port, LED_B_Pin); - /*Configure GPIO pins : LED_B_Pin LED_G_Pin LED_R_Pin */ - GPIO_InitStruct.Pin = LED_B_Pin|LED_G_Pin|LED_R_Pin; - GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; - HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + /**/ + LL_GPIO_SetOutputPin(LED_G_GPIO_Port, LED_G_Pin); + + /**/ + LL_GPIO_SetOutputPin(LED_R_GPIO_Port, LED_R_Pin); + + /**/ + GPIO_InitStruct.Pin = LED_B_Pin; + GPIO_InitStruct.Mode = LL_GPIO_MODE_OUTPUT; + GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(LED_B_GPIO_Port, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LED_G_Pin; + GPIO_InitStruct.Mode = LL_GPIO_MODE_OUTPUT; + GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(LED_G_GPIO_Port, &GPIO_InitStruct); + + /**/ + GPIO_InitStruct.Pin = LED_R_Pin; + GPIO_InitStruct.Mode = LL_GPIO_MODE_OUTPUT; + GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + LL_GPIO_Init(LED_R_GPIO_Port, &GPIO_InitStruct); } diff --git a/fw/Core/Src/stm32l0xx_hal_msp.c b/fw/Core/Src/stm32l0xx_hal_msp.c index 4c80442..f614d4a 100644 --- a/fw/Core/Src/stm32l0xx_hal_msp.c +++ b/fw/Core/Src/stm32l0xx_hal_msp.c @@ -77,138 +77,6 @@ void HAL_MspInit(void) /* USER CODE END MspInit 1 */ } -/** -* @brief I2C MSP Initialization -* This function configures the hardware resources used in this example -* @param hi2c: I2C handle pointer -* @retval None -*/ -void HAL_I2C_MspInit(I2C_HandleTypeDef* hi2c) -{ - GPIO_InitTypeDef GPIO_InitStruct = {0}; - if(hi2c->Instance==I2C1) - { - /* USER CODE BEGIN I2C1_MspInit 0 */ - - /* USER CODE END I2C1_MspInit 0 */ - - __HAL_RCC_GPIOA_CLK_ENABLE(); - /**I2C1 GPIO Configuration - PA9 ------> I2C1_SCL - PA10 ------> I2C1_SDA - */ - GPIO_InitStruct.Pin = GPIO_PIN_9|GPIO_PIN_10; - GPIO_InitStruct.Mode = GPIO_MODE_AF_OD; - GPIO_InitStruct.Pull = GPIO_PULLUP; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; - GPIO_InitStruct.Alternate = GPIO_AF1_I2C1; - HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); - - /* Peripheral clock enable */ - __HAL_RCC_I2C1_CLK_ENABLE(); - /* USER CODE BEGIN I2C1_MspInit 1 */ - - /* USER CODE END I2C1_MspInit 1 */ - } - -} - -/** -* @brief I2C MSP De-Initialization -* This function freeze the hardware resources used in this example -* @param hi2c: I2C handle pointer -* @retval None -*/ -void HAL_I2C_MspDeInit(I2C_HandleTypeDef* hi2c) -{ - if(hi2c->Instance==I2C1) - { - /* USER CODE BEGIN I2C1_MspDeInit 0 */ - - /* USER CODE END I2C1_MspDeInit 0 */ - /* Peripheral clock disable */ - __HAL_RCC_I2C1_CLK_DISABLE(); - - /**I2C1 GPIO Configuration - PA9 ------> I2C1_SCL - PA10 ------> I2C1_SDA - */ - HAL_GPIO_DeInit(GPIOA, GPIO_PIN_9); - - HAL_GPIO_DeInit(GPIOA, GPIO_PIN_10); - - /* USER CODE BEGIN I2C1_MspDeInit 1 */ - - /* USER CODE END I2C1_MspDeInit 1 */ - } - -} - -/** -* @brief UART MSP Initialization -* This function configures the hardware resources used in this example -* @param huart: UART handle pointer -* @retval None -*/ -void HAL_UART_MspInit(UART_HandleTypeDef* huart) -{ - GPIO_InitTypeDef GPIO_InitStruct = {0}; - if(huart->Instance==LPUART1) - { - /* USER CODE BEGIN LPUART1_MspInit 0 */ - - /* USER CODE END LPUART1_MspInit 0 */ - /* Peripheral clock enable */ - __HAL_RCC_LPUART1_CLK_ENABLE(); - - __HAL_RCC_GPIOA_CLK_ENABLE(); - /**LPUART1 GPIO Configuration - PA0-CK_IN ------> LPUART1_RX - PA1 ------> LPUART1_TX - */ - GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1; - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; - GPIO_InitStruct.Alternate = GPIO_AF6_LPUART1; - HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); - - /* USER CODE BEGIN LPUART1_MspInit 1 */ - - /* USER CODE END LPUART1_MspInit 1 */ - } - -} - -/** -* @brief UART MSP De-Initialization -* This function freeze the hardware resources used in this example -* @param huart: UART handle pointer -* @retval None -*/ -void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) -{ - if(huart->Instance==LPUART1) - { - /* USER CODE BEGIN LPUART1_MspDeInit 0 */ - - /* USER CODE END LPUART1_MspDeInit 0 */ - /* Peripheral clock disable */ - __HAL_RCC_LPUART1_CLK_DISABLE(); - - /**LPUART1 GPIO Configuration - PA0-CK_IN ------> LPUART1_RX - PA1 ------> LPUART1_TX - */ - HAL_GPIO_DeInit(GPIOA, GPIO_PIN_0|GPIO_PIN_1); - - /* USER CODE BEGIN LPUART1_MspDeInit 1 */ - - /* USER CODE END LPUART1_MspDeInit 1 */ - } - -} - /* USER CODE BEGIN 1 */ /* USER CODE END 1 */ diff --git a/fw/Core/Src/stm32l0xx_it.c b/fw/Core/Src/stm32l0xx_it.c index 5158a87..28664a1 100644 --- a/fw/Core/Src/stm32l0xx_it.c +++ b/fw/Core/Src/stm32l0xx_it.c @@ -23,7 +23,6 @@ #include "stm32l0xx_it.h" /* Private includes ----------------------------------------------------------*/ /* USER CODE BEGIN Includes */ -#include "led.h" /* USER CODE END Includes */ /* Private typedef -----------------------------------------------------------*/ @@ -131,7 +130,6 @@ void SysTick_Handler(void) /* USER CODE END SysTick_IRQn 0 */ HAL_IncTick(); /* USER CODE BEGIN SysTick_IRQn 1 */ - led_pwm_handler(); /* USER CODE END SysTick_IRQn 1 */ } @@ -142,6 +140,20 @@ void SysTick_Handler(void) /* please refer to the startup file (startup_stm32l0xx.s). */ /******************************************************************************/ +/** + * @brief This function handles DMA1 channel 2 and channel 3 interrupts. + */ +void DMA1_Channel2_3_IRQHandler(void) +{ + /* USER CODE BEGIN DMA1_Channel2_3_IRQn 0 */ + + /* USER CODE END DMA1_Channel2_3_IRQn 0 */ + + /* USER CODE BEGIN DMA1_Channel2_3_IRQn 1 */ + + /* USER CODE END DMA1_Channel2_3_IRQn 1 */ +} + /* USER CODE BEGIN 1 */ /* USER CODE END 1 */ diff --git a/fw/Debug/Core/Src/led.su b/fw/Debug/Core/Src/led.su new file mode 100644 index 0000000..fe5e74f --- /dev/null +++ b/fw/Debug/Core/Src/led.su @@ -0,0 +1,4 @@ +led.c:36:6:led_set_color 24 static +led.c:47:6:led_off 8 static +led.c:59:6:led_pwm_handler 24 static +led.c:105:6:led_init 24 static diff --git a/fw/Debug/Core/Src/main.d b/fw/Debug/Core/Src/main.d new file mode 100644 index 0000000..29d4f24 --- /dev/null +++ b/fw/Debug/Core/Src/main.d @@ -0,0 +1,111 @@ +Core/Src/main.o: ../Core/Src/main.c ../Core/Inc/main.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h \ + ../Core/Inc/stm32l0xx_hal_conf.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h \ + ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l011xx.h \ + ../Drivers/CMSIS/Include/core_cm0plus.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_exti.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h + +../Core/Inc/main.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h: + +../Core/Inc/stm32l0xx_hal_conf.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h: + +../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h: + +../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l011xx.h: + +../Drivers/CMSIS/Include/core_cm0plus.h: + +../Drivers/CMSIS/Include/cmsis_version.h: + +../Drivers/CMSIS/Include/cmsis_compiler.h: + +../Drivers/CMSIS/Include/cmsis_gcc.h: + +../Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_exti.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h: diff --git a/fw/Debug/Core/Src/main.o b/fw/Debug/Core/Src/main.o new file mode 100644 index 0000000..d8390c4 Binary files /dev/null and b/fw/Debug/Core/Src/main.o differ diff --git a/fw/Debug/Core/Src/main.su b/fw/Debug/Core/Src/main.su new file mode 100644 index 0000000..31270b6 --- /dev/null +++ b/fw/Debug/Core/Src/main.su @@ -0,0 +1,4 @@ +stm32l0xx_ll_bus.h:987:22:LL_IOP_GRP1_EnableClock 8 static +main.c:129:6:SystemClock_Config 104 static,ignoring_inline_asm +main.c:67:5:main 88 static +main.c:398:6:Error_Handler 0 static,ignoring_inline_asm diff --git a/fw/Debug/Core/Src/stm32l0xx_hal_msp.d b/fw/Debug/Core/Src/stm32l0xx_hal_msp.d new file mode 100644 index 0000000..521e283 --- /dev/null +++ b/fw/Debug/Core/Src/stm32l0xx_hal_msp.d @@ -0,0 +1,111 @@ +Core/Src/stm32l0xx_hal_msp.o: ../Core/Src/stm32l0xx_hal_msp.c \ + ../Core/Inc/main.h ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h \ + ../Core/Inc/stm32l0xx_hal_conf.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h \ + ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l011xx.h \ + ../Drivers/CMSIS/Include/core_cm0plus.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_exti.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h + +../Core/Inc/main.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h: + +../Core/Inc/stm32l0xx_hal_conf.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h: + +../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h: + +../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l011xx.h: + +../Drivers/CMSIS/Include/core_cm0plus.h: + +../Drivers/CMSIS/Include/cmsis_version.h: + +../Drivers/CMSIS/Include/cmsis_compiler.h: + +../Drivers/CMSIS/Include/cmsis_gcc.h: + +../Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_exti.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h: diff --git a/fw/Debug/Core/Src/stm32l0xx_hal_msp.o b/fw/Debug/Core/Src/stm32l0xx_hal_msp.o new file mode 100644 index 0000000..ed5c468 Binary files /dev/null and b/fw/Debug/Core/Src/stm32l0xx_hal_msp.o differ diff --git a/fw/Debug/Core/Src/stm32l0xx_hal_msp.su b/fw/Debug/Core/Src/stm32l0xx_hal_msp.su new file mode 100644 index 0000000..9b75000 --- /dev/null +++ b/fw/Debug/Core/Src/stm32l0xx_hal_msp.su @@ -0,0 +1 @@ +stm32l0xx_hal_msp.c:64:6:HAL_MspInit 0 static diff --git a/fw/Debug/Core/Src/stm32l0xx_it.d b/fw/Debug/Core/Src/stm32l0xx_it.d new file mode 100644 index 0000000..69cb03a --- /dev/null +++ b/fw/Debug/Core/Src/stm32l0xx_it.d @@ -0,0 +1,114 @@ +Core/Src/stm32l0xx_it.o: ../Core/Src/stm32l0xx_it.c ../Core/Inc/main.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h \ + ../Core/Inc/stm32l0xx_hal_conf.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h \ + ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l011xx.h \ + ../Drivers/CMSIS/Include/core_cm0plus.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_exti.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h \ + ../Core/Inc/stm32l0xx_it.h + +../Core/Inc/main.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h: + +../Core/Inc/stm32l0xx_hal_conf.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h: + +../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h: + +../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l011xx.h: + +../Drivers/CMSIS/Include/core_cm0plus.h: + +../Drivers/CMSIS/Include/cmsis_version.h: + +../Drivers/CMSIS/Include/cmsis_compiler.h: + +../Drivers/CMSIS/Include/cmsis_gcc.h: + +../Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_exti.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h: + +../Core/Inc/stm32l0xx_it.h: diff --git a/fw/Debug/Core/Src/stm32l0xx_it.o b/fw/Debug/Core/Src/stm32l0xx_it.o new file mode 100644 index 0000000..e53ac03 Binary files /dev/null and b/fw/Debug/Core/Src/stm32l0xx_it.o differ diff --git a/fw/Debug/Core/Src/stm32l0xx_it.su b/fw/Debug/Core/Src/stm32l0xx_it.su new file mode 100644 index 0000000..af75b7b --- /dev/null +++ b/fw/Debug/Core/Src/stm32l0xx_it.su @@ -0,0 +1,6 @@ +stm32l0xx_it.c:70:6:NMI_Handler 0 static +stm32l0xx_it.c:85:6:HardFault_Handler 0 static +stm32l0xx_it.c:100:6:SVC_Handler 0 static +stm32l0xx_it.c:113:6:PendSV_Handler 0 static +stm32l0xx_it.c:126:6:SysTick_Handler 8 static +stm32l0xx_it.c:146:6:DMA1_Channel2_3_IRQHandler 0 static diff --git a/fw/Debug/Core/Src/subdir.mk b/fw/Debug/Core/Src/subdir.mk new file mode 100644 index 0000000..8b0d555 --- /dev/null +++ b/fw/Debug/Core/Src/subdir.mk @@ -0,0 +1,45 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (9-2020-q2-update) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Core/Src/main.c \ +../Core/Src/stm32l0xx_hal_msp.c \ +../Core/Src/stm32l0xx_it.c \ +../Core/Src/syscalls.c \ +../Core/Src/sysmem.c \ +../Core/Src/system_stm32l0xx.c + +OBJS += \ +./Core/Src/main.o \ +./Core/Src/stm32l0xx_hal_msp.o \ +./Core/Src/stm32l0xx_it.o \ +./Core/Src/syscalls.o \ +./Core/Src/sysmem.o \ +./Core/Src/system_stm32l0xx.o + +C_DEPS += \ +./Core/Src/main.d \ +./Core/Src/stm32l0xx_hal_msp.d \ +./Core/Src/stm32l0xx_it.d \ +./Core/Src/syscalls.d \ +./Core/Src/sysmem.d \ +./Core/Src/system_stm32l0xx.d + + +# Each subdirectory must supply rules for building sources it contributes +Core/Src/main.o: ../Core/Src/main.c Core/Src/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m0plus -std=gnu11 -g3 -DSTM32L011xx -DDEBUG -DUSE_FULL_LL_DRIVER -DUSE_HAL_DRIVER -c -I../Core/Inc -I../Drivers/STM32L0xx_HAL_Driver/Inc -I../Drivers/CMSIS/Device/ST/STM32L0xx/Include -I../Drivers/CMSIS/Include -I../Drivers/STM32L0xx_HAL_Driver/Inc/Legacy -Os -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Core/Src/main.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" +Core/Src/stm32l0xx_hal_msp.o: ../Core/Src/stm32l0xx_hal_msp.c Core/Src/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m0plus -std=gnu11 -g3 -DSTM32L011xx -DDEBUG -DUSE_FULL_LL_DRIVER -DUSE_HAL_DRIVER -c -I../Core/Inc -I../Drivers/STM32L0xx_HAL_Driver/Inc -I../Drivers/CMSIS/Device/ST/STM32L0xx/Include -I../Drivers/CMSIS/Include -I../Drivers/STM32L0xx_HAL_Driver/Inc/Legacy -Os -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Core/Src/stm32l0xx_hal_msp.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" +Core/Src/stm32l0xx_it.o: ../Core/Src/stm32l0xx_it.c Core/Src/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m0plus -std=gnu11 -g3 -DSTM32L011xx -DDEBUG -DUSE_FULL_LL_DRIVER -DUSE_HAL_DRIVER -c -I../Core/Inc -I../Drivers/STM32L0xx_HAL_Driver/Inc -I../Drivers/CMSIS/Device/ST/STM32L0xx/Include -I../Drivers/CMSIS/Include -I../Drivers/STM32L0xx_HAL_Driver/Inc/Legacy -Os -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Core/Src/stm32l0xx_it.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" +Core/Src/syscalls.o: ../Core/Src/syscalls.c Core/Src/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m0plus -std=gnu11 -g3 -DSTM32L011xx -DDEBUG -DUSE_FULL_LL_DRIVER -DUSE_HAL_DRIVER -c -I../Core/Inc -I../Drivers/STM32L0xx_HAL_Driver/Inc -I../Drivers/CMSIS/Device/ST/STM32L0xx/Include -I../Drivers/CMSIS/Include -I../Drivers/STM32L0xx_HAL_Driver/Inc/Legacy -Os -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Core/Src/syscalls.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" +Core/Src/sysmem.o: ../Core/Src/sysmem.c Core/Src/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m0plus -std=gnu11 -g3 -DSTM32L011xx -DDEBUG -DUSE_FULL_LL_DRIVER -DUSE_HAL_DRIVER -c -I../Core/Inc -I../Drivers/STM32L0xx_HAL_Driver/Inc -I../Drivers/CMSIS/Device/ST/STM32L0xx/Include -I../Drivers/CMSIS/Include -I../Drivers/STM32L0xx_HAL_Driver/Inc/Legacy -Os -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Core/Src/sysmem.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" +Core/Src/system_stm32l0xx.o: ../Core/Src/system_stm32l0xx.c Core/Src/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m0plus -std=gnu11 -g3 -DSTM32L011xx -DDEBUG -DUSE_FULL_LL_DRIVER -DUSE_HAL_DRIVER -c -I../Core/Inc -I../Drivers/STM32L0xx_HAL_Driver/Inc -I../Drivers/CMSIS/Device/ST/STM32L0xx/Include -I../Drivers/CMSIS/Include -I../Drivers/STM32L0xx_HAL_Driver/Inc/Legacy -Os -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Core/Src/system_stm32l0xx.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + diff --git a/fw/Debug/Core/Src/syscalls.d b/fw/Debug/Core/Src/syscalls.d new file mode 100644 index 0000000..8667c70 --- /dev/null +++ b/fw/Debug/Core/Src/syscalls.d @@ -0,0 +1 @@ +Core/Src/syscalls.o: ../Core/Src/syscalls.c diff --git a/fw/Debug/Core/Src/syscalls.o b/fw/Debug/Core/Src/syscalls.o new file mode 100644 index 0000000..de72b01 Binary files /dev/null and b/fw/Debug/Core/Src/syscalls.o differ diff --git a/fw/Debug/Core/Src/syscalls.su b/fw/Debug/Core/Src/syscalls.su new file mode 100644 index 0000000..c872039 --- /dev/null +++ b/fw/Debug/Core/Src/syscalls.su @@ -0,0 +1,18 @@ +syscalls.c:48:6:initialise_monitor_handles 0 static +syscalls.c:52:5:_getpid 0 static +syscalls.c:57:5:_kill 8 static +syscalls.c:63:6:_exit 8 static +syscalls.c:69:27:_read 16 static +syscalls.c:81:27:_write 16 static +syscalls.c:92:5:_close 0 static +syscalls.c:98:5:_fstat 0 static +syscalls.c:104:5:_isatty 0 static +syscalls.c:109:5:_lseek 0 static +syscalls.c:114:5:_open 0 static +syscalls.c:120:5:_wait 8 static +syscalls.c:126:5:_unlink 8 static +syscalls.c:132:5:_times 0 static +syscalls.c:137:5:_stat 0 static +syscalls.c:143:5:_link 8 static +syscalls.c:149:5:_fork 8 static +syscalls.c:155:5:_execve 8 static diff --git a/fw/Debug/Core/Src/sysmem.d b/fw/Debug/Core/Src/sysmem.d new file mode 100644 index 0000000..74fecf9 --- /dev/null +++ b/fw/Debug/Core/Src/sysmem.d @@ -0,0 +1 @@ +Core/Src/sysmem.o: ../Core/Src/sysmem.c diff --git a/fw/Debug/Core/Src/sysmem.o b/fw/Debug/Core/Src/sysmem.o new file mode 100644 index 0000000..c1f7cb8 Binary files /dev/null and b/fw/Debug/Core/Src/sysmem.o differ diff --git a/fw/Debug/Core/Src/sysmem.su b/fw/Debug/Core/Src/sysmem.su new file mode 100644 index 0000000..c9ac5ce --- /dev/null +++ b/fw/Debug/Core/Src/sysmem.su @@ -0,0 +1 @@ +sysmem.c:54:7:_sbrk 8 static diff --git a/fw/Debug/Core/Src/system_stm32l0xx.d b/fw/Debug/Core/Src/system_stm32l0xx.d new file mode 100644 index 0000000..a40be12 --- /dev/null +++ b/fw/Debug/Core/Src/system_stm32l0xx.d @@ -0,0 +1,76 @@ +Core/Src/system_stm32l0xx.o: ../Core/Src/system_stm32l0xx.c \ + ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h \ + ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l011xx.h \ + ../Drivers/CMSIS/Include/core_cm0plus.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h \ + ../Core/Inc/stm32l0xx_hal_conf.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_exti.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h + +../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h: + +../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l011xx.h: + +../Drivers/CMSIS/Include/core_cm0plus.h: + +../Drivers/CMSIS/Include/cmsis_version.h: + +../Drivers/CMSIS/Include/cmsis_compiler.h: + +../Drivers/CMSIS/Include/cmsis_gcc.h: + +../Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h: + +../Core/Inc/stm32l0xx_hal_conf.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_exti.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h: diff --git a/fw/Debug/Core/Src/system_stm32l0xx.o b/fw/Debug/Core/Src/system_stm32l0xx.o new file mode 100644 index 0000000..c6cd1f1 Binary files /dev/null and b/fw/Debug/Core/Src/system_stm32l0xx.o differ diff --git a/fw/Debug/Core/Src/system_stm32l0xx.su b/fw/Debug/Core/Src/system_stm32l0xx.su new file mode 100644 index 0000000..f548a45 --- /dev/null +++ b/fw/Debug/Core/Src/system_stm32l0xx.su @@ -0,0 +1,2 @@ +system_stm32l0xx.c:154:6:SystemInit 0 static +system_stm32l0xx.c:200:6:SystemCoreClockUpdate 16 static diff --git a/fw/Debug/Core/Startup/startup_stm32l011f4ux.d b/fw/Debug/Core/Startup/startup_stm32l011f4ux.d new file mode 100644 index 0000000..7f6eea2 --- /dev/null +++ b/fw/Debug/Core/Startup/startup_stm32l011f4ux.d @@ -0,0 +1,2 @@ +Core/Startup/startup_stm32l011f4ux.o: \ + ../Core/Startup/startup_stm32l011f4ux.s diff --git a/fw/Debug/Core/Startup/startup_stm32l011f4ux.o b/fw/Debug/Core/Startup/startup_stm32l011f4ux.o new file mode 100644 index 0000000..6e4550b Binary files /dev/null and b/fw/Debug/Core/Startup/startup_stm32l011f4ux.o differ diff --git a/fw/Debug/Core/Startup/subdir.mk b/fw/Debug/Core/Startup/subdir.mk new file mode 100644 index 0000000..3fa16c8 --- /dev/null +++ b/fw/Debug/Core/Startup/subdir.mk @@ -0,0 +1,20 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (9-2020-q2-update) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +S_SRCS += \ +../Core/Startup/startup_stm32l011f4ux.s + +OBJS += \ +./Core/Startup/startup_stm32l011f4ux.o + +S_DEPS += \ +./Core/Startup/startup_stm32l011f4ux.d + + +# Each subdirectory must supply rules for building sources it contributes +Core/Startup/startup_stm32l011f4ux.o: ../Core/Startup/startup_stm32l011f4ux.s Core/Startup/subdir.mk + arm-none-eabi-gcc -mcpu=cortex-m0plus -g3 -c -x assembler-with-cpp -MMD -MP -MF"Core/Startup/startup_stm32l011f4ux.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" "$<" + diff --git a/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.d b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.d new file mode 100644 index 0000000..18012de --- /dev/null +++ b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.d @@ -0,0 +1,77 @@ +Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o: \ + ../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h \ + ../Core/Inc/stm32l0xx_hal_conf.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h \ + ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l011xx.h \ + ../Drivers/CMSIS/Include/core_cm0plus.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_exti.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h: + +../Core/Inc/stm32l0xx_hal_conf.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h: + +../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h: + +../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l011xx.h: + +../Drivers/CMSIS/Include/core_cm0plus.h: + +../Drivers/CMSIS/Include/cmsis_version.h: + +../Drivers/CMSIS/Include/cmsis_compiler.h: + +../Drivers/CMSIS/Include/cmsis_gcc.h: + +../Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_exti.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h: diff --git a/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o new file mode 100644 index 0000000..c098b18 Binary files /dev/null and b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o differ diff --git a/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.su b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.su new file mode 100644 index 0000000..11aafee --- /dev/null +++ b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.su @@ -0,0 +1,31 @@ +stm32l0xx_hal.c:204:13:HAL_MspInit 0 static +stm32l0xx_hal.c:215:13:HAL_MspDeInit 0 static +stm32l0xx_hal.c:178:19:HAL_DeInit 8 static +stm32l0xx_hal.c:238:26:HAL_InitTick 16 static +stm32l0xx_hal.c:140:19:HAL_Init 8 static +stm32l0xx_hal.c:294:13:HAL_IncTick 0 static +stm32l0xx_hal.c:305:17:HAL_GetTick 0 static +stm32l0xx_hal.c:314:10:HAL_GetTickPrio 0 static +stm32l0xx_hal.c:323:19:HAL_SetTickFreq 16 static +stm32l0xx_hal.c:355:21:HAL_GetTickFreq 0 static +stm32l0xx_hal.c:371:13:HAL_Delay 16 static +stm32l0xx_hal.c:397:13:HAL_SuspendTick 0 static +stm32l0xx_hal.c:413:13:HAL_ResumeTick 0 static +stm32l0xx_hal.c:423:10:HAL_GetHalVersion 0 static +stm32l0xx_hal.c:432:10:HAL_GetREVID 0 static +stm32l0xx_hal.c:441:10:HAL_GetDEVID 0 static +stm32l0xx_hal.c:450:10:HAL_GetUIDw0 0 static +stm32l0xx_hal.c:459:10:HAL_GetUIDw1 0 static +stm32l0xx_hal.c:468:10:HAL_GetUIDw2 0 static +stm32l0xx_hal.c:497:6:HAL_DBGMCU_EnableDBGSleepMode 0 static +stm32l0xx_hal.c:506:6:HAL_DBGMCU_DisableDBGSleepMode 0 static +stm32l0xx_hal.c:515:6:HAL_DBGMCU_EnableDBGStopMode 0 static +stm32l0xx_hal.c:524:6:HAL_DBGMCU_DisableDBGStopMode 0 static +stm32l0xx_hal.c:533:6:HAL_DBGMCU_EnableDBGStandbyMode 0 static +stm32l0xx_hal.c:542:6:HAL_DBGMCU_DisableDBGStandbyMode 0 static +stm32l0xx_hal.c:556:6:HAL_DBGMCU_DBG_EnableLowPowerConfig 0 static +stm32l0xx_hal.c:573:6:HAL_DBGMCU_DBG_DisableLowPowerConfig 0 static +stm32l0xx_hal.c:610:11:HAL_SYSCFG_GetBootMode 0 static +stm32l0xx_hal.c:627:6:HAL_SYSCFG_VREFINT_OutputSelect 0 static +stm32l0xx_hal.c:641:6:HAL_SYSCFG_Enable_Lock_VREFINT 0 static +stm32l0xx_hal.c:651:6:HAL_SYSCFG_Disable_Lock_VREFINT 0 static diff --git a/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.d b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.d new file mode 100644 index 0000000..c045e11 --- /dev/null +++ b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.d @@ -0,0 +1,77 @@ +Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o: \ + ../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h \ + ../Core/Inc/stm32l0xx_hal_conf.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h \ + ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l011xx.h \ + ../Drivers/CMSIS/Include/core_cm0plus.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_exti.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h: + +../Core/Inc/stm32l0xx_hal_conf.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h: + +../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h: + +../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l011xx.h: + +../Drivers/CMSIS/Include/core_cm0plus.h: + +../Drivers/CMSIS/Include/cmsis_version.h: + +../Drivers/CMSIS/Include/cmsis_compiler.h: + +../Drivers/CMSIS/Include/cmsis_gcc.h: + +../Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_exti.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h: diff --git a/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o new file mode 100644 index 0000000..2b4e0ee Binary files /dev/null and b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o differ diff --git a/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.su b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.su new file mode 100644 index 0000000..f5ff9a7 --- /dev/null +++ b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.su @@ -0,0 +1,12 @@ +stm32l0xx_hal_cortex.c:132:6:HAL_NVIC_SetPriority 12 static +stm32l0xx_hal_cortex.c:148:6:HAL_NVIC_EnableIRQ 0 static +stm32l0xx_hal_cortex.c:164:6:HAL_NVIC_DisableIRQ 0 static,ignoring_inline_asm +stm32l0xx_hal_cortex.c:177:6:HAL_NVIC_SystemReset 0 static,ignoring_inline_asm +stm32l0xx_hal_cortex.c:190:10:HAL_SYSTICK_Config 0 static +stm32l0xx_hal_cortex.c:222:10:HAL_NVIC_GetPriority 0 static +stm32l0xx_hal_cortex.c:235:6:HAL_NVIC_SetPendingIRQ 0 static +stm32l0xx_hal_cortex.c:250:10:HAL_NVIC_GetPendingIRQ 0 static +stm32l0xx_hal_cortex.c:263:6:HAL_NVIC_ClearPendingIRQ 0 static +stm32l0xx_hal_cortex.c:278:6:HAL_SYSTICK_CLKSourceConfig 0 static +stm32l0xx_hal_cortex.c:305:13:HAL_SYSTICK_Callback 0 static +stm32l0xx_hal_cortex.c:296:6:HAL_SYSTICK_IRQHandler 8 static diff --git a/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.d b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.d new file mode 100644 index 0000000..1d58e61 --- /dev/null +++ b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.d @@ -0,0 +1,77 @@ +Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o: \ + ../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h \ + ../Core/Inc/stm32l0xx_hal_conf.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h \ + ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l011xx.h \ + ../Drivers/CMSIS/Include/core_cm0plus.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_exti.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h: + +../Core/Inc/stm32l0xx_hal_conf.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h: + +../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h: + +../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l011xx.h: + +../Drivers/CMSIS/Include/core_cm0plus.h: + +../Drivers/CMSIS/Include/cmsis_version.h: + +../Drivers/CMSIS/Include/cmsis_compiler.h: + +../Drivers/CMSIS/Include/cmsis_gcc.h: + +../Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_exti.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h: diff --git a/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o new file mode 100644 index 0000000..454136b Binary files /dev/null and b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o differ diff --git a/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.su b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.su new file mode 100644 index 0000000..4e26e73 --- /dev/null +++ b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.su @@ -0,0 +1,12 @@ +stm32l0xx_hal_dma.c:139:19:HAL_DMA_Init 24 static +stm32l0xx_hal_dma.c:214:19:HAL_DMA_DeInit 16 static +stm32l0xx_hal_dma.c:294:19:HAL_DMA_Start 32 static +stm32l0xx_hal_dma.c:337:19:HAL_DMA_Start_IT 32 static +stm32l0xx_hal_dma.c:392:19:HAL_DMA_Abort 12 static +stm32l0xx_hal_dma.c:433:19:HAL_DMA_Abort_IT 16 static +stm32l0xx_hal_dma.c:478:19:HAL_DMA_PollForTransfer 40 static +stm32l0xx_hal_dma.c:579:6:HAL_DMA_IRQHandler 24 static +stm32l0xx_hal_dma.c:673:19:HAL_DMA_RegisterCallback 12 static +stm32l0xx_hal_dma.c:724:19:HAL_DMA_UnRegisterCallback 12 static +stm32l0xx_hal_dma.c:802:22:HAL_DMA_GetState 0 static +stm32l0xx_hal_dma.c:814:10:HAL_DMA_GetError 0 static diff --git a/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.d b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.d new file mode 100644 index 0000000..445f568 --- /dev/null +++ b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.d @@ -0,0 +1,77 @@ +Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o: \ + ../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.c \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h \ + ../Core/Inc/stm32l0xx_hal_conf.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h \ + ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l011xx.h \ + ../Drivers/CMSIS/Include/core_cm0plus.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_exti.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h: + +../Core/Inc/stm32l0xx_hal_conf.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h: + +../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h: + +../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l011xx.h: + +../Drivers/CMSIS/Include/core_cm0plus.h: + +../Drivers/CMSIS/Include/cmsis_version.h: + +../Drivers/CMSIS/Include/cmsis_compiler.h: + +../Drivers/CMSIS/Include/cmsis_gcc.h: + +../Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_exti.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h: diff --git a/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o new file mode 100644 index 0000000..0472394 Binary files /dev/null and b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o differ diff --git a/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.su b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.su new file mode 100644 index 0000000..0a1159b --- /dev/null +++ b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.su @@ -0,0 +1,9 @@ +stm32l0xx_hal_exti.c:143:19:HAL_EXTI_SetConfigLine 16 static +stm32l0xx_hal_exti.c:238:19:HAL_EXTI_GetConfigLine 20 static +stm32l0xx_hal_exti.c:327:19:HAL_EXTI_ClearConfigLine 12 static +stm32l0xx_hal_exti.c:380:19:HAL_EXTI_RegisterCallback 0 static +stm32l0xx_hal_exti.c:405:19:HAL_EXTI_GetHandle 0 static +stm32l0xx_hal_exti.c:445:6:HAL_EXTI_IRQHandler 8 static +stm32l0xx_hal_exti.c:477:10:HAL_EXTI_GetPending 0 static +stm32l0xx_hal_exti.c:506:6:HAL_EXTI_ClearPending 0 static +stm32l0xx_hal_exti.c:527:6:HAL_EXTI_GenerateSWI 0 static diff --git a/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.d b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.d new file mode 100644 index 0000000..fac570a --- /dev/null +++ b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.d @@ -0,0 +1,77 @@ +Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o: \ + ../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h \ + ../Core/Inc/stm32l0xx_hal_conf.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h \ + ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l011xx.h \ + ../Drivers/CMSIS/Include/core_cm0plus.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_exti.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h: + +../Core/Inc/stm32l0xx_hal_conf.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h: + +../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h: + +../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l011xx.h: + +../Drivers/CMSIS/Include/core_cm0plus.h: + +../Drivers/CMSIS/Include/cmsis_version.h: + +../Drivers/CMSIS/Include/cmsis_compiler.h: + +../Drivers/CMSIS/Include/cmsis_gcc.h: + +../Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_exti.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h: diff --git a/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o new file mode 100644 index 0000000..b1d6d7e Binary files /dev/null and b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o differ diff --git a/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.su b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.su new file mode 100644 index 0000000..66e2d88 --- /dev/null +++ b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.su @@ -0,0 +1,13 @@ +stm32l0xx_hal_flash.c:703:13:FLASH_SetErrorCode 12 static +stm32l0xx_hal_flash.c:273:19:HAL_FLASH_Program_IT 16 static +stm32l0xx_hal_flash.c:428:13:HAL_FLASH_EndOfOperationCallback 0 static +stm32l0xx_hal_flash.c:445:13:HAL_FLASH_OperationErrorCallback 0 static +stm32l0xx_hal_flash.c:304:6:HAL_FLASH_IRQHandler 16 static +stm32l0xx_hal_flash.c:478:19:HAL_FLASH_Unlock 8 static,ignoring_inline_asm +stm32l0xx_hal_flash.c:527:19:HAL_FLASH_Lock 0 static +stm32l0xx_hal_flash.c:542:19:HAL_FLASH_OB_Unlock 0 static,ignoring_inline_asm +stm32l0xx_hal_flash.c:579:19:HAL_FLASH_OB_Lock 0 static +stm32l0xx_hal_flash.c:624:10:HAL_FLASH_GetError 0 static +stm32l0xx_hal_flash.c:646:19:FLASH_WaitForLastOperation 16 static +stm32l0xx_hal_flash.c:231:19:HAL_FLASH_Program 16 static +stm32l0xx_hal_flash.c:592:19:HAL_FLASH_OB_Launch 8 static diff --git a/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.d b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.d new file mode 100644 index 0000000..7827c1f --- /dev/null +++ b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.d @@ -0,0 +1,77 @@ +Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o: \ + ../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h \ + ../Core/Inc/stm32l0xx_hal_conf.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h \ + ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l011xx.h \ + ../Drivers/CMSIS/Include/core_cm0plus.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_exti.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h: + +../Core/Inc/stm32l0xx_hal_conf.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h: + +../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h: + +../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l011xx.h: + +../Drivers/CMSIS/Include/core_cm0plus.h: + +../Drivers/CMSIS/Include/cmsis_version.h: + +../Drivers/CMSIS/Include/cmsis_compiler.h: + +../Drivers/CMSIS/Include/cmsis_gcc.h: + +../Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_exti.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h: diff --git a/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o new file mode 100644 index 0000000..52b7b72 Binary files /dev/null and b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o differ diff --git a/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.su b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.su new file mode 100644 index 0000000..2342f6d --- /dev/null +++ b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.su @@ -0,0 +1,16 @@ +stm32l0xx_hal_flash_ex.c:1046:26:FLASH_OB_ProtectedSectorsConfig 16 static +stm32l0xx_hal_flash_ex.c:327:19:HAL_FLASHEx_OBProgram 32 static +stm32l0xx_hal_flash_ex.c:410:6:HAL_FLASHEx_OBGetConfig 0 static +stm32l0xx_hal_flash_ex.c:443:19:HAL_FLASHEx_AdvOBProgram 8 static +stm32l0xx_hal_flash_ex.c:486:6:HAL_FLASHEx_AdvOBGetConfig 0 static +stm32l0xx_hal_flash_ex.c:526:19:HAL_FLASHEx_OB_SelectPCROP 8 static +stm32l0xx_hal_flash_ex.c:568:19:HAL_FLASHEx_OB_DeSelectPCROP 8 static +stm32l0xx_hal_flash_ex.c:634:19:HAL_FLASHEx_DATAEEPROM_Unlock 0 static,ignoring_inline_asm +stm32l0xx_hal_flash_ex.c:664:19:HAL_FLASHEx_DATAEEPROM_Lock 0 static +stm32l0xx_hal_flash_ex.c:682:19:HAL_FLASHEx_DATAEEPROM_Erase 8 static +stm32l0xx_hal_flash_ex.c:724:21:HAL_FLASHEx_DATAEEPROM_Program 24 static +stm32l0xx_hal_flash_ex.c:780:6:HAL_FLASHEx_DATAEEPROM_EnableFixedTimeProgram 0 static +stm32l0xx_hal_flash_ex.c:789:6:HAL_FLASHEx_DATAEEPROM_DisableFixedTimeProgram 0 static +stm32l0xx_hal_flash_ex.c:1246:6:FLASH_PageErase 8 static +stm32l0xx_hal_flash_ex.c:171:19:HAL_FLASHEx_Erase 24 static +stm32l0xx_hal_flash_ex.c:235:19:HAL_FLASHEx_Erase_IT 32 static diff --git a/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.d b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.d new file mode 100644 index 0000000..56317e1 --- /dev/null +++ b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.d @@ -0,0 +1,77 @@ +Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o: \ + ../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h \ + ../Core/Inc/stm32l0xx_hal_conf.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h \ + ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l011xx.h \ + ../Drivers/CMSIS/Include/core_cm0plus.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_exti.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h: + +../Core/Inc/stm32l0xx_hal_conf.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h: + +../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h: + +../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l011xx.h: + +../Drivers/CMSIS/Include/core_cm0plus.h: + +../Drivers/CMSIS/Include/cmsis_version.h: + +../Drivers/CMSIS/Include/cmsis_compiler.h: + +../Drivers/CMSIS/Include/cmsis_gcc.h: + +../Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_exti.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h: diff --git a/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o new file mode 100644 index 0000000..3b46d67 Binary files /dev/null and b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o differ diff --git a/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.su b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.su new file mode 100644 index 0000000..66b7015 --- /dev/null +++ b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.su @@ -0,0 +1,5 @@ +stm32l0xx_hal_flash_ramfunc.c:458:37:FLASHRAM_WaitForLastOperation.constprop 12 static +stm32l0xx_hal_flash_ramfunc.c:115:30:HAL_FLASHEx_EnableRunPowerDown 0 static +stm32l0xx_hal_flash_ramfunc.c:128:30:HAL_FLASHEx_DisableRunPowerDown 0 static +stm32l0xx_hal_flash_ramfunc.c:305:30:HAL_FLASHEx_HalfPageProgram 16 static,ignoring_inline_asm +stm32l0xx_hal_flash_ramfunc.c:376:30:HAL_FLASHEx_GetError 0 static diff --git a/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.d b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.d new file mode 100644 index 0000000..c536a70 --- /dev/null +++ b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.d @@ -0,0 +1,77 @@ +Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o: \ + ../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h \ + ../Core/Inc/stm32l0xx_hal_conf.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h \ + ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l011xx.h \ + ../Drivers/CMSIS/Include/core_cm0plus.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_exti.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h: + +../Core/Inc/stm32l0xx_hal_conf.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h: + +../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h: + +../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l011xx.h: + +../Drivers/CMSIS/Include/core_cm0plus.h: + +../Drivers/CMSIS/Include/cmsis_version.h: + +../Drivers/CMSIS/Include/cmsis_compiler.h: + +../Drivers/CMSIS/Include/cmsis_gcc.h: + +../Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_exti.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h: diff --git a/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o new file mode 100644 index 0000000..5b74693 Binary files /dev/null and b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o differ diff --git a/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.su b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.su new file mode 100644 index 0000000..74261e1 --- /dev/null +++ b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.su @@ -0,0 +1,8 @@ +stm32l0xx_hal_gpio.c:167:6:HAL_GPIO_Init 40 static +stm32l0xx_hal_gpio.c:292:6:HAL_GPIO_DeInit 40 static +stm32l0xx_hal_gpio.c:373:15:HAL_GPIO_ReadPin 0 static +stm32l0xx_hal_gpio.c:409:6:HAL_GPIO_WritePin 0 static +stm32l0xx_hal_gpio.c:433:6:HAL_GPIO_TogglePin 0 static +stm32l0xx_hal_gpio.c:460:19:HAL_GPIO_LockPin 8 static +stm32l0xx_hal_gpio.c:508:13:HAL_GPIO_EXTI_Callback 0 static +stm32l0xx_hal_gpio.c:493:6:HAL_GPIO_EXTI_IRQHandler 8 static diff --git a/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.d b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.d new file mode 100644 index 0000000..b4e166f --- /dev/null +++ b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.d @@ -0,0 +1,77 @@ +Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o: \ + ../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h \ + ../Core/Inc/stm32l0xx_hal_conf.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h \ + ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l011xx.h \ + ../Drivers/CMSIS/Include/core_cm0plus.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_exti.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h: + +../Core/Inc/stm32l0xx_hal_conf.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h: + +../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h: + +../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l011xx.h: + +../Drivers/CMSIS/Include/core_cm0plus.h: + +../Drivers/CMSIS/Include/cmsis_version.h: + +../Drivers/CMSIS/Include/cmsis_compiler.h: + +../Drivers/CMSIS/Include/cmsis_gcc.h: + +../Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_exti.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h: diff --git a/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o new file mode 100644 index 0000000..802181e Binary files /dev/null and b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o differ diff --git a/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.su b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.su new file mode 100644 index 0000000..b02113a --- /dev/null +++ b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.su @@ -0,0 +1,79 @@ +stm32l0xx_hal_i2c.c:6005:13:I2C_Flush_TXDR 0 static +stm32l0xx_hal_i2c.c:6453:13:I2C_TransferConfig 12 static +stm32l0xx_hal_i2c.c:6476:13:I2C_Enable_IRQ 8 static +stm32l0xx_hal_i2c.c:6547:13:I2C_Disable_IRQ 8 static +stm32l0xx_hal_i2c.c:6610:13:I2C_ConvertOtherXferOptions 0 static +stm32l0xx_hal_i2c.c:6385:26:I2C_IsAcknowledgeFailed 24 static +stm32l0xx_hal_i2c.c:6322:26:I2C_WaitOnRXNEFlagUntilTimeout 24 static +stm32l0xx_hal_i2c.c:6288:26:I2C_WaitOnSTOPFlagUntilTimeout 24 static +stm32l0xx_hal_i2c.c:6220:26:I2C_WaitOnFlagUntilTimeout 24 static +stm32l0xx_hal_i2c.c:6251:26:I2C_WaitOnTXISFlagUntilTimeout 24 static +stm32l0xx_hal_i2c.c:5178:26:I2C_RequestMemoryWrite 32 static +stm32l0xx_hal_i2c.c:5232:26:I2C_RequestMemoryRead 32 static +stm32l0xx_hal_i2c.c:631:13:HAL_I2C_MspInit 0 static +stm32l0xx_hal_i2c.c:476:19:HAL_I2C_Init 16 static +stm32l0xx_hal_i2c.c:647:13:HAL_I2C_MspDeInit 0 static +stm32l0xx_hal_i2c.c:585:19:HAL_I2C_DeInit 16 static +stm32l0xx_hal_i2c.c:1068:19:HAL_I2C_Master_Transmit 48 static +stm32l0xx_hal_i2c.c:1183:19:HAL_I2C_Master_Receive 48 static +stm32l0xx_hal_i2c.c:1297:19:HAL_I2C_Slave_Transmit 48 static +stm32l0xx_hal_i2c.c:1434:19:HAL_I2C_Slave_Receive 56 static +stm32l0xx_hal_i2c.c:1560:19:HAL_I2C_Master_Transmit_IT 40 static +stm32l0xx_hal_i2c.c:1630:19:HAL_I2C_Master_Receive_IT 40 static +stm32l0xx_hal_i2c.c:1697:19:HAL_I2C_Slave_Transmit_IT 24 static +stm32l0xx_hal_i2c.c:1746:19:HAL_I2C_Slave_Receive_IT 24 static +stm32l0xx_hal_i2c.c:1797:19:HAL_I2C_Master_Transmit_DMA 48 static +stm32l0xx_hal_i2c.c:1941:19:HAL_I2C_Master_Receive_DMA 48 static +stm32l0xx_hal_i2c.c:2083:19:HAL_I2C_Slave_Transmit_DMA 32 static +stm32l0xx_hal_i2c.c:2186:19:HAL_I2C_Slave_Receive_DMA 32 static +stm32l0xx_hal_i2c.c:2293:19:HAL_I2C_Mem_Write 56 static +stm32l0xx_hal_i2c.c:2428:19:HAL_I2C_Mem_Read 64 static +stm32l0xx_hal_i2c.c:2561:19:HAL_I2C_Mem_Write_IT 56 static +stm32l0xx_hal_i2c.c:2653:19:HAL_I2C_Mem_Read_IT 56 static +stm32l0xx_hal_i2c.c:2744:19:HAL_I2C_Mem_Write_DMA 56 static +stm32l0xx_hal_i2c.c:2889:19:HAL_I2C_Mem_Read_DMA 56 static +stm32l0xx_hal_i2c.c:3031:19:HAL_I2C_IsDeviceReady 56 static +stm32l0xx_hal_i2c.c:3172:19:HAL_I2C_Master_Seq_Transmit_IT 40 static +stm32l0xx_hal_i2c.c:3257:19:HAL_I2C_Master_Seq_Transmit_DMA 56 static +stm32l0xx_hal_i2c.c:3420:19:HAL_I2C_Master_Seq_Receive_IT 40 static +stm32l0xx_hal_i2c.c:3505:19:HAL_I2C_Master_Seq_Receive_DMA 56 static +stm32l0xx_hal_i2c.c:3666:19:HAL_I2C_Slave_Seq_Transmit_IT 40 static +stm32l0xx_hal_i2c.c:3762:19:HAL_I2C_Slave_Seq_Transmit_DMA 40 static +stm32l0xx_hal_i2c.c:3942:19:HAL_I2C_Slave_Seq_Receive_IT 40 static +stm32l0xx_hal_i2c.c:4038:19:HAL_I2C_Slave_Seq_Receive_DMA 48 static +stm32l0xx_hal_i2c.c:4214:19:HAL_I2C_EnableListen_IT 8 static +stm32l0xx_hal_i2c.c:4238:19:HAL_I2C_DisableListen_IT 16 static +stm32l0xx_hal_i2c.c:4271:19:HAL_I2C_Master_Abort_IT 32 static +stm32l0xx_hal_i2c.c:4333:6:HAL_I2C_EV_IRQHandler 8 static +stm32l0xx_hal_i2c.c:4401:13:HAL_I2C_MasterTxCpltCallback 0 static +stm32l0xx_hal_i2c.c:4417:13:HAL_I2C_MasterRxCpltCallback 0 static +stm32l0xx_hal_i2c.c:5375:13:I2C_ITMasterSeqCplt 16 static +stm32l0xx_hal_i2c.c:4432:13:HAL_I2C_SlaveTxCpltCallback 0 static +stm32l0xx_hal_i2c.c:4448:13:HAL_I2C_SlaveRxCpltCallback 0 static +stm32l0xx_hal_i2c.c:5428:13:I2C_ITSlaveSeqCplt 8 static +stm32l0xx_hal_i2c.c:6074:13:I2C_DMASlaveTransmitCplt 8 static +stm32l0xx_hal_i2c.c:6149:13:I2C_DMASlaveReceiveCplt 8 static +stm32l0xx_hal_i2c.c:4466:13:HAL_I2C_AddrCallback 0 static +stm32l0xx_hal_i2c.c:5280:13:I2C_ITAddrCplt.isra.0 32 static +stm32l0xx_hal_i2c.c:4484:13:HAL_I2C_ListenCpltCallback 0 static +stm32l0xx_hal_i2c.c:5804:13:I2C_ITListenCplt 8 static +stm32l0xx_hal_i2c.c:4500:13:HAL_I2C_MemTxCpltCallback 0 static +stm32l0xx_hal_i2c.c:4516:13:HAL_I2C_MemRxCpltCallback 0 static +stm32l0xx_hal_i2c.c:4532:13:HAL_I2C_ErrorCallback 0 static +stm32l0xx_hal_i2c.c:4548:13:HAL_I2C_AbortCpltCallback 0 static +stm32l0xx_hal_i2c.c:5967:13:I2C_TreatErrorCallback 8 static +stm32l0xx_hal_i2c.c:5855:13:I2C_ITError 16 static +stm32l0xx_hal_i2c.c:5645:13:I2C_ITSlaveCplt 32 static +stm32l0xx_hal_i2c.c:4768:26:I2C_Slave_ISR_IT 32 static +stm32l0xx_hal_i2c.c:5502:13:I2C_ITMasterCplt 24 static +stm32l0xx_hal_i2c.c:4631:26:I2C_Master_ISR_IT 32 static +stm32l0xx_hal_i2c.c:5038:26:I2C_Slave_ISR_DMA 32 static +stm32l0xx_hal_i2c.c:4903:26:I2C_Master_ISR_DMA 24 static +stm32l0xx_hal_i2c.c:6176:13:I2C_DMAError 8 static +stm32l0xx_hal_i2c.c:6026:13:I2C_DMAMasterTransmitCplt 8 static +stm32l0xx_hal_i2c.c:6101:13:I2C_DMAMasterReceiveCplt 8 static +stm32l0xx_hal_i2c.c:4352:6:HAL_I2C_ER_IRQHandler 16 static +stm32l0xx_hal_i2c.c:6193:13:I2C_DMAAbort 8 static +stm32l0xx_hal_i2c.c:4583:22:HAL_I2C_GetState 0 static +stm32l0xx_hal_i2c.c:4595:21:HAL_I2C_GetMode 0 static +stm32l0xx_hal_i2c.c:4606:10:HAL_I2C_GetError 0 static diff --git a/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.d b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.d new file mode 100644 index 0000000..4757393 --- /dev/null +++ b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.d @@ -0,0 +1,77 @@ +Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o: \ + ../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h \ + ../Core/Inc/stm32l0xx_hal_conf.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h \ + ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l011xx.h \ + ../Drivers/CMSIS/Include/core_cm0plus.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_exti.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h: + +../Core/Inc/stm32l0xx_hal_conf.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h: + +../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h: + +../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l011xx.h: + +../Drivers/CMSIS/Include/core_cm0plus.h: + +../Drivers/CMSIS/Include/cmsis_version.h: + +../Drivers/CMSIS/Include/cmsis_compiler.h: + +../Drivers/CMSIS/Include/cmsis_gcc.h: + +../Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_exti.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h: diff --git a/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o new file mode 100644 index 0000000..e509582 Binary files /dev/null and b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o differ diff --git a/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.su b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.su new file mode 100644 index 0000000..86511b8 --- /dev/null +++ b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.su @@ -0,0 +1,6 @@ +stm32l0xx_hal_i2c_ex.c:97:19:HAL_I2CEx_ConfigAnalogFilter 20 static +stm32l0xx_hal_i2c_ex.c:141:19:HAL_I2CEx_ConfigDigitalFilter 20 static +stm32l0xx_hal_i2c_ex.c:192:19:HAL_I2CEx_EnableWakeUp 16 static +stm32l0xx_hal_i2c_ex.c:231:19:HAL_I2CEx_DisableWakeUp 16 static +stm32l0xx_hal_i2c_ex.c:280:6:HAL_I2CEx_EnableFastModePlus 0 static +stm32l0xx_hal_i2c_ex.c:307:6:HAL_I2CEx_DisableFastModePlus 0 static diff --git a/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.d b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.d new file mode 100644 index 0000000..31f49b6 --- /dev/null +++ b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.d @@ -0,0 +1,77 @@ +Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o: \ + ../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h \ + ../Core/Inc/stm32l0xx_hal_conf.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h \ + ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l011xx.h \ + ../Drivers/CMSIS/Include/core_cm0plus.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_exti.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h: + +../Core/Inc/stm32l0xx_hal_conf.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h: + +../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h: + +../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l011xx.h: + +../Drivers/CMSIS/Include/core_cm0plus.h: + +../Drivers/CMSIS/Include/cmsis_version.h: + +../Drivers/CMSIS/Include/cmsis_compiler.h: + +../Drivers/CMSIS/Include/cmsis_gcc.h: + +../Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_exti.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h: diff --git a/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o new file mode 100644 index 0000000..f2cca91 Binary files /dev/null and b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o differ diff --git a/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.su b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.su new file mode 100644 index 0000000..eb3608d --- /dev/null +++ b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.su @@ -0,0 +1,17 @@ +stm32l0xx_hal_pwr.c:80:6:HAL_PWR_DeInit 0 static +stm32l0xx_hal_pwr.c:327:6:HAL_PWR_EnableBkUpAccess 0 static +stm32l0xx_hal_pwr.c:340:6:HAL_PWR_DisableBkUpAccess 0 static +stm32l0xx_hal_pwr.c:356:6:HAL_PWR_ConfigPVD 0 static +stm32l0xx_hal_pwr.c:399:6:HAL_PWR_EnablePVD 0 static +stm32l0xx_hal_pwr.c:409:6:HAL_PWR_DisablePVD 0 static +stm32l0xx_hal_pwr.c:425:6:HAL_PWR_EnableWakeUpPin 0 static +stm32l0xx_hal_pwr.c:442:6:HAL_PWR_DisableWakeUpPin 0 static +stm32l0xx_hal_pwr.c:465:6:HAL_PWR_EnterSLEEPMode 20 static,ignoring_inline_asm +stm32l0xx_hal_pwr.c:546:6:HAL_PWR_EnterSTOPMode 20 static,ignoring_inline_asm +stm32l0xx_hal_pwr.c:615:6:HAL_PWR_EnterSTANDBYMode 0 static,ignoring_inline_asm +stm32l0xx_hal_pwr.c:639:6:HAL_PWR_EnableSleepOnExit 0 static +stm32l0xx_hal_pwr.c:652:6:HAL_PWR_DisableSleepOnExit 0 static +stm32l0xx_hal_pwr.c:665:6:HAL_PWR_EnableSEVOnPend 0 static +stm32l0xx_hal_pwr.c:678:6:HAL_PWR_DisableSEVOnPend 0 static +stm32l0xx_hal_pwr.c:707:13:HAL_PWR_PVDCallback 0 static +stm32l0xx_hal_pwr.c:690:6:HAL_PWR_PVD_IRQHandler 16 static diff --git a/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.d b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.d new file mode 100644 index 0000000..730ee4c --- /dev/null +++ b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.d @@ -0,0 +1,77 @@ +Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o: \ + ../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h \ + ../Core/Inc/stm32l0xx_hal_conf.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h \ + ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l011xx.h \ + ../Drivers/CMSIS/Include/core_cm0plus.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_exti.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h: + +../Core/Inc/stm32l0xx_hal_conf.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h: + +../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h: + +../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l011xx.h: + +../Drivers/CMSIS/Include/core_cm0plus.h: + +../Drivers/CMSIS/Include/cmsis_version.h: + +../Drivers/CMSIS/Include/cmsis_compiler.h: + +../Drivers/CMSIS/Include/cmsis_gcc.h: + +../Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_exti.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h: diff --git a/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o new file mode 100644 index 0000000..7b463b8 Binary files /dev/null and b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o differ diff --git a/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.su b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.su new file mode 100644 index 0000000..3a06fb6 --- /dev/null +++ b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.su @@ -0,0 +1,7 @@ +stm32l0xx_hal_pwr_ex.c:70:10:HAL_PWREx_GetVoltageRange 0 static +stm32l0xx_hal_pwr_ex.c:83:6:HAL_PWREx_EnableFastWakeUp 0 static +stm32l0xx_hal_pwr_ex.c:93:6:HAL_PWREx_DisableFastWakeUp 0 static +stm32l0xx_hal_pwr_ex.c:103:6:HAL_PWREx_EnableUltraLowPower 0 static +stm32l0xx_hal_pwr_ex.c:113:6:HAL_PWREx_DisableUltraLowPower 0 static +stm32l0xx_hal_pwr_ex.c:131:6:HAL_PWREx_EnableLowPowerRunMode 0 static +stm32l0xx_hal_pwr_ex.c:146:19:HAL_PWREx_DisableLowPowerRunMode 8 static diff --git a/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.d b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.d new file mode 100644 index 0000000..07ba01e --- /dev/null +++ b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.d @@ -0,0 +1,77 @@ +Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o: \ + ../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h \ + ../Core/Inc/stm32l0xx_hal_conf.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h \ + ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l011xx.h \ + ../Drivers/CMSIS/Include/core_cm0plus.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_exti.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h: + +../Core/Inc/stm32l0xx_hal_conf.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h: + +../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h: + +../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l011xx.h: + +../Drivers/CMSIS/Include/core_cm0plus.h: + +../Drivers/CMSIS/Include/cmsis_version.h: + +../Drivers/CMSIS/Include/cmsis_compiler.h: + +../Drivers/CMSIS/Include/cmsis_gcc.h: + +../Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_exti.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h: diff --git a/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o new file mode 100644 index 0000000..aaf9636 Binary files /dev/null and b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o differ diff --git a/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.su b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.su new file mode 100644 index 0000000..57d4d05 --- /dev/null +++ b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.su @@ -0,0 +1,10 @@ +stm32l0xx_hal_rcc.c:223:19:HAL_RCC_DeInit 32 static +stm32l0xx_hal_rcc.c:1120:6:HAL_RCC_MCOConfig 56 static +stm32l0xx_hal_rcc.c:1213:10:HAL_RCC_GetSysClockFreq 16 static +stm32l0xx_hal_rcc.c:338:19:HAL_RCC_OscConfig 48 static +stm32l0xx_hal_rcc.c:859:19:HAL_RCC_ClockConfig 32 static +stm32l0xx_hal_rcc.c:1283:10:HAL_RCC_GetHCLKFreq 0 static +stm32l0xx_hal_rcc.c:1294:10:HAL_RCC_GetPCLK1Freq 0 static +stm32l0xx_hal_rcc.c:1306:10:HAL_RCC_GetPCLK2Freq 0 static +stm32l0xx_hal_rcc.c:1319:6:HAL_RCC_GetOscConfig 8 static +stm32l0xx_hal_rcc.c:1422:6:HAL_RCC_GetClockConfig 12 static diff --git a/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.d b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.d new file mode 100644 index 0000000..944b750 --- /dev/null +++ b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.d @@ -0,0 +1,77 @@ +Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o: \ + ../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h \ + ../Core/Inc/stm32l0xx_hal_conf.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h \ + ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l011xx.h \ + ../Drivers/CMSIS/Include/core_cm0plus.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_exti.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h: + +../Core/Inc/stm32l0xx_hal_conf.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h: + +../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h: + +../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l011xx.h: + +../Drivers/CMSIS/Include/core_cm0plus.h: + +../Drivers/CMSIS/Include/cmsis_version.h: + +../Drivers/CMSIS/Include/cmsis_compiler.h: + +../Drivers/CMSIS/Include/cmsis_gcc.h: + +../Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_exti.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h: diff --git a/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o new file mode 100644 index 0000000..07132d2 Binary files /dev/null and b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o differ diff --git a/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.su b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.su new file mode 100644 index 0000000..6c89855 --- /dev/null +++ b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.su @@ -0,0 +1,8 @@ +stm32l0xx_hal_rcc_ex.c:97:19:HAL_RCCEx_PeriphCLKConfig 32 static +stm32l0xx_hal_rcc_ex.c:296:6:HAL_RCCEx_GetPeriphCLKConfig 0 static +stm32l0xx_hal_rcc_ex.c:374:10:HAL_RCCEx_GetPeriphCLKFreq 16 static +stm32l0xx_hal_rcc_ex.c:744:6:HAL_RCCEx_EnableLSECSS 0 static +stm32l0xx_hal_rcc_ex.c:756:6:HAL_RCCEx_DisableLSECSS 0 static +stm32l0xx_hal_rcc_ex.c:770:6:HAL_RCCEx_EnableLSECSS_IT 0 static +stm32l0xx_hal_rcc_ex.c:804:13:HAL_RCCEx_LSECSS_Callback 0 static +stm32l0xx_hal_rcc_ex.c:787:6:HAL_RCCEx_LSECSS_IRQHandler 16 static diff --git a/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.d b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.d new file mode 100644 index 0000000..41e02c5 --- /dev/null +++ b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.d @@ -0,0 +1,77 @@ +Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o: \ + ../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h \ + ../Core/Inc/stm32l0xx_hal_conf.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h \ + ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l011xx.h \ + ../Drivers/CMSIS/Include/core_cm0plus.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_exti.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h: + +../Core/Inc/stm32l0xx_hal_conf.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h: + +../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h: + +../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l011xx.h: + +../Drivers/CMSIS/Include/core_cm0plus.h: + +../Drivers/CMSIS/Include/cmsis_version.h: + +../Drivers/CMSIS/Include/cmsis_compiler.h: + +../Drivers/CMSIS/Include/cmsis_gcc.h: + +../Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_exti.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h: diff --git a/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o new file mode 100644 index 0000000..dba2695 Binary files /dev/null and b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o differ diff --git a/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.su b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.su new file mode 100644 index 0000000..e69de29 diff --git a/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.d b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.d new file mode 100644 index 0000000..28406c1 --- /dev/null +++ b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.d @@ -0,0 +1,77 @@ +Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o: \ + ../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h \ + ../Core/Inc/stm32l0xx_hal_conf.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h \ + ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l011xx.h \ + ../Drivers/CMSIS/Include/core_cm0plus.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_exti.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h: + +../Core/Inc/stm32l0xx_hal_conf.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h: + +../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h: + +../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l011xx.h: + +../Drivers/CMSIS/Include/core_cm0plus.h: + +../Drivers/CMSIS/Include/cmsis_version.h: + +../Drivers/CMSIS/Include/cmsis_compiler.h: + +../Drivers/CMSIS/Include/cmsis_gcc.h: + +../Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_exti.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h: diff --git a/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o new file mode 100644 index 0000000..bf36455 Binary files /dev/null and b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o differ diff --git a/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.su b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.su new file mode 100644 index 0000000..e69de29 diff --git a/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.su b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.su new file mode 100644 index 0000000..addc091 --- /dev/null +++ b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.su @@ -0,0 +1,64 @@ +stm32l0xx_hal_uart.c:3515:13:UART_EndRxTransfer 0 static +stm32l0xx_hal_uart.c:3910:13:UART_TxISR_8BIT 8 static +stm32l0xx_hal_uart.c:3939:13:UART_TxISR_16BIT 8 static +stm32l0xx_hal_uart.c:653:13:HAL_UART_MspInit 0 static +stm32l0xx_hal_uart.c:668:13:HAL_UART_MspDeInit 0 static +stm32l0xx_hal_uart.c:607:19:HAL_UART_DeInit 16 static +stm32l0xx_hal_uart.c:1288:19:HAL_UART_Transmit_IT 16 static +stm32l0xx_hal_uart.c:1416:19:HAL_UART_Transmit_DMA 32 static +stm32l0xx_hal_uart.c:1557:19:HAL_UART_DMAPause 12 static +stm32l0xx_hal_uart.c:1591:19:HAL_UART_DMAResume 8 static +stm32l0xx_hal_uart.c:1623:19:HAL_UART_DMAStop 16 static +stm32l0xx_hal_uart.c:1698:19:HAL_UART_Abort 16 static +stm32l0xx_hal_uart.c:1793:19:HAL_UART_AbortTransmit 8 static +stm32l0xx_hal_uart.c:1845:19:HAL_UART_AbortReceive 8 static +stm32l0xx_hal_uart.c:2525:13:HAL_UART_TxCpltCallback 0 static +stm32l0xx_hal_uart.c:3541:13:UART_DMATransmitCplt 8 static +stm32l0xx_hal_uart.c:2540:13:HAL_UART_TxHalfCpltCallback 0 static +stm32l0xx_hal_uart.c:3575:13:UART_DMATxHalfCplt 8 static +stm32l0xx_hal_uart.c:2555:13:HAL_UART_RxCpltCallback 0 static +stm32l0xx_hal_uart.c:2570:13:HAL_UART_RxHalfCpltCallback 0 static +stm32l0xx_hal_uart.c:2585:13:HAL_UART_ErrorCallback 0 static +stm32l0xx_hal_uart.c:3684:13:UART_DMAError 8 static +stm32l0xx_hal_uart.c:3724:13:UART_DMAAbortOnError 8 static +stm32l0xx_hal_uart.c:2600:13:HAL_UART_AbortCpltCallback 0 static +stm32l0xx_hal_uart.c:1912:19:HAL_UART_Abort_IT 16 static +stm32l0xx_hal_uart.c:3797:13:UART_DMARxAbortCallback 8 static +stm32l0xx_hal_uart.c:3747:13:UART_DMATxAbortCallback 8 static +stm32l0xx_hal_uart.c:2615:13:HAL_UART_AbortTransmitCpltCallback 0 static +stm32l0xx_hal_uart.c:2058:19:HAL_UART_AbortTransmit_IT 8 static +stm32l0xx_hal_uart.c:3849:13:UART_DMATxOnlyAbortCallback 8 static +stm32l0xx_hal_uart.c:2630:13:HAL_UART_AbortReceiveCpltCallback 0 static +stm32l0xx_hal_uart.c:2142:19:HAL_UART_AbortReceive_IT 8 static +stm32l0xx_hal_uart.c:3877:13:UART_DMARxOnlyAbortCallback 8 static +stm32l0xx_hal_uart.c:2647:13:HAL_UARTEx_RxEventCallback 0 static +stm32l0xx_hal_uart.c:2234:6:HAL_UART_IRQHandler 32 static +stm32l0xx_hal_uart.c:3996:13:UART_RxISR_8BIT 8 static +stm32l0xx_hal_uart.c:4066:13:UART_RxISR_16BIT 8 static +stm32l0xx_hal_uart.c:3650:13:UART_DMARxHalfCplt 8 static +stm32l0xx_hal_uart.c:3593:13:UART_DMAReceiveCplt 8 static +stm32l0xx_hal_uart.c:2695:6:HAL_UART_ReceiverTimeout_Config 0 static +stm32l0xx_hal_uart.c:2710:19:HAL_UART_EnableReceiverTimeout 12 static +stm32l0xx_hal_uart.c:2748:19:HAL_UART_DisableReceiverTimeout 12 static +stm32l0xx_hal_uart.c:2826:6:HAL_MultiProcessor_EnterMuteMode 0 static +stm32l0xx_hal_uart.c:2836:19:HAL_HalfDuplex_EnableTransmitter 8 static +stm32l0xx_hal_uart.c:2859:19:HAL_HalfDuplex_EnableReceiver 8 static +stm32l0xx_hal_uart.c:2883:19:HAL_LIN_SendBreak 8 static +stm32l0xx_hal_uart.c:2928:23:HAL_UART_GetState 0 static +stm32l0xx_hal_uart.c:2944:10:HAL_UART_GetError 0 static +stm32l0xx_hal_uart.c:2988:19:UART_SetConfig 24 static +stm32l0xx_hal_uart.c:3212:6:UART_AdvFeatureConfig 12 static +stm32l0xx_hal_uart.c:3337:19:UART_WaitOnFlagUntilTimeout 32 static +stm32l0xx_hal_uart.c:1085:19:HAL_UART_Transmit 48 static +stm32l0xx_hal_uart.c:1186:19:HAL_UART_Receive 48 static +stm32l0xx_hal_uart.c:3286:19:UART_CheckIdleState 24 static +stm32l0xx_hal_uart.c:290:19:HAL_UART_Init 8 static +stm32l0xx_hal_uart.c:363:19:HAL_HalfDuplex_Init 8 static +stm32l0xx_hal_uart.c:436:19:HAL_LIN_Init 16 static +stm32l0xx_hal_uart.c:533:19:HAL_MultiProcessor_Init 16 static +stm32l0xx_hal_uart.c:2786:19:HAL_MultiProcessor_EnableMuteMode 8 static +stm32l0xx_hal_uart.c:2806:19:HAL_MultiProcessor_DisableMuteMode 8 static +stm32l0xx_hal_uart.c:3399:19:UART_Start_Receive_IT 8 static +stm32l0xx_hal_uart.c:1357:19:HAL_UART_Receive_IT 16 static +stm32l0xx_hal_uart.c:3443:19:UART_Start_Receive_DMA 32 static +stm32l0xx_hal_uart.c:1508:19:HAL_UART_Receive_DMA 16 static diff --git a/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.su b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.su new file mode 100644 index 0000000..de544b1 --- /dev/null +++ b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.su @@ -0,0 +1,11 @@ +stm32l0xx_hal_uart_ex.c:148:19:HAL_RS485Ex_Init 24 static +stm32l0xx_hal_uart_ex.c:250:13:HAL_UARTEx_WakeupCallback 0 static +stm32l0xx_hal_uart_ex.c:330:19:HAL_UARTEx_EnableClockStopMode 0 static +stm32l0xx_hal_uart_ex.c:349:19:HAL_UARTEx_DisableClockStopMode 0 static +stm32l0xx_hal_uart_ex.c:376:19:HAL_MultiProcessorEx_AddressLength_Set 16 static +stm32l0xx_hal_uart_ex.c:414:19:HAL_UARTEx_StopModeWakeUpSourceConfig 32 static +stm32l0xx_hal_uart_ex.c:469:19:HAL_UARTEx_EnableStopMode 8 static +stm32l0xx_hal_uart_ex.c:488:19:HAL_UARTEx_DisableStopMode 8 static +stm32l0xx_hal_uart_ex.c:521:19:HAL_UARTEx_ReceiveToIdle 40 static +stm32l0xx_hal_uart_ex.c:659:19:HAL_UARTEx_ReceiveToIdle_IT 16 static +stm32l0xx_hal_uart_ex.c:735:19:HAL_UARTEx_ReceiveToIdle_DMA 16 static diff --git a/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.d b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.d new file mode 100644 index 0000000..47760b1 --- /dev/null +++ b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.d @@ -0,0 +1,83 @@ +Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.o: \ + ../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h \ + ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h \ + ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l011xx.h \ + ../Drivers/CMSIS/Include/core_cm0plus.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h \ + ../Core/Inc/stm32l0xx_hal_conf.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_exti.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h: + +../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h: + +../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l011xx.h: + +../Drivers/CMSIS/Include/core_cm0plus.h: + +../Drivers/CMSIS/Include/cmsis_version.h: + +../Drivers/CMSIS/Include/cmsis_compiler.h: + +../Drivers/CMSIS/Include/cmsis_gcc.h: + +../Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h: + +../Core/Inc/stm32l0xx_hal_conf.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_exti.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h: diff --git a/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.o b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.o new file mode 100644 index 0000000..e18332f Binary files /dev/null and b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.o differ diff --git a/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.su b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.su new file mode 100644 index 0000000..7e34b01 --- /dev/null +++ b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.su @@ -0,0 +1,3 @@ +stm32l0xx_ll_dma.c:150:13:LL_DMA_DeInit 16 static +stm32l0xx_ll_dma.c:275:13:LL_DMA_Init 16 static +stm32l0xx_ll_dma.c:343:6:LL_DMA_StructInit 0 static diff --git a/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.d b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.d new file mode 100644 index 0000000..a8b7a20 --- /dev/null +++ b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.d @@ -0,0 +1,80 @@ +Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.o: \ + ../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h \ + ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h \ + ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l011xx.h \ + ../Drivers/CMSIS/Include/core_cm0plus.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h \ + ../Core/Inc/stm32l0xx_hal_conf.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_exti.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h: + +../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h: + +../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l011xx.h: + +../Drivers/CMSIS/Include/core_cm0plus.h: + +../Drivers/CMSIS/Include/cmsis_version.h: + +../Drivers/CMSIS/Include/cmsis_compiler.h: + +../Drivers/CMSIS/Include/cmsis_gcc.h: + +../Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h: + +../Core/Inc/stm32l0xx_hal_conf.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_exti.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h: diff --git a/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.o b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.o new file mode 100644 index 0000000..c54f927 Binary files /dev/null and b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.o differ diff --git a/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.su b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.su new file mode 100644 index 0000000..ca187b5 --- /dev/null +++ b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.su @@ -0,0 +1,3 @@ +stm32l0xx_ll_exti.c:80:10:LL_EXTI_DeInit 0 static +stm32l0xx_ll_exti.c:105:10:LL_EXTI_Init 8 static +stm32l0xx_ll_exti.c:186:6:LL_EXTI_StructInit 0 static diff --git a/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.d b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.d new file mode 100644 index 0000000..b01e799 --- /dev/null +++ b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.d @@ -0,0 +1,83 @@ +Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.o: \ + ../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h \ + ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h \ + ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l011xx.h \ + ../Drivers/CMSIS/Include/core_cm0plus.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h \ + ../Core/Inc/stm32l0xx_hal_conf.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_exti.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h: + +../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h: + +../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l011xx.h: + +../Drivers/CMSIS/Include/core_cm0plus.h: + +../Drivers/CMSIS/Include/cmsis_version.h: + +../Drivers/CMSIS/Include/cmsis_compiler.h: + +../Drivers/CMSIS/Include/cmsis_gcc.h: + +../Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h: + +../Core/Inc/stm32l0xx_hal_conf.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_exti.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h: diff --git a/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.o b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.o new file mode 100644 index 0000000..0e34ffb Binary files /dev/null and b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.o differ diff --git a/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.su b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.su new file mode 100644 index 0000000..bc587a1 --- /dev/null +++ b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.su @@ -0,0 +1,3 @@ +stm32l0xx_ll_gpio.c:96:13:LL_GPIO_DeInit 0 static +stm32l0xx_ll_gpio.c:157:13:LL_GPIO_Init 32 static +stm32l0xx_ll_gpio.c:231:6:LL_GPIO_StructInit 0 static diff --git a/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.d b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.d new file mode 100644 index 0000000..f0883c0 --- /dev/null +++ b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.d @@ -0,0 +1,83 @@ +Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.o: \ + ../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h \ + ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h \ + ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l011xx.h \ + ../Drivers/CMSIS/Include/core_cm0plus.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h \ + ../Core/Inc/stm32l0xx_hal_conf.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_exti.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h: + +../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h: + +../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l011xx.h: + +../Drivers/CMSIS/Include/core_cm0plus.h: + +../Drivers/CMSIS/Include/cmsis_version.h: + +../Drivers/CMSIS/Include/cmsis_compiler.h: + +../Drivers/CMSIS/Include/cmsis_gcc.h: + +../Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h: + +../Core/Inc/stm32l0xx_hal_conf.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_exti.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h: diff --git a/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.o b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.o new file mode 100644 index 0000000..88f5eed Binary files /dev/null and b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.o differ diff --git a/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.su b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.su new file mode 100644 index 0000000..bfa06c8 --- /dev/null +++ b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.su @@ -0,0 +1,3 @@ +stm32l0xx_ll_i2c.c:87:13:LL_I2C_DeInit 0 static +stm32l0xx_ll_i2c.c:139:13:LL_I2C_Init 12 static +stm32l0xx_ll_i2c.c:207:6:LL_I2C_StructInit 0 static diff --git a/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.d b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.d new file mode 100644 index 0000000..3b2c8f9 --- /dev/null +++ b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.d @@ -0,0 +1,86 @@ +Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.o: \ + ../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h \ + ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h \ + ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l011xx.h \ + ../Drivers/CMSIS/Include/core_cm0plus.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h \ + ../Core/Inc/stm32l0xx_hal_conf.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_exti.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h: + +../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h: + +../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l011xx.h: + +../Drivers/CMSIS/Include/core_cm0plus.h: + +../Drivers/CMSIS/Include/cmsis_version.h: + +../Drivers/CMSIS/Include/cmsis_compiler.h: + +../Drivers/CMSIS/Include/cmsis_gcc.h: + +../Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h: + +../Core/Inc/stm32l0xx_hal_conf.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_exti.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h: diff --git a/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.o b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.o new file mode 100644 index 0000000..f6406bb Binary files /dev/null and b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.o differ diff --git a/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.su b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.su new file mode 100644 index 0000000..2af37eb --- /dev/null +++ b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.su @@ -0,0 +1,3 @@ +stm32l0xx_ll_lpuart.c:117:13:LL_LPUART_DeInit 0 static +stm32l0xx_ll_lpuart.c:155:13:LL_LPUART_Init 24 static +stm32l0xx_ll_lpuart.c:232:6:LL_LPUART_StructInit 0 static diff --git a/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_pwr.d b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_pwr.d new file mode 100644 index 0000000..b22a85d --- /dev/null +++ b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_pwr.d @@ -0,0 +1,29 @@ +Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_pwr.o: \ + ../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_pwr.c \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h \ + ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h \ + ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l011xx.h \ + ../Drivers/CMSIS/Include/core_cm0plus.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h: + +../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h: + +../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l011xx.h: + +../Drivers/CMSIS/Include/core_cm0plus.h: + +../Drivers/CMSIS/Include/cmsis_version.h: + +../Drivers/CMSIS/Include/cmsis_compiler.h: + +../Drivers/CMSIS/Include/cmsis_gcc.h: + +../Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h: diff --git a/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_pwr.su b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_pwr.su new file mode 100644 index 0000000..c2f6d7c --- /dev/null +++ b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_pwr.su @@ -0,0 +1,3 @@ +stm32l0xx_ll_bus.h:595:22:LL_APB1_GRP1_ForceReset 16 static +stm32l0xx_ll_bus.h:646:22:LL_APB1_GRP1_ReleaseReset 16 static +stm32l0xx_ll_pwr.c:56:13:LL_PWR_DeInit 8 static diff --git a/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.d b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.d new file mode 100644 index 0000000..58f601e --- /dev/null +++ b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.d @@ -0,0 +1,80 @@ +Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.o: \ + ../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h \ + ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h \ + ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l011xx.h \ + ../Drivers/CMSIS/Include/core_cm0plus.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h \ + ../Core/Inc/stm32l0xx_hal_conf.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_exti.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h: + +../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h: + +../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l011xx.h: + +../Drivers/CMSIS/Include/core_cm0plus.h: + +../Drivers/CMSIS/Include/cmsis_version.h: + +../Drivers/CMSIS/Include/cmsis_compiler.h: + +../Drivers/CMSIS/Include/cmsis_gcc.h: + +../Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h: + +../Core/Inc/stm32l0xx_hal_conf.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_exti.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h: diff --git a/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.o b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.o new file mode 100644 index 0000000..5cf0e08 Binary files /dev/null and b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.o differ diff --git a/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.su b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.su new file mode 100644 index 0000000..0819a7b --- /dev/null +++ b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.su @@ -0,0 +1,13 @@ +stm32l0xx_ll_rcc.h:802:26:LL_RCC_HSI_IsReady 0 static +stm32l0xx_ll_rcc.h:2097:26:LL_RCC_IsActiveFlag_HSIDIV 0 static +stm32l0xx_ll_rcc.c:112:13:LL_RCC_DeInit 16 static,ignoring_inline_asm +stm32l0xx_ll_rcc.c:622:10:RCC_GetHCLKClockFreq 0 static +stm32l0xx_ll_rcc.c:633:10:RCC_GetPCLK1ClockFreq 0 static +stm32l0xx_ll_rcc.c:644:10:RCC_GetPCLK2ClockFreq 0 static +stm32l0xx_ll_rcc.c:654:10:RCC_PLL_GetFreqDomain_SYS 8 static +stm32l0xx_ll_rcc.c:579:10:RCC_GetSystemClockFreq 8 static +stm32l0xx_ll_rcc.c:222:6:LL_RCC_GetSystemClocksFreq 8 static +stm32l0xx_ll_rcc.c:247:10:LL_RCC_GetUSARTClockFreq 8 static +stm32l0xx_ll_rcc.c:344:10:LL_RCC_GetI2CClockFreq 8 static +stm32l0xx_ll_rcc.c:423:10:LL_RCC_GetLPUARTClockFreq 8 static +stm32l0xx_ll_rcc.c:474:10:LL_RCC_GetLPTIMClockFreq 8 static diff --git a/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.d b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.d new file mode 100644 index 0000000..4917ee8 --- /dev/null +++ b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.d @@ -0,0 +1,89 @@ +Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.o: \ + ../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h \ + ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h \ + ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l011xx.h \ + ../Drivers/CMSIS/Include/core_cm0plus.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h \ + ../Core/Inc/stm32l0xx_hal_conf.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_exti.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h \ + ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h: + +../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h: + +../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l011xx.h: + +../Drivers/CMSIS/Include/core_cm0plus.h: + +../Drivers/CMSIS/Include/cmsis_version.h: + +../Drivers/CMSIS/Include/cmsis_compiler.h: + +../Drivers/CMSIS/Include/cmsis_gcc.h: + +../Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal.h: + +../Core/Inc/stm32l0xx_hal_conf.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_def.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_rcc_ex.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_exti.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_gpio_ex.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_dma.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_cortex.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ex.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_flash_ramfunc.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_i2c_ex.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_pwr_ex.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h: + +../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h: diff --git a/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.o b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.o new file mode 100644 index 0000000..ba0cf0e Binary files /dev/null and b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.o differ diff --git a/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.su b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.su new file mode 100644 index 0000000..ab2a69f --- /dev/null +++ b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.su @@ -0,0 +1,7 @@ +stm32l0xx_ll_utils.c:147:6:LL_Init1msTick 8 static +stm32l0xx_ll_utils.c:163:6:LL_mDelay 8 static +stm32l0xx_ll_utils.c:225:6:LL_SetSystemCoreClock 0 static +stm32l0xx_ll_utils.c:239:13:LL_SetFlashLatency 8 static +stm32l0xx_ll_utils.c:521:20:UTILS_EnablePLLAndSwitchSystem 16 static +stm32l0xx_ll_utils.c:338:13:LL_PLL_ConfigSystemClock_HSI 24 static +stm32l0xx_ll_utils.c:397:13:LL_PLL_ConfigSystemClock_HSE 24 static diff --git a/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/subdir.mk b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/subdir.mk new file mode 100644 index 0000000..bd42155 --- /dev/null +++ b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/subdir.mk @@ -0,0 +1,130 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (9-2020-q2-update) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c \ +../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c \ +../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c \ +../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.c \ +../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c \ +../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c \ +../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c \ +../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c \ +../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c \ +../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c \ +../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c \ +../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c \ +../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c \ +../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c \ +../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c \ +../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c \ +../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c \ +../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c \ +../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c \ +../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c \ +../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c \ +../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c \ +../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c + +OBJS += \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.o \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.o \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.o \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.o \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.o \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.o \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.o + +C_DEPS += \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.d \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.d \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.d \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.d \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.d \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.d \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.d \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.d \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.d \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.d \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.d \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.d \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.d \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.d \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.d \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.d \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.d \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.d \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.d \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.d \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.d \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.d \ +./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.d + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o: ../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.c Drivers/STM32L0xx_HAL_Driver/Src/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m0plus -std=gnu11 -g3 -DSTM32L011xx -DDEBUG -DUSE_FULL_LL_DRIVER -DUSE_HAL_DRIVER -c -I../Core/Inc -I../Drivers/STM32L0xx_HAL_Driver/Inc -I../Drivers/CMSIS/Device/ST/STM32L0xx/Include -I../Drivers/CMSIS/Include -I../Drivers/STM32L0xx_HAL_Driver/Inc/Legacy -Os -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" +Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o: ../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.c Drivers/STM32L0xx_HAL_Driver/Src/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m0plus -std=gnu11 -g3 -DSTM32L011xx -DDEBUG -DUSE_FULL_LL_DRIVER -DUSE_HAL_DRIVER -c -I../Core/Inc -I../Drivers/STM32L0xx_HAL_Driver/Inc -I../Drivers/CMSIS/Device/ST/STM32L0xx/Include -I../Drivers/CMSIS/Include -I../Drivers/STM32L0xx_HAL_Driver/Inc/Legacy -Os -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" +Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o: ../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.c Drivers/STM32L0xx_HAL_Driver/Src/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m0plus -std=gnu11 -g3 -DSTM32L011xx -DDEBUG -DUSE_FULL_LL_DRIVER -DUSE_HAL_DRIVER -c -I../Core/Inc -I../Drivers/STM32L0xx_HAL_Driver/Inc -I../Drivers/CMSIS/Device/ST/STM32L0xx/Include -I../Drivers/CMSIS/Include -I../Drivers/STM32L0xx_HAL_Driver/Inc/Legacy -Os -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" +Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o: ../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.c Drivers/STM32L0xx_HAL_Driver/Src/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m0plus -std=gnu11 -g3 -DSTM32L011xx -DDEBUG -DUSE_FULL_LL_DRIVER -DUSE_HAL_DRIVER -c -I../Core/Inc -I../Drivers/STM32L0xx_HAL_Driver/Inc -I../Drivers/CMSIS/Device/ST/STM32L0xx/Include -I../Drivers/CMSIS/Include -I../Drivers/STM32L0xx_HAL_Driver/Inc/Legacy -Os -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" +Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o: ../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.c Drivers/STM32L0xx_HAL_Driver/Src/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m0plus -std=gnu11 -g3 -DSTM32L011xx -DDEBUG -DUSE_FULL_LL_DRIVER -DUSE_HAL_DRIVER -c -I../Core/Inc -I../Drivers/STM32L0xx_HAL_Driver/Inc -I../Drivers/CMSIS/Device/ST/STM32L0xx/Include -I../Drivers/CMSIS/Include -I../Drivers/STM32L0xx_HAL_Driver/Inc/Legacy -Os -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" +Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o: ../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.c Drivers/STM32L0xx_HAL_Driver/Src/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m0plus -std=gnu11 -g3 -DSTM32L011xx -DDEBUG -DUSE_FULL_LL_DRIVER -DUSE_HAL_DRIVER -c -I../Core/Inc -I../Drivers/STM32L0xx_HAL_Driver/Inc -I../Drivers/CMSIS/Device/ST/STM32L0xx/Include -I../Drivers/CMSIS/Include -I../Drivers/STM32L0xx_HAL_Driver/Inc/Legacy -Os -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" +Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o: ../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.c Drivers/STM32L0xx_HAL_Driver/Src/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m0plus -std=gnu11 -g3 -DSTM32L011xx -DDEBUG -DUSE_FULL_LL_DRIVER -DUSE_HAL_DRIVER -c -I../Core/Inc -I../Drivers/STM32L0xx_HAL_Driver/Inc -I../Drivers/CMSIS/Device/ST/STM32L0xx/Include -I../Drivers/CMSIS/Include -I../Drivers/STM32L0xx_HAL_Driver/Inc/Legacy -Os -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" +Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o: ../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.c Drivers/STM32L0xx_HAL_Driver/Src/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m0plus -std=gnu11 -g3 -DSTM32L011xx -DDEBUG -DUSE_FULL_LL_DRIVER -DUSE_HAL_DRIVER -c -I../Core/Inc -I../Drivers/STM32L0xx_HAL_Driver/Inc -I../Drivers/CMSIS/Device/ST/STM32L0xx/Include -I../Drivers/CMSIS/Include -I../Drivers/STM32L0xx_HAL_Driver/Inc/Legacy -Os -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" +Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o: ../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.c Drivers/STM32L0xx_HAL_Driver/Src/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m0plus -std=gnu11 -g3 -DSTM32L011xx -DDEBUG -DUSE_FULL_LL_DRIVER -DUSE_HAL_DRIVER -c -I../Core/Inc -I../Drivers/STM32L0xx_HAL_Driver/Inc -I../Drivers/CMSIS/Device/ST/STM32L0xx/Include -I../Drivers/CMSIS/Include -I../Drivers/STM32L0xx_HAL_Driver/Inc/Legacy -Os -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" +Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o: ../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.c Drivers/STM32L0xx_HAL_Driver/Src/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m0plus -std=gnu11 -g3 -DSTM32L011xx -DDEBUG -DUSE_FULL_LL_DRIVER -DUSE_HAL_DRIVER -c -I../Core/Inc -I../Drivers/STM32L0xx_HAL_Driver/Inc -I../Drivers/CMSIS/Device/ST/STM32L0xx/Include -I../Drivers/CMSIS/Include -I../Drivers/STM32L0xx_HAL_Driver/Inc/Legacy -Os -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" +Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o: ../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.c Drivers/STM32L0xx_HAL_Driver/Src/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m0plus -std=gnu11 -g3 -DSTM32L011xx -DDEBUG -DUSE_FULL_LL_DRIVER -DUSE_HAL_DRIVER -c -I../Core/Inc -I../Drivers/STM32L0xx_HAL_Driver/Inc -I../Drivers/CMSIS/Device/ST/STM32L0xx/Include -I../Drivers/CMSIS/Include -I../Drivers/STM32L0xx_HAL_Driver/Inc/Legacy -Os -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" +Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o: ../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.c Drivers/STM32L0xx_HAL_Driver/Src/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m0plus -std=gnu11 -g3 -DSTM32L011xx -DDEBUG -DUSE_FULL_LL_DRIVER -DUSE_HAL_DRIVER -c -I../Core/Inc -I../Drivers/STM32L0xx_HAL_Driver/Inc -I../Drivers/CMSIS/Device/ST/STM32L0xx/Include -I../Drivers/CMSIS/Include -I../Drivers/STM32L0xx_HAL_Driver/Inc/Legacy -Os -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" +Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o: ../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.c Drivers/STM32L0xx_HAL_Driver/Src/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m0plus -std=gnu11 -g3 -DSTM32L011xx -DDEBUG -DUSE_FULL_LL_DRIVER -DUSE_HAL_DRIVER -c -I../Core/Inc -I../Drivers/STM32L0xx_HAL_Driver/Inc -I../Drivers/CMSIS/Device/ST/STM32L0xx/Include -I../Drivers/CMSIS/Include -I../Drivers/STM32L0xx_HAL_Driver/Inc/Legacy -Os -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" +Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o: ../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.c Drivers/STM32L0xx_HAL_Driver/Src/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m0plus -std=gnu11 -g3 -DSTM32L011xx -DDEBUG -DUSE_FULL_LL_DRIVER -DUSE_HAL_DRIVER -c -I../Core/Inc -I../Drivers/STM32L0xx_HAL_Driver/Inc -I../Drivers/CMSIS/Device/ST/STM32L0xx/Include -I../Drivers/CMSIS/Include -I../Drivers/STM32L0xx_HAL_Driver/Inc/Legacy -Os -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" +Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o: ../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.c Drivers/STM32L0xx_HAL_Driver/Src/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m0plus -std=gnu11 -g3 -DSTM32L011xx -DDEBUG -DUSE_FULL_LL_DRIVER -DUSE_HAL_DRIVER -c -I../Core/Inc -I../Drivers/STM32L0xx_HAL_Driver/Inc -I../Drivers/CMSIS/Device/ST/STM32L0xx/Include -I../Drivers/CMSIS/Include -I../Drivers/STM32L0xx_HAL_Driver/Inc/Legacy -Os -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" +Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o: ../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.c Drivers/STM32L0xx_HAL_Driver/Src/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m0plus -std=gnu11 -g3 -DSTM32L011xx -DDEBUG -DUSE_FULL_LL_DRIVER -DUSE_HAL_DRIVER -c -I../Core/Inc -I../Drivers/STM32L0xx_HAL_Driver/Inc -I../Drivers/CMSIS/Device/ST/STM32L0xx/Include -I../Drivers/CMSIS/Include -I../Drivers/STM32L0xx_HAL_Driver/Inc/Legacy -Os -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" +Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.o: ../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c Drivers/STM32L0xx_HAL_Driver/Src/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m0plus -std=gnu11 -g3 -DSTM32L011xx -DDEBUG -DUSE_FULL_LL_DRIVER -DUSE_HAL_DRIVER -c -I../Core/Inc -I../Drivers/STM32L0xx_HAL_Driver/Inc -I../Drivers/CMSIS/Device/ST/STM32L0xx/Include -I../Drivers/CMSIS/Include -I../Drivers/STM32L0xx_HAL_Driver/Inc/Legacy -Os -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" +Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.o: ../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c Drivers/STM32L0xx_HAL_Driver/Src/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m0plus -std=gnu11 -g3 -DSTM32L011xx -DDEBUG -DUSE_FULL_LL_DRIVER -DUSE_HAL_DRIVER -c -I../Core/Inc -I../Drivers/STM32L0xx_HAL_Driver/Inc -I../Drivers/CMSIS/Device/ST/STM32L0xx/Include -I../Drivers/CMSIS/Include -I../Drivers/STM32L0xx_HAL_Driver/Inc/Legacy -Os -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" +Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.o: ../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c Drivers/STM32L0xx_HAL_Driver/Src/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m0plus -std=gnu11 -g3 -DSTM32L011xx -DDEBUG -DUSE_FULL_LL_DRIVER -DUSE_HAL_DRIVER -c -I../Core/Inc -I../Drivers/STM32L0xx_HAL_Driver/Inc -I../Drivers/CMSIS/Device/ST/STM32L0xx/Include -I../Drivers/CMSIS/Include -I../Drivers/STM32L0xx_HAL_Driver/Inc/Legacy -Os -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" +Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.o: ../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c Drivers/STM32L0xx_HAL_Driver/Src/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m0plus -std=gnu11 -g3 -DSTM32L011xx -DDEBUG -DUSE_FULL_LL_DRIVER -DUSE_HAL_DRIVER -c -I../Core/Inc -I../Drivers/STM32L0xx_HAL_Driver/Inc -I../Drivers/CMSIS/Device/ST/STM32L0xx/Include -I../Drivers/CMSIS/Include -I../Drivers/STM32L0xx_HAL_Driver/Inc/Legacy -Os -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" +Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.o: ../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c Drivers/STM32L0xx_HAL_Driver/Src/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m0plus -std=gnu11 -g3 -DSTM32L011xx -DDEBUG -DUSE_FULL_LL_DRIVER -DUSE_HAL_DRIVER -c -I../Core/Inc -I../Drivers/STM32L0xx_HAL_Driver/Inc -I../Drivers/CMSIS/Device/ST/STM32L0xx/Include -I../Drivers/CMSIS/Include -I../Drivers/STM32L0xx_HAL_Driver/Inc/Legacy -Os -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" +Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.o: ../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c Drivers/STM32L0xx_HAL_Driver/Src/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m0plus -std=gnu11 -g3 -DSTM32L011xx -DDEBUG -DUSE_FULL_LL_DRIVER -DUSE_HAL_DRIVER -c -I../Core/Inc -I../Drivers/STM32L0xx_HAL_Driver/Inc -I../Drivers/CMSIS/Device/ST/STM32L0xx/Include -I../Drivers/CMSIS/Include -I../Drivers/STM32L0xx_HAL_Driver/Inc/Legacy -Os -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" +Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.o: ../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c Drivers/STM32L0xx_HAL_Driver/Src/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m0plus -std=gnu11 -g3 -DSTM32L011xx -DDEBUG -DUSE_FULL_LL_DRIVER -DUSE_HAL_DRIVER -c -I../Core/Inc -I../Drivers/STM32L0xx_HAL_Driver/Inc -I../Drivers/CMSIS/Device/ST/STM32L0xx/Include -I../Drivers/CMSIS/Include -I../Drivers/STM32L0xx_HAL_Driver/Inc/Legacy -Os -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + diff --git a/fw/Debug/iaq_wired_sensor.bin b/fw/Debug/iaq_wired_sensor.bin new file mode 100755 index 0000000..292d6f9 Binary files /dev/null and b/fw/Debug/iaq_wired_sensor.bin differ diff --git a/fw/Debug/iaq_wired_sensor.elf b/fw/Debug/iaq_wired_sensor.elf new file mode 100755 index 0000000..09eee6f Binary files /dev/null and b/fw/Debug/iaq_wired_sensor.elf differ diff --git a/fw/Debug/iaq_wired_sensor.list b/fw/Debug/iaq_wired_sensor.list new file mode 100644 index 0000000..120fdcf --- /dev/null +++ b/fw/Debug/iaq_wired_sensor.list @@ -0,0 +1,3738 @@ + +iaq_wired_sensor.elf: file format elf32-littlearm + +Sections: +Idx Name Size VMA LMA File off Algn + 0 .isr_vector 000000c0 08000000 08000000 00010000 2**0 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 1 .text 00001540 080000c0 080000c0 000100c0 2**2 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 2 .rodata 00000024 08001600 08001600 00011600 2**0 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 3 .ARM.extab 00000000 08001624 08001624 0002000c 2**0 + CONTENTS + 4 .ARM 00000008 08001624 08001624 00011624 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 5 .preinit_array 00000000 0800162c 0800162c 0002000c 2**0 + CONTENTS, ALLOC, LOAD, DATA + 6 .init_array 00000004 0800162c 0800162c 0001162c 2**2 + CONTENTS, ALLOC, LOAD, DATA + 7 .fini_array 00000004 08001630 08001630 00011630 2**2 + CONTENTS, ALLOC, LOAD, DATA + 8 .data 0000000c 20000000 08001634 00020000 2**2 + CONTENTS, ALLOC, LOAD, DATA + 9 .bss 00000020 2000000c 08001640 0002000c 2**2 + ALLOC + 10 ._user_heap_stack 00000604 2000002c 08001640 0002002c 2**0 + ALLOC + 11 .ARM.attributes 00000028 00000000 00000000 0002000c 2**0 + CONTENTS, READONLY + 12 .debug_info 00006c2d 00000000 00000000 00020034 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 13 .debug_abbrev 00001b63 00000000 00000000 00026c61 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 14 .debug_loc 00002331 00000000 00000000 000287c4 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 15 .debug_aranges 00000430 00000000 00000000 0002aaf8 2**3 + CONTENTS, READONLY, DEBUGGING, OCTETS + 16 .debug_ranges 00000a18 00000000 00000000 0002af28 2**3 + CONTENTS, READONLY, DEBUGGING, OCTETS + 17 .debug_macro 0001133a 00000000 00000000 0002b940 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 18 .debug_line 00007f60 00000000 00000000 0003cc7a 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 19 .debug_str 00062aa3 00000000 00000000 00044bda 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 20 .comment 00000053 00000000 00000000 000a767d 2**0 + CONTENTS, READONLY + 21 .debug_frame 0000091c 00000000 00000000 000a76d0 2**2 + CONTENTS, READONLY, DEBUGGING, OCTETS + +Disassembly of section .text: + +080000c0 <__do_global_dtors_aux>: + 80000c0: b510 push {r4, lr} + 80000c2: 4c06 ldr r4, [pc, #24] ; (80000dc <__do_global_dtors_aux+0x1c>) + 80000c4: 7823 ldrb r3, [r4, #0] + 80000c6: 2b00 cmp r3, #0 + 80000c8: d107 bne.n 80000da <__do_global_dtors_aux+0x1a> + 80000ca: 4b05 ldr r3, [pc, #20] ; (80000e0 <__do_global_dtors_aux+0x20>) + 80000cc: 2b00 cmp r3, #0 + 80000ce: d002 beq.n 80000d6 <__do_global_dtors_aux+0x16> + 80000d0: 4804 ldr r0, [pc, #16] ; (80000e4 <__do_global_dtors_aux+0x24>) + 80000d2: e000 b.n 80000d6 <__do_global_dtors_aux+0x16> + 80000d4: bf00 nop + 80000d6: 2301 movs r3, #1 + 80000d8: 7023 strb r3, [r4, #0] + 80000da: bd10 pop {r4, pc} + 80000dc: 2000000c .word 0x2000000c + 80000e0: 00000000 .word 0x00000000 + 80000e4: 080015e8 .word 0x080015e8 + +080000e8 : + 80000e8: 4b04 ldr r3, [pc, #16] ; (80000fc ) + 80000ea: b510 push {r4, lr} + 80000ec: 2b00 cmp r3, #0 + 80000ee: d003 beq.n 80000f8 + 80000f0: 4903 ldr r1, [pc, #12] ; (8000100 ) + 80000f2: 4804 ldr r0, [pc, #16] ; (8000104 ) + 80000f4: e000 b.n 80000f8 + 80000f6: bf00 nop + 80000f8: bd10 pop {r4, pc} + 80000fa: 46c0 nop ; (mov r8, r8) + 80000fc: 00000000 .word 0x00000000 + 8000100: 20000010 .word 0x20000010 + 8000104: 080015e8 .word 0x080015e8 + +08000108 <__udivsi3>: + 8000108: 2200 movs r2, #0 + 800010a: 0843 lsrs r3, r0, #1 + 800010c: 428b cmp r3, r1 + 800010e: d374 bcc.n 80001fa <__udivsi3+0xf2> + 8000110: 0903 lsrs r3, r0, #4 + 8000112: 428b cmp r3, r1 + 8000114: d35f bcc.n 80001d6 <__udivsi3+0xce> + 8000116: 0a03 lsrs r3, r0, #8 + 8000118: 428b cmp r3, r1 + 800011a: d344 bcc.n 80001a6 <__udivsi3+0x9e> + 800011c: 0b03 lsrs r3, r0, #12 + 800011e: 428b cmp r3, r1 + 8000120: d328 bcc.n 8000174 <__udivsi3+0x6c> + 8000122: 0c03 lsrs r3, r0, #16 + 8000124: 428b cmp r3, r1 + 8000126: d30d bcc.n 8000144 <__udivsi3+0x3c> + 8000128: 22ff movs r2, #255 ; 0xff + 800012a: 0209 lsls r1, r1, #8 + 800012c: ba12 rev r2, r2 + 800012e: 0c03 lsrs r3, r0, #16 + 8000130: 428b cmp r3, r1 + 8000132: d302 bcc.n 800013a <__udivsi3+0x32> + 8000134: 1212 asrs r2, r2, #8 + 8000136: 0209 lsls r1, r1, #8 + 8000138: d065 beq.n 8000206 <__udivsi3+0xfe> + 800013a: 0b03 lsrs r3, r0, #12 + 800013c: 428b cmp r3, r1 + 800013e: d319 bcc.n 8000174 <__udivsi3+0x6c> + 8000140: e000 b.n 8000144 <__udivsi3+0x3c> + 8000142: 0a09 lsrs r1, r1, #8 + 8000144: 0bc3 lsrs r3, r0, #15 + 8000146: 428b cmp r3, r1 + 8000148: d301 bcc.n 800014e <__udivsi3+0x46> + 800014a: 03cb lsls r3, r1, #15 + 800014c: 1ac0 subs r0, r0, r3 + 800014e: 4152 adcs r2, r2 + 8000150: 0b83 lsrs r3, r0, #14 + 8000152: 428b cmp r3, r1 + 8000154: d301 bcc.n 800015a <__udivsi3+0x52> + 8000156: 038b lsls r3, r1, #14 + 8000158: 1ac0 subs r0, r0, r3 + 800015a: 4152 adcs r2, r2 + 800015c: 0b43 lsrs r3, r0, #13 + 800015e: 428b cmp r3, r1 + 8000160: d301 bcc.n 8000166 <__udivsi3+0x5e> + 8000162: 034b lsls r3, r1, #13 + 8000164: 1ac0 subs r0, r0, r3 + 8000166: 4152 adcs r2, r2 + 8000168: 0b03 lsrs r3, r0, #12 + 800016a: 428b cmp r3, r1 + 800016c: d301 bcc.n 8000172 <__udivsi3+0x6a> + 800016e: 030b lsls r3, r1, #12 + 8000170: 1ac0 subs r0, r0, r3 + 8000172: 4152 adcs r2, r2 + 8000174: 0ac3 lsrs r3, r0, #11 + 8000176: 428b cmp r3, r1 + 8000178: d301 bcc.n 800017e <__udivsi3+0x76> + 800017a: 02cb lsls r3, r1, #11 + 800017c: 1ac0 subs r0, r0, r3 + 800017e: 4152 adcs r2, r2 + 8000180: 0a83 lsrs r3, r0, #10 + 8000182: 428b cmp r3, r1 + 8000184: d301 bcc.n 800018a <__udivsi3+0x82> + 8000186: 028b lsls r3, r1, #10 + 8000188: 1ac0 subs r0, r0, r3 + 800018a: 4152 adcs r2, r2 + 800018c: 0a43 lsrs r3, r0, #9 + 800018e: 428b cmp r3, r1 + 8000190: d301 bcc.n 8000196 <__udivsi3+0x8e> + 8000192: 024b lsls r3, r1, #9 + 8000194: 1ac0 subs r0, r0, r3 + 8000196: 4152 adcs r2, r2 + 8000198: 0a03 lsrs r3, r0, #8 + 800019a: 428b cmp r3, r1 + 800019c: d301 bcc.n 80001a2 <__udivsi3+0x9a> + 800019e: 020b lsls r3, r1, #8 + 80001a0: 1ac0 subs r0, r0, r3 + 80001a2: 4152 adcs r2, r2 + 80001a4: d2cd bcs.n 8000142 <__udivsi3+0x3a> + 80001a6: 09c3 lsrs r3, r0, #7 + 80001a8: 428b cmp r3, r1 + 80001aa: d301 bcc.n 80001b0 <__udivsi3+0xa8> + 80001ac: 01cb lsls r3, r1, #7 + 80001ae: 1ac0 subs r0, r0, r3 + 80001b0: 4152 adcs r2, r2 + 80001b2: 0983 lsrs r3, r0, #6 + 80001b4: 428b cmp r3, r1 + 80001b6: d301 bcc.n 80001bc <__udivsi3+0xb4> + 80001b8: 018b lsls r3, r1, #6 + 80001ba: 1ac0 subs r0, r0, r3 + 80001bc: 4152 adcs r2, r2 + 80001be: 0943 lsrs r3, r0, #5 + 80001c0: 428b cmp r3, r1 + 80001c2: d301 bcc.n 80001c8 <__udivsi3+0xc0> + 80001c4: 014b lsls r3, r1, #5 + 80001c6: 1ac0 subs r0, r0, r3 + 80001c8: 4152 adcs r2, r2 + 80001ca: 0903 lsrs r3, r0, #4 + 80001cc: 428b cmp r3, r1 + 80001ce: d301 bcc.n 80001d4 <__udivsi3+0xcc> + 80001d0: 010b lsls r3, r1, #4 + 80001d2: 1ac0 subs r0, r0, r3 + 80001d4: 4152 adcs r2, r2 + 80001d6: 08c3 lsrs r3, r0, #3 + 80001d8: 428b cmp r3, r1 + 80001da: d301 bcc.n 80001e0 <__udivsi3+0xd8> + 80001dc: 00cb lsls r3, r1, #3 + 80001de: 1ac0 subs r0, r0, r3 + 80001e0: 4152 adcs r2, r2 + 80001e2: 0883 lsrs r3, r0, #2 + 80001e4: 428b cmp r3, r1 + 80001e6: d301 bcc.n 80001ec <__udivsi3+0xe4> + 80001e8: 008b lsls r3, r1, #2 + 80001ea: 1ac0 subs r0, r0, r3 + 80001ec: 4152 adcs r2, r2 + 80001ee: 0843 lsrs r3, r0, #1 + 80001f0: 428b cmp r3, r1 + 80001f2: d301 bcc.n 80001f8 <__udivsi3+0xf0> + 80001f4: 004b lsls r3, r1, #1 + 80001f6: 1ac0 subs r0, r0, r3 + 80001f8: 4152 adcs r2, r2 + 80001fa: 1a41 subs r1, r0, r1 + 80001fc: d200 bcs.n 8000200 <__udivsi3+0xf8> + 80001fe: 4601 mov r1, r0 + 8000200: 4152 adcs r2, r2 + 8000202: 4610 mov r0, r2 + 8000204: 4770 bx lr + 8000206: e7ff b.n 8000208 <__udivsi3+0x100> + 8000208: b501 push {r0, lr} + 800020a: 2000 movs r0, #0 + 800020c: f000 f806 bl 800021c <__aeabi_idiv0> + 8000210: bd02 pop {r1, pc} + 8000212: 46c0 nop ; (mov r8, r8) + +08000214 <__aeabi_uidivmod>: + 8000214: 2900 cmp r1, #0 + 8000216: d0f7 beq.n 8000208 <__udivsi3+0x100> + 8000218: e776 b.n 8000108 <__udivsi3> + 800021a: 4770 bx lr + +0800021c <__aeabi_idiv0>: + 800021c: 4770 bx lr + 800021e: 46c0 nop ; (mov r8, r8) + +08000220 <__aeabi_uldivmod>: + 8000220: 2b00 cmp r3, #0 + 8000222: d111 bne.n 8000248 <__aeabi_uldivmod+0x28> + 8000224: 2a00 cmp r2, #0 + 8000226: d10f bne.n 8000248 <__aeabi_uldivmod+0x28> + 8000228: 2900 cmp r1, #0 + 800022a: d100 bne.n 800022e <__aeabi_uldivmod+0xe> + 800022c: 2800 cmp r0, #0 + 800022e: d002 beq.n 8000236 <__aeabi_uldivmod+0x16> + 8000230: 2100 movs r1, #0 + 8000232: 43c9 mvns r1, r1 + 8000234: 1c08 adds r0, r1, #0 + 8000236: b407 push {r0, r1, r2} + 8000238: 4802 ldr r0, [pc, #8] ; (8000244 <__aeabi_uldivmod+0x24>) + 800023a: a102 add r1, pc, #8 ; (adr r1, 8000244 <__aeabi_uldivmod+0x24>) + 800023c: 1840 adds r0, r0, r1 + 800023e: 9002 str r0, [sp, #8] + 8000240: bd03 pop {r0, r1, pc} + 8000242: 46c0 nop ; (mov r8, r8) + 8000244: ffffffd9 .word 0xffffffd9 + 8000248: b403 push {r0, r1} + 800024a: 4668 mov r0, sp + 800024c: b501 push {r0, lr} + 800024e: 9802 ldr r0, [sp, #8] + 8000250: f000 f82e bl 80002b0 <__udivmoddi4> + 8000254: 9b01 ldr r3, [sp, #4] + 8000256: 469e mov lr, r3 + 8000258: b002 add sp, #8 + 800025a: bc0c pop {r2, r3} + 800025c: 4770 bx lr + 800025e: 46c0 nop ; (mov r8, r8) + +08000260 <__aeabi_lmul>: + 8000260: b5f0 push {r4, r5, r6, r7, lr} + 8000262: 0415 lsls r5, r2, #16 + 8000264: 0c2d lsrs r5, r5, #16 + 8000266: 000f movs r7, r1 + 8000268: 0001 movs r1, r0 + 800026a: 002e movs r6, r5 + 800026c: 46c6 mov lr, r8 + 800026e: 4684 mov ip, r0 + 8000270: 0400 lsls r0, r0, #16 + 8000272: 0c14 lsrs r4, r2, #16 + 8000274: 0c00 lsrs r0, r0, #16 + 8000276: 0c09 lsrs r1, r1, #16 + 8000278: 4346 muls r6, r0 + 800027a: 434d muls r5, r1 + 800027c: 4360 muls r0, r4 + 800027e: 4361 muls r1, r4 + 8000280: 1940 adds r0, r0, r5 + 8000282: 0c34 lsrs r4, r6, #16 + 8000284: 1824 adds r4, r4, r0 + 8000286: b500 push {lr} + 8000288: 42a5 cmp r5, r4 + 800028a: d903 bls.n 8000294 <__aeabi_lmul+0x34> + 800028c: 2080 movs r0, #128 ; 0x80 + 800028e: 0240 lsls r0, r0, #9 + 8000290: 4680 mov r8, r0 + 8000292: 4441 add r1, r8 + 8000294: 0c25 lsrs r5, r4, #16 + 8000296: 186d adds r5, r5, r1 + 8000298: 4661 mov r1, ip + 800029a: 4359 muls r1, r3 + 800029c: 437a muls r2, r7 + 800029e: 0430 lsls r0, r6, #16 + 80002a0: 1949 adds r1, r1, r5 + 80002a2: 0424 lsls r4, r4, #16 + 80002a4: 0c00 lsrs r0, r0, #16 + 80002a6: 1820 adds r0, r4, r0 + 80002a8: 1889 adds r1, r1, r2 + 80002aa: bc80 pop {r7} + 80002ac: 46b8 mov r8, r7 + 80002ae: bdf0 pop {r4, r5, r6, r7, pc} + +080002b0 <__udivmoddi4>: + 80002b0: b5f0 push {r4, r5, r6, r7, lr} + 80002b2: 4657 mov r7, sl + 80002b4: 464e mov r6, r9 + 80002b6: 4645 mov r5, r8 + 80002b8: 46de mov lr, fp + 80002ba: b5e0 push {r5, r6, r7, lr} + 80002bc: 0004 movs r4, r0 + 80002be: 000d movs r5, r1 + 80002c0: 4692 mov sl, r2 + 80002c2: 4699 mov r9, r3 + 80002c4: b083 sub sp, #12 + 80002c6: 428b cmp r3, r1 + 80002c8: d830 bhi.n 800032c <__udivmoddi4+0x7c> + 80002ca: d02d beq.n 8000328 <__udivmoddi4+0x78> + 80002cc: 4649 mov r1, r9 + 80002ce: 4650 mov r0, sl + 80002d0: f000 f8ba bl 8000448 <__clzdi2> + 80002d4: 0029 movs r1, r5 + 80002d6: 0006 movs r6, r0 + 80002d8: 0020 movs r0, r4 + 80002da: f000 f8b5 bl 8000448 <__clzdi2> + 80002de: 1a33 subs r3, r6, r0 + 80002e0: 4698 mov r8, r3 + 80002e2: 3b20 subs r3, #32 + 80002e4: 469b mov fp, r3 + 80002e6: d433 bmi.n 8000350 <__udivmoddi4+0xa0> + 80002e8: 465a mov r2, fp + 80002ea: 4653 mov r3, sl + 80002ec: 4093 lsls r3, r2 + 80002ee: 4642 mov r2, r8 + 80002f0: 001f movs r7, r3 + 80002f2: 4653 mov r3, sl + 80002f4: 4093 lsls r3, r2 + 80002f6: 001e movs r6, r3 + 80002f8: 42af cmp r7, r5 + 80002fa: d83a bhi.n 8000372 <__udivmoddi4+0xc2> + 80002fc: 42af cmp r7, r5 + 80002fe: d100 bne.n 8000302 <__udivmoddi4+0x52> + 8000300: e078 b.n 80003f4 <__udivmoddi4+0x144> + 8000302: 465b mov r3, fp + 8000304: 1ba4 subs r4, r4, r6 + 8000306: 41bd sbcs r5, r7 + 8000308: 2b00 cmp r3, #0 + 800030a: da00 bge.n 800030e <__udivmoddi4+0x5e> + 800030c: e075 b.n 80003fa <__udivmoddi4+0x14a> + 800030e: 2200 movs r2, #0 + 8000310: 2300 movs r3, #0 + 8000312: 9200 str r2, [sp, #0] + 8000314: 9301 str r3, [sp, #4] + 8000316: 2301 movs r3, #1 + 8000318: 465a mov r2, fp + 800031a: 4093 lsls r3, r2 + 800031c: 9301 str r3, [sp, #4] + 800031e: 2301 movs r3, #1 + 8000320: 4642 mov r2, r8 + 8000322: 4093 lsls r3, r2 + 8000324: 9300 str r3, [sp, #0] + 8000326: e028 b.n 800037a <__udivmoddi4+0xca> + 8000328: 4282 cmp r2, r0 + 800032a: d9cf bls.n 80002cc <__udivmoddi4+0x1c> + 800032c: 2200 movs r2, #0 + 800032e: 2300 movs r3, #0 + 8000330: 9200 str r2, [sp, #0] + 8000332: 9301 str r3, [sp, #4] + 8000334: 9b0c ldr r3, [sp, #48] ; 0x30 + 8000336: 2b00 cmp r3, #0 + 8000338: d001 beq.n 800033e <__udivmoddi4+0x8e> + 800033a: 601c str r4, [r3, #0] + 800033c: 605d str r5, [r3, #4] + 800033e: 9800 ldr r0, [sp, #0] + 8000340: 9901 ldr r1, [sp, #4] + 8000342: b003 add sp, #12 + 8000344: bcf0 pop {r4, r5, r6, r7} + 8000346: 46bb mov fp, r7 + 8000348: 46b2 mov sl, r6 + 800034a: 46a9 mov r9, r5 + 800034c: 46a0 mov r8, r4 + 800034e: bdf0 pop {r4, r5, r6, r7, pc} + 8000350: 4642 mov r2, r8 + 8000352: 2320 movs r3, #32 + 8000354: 1a9b subs r3, r3, r2 + 8000356: 4652 mov r2, sl + 8000358: 40da lsrs r2, r3 + 800035a: 4641 mov r1, r8 + 800035c: 0013 movs r3, r2 + 800035e: 464a mov r2, r9 + 8000360: 408a lsls r2, r1 + 8000362: 0017 movs r7, r2 + 8000364: 4642 mov r2, r8 + 8000366: 431f orrs r7, r3 + 8000368: 4653 mov r3, sl + 800036a: 4093 lsls r3, r2 + 800036c: 001e movs r6, r3 + 800036e: 42af cmp r7, r5 + 8000370: d9c4 bls.n 80002fc <__udivmoddi4+0x4c> + 8000372: 2200 movs r2, #0 + 8000374: 2300 movs r3, #0 + 8000376: 9200 str r2, [sp, #0] + 8000378: 9301 str r3, [sp, #4] + 800037a: 4643 mov r3, r8 + 800037c: 2b00 cmp r3, #0 + 800037e: d0d9 beq.n 8000334 <__udivmoddi4+0x84> + 8000380: 07fb lsls r3, r7, #31 + 8000382: 0872 lsrs r2, r6, #1 + 8000384: 431a orrs r2, r3 + 8000386: 4646 mov r6, r8 + 8000388: 087b lsrs r3, r7, #1 + 800038a: e00e b.n 80003aa <__udivmoddi4+0xfa> + 800038c: 42ab cmp r3, r5 + 800038e: d101 bne.n 8000394 <__udivmoddi4+0xe4> + 8000390: 42a2 cmp r2, r4 + 8000392: d80c bhi.n 80003ae <__udivmoddi4+0xfe> + 8000394: 1aa4 subs r4, r4, r2 + 8000396: 419d sbcs r5, r3 + 8000398: 2001 movs r0, #1 + 800039a: 1924 adds r4, r4, r4 + 800039c: 416d adcs r5, r5 + 800039e: 2100 movs r1, #0 + 80003a0: 3e01 subs r6, #1 + 80003a2: 1824 adds r4, r4, r0 + 80003a4: 414d adcs r5, r1 + 80003a6: 2e00 cmp r6, #0 + 80003a8: d006 beq.n 80003b8 <__udivmoddi4+0x108> + 80003aa: 42ab cmp r3, r5 + 80003ac: d9ee bls.n 800038c <__udivmoddi4+0xdc> + 80003ae: 3e01 subs r6, #1 + 80003b0: 1924 adds r4, r4, r4 + 80003b2: 416d adcs r5, r5 + 80003b4: 2e00 cmp r6, #0 + 80003b6: d1f8 bne.n 80003aa <__udivmoddi4+0xfa> + 80003b8: 9800 ldr r0, [sp, #0] + 80003ba: 9901 ldr r1, [sp, #4] + 80003bc: 465b mov r3, fp + 80003be: 1900 adds r0, r0, r4 + 80003c0: 4169 adcs r1, r5 + 80003c2: 2b00 cmp r3, #0 + 80003c4: db24 blt.n 8000410 <__udivmoddi4+0x160> + 80003c6: 002b movs r3, r5 + 80003c8: 465a mov r2, fp + 80003ca: 4644 mov r4, r8 + 80003cc: 40d3 lsrs r3, r2 + 80003ce: 002a movs r2, r5 + 80003d0: 40e2 lsrs r2, r4 + 80003d2: 001c movs r4, r3 + 80003d4: 465b mov r3, fp + 80003d6: 0015 movs r5, r2 + 80003d8: 2b00 cmp r3, #0 + 80003da: db2a blt.n 8000432 <__udivmoddi4+0x182> + 80003dc: 0026 movs r6, r4 + 80003de: 409e lsls r6, r3 + 80003e0: 0033 movs r3, r6 + 80003e2: 0026 movs r6, r4 + 80003e4: 4647 mov r7, r8 + 80003e6: 40be lsls r6, r7 + 80003e8: 0032 movs r2, r6 + 80003ea: 1a80 subs r0, r0, r2 + 80003ec: 4199 sbcs r1, r3 + 80003ee: 9000 str r0, [sp, #0] + 80003f0: 9101 str r1, [sp, #4] + 80003f2: e79f b.n 8000334 <__udivmoddi4+0x84> + 80003f4: 42a3 cmp r3, r4 + 80003f6: d8bc bhi.n 8000372 <__udivmoddi4+0xc2> + 80003f8: e783 b.n 8000302 <__udivmoddi4+0x52> + 80003fa: 4642 mov r2, r8 + 80003fc: 2320 movs r3, #32 + 80003fe: 2100 movs r1, #0 + 8000400: 1a9b subs r3, r3, r2 + 8000402: 2200 movs r2, #0 + 8000404: 9100 str r1, [sp, #0] + 8000406: 9201 str r2, [sp, #4] + 8000408: 2201 movs r2, #1 + 800040a: 40da lsrs r2, r3 + 800040c: 9201 str r2, [sp, #4] + 800040e: e786 b.n 800031e <__udivmoddi4+0x6e> + 8000410: 4642 mov r2, r8 + 8000412: 2320 movs r3, #32 + 8000414: 1a9b subs r3, r3, r2 + 8000416: 002a movs r2, r5 + 8000418: 4646 mov r6, r8 + 800041a: 409a lsls r2, r3 + 800041c: 0023 movs r3, r4 + 800041e: 40f3 lsrs r3, r6 + 8000420: 4644 mov r4, r8 + 8000422: 4313 orrs r3, r2 + 8000424: 002a movs r2, r5 + 8000426: 40e2 lsrs r2, r4 + 8000428: 001c movs r4, r3 + 800042a: 465b mov r3, fp + 800042c: 0015 movs r5, r2 + 800042e: 2b00 cmp r3, #0 + 8000430: dad4 bge.n 80003dc <__udivmoddi4+0x12c> + 8000432: 4642 mov r2, r8 + 8000434: 002f movs r7, r5 + 8000436: 2320 movs r3, #32 + 8000438: 0026 movs r6, r4 + 800043a: 4097 lsls r7, r2 + 800043c: 1a9b subs r3, r3, r2 + 800043e: 40de lsrs r6, r3 + 8000440: 003b movs r3, r7 + 8000442: 4333 orrs r3, r6 + 8000444: e7cd b.n 80003e2 <__udivmoddi4+0x132> + 8000446: 46c0 nop ; (mov r8, r8) + +08000448 <__clzdi2>: + 8000448: b510 push {r4, lr} + 800044a: 2900 cmp r1, #0 + 800044c: d103 bne.n 8000456 <__clzdi2+0xe> + 800044e: f000 f807 bl 8000460 <__clzsi2> + 8000452: 3020 adds r0, #32 + 8000454: e002 b.n 800045c <__clzdi2+0x14> + 8000456: 1c08 adds r0, r1, #0 + 8000458: f000 f802 bl 8000460 <__clzsi2> + 800045c: bd10 pop {r4, pc} + 800045e: 46c0 nop ; (mov r8, r8) + +08000460 <__clzsi2>: + 8000460: 211c movs r1, #28 + 8000462: 2301 movs r3, #1 + 8000464: 041b lsls r3, r3, #16 + 8000466: 4298 cmp r0, r3 + 8000468: d301 bcc.n 800046e <__clzsi2+0xe> + 800046a: 0c00 lsrs r0, r0, #16 + 800046c: 3910 subs r1, #16 + 800046e: 0a1b lsrs r3, r3, #8 + 8000470: 4298 cmp r0, r3 + 8000472: d301 bcc.n 8000478 <__clzsi2+0x18> + 8000474: 0a00 lsrs r0, r0, #8 + 8000476: 3908 subs r1, #8 + 8000478: 091b lsrs r3, r3, #4 + 800047a: 4298 cmp r0, r3 + 800047c: d301 bcc.n 8000482 <__clzsi2+0x22> + 800047e: 0900 lsrs r0, r0, #4 + 8000480: 3904 subs r1, #4 + 8000482: a202 add r2, pc, #8 ; (adr r2, 800048c <__clzsi2+0x2c>) + 8000484: 5c10 ldrb r0, [r2, r0] + 8000486: 1840 adds r0, r0, r1 + 8000488: 4770 bx lr + 800048a: 46c0 nop ; (mov r8, r8) + 800048c: 02020304 .word 0x02020304 + 8000490: 01010101 .word 0x01010101 + ... + +0800049c : + * @retval None +*/ +__STATIC_INLINE void LL_IOP_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->IOPENR, Periphs); + 800049c: 4b05 ldr r3, [pc, #20] ; (80004b4 ) +{ + 800049e: b082 sub sp, #8 + SET_BIT(RCC->IOPENR, Periphs); + 80004a0: 6ada ldr r2, [r3, #44] ; 0x2c + 80004a2: 4302 orrs r2, r0 + 80004a4: 62da str r2, [r3, #44] ; 0x2c + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->IOPENR, Periphs); + 80004a6: 6adb ldr r3, [r3, #44] ; 0x2c + 80004a8: 4018 ands r0, r3 + 80004aa: 9001 str r0, [sp, #4] + (void)tmpreg; + 80004ac: 9b01 ldr r3, [sp, #4] +} + 80004ae: b002 add sp, #8 + 80004b0: 4770 bx lr + 80004b2: 46c0 nop ; (mov r8, r8) + 80004b4: 40021000 .word 0x40021000 + +080004b8 : +/** + * @brief System Clock Configuration + * @retval None + */ +void SystemClock_Config(void) +{ + 80004b8: b500 push {lr} + 80004ba: b099 sub sp, #100 ; 0x64 + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + 80004bc: 2230 movs r2, #48 ; 0x30 + 80004be: 2100 movs r1, #0 + 80004c0: a80c add r0, sp, #48 ; 0x30 + 80004c2: f001 f889 bl 80015d8 + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + 80004c6: 2214 movs r2, #20 + 80004c8: 2100 movs r1, #0 + 80004ca: 4668 mov r0, sp + 80004cc: f001 f884 bl 80015d8 + RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; + 80004d0: 2218 movs r2, #24 + 80004d2: 2100 movs r1, #0 + 80004d4: a805 add r0, sp, #20 + 80004d6: f001 f87f bl 80015d8 + + /** Configure the main internal regulator output voltage + */ + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); + 80004da: 4919 ldr r1, [pc, #100] ; (8000540 ) + 80004dc: 4a19 ldr r2, [pc, #100] ; (8000544 ) + 80004de: 680b ldr r3, [r1, #0] + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI; + RCC_OscInitStruct.MSIState = RCC_MSI_ON; + RCC_OscInitStruct.MSICalibrationValue = 0; + RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_5; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + 80004e0: a80b add r0, sp, #44 ; 0x2c + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); + 80004e2: 401a ands r2, r3 + 80004e4: 2380 movs r3, #128 ; 0x80 + 80004e6: 011b lsls r3, r3, #4 + 80004e8: 4313 orrs r3, r2 + 80004ea: 600b str r3, [r1, #0] + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI; + 80004ec: 2310 movs r3, #16 + RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_5; + 80004ee: 22a0 movs r2, #160 ; 0xa0 + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI; + 80004f0: 930b str r3, [sp, #44] ; 0x2c + RCC_OscInitStruct.MSIState = RCC_MSI_ON; + 80004f2: 3b0f subs r3, #15 + 80004f4: 9311 str r3, [sp, #68] ; 0x44 + RCC_OscInitStruct.MSICalibrationValue = 0; + 80004f6: 2300 movs r3, #0 + RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_5; + 80004f8: 0212 lsls r2, r2, #8 + RCC_OscInitStruct.MSICalibrationValue = 0; + 80004fa: 9312 str r3, [sp, #72] ; 0x48 + RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_5; + 80004fc: 9213 str r2, [sp, #76] ; 0x4c + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; + 80004fe: 9314 str r3, [sp, #80] ; 0x50 + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + 8000500: f000 faec bl 8000adc + 8000504: 1e01 subs r1, r0, #0 + 8000506: d001 beq.n 800050c + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); + 8000508: b672 cpsid i +void Error_Handler(void) +{ + /* USER CODE BEGIN Error_Handler_Debug */ + /* User can add his own implementation to report the HAL error return state */ + __disable_irq(); + while (1) + 800050a: e7fe b.n 800050a + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK + 800050c: 230f movs r3, #15 + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI; + 800050e: 9001 str r0, [sp, #4] + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + 8000510: 9002 str r0, [sp, #8] + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; + 8000512: 9003 str r0, [sp, #12] + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; + 8000514: 9004 str r0, [sp, #16] + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK) + 8000516: 4668 mov r0, sp + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK + 8000518: 9300 str r3, [sp, #0] + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK) + 800051a: f000 fd2f bl 8000f7c + 800051e: 2800 cmp r0, #0 + 8000520: d001 beq.n 8000526 + 8000522: b672 cpsid i + while (1) + 8000524: e7fe b.n 8000524 + PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_LPUART1|RCC_PERIPHCLK_I2C1; + 8000526: 230c movs r3, #12 + PeriphClkInit.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_PCLK1; + 8000528: 9008 str r0, [sp, #32] + PeriphClkInit.I2c1ClockSelection = RCC_I2C1CLKSOURCE_PCLK1; + 800052a: 9009 str r0, [sp, #36] ; 0x24 + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) + 800052c: a805 add r0, sp, #20 + PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_LPUART1|RCC_PERIPHCLK_I2C1; + 800052e: 9305 str r3, [sp, #20] + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) + 8000530: f000 fdf2 bl 8001118 + 8000534: 2800 cmp r0, #0 + 8000536: d001 beq.n 800053c + 8000538: b672 cpsid i + while (1) + 800053a: e7fe b.n 800053a +} + 800053c: b019 add sp, #100 ; 0x64 + 800053e: bd00 pop {pc} + 8000540: 40007000 .word 0x40007000 + 8000544: ffffe7ff .word 0xffffe7ff + +08000548
: +{ + 8000548: b5f0 push {r4, r5, r6, r7, lr} + 800054a: b091 sub sp, #68 ; 0x44 + HAL_Init(); + 800054c: f000 fa02 bl 8000954 + SystemClock_Config(); + 8000550: f7ff ffb2 bl 80004b8 + LL_GPIO_InitTypeDef GPIO_InitStruct = {0}; + 8000554: 2218 movs r2, #24 + 8000556: 2100 movs r1, #0 + 8000558: a809 add r0, sp, #36 ; 0x24 + 800055a: f001 f83d bl 80015d8 + LL_IOP_GRP1_EnableClock(LL_IOP_GRP1_PERIPH_GPIOA); + 800055e: 2001 movs r0, #1 + 8000560: f7ff ff9c bl 800049c + * @arg @ref LL_GPIO_PIN_ALL + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + WRITE_REG(GPIOx->BSRR, PinMask); + 8000564: 25a0 movs r5, #160 ; 0xa0 + LL_IOP_GRP1_EnableClock(LL_IOP_GRP1_PERIPH_GPIOB); + 8000566: 2002 movs r0, #2 + 8000568: f7ff ff98 bl 800049c + 800056c: 2780 movs r7, #128 ; 0x80 + 800056e: 2320 movs r3, #32 + 8000570: 2240 movs r2, #64 ; 0x40 + GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_LOW; + 8000572: 2400 movs r4, #0 + GPIO_InitStruct.Mode = LL_GPIO_MODE_OUTPUT; + 8000574: 2601 movs r6, #1 + 8000576: 05ed lsls r5, r5, #23 + LL_GPIO_Init(LED_B_GPIO_Port, &GPIO_InitStruct); + 8000578: a809 add r0, sp, #36 ; 0x24 + 800057a: 61ab str r3, [r5, #24] + 800057c: 0001 movs r1, r0 + 800057e: 61aa str r2, [r5, #24] + 8000580: 0028 movs r0, r5 + 8000582: 61af str r7, [r5, #24] + GPIO_InitStruct.Pin = LED_B_Pin; + 8000584: 9309 str r3, [sp, #36] ; 0x24 + GPIO_InitStruct.Mode = LL_GPIO_MODE_OUTPUT; + 8000586: 960a str r6, [sp, #40] ; 0x28 + GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_LOW; + 8000588: 940b str r4, [sp, #44] ; 0x2c + GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; + 800058a: 940c str r4, [sp, #48] ; 0x30 + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + 800058c: 940d str r4, [sp, #52] ; 0x34 + LL_GPIO_Init(LED_B_GPIO_Port, &GPIO_InitStruct); + 800058e: f000 fe7f bl 8001290 + GPIO_InitStruct.Pin = LED_G_Pin; + 8000592: 2240 movs r2, #64 ; 0x40 + LL_GPIO_Init(LED_G_GPIO_Port, &GPIO_InitStruct); + 8000594: a909 add r1, sp, #36 ; 0x24 + 8000596: 0028 movs r0, r5 + GPIO_InitStruct.Pin = LED_G_Pin; + 8000598: 9209 str r2, [sp, #36] ; 0x24 + GPIO_InitStruct.Mode = LL_GPIO_MODE_OUTPUT; + 800059a: 960a str r6, [sp, #40] ; 0x28 + GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_LOW; + 800059c: 940b str r4, [sp, #44] ; 0x2c + GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; + 800059e: 940c str r4, [sp, #48] ; 0x30 + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + 80005a0: 940d str r4, [sp, #52] ; 0x34 + LL_GPIO_Init(LED_G_GPIO_Port, &GPIO_InitStruct); + 80005a2: f000 fe75 bl 8001290 + GPIO_InitStruct.Pin = LED_R_Pin; + 80005a6: 9709 str r7, [sp, #36] ; 0x24 + LL_GPIO_Init(LED_R_GPIO_Port, &GPIO_InitStruct); + 80005a8: a809 add r0, sp, #36 ; 0x24 + SET_BIT(RCC->AHBENR, Periphs); + 80005aa: 4f98 ldr r7, [pc, #608] ; (800080c ) + 80005ac: 0001 movs r1, r0 + 80005ae: 0028 movs r0, r5 + GPIO_InitStruct.Mode = LL_GPIO_MODE_OUTPUT; + 80005b0: 960a str r6, [sp, #40] ; 0x28 + GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_LOW; + 80005b2: 940b str r4, [sp, #44] ; 0x2c + GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; + 80005b4: 940c str r4, [sp, #48] ; 0x30 + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + 80005b6: 940d str r4, [sp, #52] ; 0x34 + LL_GPIO_Init(LED_R_GPIO_Port, &GPIO_InitStruct); + 80005b8: f000 fe6a bl 8001290 + 80005bc: 6b3b ldr r3, [r7, #48] ; 0x30 + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + 80005be: 21c2 movs r1, #194 ; 0xc2 + 80005c0: 4333 orrs r3, r6 + 80005c2: 633b str r3, [r7, #48] ; 0x30 + tmpreg = READ_BIT(RCC->AHBENR, Periphs); + 80005c4: 6b3b ldr r3, [r7, #48] ; 0x30 + 80005c6: 0089 lsls r1, r1, #2 + 80005c8: 4033 ands r3, r6 + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + 80005ca: 2680 movs r6, #128 ; 0x80 + 80005cc: 9300 str r3, [sp, #0] + (void)tmpreg; + 80005ce: 9b00 ldr r3, [sp, #0] + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + 80005d0: 4b8f ldr r3, [pc, #572] ; (8000810 ) + 80005d2: 4890 ldr r0, [pc, #576] ; (8000814 ) + 80005d4: 585a ldr r2, [r3, r1] + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + 80005d6: 00f6 lsls r6, r6, #3 + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + 80005d8: 4002 ands r2, r0 + 80005da: 505a str r2, [r3, r1] + LL_I2C_InitTypeDef I2C_InitStruct = {0}; + 80005dc: a809 add r0, sp, #36 ; 0x24 + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + 80005de: 601e str r6, [r3, #0] + 80005e0: 221c movs r2, #28 + 80005e2: 0021 movs r1, r4 + 80005e4: f000 fff8 bl 80015d8 + LL_GPIO_InitTypeDef GPIO_InitStruct = {0}; + 80005e8: 2218 movs r2, #24 + 80005ea: 0021 movs r1, r4 + 80005ec: a803 add r0, sp, #12 + 80005ee: f000 fff3 bl 80015d8 + LL_IOP_GRP1_EnableClock(LL_IOP_GRP1_PERIPH_GPIOA); + 80005f2: 2001 movs r0, #1 + 80005f4: f7ff ff52 bl 800049c + GPIO_InitStruct.Pin = LL_GPIO_PIN_9; + 80005f8: 2380 movs r3, #128 ; 0x80 + GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; + 80005fa: 2103 movs r1, #3 + GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_OPENDRAIN; + 80005fc: 2201 movs r2, #1 + GPIO_InitStruct.Pin = LL_GPIO_PIN_9; + 80005fe: 009b lsls r3, r3, #2 + 8000600: 9303 str r3, [sp, #12] + LL_GPIO_Init(GPIOA, &GPIO_InitStruct); + 8000602: a803 add r0, sp, #12 + GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; + 8000604: 3bff subs r3, #255 ; 0xff + 8000606: 3bff subs r3, #255 ; 0xff + GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; + 8000608: 9105 str r1, [sp, #20] + LL_GPIO_Init(GPIOA, &GPIO_InitStruct); + 800060a: 0001 movs r1, r0 + 800060c: 0028 movs r0, r5 + GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; + 800060e: 9304 str r3, [sp, #16] + GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_OPENDRAIN; + 8000610: 9206 str r2, [sp, #24] + GPIO_InitStruct.Pull = LL_GPIO_PULL_UP; + 8000612: 9207 str r2, [sp, #28] + GPIO_InitStruct.Alternate = LL_GPIO_AF_1; + 8000614: 9208 str r2, [sp, #32] + LL_GPIO_Init(GPIOA, &GPIO_InitStruct); + 8000616: f000 fe3b bl 8001290 + GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; + 800061a: 2103 movs r1, #3 + GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_OPENDRAIN; + 800061c: 2201 movs r2, #1 + GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; + 800061e: 2302 movs r3, #2 + GPIO_InitStruct.Pin = LL_GPIO_PIN_10; + 8000620: 9603 str r6, [sp, #12] + LL_GPIO_Init(GPIOA, &GPIO_InitStruct); + 8000622: ae03 add r6, sp, #12 + GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; + 8000624: 9105 str r1, [sp, #20] + LL_GPIO_Init(GPIOA, &GPIO_InitStruct); + 8000626: 0028 movs r0, r5 + 8000628: 0031 movs r1, r6 + GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; + 800062a: 9304 str r3, [sp, #16] + GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_OPENDRAIN; + 800062c: 9206 str r2, [sp, #24] + GPIO_InitStruct.Pull = LL_GPIO_PULL_UP; + 800062e: 9207 str r2, [sp, #28] + GPIO_InitStruct.Alternate = LL_GPIO_AF_1; + 8000630: 9208 str r2, [sp, #32] + LL_GPIO_Init(GPIOA, &GPIO_InitStruct); + 8000632: f000 fe2d bl 8001290 + SET_BIT(RCC->APB1ENR, Periphs); + 8000636: 2180 movs r1, #128 ; 0x80 + 8000638: 6bba ldr r2, [r7, #56] ; 0x38 + 800063a: 0389 lsls r1, r1, #14 + 800063c: 430a orrs r2, r1 + 800063e: 63ba str r2, [r7, #56] ; 0x38 + tmpreg = READ_BIT(RCC->APB1ENR, Periphs); + 8000640: 6bbb ldr r3, [r7, #56] ; 0x38 + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableAutoEndMode(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR2, I2C_CR2_AUTOEND); + 8000642: 4e75 ldr r6, [pc, #468] ; (8000818 ) + 8000644: 400b ands r3, r1 + 8000646: 9301 str r3, [sp, #4] + (void)tmpreg; + 8000648: 9b01 ldr r3, [sp, #4] + 800064a: 2380 movs r3, #128 ; 0x80 + 800064c: 6872 ldr r2, [r6, #4] + 800064e: 049b lsls r3, r3, #18 + 8000650: 4313 orrs r3, r2 + 8000652: 6073 str r3, [r6, #4] + CLEAR_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN); + 8000654: 68f3 ldr r3, [r6, #12] + 8000656: 4871 ldr r0, [pc, #452] ; (800081c ) + CLEAR_BIT(I2Cx->CR1, I2C_CR1_GCEN); + 8000658: 4a71 ldr r2, [pc, #452] ; (8000820 ) + CLEAR_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN); + 800065a: 4003 ands r3, r0 + 800065c: 60f3 str r3, [r6, #12] + CLEAR_BIT(I2Cx->CR1, I2C_CR1_GCEN); + 800065e: 6833 ldr r3, [r6, #0] + LL_I2C_Init(I2C1, &I2C_InitStruct); + 8000660: 0030 movs r0, r6 + 8000662: 4013 ands r3, r2 + 8000664: 6033 str r3, [r6, #0] + CLEAR_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH); + 8000666: 6833 ldr r3, [r6, #0] + 8000668: 4a6e ldr r2, [pc, #440] ; (8000824 ) + 800066a: 4013 ands r3, r2 + 800066c: 6033 str r3, [r6, #0] + I2C_InitStruct.Timing = 0x00000708; + 800066e: 23e1 movs r3, #225 ; 0xe1 + LL_I2C_Init(I2C1, &I2C_InitStruct); + 8000670: aa09 add r2, sp, #36 ; 0x24 + 8000672: 0011 movs r1, r2 + I2C_InitStruct.Timing = 0x00000708; + 8000674: 00db lsls r3, r3, #3 + 8000676: 930a str r3, [sp, #40] ; 0x28 + I2C_InitStruct.PeripheralMode = LL_I2C_MODE_I2C; + 8000678: 9409 str r4, [sp, #36] ; 0x24 + I2C_InitStruct.AnalogFilter = LL_I2C_ANALOGFILTER_ENABLE; + 800067a: 940b str r4, [sp, #44] ; 0x2c + I2C_InitStruct.DigitalFilter = 0; + 800067c: 940c str r4, [sp, #48] ; 0x30 + I2C_InitStruct.OwnAddress1 = 0; + 800067e: 940d str r4, [sp, #52] ; 0x34 + I2C_InitStruct.TypeAcknowledge = LL_I2C_ACK; + 8000680: 940e str r4, [sp, #56] ; 0x38 + I2C_InitStruct.OwnAddrSize = LL_I2C_OWNADDRESS1_7BIT; + 8000682: 940f str r4, [sp, #60] ; 0x3c + LL_I2C_Init(I2C1, &I2C_InitStruct); + 8000684: f000 fe56 bl 8001334 + MODIFY_REG(I2Cx->OAR2, I2C_OAR2_OA2 | I2C_OAR2_OA2MSK, OwnAddress2 | OwnAddrMask); + 8000688: 68f3 ldr r3, [r6, #12] + 800068a: 4a67 ldr r2, [pc, #412] ; (8000828 ) + LL_LPUART_InitTypeDef LPUART_InitStruct = {0}; + 800068c: 0021 movs r1, r4 + 800068e: 4013 ands r3, r2 + 8000690: 60f3 str r3, [r6, #12] + 8000692: ae03 add r6, sp, #12 + 8000694: 2218 movs r2, #24 + 8000696: 0030 movs r0, r6 + LL_GPIO_InitTypeDef GPIO_InitStruct = {0}; + 8000698: ae09 add r6, sp, #36 ; 0x24 + LL_LPUART_InitTypeDef LPUART_InitStruct = {0}; + 800069a: f000 ff9d bl 80015d8 + LL_GPIO_InitTypeDef GPIO_InitStruct = {0}; + 800069e: 2218 movs r2, #24 + 80006a0: 0021 movs r1, r4 + 80006a2: 0030 movs r0, r6 + 80006a4: f000 ff98 bl 80015d8 + SET_BIT(RCC->APB1ENR, Periphs); + 80006a8: 2180 movs r1, #128 ; 0x80 + 80006aa: 6bba ldr r2, [r7, #56] ; 0x38 + 80006ac: 02c9 lsls r1, r1, #11 + 80006ae: 430a orrs r2, r1 + 80006b0: 63ba str r2, [r7, #56] ; 0x38 + tmpreg = READ_BIT(RCC->APB1ENR, Periphs); + 80006b2: 6bbb ldr r3, [r7, #56] ; 0x38 + LL_IOP_GRP1_EnableClock(LL_IOP_GRP1_PERIPH_GPIOA); + 80006b4: 2001 movs r0, #1 + 80006b6: 400b ands r3, r1 + 80006b8: 9302 str r3, [sp, #8] + (void)tmpreg; + 80006ba: 9b02 ldr r3, [sp, #8] + 80006bc: f7ff feee bl 800049c + LL_IOP_GRP1_EnableClock(LL_IOP_GRP1_PERIPH_GPIOB); + 80006c0: 2002 movs r0, #2 + 80006c2: f7ff feeb bl 800049c + GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; + 80006c6: 2103 movs r1, #3 + GPIO_InitStruct.Pin = LL_GPIO_PIN_0; + 80006c8: 2701 movs r7, #1 + GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; + 80006ca: 2302 movs r3, #2 + GPIO_InitStruct.Alternate = LL_GPIO_AF_6; + 80006cc: 2606 movs r6, #6 + LL_GPIO_Init(GPIOA, &GPIO_InitStruct); + 80006ce: aa09 add r2, sp, #36 ; 0x24 + GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; + 80006d0: 910b str r1, [sp, #44] ; 0x2c + LL_GPIO_Init(GPIOA, &GPIO_InitStruct); + 80006d2: 0028 movs r0, r5 + 80006d4: 0011 movs r1, r2 + GPIO_InitStruct.Pin = LL_GPIO_PIN_0; + 80006d6: 9709 str r7, [sp, #36] ; 0x24 + GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; + 80006d8: 930a str r3, [sp, #40] ; 0x28 + GPIO_InitStruct.Alternate = LL_GPIO_AF_6; + 80006da: 960e str r6, [sp, #56] ; 0x38 + GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; + 80006dc: 940c str r4, [sp, #48] ; 0x30 + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + 80006de: 940d str r4, [sp, #52] ; 0x34 + LL_GPIO_Init(GPIOA, &GPIO_InitStruct); + 80006e0: f000 fdd6 bl 8001290 + GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; + 80006e4: 2103 movs r1, #3 + GPIO_InitStruct.Pin = LL_GPIO_PIN_1; + 80006e6: 2302 movs r3, #2 + GPIO_InitStruct.Alternate = LL_GPIO_AF_6; + 80006e8: 960e str r6, [sp, #56] ; 0x38 + LL_GPIO_Init(GPIOA, &GPIO_InitStruct); + 80006ea: ae09 add r6, sp, #36 ; 0x24 + GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; + 80006ec: 910b str r1, [sp, #44] ; 0x2c + LL_GPIO_Init(GPIOA, &GPIO_InitStruct); + 80006ee: 0028 movs r0, r5 + 80006f0: 0031 movs r1, r6 + GPIO_InitStruct.Pin = LL_GPIO_PIN_1; + 80006f2: 9309 str r3, [sp, #36] ; 0x24 + GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; + 80006f4: 930a str r3, [sp, #40] ; 0x28 + GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; + 80006f6: 940c str r4, [sp, #48] ; 0x30 + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + 80006f8: 940d str r4, [sp, #52] ; 0x34 + LL_GPIO_Init(GPIOA, &GPIO_InitStruct); + 80006fa: f000 fdc9 bl 8001290 + GPIO_InitStruct.Pin = LL_GPIO_PIN_1; + 80006fe: 2302 movs r3, #2 + GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; + 8000700: 2103 movs r1, #3 + LL_GPIO_Init(GPIOB, &GPIO_InitStruct); + 8000702: ae09 add r6, sp, #36 ; 0x24 + GPIO_InitStruct.Pin = LL_GPIO_PIN_1; + 8000704: 9309 str r3, [sp, #36] ; 0x24 + GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; + 8000706: 930a str r3, [sp, #40] ; 0x28 + GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; + 8000708: 910b str r1, [sp, #44] ; 0x2c + GPIO_InitStruct.Alternate = LL_GPIO_AF_4; + 800070a: 18db adds r3, r3, r3 + LL_GPIO_Init(GPIOB, &GPIO_InitStruct); + 800070c: 0031 movs r1, r6 + 800070e: 4847 ldr r0, [pc, #284] ; (800082c ) + GPIO_InitStruct.Alternate = LL_GPIO_AF_4; + 8000710: 930e str r3, [sp, #56] ; 0x38 + GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; + 8000712: 940c str r4, [sp, #48] ; 0x30 + GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; + 8000714: 940d str r4, [sp, #52] ; 0x34 + LL_GPIO_Init(GPIOB, &GPIO_InitStruct); + 8000716: f000 fdbb bl 8001290 + * @arg @ref LL_DMA_REQUEST_15 + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Request) +{ + MODIFY_REG(((DMA_Request_TypeDef *)((uint32_t)((uint32_t)DMAx + DMA_CSELR_OFFSET)))->CSELR, + 800071a: 4945 ldr r1, [pc, #276] ; (8000830 ) + 800071c: 4a45 ldr r2, [pc, #276] ; (8000834 ) + 800071e: 680b ldr r3, [r1, #0] + MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PINC, + 8000720: 2040 movs r0, #64 ; 0x40 + MODIFY_REG(((DMA_Request_TypeDef *)((uint32_t)((uint32_t)DMAx + DMA_CSELR_OFFSET)))->CSELR, + 8000722: 401a ands r2, r3 + 8000724: 23a0 movs r3, #160 ; 0xa0 + 8000726: 00db lsls r3, r3, #3 + 8000728: 4313 orrs r3, r2 + 800072a: 600b str r3, [r1, #0] + MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + 800072c: 4b42 ldr r3, [pc, #264] ; (8000838 ) + 800072e: 4943 ldr r1, [pc, #268] ; (800083c ) + 8000730: 681a ldr r2, [r3, #0] + LL_LPUART_Init(LPUART1, &LPUART_InitStruct); + 8000732: 4e43 ldr r6, [pc, #268] ; (8000840 ) + 8000734: 400a ands r2, r1 + 8000736: 601a str r2, [r3, #0] + MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PL, + 8000738: 681a ldr r2, [r3, #0] + 800073a: 4942 ldr r1, [pc, #264] ; (8000844 ) + 800073c: 4011 ands r1, r2 + 800073e: 2280 movs r2, #128 ; 0x80 + 8000740: 0152 lsls r2, r2, #5 + 8000742: 430a orrs r2, r1 + MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_CIRC, + 8000744: 2120 movs r1, #32 + MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PL, + 8000746: 601a str r2, [r3, #0] + MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_CIRC, + 8000748: 681a ldr r2, [r3, #0] + 800074a: 438a bics r2, r1 + 800074c: 430a orrs r2, r1 + 800074e: 601a str r2, [r3, #0] + MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PINC, + 8000750: 681a ldr r2, [r3, #0] + MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MINC, + 8000752: 3160 adds r1, #96 ; 0x60 + MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PINC, + 8000754: 4382 bics r2, r0 + 8000756: 601a str r2, [r3, #0] + MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MINC, + 8000758: 681a ldr r2, [r3, #0] + 800075a: 0030 movs r0, r6 + 800075c: 438a bics r2, r1 + 800075e: 430a orrs r2, r1 + 8000760: 601a str r2, [r3, #0] + MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PSIZE, + 8000762: 681a ldr r2, [r3, #0] + 8000764: 4938 ldr r1, [pc, #224] ; (8000848 ) + 8000766: 400a ands r2, r1 + 8000768: 601a str r2, [r3, #0] + MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MSIZE, + 800076a: 681a ldr r2, [r3, #0] + 800076c: 4937 ldr r1, [pc, #220] ; (800084c ) + 800076e: 400a ands r2, r1 + 8000770: 601a str r2, [r3, #0] + LPUART_InitStruct.BaudRate = 115200; + 8000772: 23e1 movs r3, #225 ; 0xe1 + 8000774: 025b lsls r3, r3, #9 + 8000776: 9303 str r3, [sp, #12] + LPUART_InitStruct.TransferDirection = LL_LPUART_DIRECTION_TX_RX; + 8000778: 230c movs r3, #12 + LL_LPUART_Init(LPUART1, &LPUART_InitStruct); + 800077a: a903 add r1, sp, #12 + LPUART_InitStruct.TransferDirection = LL_LPUART_DIRECTION_TX_RX; + 800077c: 9307 str r3, [sp, #28] + LPUART_InitStruct.DataWidth = LL_LPUART_DATAWIDTH_8B; + 800077e: 9404 str r4, [sp, #16] + LPUART_InitStruct.StopBits = LL_LPUART_STOPBITS_1; + 8000780: 9405 str r4, [sp, #20] + LPUART_InitStruct.Parity = LL_LPUART_PARITY_NONE; + 8000782: 9406 str r4, [sp, #24] + LPUART_InitStruct.HardwareFlowControl = LL_LPUART_HWCONTROL_NONE; + 8000784: 9408 str r4, [sp, #32] + LL_LPUART_Init(LPUART1, &LPUART_InitStruct); + 8000786: f000 fe0f bl 80013a8 + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableDEMode(USART_TypeDef *LPUARTx) +{ + SET_BIT(LPUARTx->CR3, USART_CR3_DEM); + 800078a: 2380 movs r3, #128 ; 0x80 + 800078c: 68b2 ldr r2, [r6, #8] + 800078e: 01db lsls r3, r3, #7 + 8000790: 4313 orrs r3, r2 + 8000792: 60b3 str r3, [r6, #8] + * @arg @ref LL_LPUART_DE_POLARITY_LOW + * @retval None + */ +__STATIC_INLINE void LL_LPUART_SetDESignalPolarity(USART_TypeDef *LPUARTx, uint32_t Polarity) +{ + MODIFY_REG(LPUARTx->CR3, USART_CR3_DEP, Polarity); + 8000794: 68b3 ldr r3, [r6, #8] + 8000796: 4821 ldr r0, [pc, #132] ; (800081c ) + MODIFY_REG(LPUARTx->CR1, USART_CR1_DEAT, Time << USART_CR1_DEAT_Pos); + 8000798: 4a2d ldr r2, [pc, #180] ; (8000850 ) + MODIFY_REG(LPUARTx->CR3, USART_CR3_DEP, Polarity); + 800079a: 4003 ands r3, r0 + 800079c: 60b3 str r3, [r6, #8] + MODIFY_REG(LPUARTx->CR1, USART_CR1_DEAT, Time << USART_CR1_DEAT_Pos); + 800079e: 6833 ldr r3, [r6, #0] + 80007a0: 401a ands r2, r3 + 80007a2: 23a0 movs r3, #160 ; 0xa0 + 80007a4: 049b lsls r3, r3, #18 + 80007a6: 4313 orrs r3, r2 + 80007a8: 6033 str r3, [r6, #0] + MODIFY_REG(LPUARTx->CR1, USART_CR1_DEDT, Time << USART_CR1_DEDT_Pos); + 80007aa: 6833 ldr r3, [r6, #0] + 80007ac: 4a29 ldr r2, [pc, #164] ; (8000854 ) + 80007ae: 401a ands r2, r3 + 80007b0: 23a0 movs r3, #160 ; 0xa0 + 80007b2: 035b lsls r3, r3, #13 + 80007b4: 4313 orrs r3, r2 + 80007b6: 6033 str r3, [r6, #0] + SET_BIT(LPUARTx->CR1, USART_CR1_UE); + 80007b8: 6833 ldr r3, [r6, #0] + 80007ba: 433b orrs r3, r7 + 80007bc: 6033 str r3, [r6, #0] + * @retval None + */ +__STATIC_INLINE void LL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + uint32_t odr = READ_REG(GPIOx->ODR); + WRITE_REG(GPIOx->BSRR, ((odr & PinMask) << 16u) | (~odr & PinMask)); + 80007be: 377f adds r7, #127 ; 0x7f + 80007c0: 2180 movs r1, #128 ; 0x80 + uint32_t odr = READ_REG(GPIOx->ODR); + 80007c2: 696a ldr r2, [r5, #20] + WRITE_REG(GPIOx->BSRR, ((odr & PinMask) << 16u) | (~odr & PinMask)); + 80007c4: 0409 lsls r1, r1, #16 + 80007c6: 0413 lsls r3, r2, #16 + 80007c8: 400b ands r3, r1 + 80007ca: 0039 movs r1, r7 + 80007cc: 4391 bics r1, r2 + 80007ce: 2280 movs r2, #128 ; 0x80 + 80007d0: 430b orrs r3, r1 + 80007d2: 61ab str r3, [r5, #24] + uint32_t odr = READ_REG(GPIOx->ODR); + 80007d4: 6969 ldr r1, [r5, #20] + WRITE_REG(GPIOx->BSRR, ((odr & PinMask) << 16u) | (~odr & PinMask)); + 80007d6: 03d2 lsls r2, r2, #15 + 80007d8: 040b lsls r3, r1, #16 + 80007da: 4013 ands r3, r2 + 80007dc: 2240 movs r2, #64 ; 0x40 + 80007de: 438a bics r2, r1 + 80007e0: 4313 orrs r3, r2 + 80007e2: 2280 movs r2, #128 ; 0x80 + 80007e4: 61ab str r3, [r5, #24] + uint32_t odr = READ_REG(GPIOx->ODR); + 80007e6: 6969 ldr r1, [r5, #20] + WRITE_REG(GPIOx->BSRR, ((odr & PinMask) << 16u) | (~odr & PinMask)); + 80007e8: 0392 lsls r2, r2, #14 + 80007ea: 040b lsls r3, r1, #16 + 80007ec: 4013 ands r3, r2 + 80007ee: 2220 movs r2, #32 + 80007f0: 438a bics r2, r1 + 80007f2: 4313 orrs r3, r2 + 80007f4: 61ab str r3, [r5, #24] + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXE(USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->ISR, USART_ISR_TXE) == (USART_ISR_TXE)) ? 1UL : 0UL); + 80007f6: 69f3 ldr r3, [r6, #28] + 80007f8: 423b tst r3, r7 + 80007fa: d0fc beq.n 80007f6 + HAL_Delay(1000); + 80007fc: 20fa movs r0, #250 ; 0xfa + * @param Value between Min_Data=0x00 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void LL_LPUART_TransmitData8(USART_TypeDef *LPUARTx, uint8_t Value) +{ + LPUARTx->TDR = Value; + 80007fe: 62b4 str r4, [r6, #40] ; 0x28 + 8000800: 0080 lsls r0, r0, #2 + i++; + 8000802: 3401 adds r4, #1 + 8000804: b2e4 uxtb r4, r4 + HAL_Delay(1000); + 8000806: f000 f8cb bl 80009a0 + LL_GPIO_TogglePin(LED_R_GPIO_Port, LED_R_Pin); + 800080a: e7d9 b.n 80007c0 + 800080c: 40021000 .word 0x40021000 + 8000810: e000e100 .word 0xe000e100 + 8000814: ff00ffff .word 0xff00ffff + 8000818: 40005400 .word 0x40005400 + 800081c: ffff7fff .word 0xffff7fff + 8000820: fff7ffff .word 0xfff7ffff + 8000824: fffdffff .word 0xfffdffff + 8000828: fffff801 .word 0xfffff801 + 800082c: 50000400 .word 0x50000400 + 8000830: 400200a8 .word 0x400200a8 + 8000834: fffff0ff .word 0xfffff0ff + 8000838: 40020030 .word 0x40020030 + 800083c: ffffbfef .word 0xffffbfef + 8000840: 40004800 .word 0x40004800 + 8000844: ffffcfff .word 0xffffcfff + 8000848: fffffcff .word 0xfffffcff + 800084c: fffff3ff .word 0xfffff3ff + 8000850: fc1fffff .word 0xfc1fffff + 8000854: ffe0ffff .word 0xffe0ffff + +08000858 : +{ + /* USER CODE BEGIN MspInit 0 */ + + /* USER CODE END MspInit 0 */ + + __HAL_RCC_SYSCFG_CLK_ENABLE(); + 8000858: 2201 movs r2, #1 + 800085a: 4b05 ldr r3, [pc, #20] ; (8000870 ) + 800085c: 6b59 ldr r1, [r3, #52] ; 0x34 + 800085e: 430a orrs r2, r1 + 8000860: 635a str r2, [r3, #52] ; 0x34 + __HAL_RCC_PWR_CLK_ENABLE(); + 8000862: 2280 movs r2, #128 ; 0x80 + 8000864: 6b99 ldr r1, [r3, #56] ; 0x38 + 8000866: 0552 lsls r2, r2, #21 + 8000868: 430a orrs r2, r1 + 800086a: 639a str r2, [r3, #56] ; 0x38 + /* System interrupt init*/ + + /* USER CODE BEGIN MspInit 1 */ + + /* USER CODE END MspInit 1 */ +} + 800086c: 4770 bx lr + 800086e: 46c0 nop ; (mov r8, r8) + 8000870: 40021000 .word 0x40021000 + +08000874 : +{ + /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ + + /* USER CODE END NonMaskableInt_IRQn 0 */ + /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ + while (1) + 8000874: e7fe b.n 8000874 + +08000876 : +void HardFault_Handler(void) +{ + /* USER CODE BEGIN HardFault_IRQn 0 */ + + /* USER CODE END HardFault_IRQn 0 */ + while (1) + 8000876: e7fe b.n 8000876 + +08000878 : + + /* USER CODE END SVC_IRQn 0 */ + /* USER CODE BEGIN SVC_IRQn 1 */ + + /* USER CODE END SVC_IRQn 1 */ +} + 8000878: 4770 bx lr + +0800087a : + 800087a: 4770 bx lr + +0800087c : + +/** + * @brief This function handles System tick timer. + */ +void SysTick_Handler(void) +{ + 800087c: b510 push {r4, lr} + /* USER CODE BEGIN SysTick_IRQn 0 */ + + /* USER CODE END SysTick_IRQn 0 */ + HAL_IncTick(); + 800087e: f000 f87d bl 800097c + /* USER CODE BEGIN SysTick_IRQn 1 */ + /* USER CODE END SysTick_IRQn 1 */ +} + 8000882: bd10 pop {r4, pc} + +08000884 : + 8000884: 4770 bx lr + +08000886 : +{ + /* Configure the Vector Table location add offset address ------------------*/ +#if defined (USER_VECT_TAB_ADDRESS) + SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#endif /* USER_VECT_TAB_ADDRESS */ +} + 8000886: 4770 bx lr + +08000888 : + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr r0, =_estack + 8000888: 4813 ldr r0, [pc, #76] ; (80008d8 ) + mov sp, r0 /* set stack pointer */ + 800088a: 4685 mov sp, r0 + +/*Check if boot space corresponds to system memory*/ + + LDR R0,=0x00000004 + 800088c: 4813 ldr r0, [pc, #76] ; (80008dc ) + LDR R1, [R0] + 800088e: 6801 ldr r1, [r0, #0] + LSRS R1, R1, #24 + 8000890: 0e09 lsrs r1, r1, #24 + LDR R2,=0x1F + 8000892: 4a13 ldr r2, [pc, #76] ; (80008e0 ) + CMP R1, R2 + 8000894: 4291 cmp r1, r2 + BNE ApplicationStart + 8000896: d105 bne.n 80008a4 + + /*SYSCFG clock enable*/ + LDR R0,=0x40021034 + 8000898: 4812 ldr r0, [pc, #72] ; (80008e4 ) + LDR R1,=0x00000001 + 800089a: 4913 ldr r1, [pc, #76] ; (80008e8 ) + STR R1, [R0] + 800089c: 6001 str r1, [r0, #0] + +/*Set CFGR1 register with flash memory remap at address 0*/ + LDR R0,=0x40010000 + 800089e: 4813 ldr r0, [pc, #76] ; (80008ec ) + LDR R1,=0x00000000 + 80008a0: 4913 ldr r1, [pc, #76] ; (80008f0 ) + STR R1, [R0] + 80008a2: 6001 str r1, [r0, #0] + +080008a4 : + +ApplicationStart: +/* Copy the data segment initializers from flash to SRAM */ + ldr r0, =_sdata + 80008a4: 4813 ldr r0, [pc, #76] ; (80008f4 ) + ldr r1, =_edata + 80008a6: 4914 ldr r1, [pc, #80] ; (80008f8 ) + ldr r2, =_sidata + 80008a8: 4a14 ldr r2, [pc, #80] ; (80008fc ) + movs r3, #0 + 80008aa: 2300 movs r3, #0 + b LoopCopyDataInit + 80008ac: e002 b.n 80008b4 + +080008ae : + +CopyDataInit: + ldr r4, [r2, r3] + 80008ae: 58d4 ldr r4, [r2, r3] + str r4, [r0, r3] + 80008b0: 50c4 str r4, [r0, r3] + adds r3, r3, #4 + 80008b2: 3304 adds r3, #4 + +080008b4 : + +LoopCopyDataInit: + adds r4, r0, r3 + 80008b4: 18c4 adds r4, r0, r3 + cmp r4, r1 + 80008b6: 428c cmp r4, r1 + bcc CopyDataInit + 80008b8: d3f9 bcc.n 80008ae + +/* Zero fill the bss segment. */ + ldr r2, =_sbss + 80008ba: 4a11 ldr r2, [pc, #68] ; (8000900 ) + ldr r4, =_ebss + 80008bc: 4c11 ldr r4, [pc, #68] ; (8000904 ) + movs r3, #0 + 80008be: 2300 movs r3, #0 + b LoopFillZerobss + 80008c0: e001 b.n 80008c6 + +080008c2 : + +FillZerobss: + str r3, [r2] + 80008c2: 6013 str r3, [r2, #0] + adds r2, r2, #4 + 80008c4: 3204 adds r2, #4 + +080008c6 : + +LoopFillZerobss: + cmp r2, r4 + 80008c6: 42a2 cmp r2, r4 + bcc FillZerobss + 80008c8: d3fb bcc.n 80008c2 + +/* Call the clock system intitialization function.*/ + bl SystemInit + 80008ca: f7ff ffdc bl 8000886 +/* Call static constructors */ + bl __libc_init_array + 80008ce: f000 fe5f bl 8001590 <__libc_init_array> +/* Call the application's entry point.*/ + bl main + 80008d2: f7ff fe39 bl 8000548
+ +080008d6 : + +LoopForever: + b LoopForever + 80008d6: e7fe b.n 80008d6 + ldr r0, =_estack + 80008d8: 20000800 .word 0x20000800 + LDR R0,=0x00000004 + 80008dc: 00000004 .word 0x00000004 + LDR R2,=0x1F + 80008e0: 0000001f .word 0x0000001f + LDR R0,=0x40021034 + 80008e4: 40021034 .word 0x40021034 + LDR R1,=0x00000001 + 80008e8: 00000001 .word 0x00000001 + LDR R0,=0x40010000 + 80008ec: 40010000 .word 0x40010000 + LDR R1,=0x00000000 + 80008f0: 00000000 .word 0x00000000 + ldr r0, =_sdata + 80008f4: 20000000 .word 0x20000000 + ldr r1, =_edata + 80008f8: 2000000c .word 0x2000000c + ldr r2, =_sidata + 80008fc: 08001634 .word 0x08001634 + ldr r2, =_sbss + 8000900: 2000000c .word 0x2000000c + ldr r4, =_ebss + 8000904: 2000002c .word 0x2000002c + +08000908 : + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + 8000908: e7fe b.n 8000908 + ... + +0800090c : + * implementation in user file. + * @param TickPriority Tick interrupt priority. + * @retval HAL status + */ +__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) +{ + 800090c: b570 push {r4, r5, r6, lr} + 800090e: 0005 movs r5, r0 + /* Configure the SysTick to have interrupt in 1ms time basis*/ + if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U) + 8000910: 20fa movs r0, #250 ; 0xfa + 8000912: 4b0d ldr r3, [pc, #52] ; (8000948 ) + 8000914: 0080 lsls r0, r0, #2 + 8000916: 7819 ldrb r1, [r3, #0] + 8000918: f7ff fbf6 bl 8000108 <__udivsi3> + 800091c: 4b0b ldr r3, [pc, #44] ; (800094c ) + 800091e: 0001 movs r1, r0 + 8000920: 6818 ldr r0, [r3, #0] + 8000922: f7ff fbf1 bl 8000108 <__udivsi3> + 8000926: f000 f877 bl 8000a18 + 800092a: 0004 movs r4, r0 + { + return HAL_ERROR; + 800092c: 2001 movs r0, #1 + if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U) + 800092e: 2c00 cmp r4, #0 + 8000930: d109 bne.n 8000946 + } + + /* Configure the SysTick IRQ priority */ + if (TickPriority < (1UL << __NVIC_PRIO_BITS)) + 8000932: 2d03 cmp r5, #3 + 8000934: d807 bhi.n 8000946 + { + HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); + 8000936: 3802 subs r0, #2 + 8000938: 0022 movs r2, r4 + 800093a: 0029 movs r1, r5 + 800093c: f000 f842 bl 80009c4 + uwTickPrio = TickPriority; + 8000940: 0020 movs r0, r4 + 8000942: 4b03 ldr r3, [pc, #12] ; (8000950 ) + 8000944: 601d str r5, [r3, #0] + return HAL_ERROR; + } + + /* Return function status */ + return HAL_OK; +} + 8000946: bd70 pop {r4, r5, r6, pc} + 8000948: 20000004 .word 0x20000004 + 800094c: 20000000 .word 0x20000000 + 8000950: 20000008 .word 0x20000008 + +08000954 : + __HAL_FLASH_PREREAD_BUFFER_ENABLE(); + 8000954: 2340 movs r3, #64 ; 0x40 + 8000956: 4a08 ldr r2, [pc, #32] ; (8000978 ) +{ + 8000958: b510 push {r4, lr} + __HAL_FLASH_PREREAD_BUFFER_ENABLE(); + 800095a: 6811 ldr r1, [r2, #0] + if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK) + 800095c: 2000 movs r0, #0 + __HAL_FLASH_PREREAD_BUFFER_ENABLE(); + 800095e: 430b orrs r3, r1 + 8000960: 6013 str r3, [r2, #0] + if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK) + 8000962: f7ff ffd3 bl 800090c + 8000966: 1e04 subs r4, r0, #0 + 8000968: d103 bne.n 8000972 + HAL_MspInit(); + 800096a: f7ff ff75 bl 8000858 +} + 800096e: 0020 movs r0, r4 + 8000970: bd10 pop {r4, pc} + status = HAL_ERROR; + 8000972: 2401 movs r4, #1 + 8000974: e7fb b.n 800096e + 8000976: 46c0 nop ; (mov r8, r8) + 8000978: 40022000 .word 0x40022000 + +0800097c : + * implementations in user file. + * @retval None + */ +__weak void HAL_IncTick(void) +{ + uwTick += uwTickFreq; + 800097c: 4a03 ldr r2, [pc, #12] ; (800098c ) + 800097e: 4b04 ldr r3, [pc, #16] ; (8000990 ) + 8000980: 6811 ldr r1, [r2, #0] + 8000982: 781b ldrb r3, [r3, #0] + 8000984: 185b adds r3, r3, r1 + 8000986: 6013 str r3, [r2, #0] +} + 8000988: 4770 bx lr + 800098a: 46c0 nop ; (mov r8, r8) + 800098c: 20000028 .word 0x20000028 + 8000990: 20000004 .word 0x20000004 + +08000994 : + * implementations in user file. + * @retval tick value + */ +__weak uint32_t HAL_GetTick(void) +{ + return uwTick; + 8000994: 4b01 ldr r3, [pc, #4] ; (800099c ) + 8000996: 6818 ldr r0, [r3, #0] +} + 8000998: 4770 bx lr + 800099a: 46c0 nop ; (mov r8, r8) + 800099c: 20000028 .word 0x20000028 + +080009a0 : + * implementations in user file. + * @param Delay specifies the delay time length, in milliseconds. + * @retval None + */ +__weak void HAL_Delay(uint32_t Delay) +{ + 80009a0: b570 push {r4, r5, r6, lr} + 80009a2: 0004 movs r4, r0 + uint32_t tickstart = HAL_GetTick(); + 80009a4: f7ff fff6 bl 8000994 + 80009a8: 0005 movs r5, r0 + uint32_t wait = Delay; + + /* Add a freq to guarantee minimum wait */ + if (wait < HAL_MAX_DELAY) + 80009aa: 1c63 adds r3, r4, #1 + 80009ac: d002 beq.n 80009b4 + { + wait += (uint32_t)(uwTickFreq); + 80009ae: 4b04 ldr r3, [pc, #16] ; (80009c0 ) + 80009b0: 781b ldrb r3, [r3, #0] + 80009b2: 18e4 adds r4, r4, r3 + } + + while((HAL_GetTick() - tickstart) < wait) + 80009b4: f7ff ffee bl 8000994 + 80009b8: 1b40 subs r0, r0, r5 + 80009ba: 42a0 cmp r0, r4 + 80009bc: d3fa bcc.n 80009b4 + { + } +} + 80009be: bd70 pop {r4, r5, r6, pc} + 80009c0: 20000004 .word 0x20000004 + +080009c4 : + * with stm32l0xx devices, this parameter is a dummy value and it is ignored, because + * no subpriority supported in Cortex M0+ based products. + * @retval None + */ +void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) +{ + 80009c4: b530 push {r4, r5, lr} + 80009c6: 25ff movs r5, #255 ; 0xff + 80009c8: 2403 movs r4, #3 + 80009ca: 002a movs r2, r5 + 80009cc: 4004 ands r4, r0 + 80009ce: 00e4 lsls r4, r4, #3 + 80009d0: 40a2 lsls r2, r4 + 80009d2: 0189 lsls r1, r1, #6 + 80009d4: 4029 ands r1, r5 + 80009d6: 43d2 mvns r2, r2 + 80009d8: 40a1 lsls r1, r4 + 80009da: b2c3 uxtb r3, r0 + if ((int32_t)(IRQn) >= 0) + 80009dc: 2800 cmp r0, #0 + 80009de: db0a blt.n 80009f6 + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + 80009e0: 24c0 movs r4, #192 ; 0xc0 + 80009e2: 4b0b ldr r3, [pc, #44] ; (8000a10 ) + 80009e4: 0880 lsrs r0, r0, #2 + 80009e6: 0080 lsls r0, r0, #2 + 80009e8: 18c0 adds r0, r0, r3 + 80009ea: 00a4 lsls r4, r4, #2 + 80009ec: 5903 ldr r3, [r0, r4] + 80009ee: 401a ands r2, r3 + 80009f0: 4311 orrs r1, r2 + 80009f2: 5101 str r1, [r0, r4] + /* Check the parameters */ + assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); + NVIC_SetPriority(IRQn,PreemptPriority); +} + 80009f4: bd30 pop {r4, r5, pc} + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + 80009f6: 200f movs r0, #15 + 80009f8: 4003 ands r3, r0 + 80009fa: 3b08 subs r3, #8 + 80009fc: 4805 ldr r0, [pc, #20] ; (8000a14 ) + 80009fe: 089b lsrs r3, r3, #2 + 8000a00: 009b lsls r3, r3, #2 + 8000a02: 181b adds r3, r3, r0 + 8000a04: 69d8 ldr r0, [r3, #28] + 8000a06: 4002 ands r2, r0 + 8000a08: 4311 orrs r1, r2 + 8000a0a: 61d9 str r1, [r3, #28] + 8000a0c: e7f2 b.n 80009f4 + 8000a0e: 46c0 nop ; (mov r8, r8) + 8000a10: e000e100 .word 0xe000e100 + 8000a14: e000ed00 .word 0xe000ed00 + +08000a18 : + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + 8000a18: 2280 movs r2, #128 ; 0x80 + 8000a1a: 1e43 subs r3, r0, #1 + 8000a1c: 0452 lsls r2, r2, #17 + { + return (1UL); /* Reload value impossible */ + 8000a1e: 2001 movs r0, #1 + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + 8000a20: 4293 cmp r3, r2 + 8000a22: d20d bcs.n 8000a40 + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + 8000a24: 21c0 movs r1, #192 ; 0xc0 + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + 8000a26: 4a07 ldr r2, [pc, #28] ; (8000a44 ) + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + 8000a28: 4807 ldr r0, [pc, #28] ; (8000a48 ) + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + 8000a2a: 6053 str r3, [r2, #4] + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + 8000a2c: 6a03 ldr r3, [r0, #32] + 8000a2e: 0609 lsls r1, r1, #24 + 8000a30: 021b lsls r3, r3, #8 + 8000a32: 0a1b lsrs r3, r3, #8 + 8000a34: 430b orrs r3, r1 + 8000a36: 6203 str r3, [r0, #32] + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + 8000a38: 2000 movs r0, #0 + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + 8000a3a: 2307 movs r3, #7 + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + 8000a3c: 6090 str r0, [r2, #8] + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + 8000a3e: 6013 str r3, [r2, #0] + * - 1 Function failed. + */ +uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) +{ + return SysTick_Config(TicksNumb); +} + 8000a40: 4770 bx lr + 8000a42: 46c0 nop ; (mov r8, r8) + 8000a44: e000e010 .word 0xe000e010 + 8000a48: e000ed00 .word 0xe000ed00 + +08000a4c : + uint32_t sysclockfreq; + + tmpreg = RCC->CFGR; + + /* Get SYSCLK source -------------------------------------------------------*/ + switch (tmpreg & RCC_CFGR_SWS) + 8000a4c: 220c movs r2, #12 + tmpreg = RCC->CFGR; + 8000a4e: 4b1d ldr r3, [pc, #116] ; (8000ac4 ) +{ + 8000a50: b570 push {r4, r5, r6, lr} + tmpreg = RCC->CFGR; + 8000a52: 68dc ldr r4, [r3, #12] + switch (tmpreg & RCC_CFGR_SWS) + 8000a54: 4022 ands r2, r4 + 8000a56: 2a08 cmp r2, #8 + 8000a58: d031 beq.n 8000abe + 8000a5a: 2a0c cmp r2, #12 + 8000a5c: d009 beq.n 8000a72 + 8000a5e: 2a04 cmp r2, #4 + 8000a60: d125 bne.n 8000aae + { + case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */ + { + if ((RCC->CR & RCC_CR_HSIDIVF) != 0U) + 8000a62: 6818 ldr r0, [r3, #0] + { + sysclockfreq = (HSI_VALUE >> 2); + } + else + { + sysclockfreq = HSI_VALUE; + 8000a64: 4b18 ldr r3, [pc, #96] ; (8000ac8 ) + if ((RCC->CR & RCC_CR_HSIDIVF) != 0U) + 8000a66: 06c0 lsls r0, r0, #27 + sysclockfreq = HSI_VALUE; + 8000a68: 17c0 asrs r0, r0, #31 + 8000a6a: 4018 ands r0, r3 + 8000a6c: 4b17 ldr r3, [pc, #92] ; (8000acc ) + 8000a6e: 18c0 adds r0, r0, r3 + sysclockfreq = (32768U * (1UL << (msiclkrange + 1U))); + break; + } + } + return sysclockfreq; +} + 8000a70: bd70 pop {r4, r5, r6, pc} + pllm = PLLMulTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMUL) >> RCC_CFGR_PLLMUL_Pos]; + 8000a72: 02a2 lsls r2, r4, #10 + 8000a74: 4816 ldr r0, [pc, #88] ; (8000ad0 ) + 8000a76: 0f12 lsrs r2, r2, #28 + 8000a78: 5c80 ldrb r0, [r0, r2] + if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI) + 8000a7a: 2280 movs r2, #128 ; 0x80 + plld = ((uint32_t)(tmpreg & RCC_CFGR_PLLDIV) >> RCC_CFGR_PLLDIV_Pos) + 1U; + 8000a7c: 0224 lsls r4, r4, #8 + if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI) + 8000a7e: 68d9 ldr r1, [r3, #12] + plld = ((uint32_t)(tmpreg & RCC_CFGR_PLLDIV) >> RCC_CFGR_PLLDIV_Pos) + 1U; + 8000a80: 0fa4 lsrs r4, r4, #30 + if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI) + 8000a82: 0252 lsls r2, r2, #9 + plld = ((uint32_t)(tmpreg & RCC_CFGR_PLLDIV) >> RCC_CFGR_PLLDIV_Pos) + 1U; + 8000a84: 3401 adds r4, #1 + if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI) + 8000a86: 4211 tst r1, r2 + 8000a88: d009 beq.n 8000a9e + pllvco = (uint32_t)(((uint64_t)HSE_VALUE * (uint64_t)pllm) / (uint64_t)plld); + 8000a8a: 4a12 ldr r2, [pc, #72] ; (8000ad4 ) + 8000a8c: 2300 movs r3, #0 + 8000a8e: 2100 movs r1, #0 + 8000a90: f7ff fbe6 bl 8000260 <__aeabi_lmul> + 8000a94: 0022 movs r2, r4 + 8000a96: 2300 movs r3, #0 + 8000a98: f7ff fbc2 bl 8000220 <__aeabi_uldivmod> + 8000a9c: e7e8 b.n 8000a70 + if ((RCC->CR & RCC_CR_HSIDIVF) != 0U) + 8000a9e: 681a ldr r2, [r3, #0] + 8000aa0: 2310 movs r3, #16 + 8000aa2: 421a tst r2, r3 + 8000aa4: d001 beq.n 8000aaa + pllvco = (uint32_t)((((uint64_t)(HSI_VALUE >> 2)) * (uint64_t)pllm) / (uint64_t)plld); + 8000aa6: 4a0c ldr r2, [pc, #48] ; (8000ad8 ) + 8000aa8: e7f0 b.n 8000a8c + pllvco = (uint32_t)(((uint64_t)HSI_VALUE * (uint64_t)pllm) / (uint64_t)plld); + 8000aaa: 4a08 ldr r2, [pc, #32] ; (8000acc ) + 8000aac: e7ee b.n 8000a8c + sysclockfreq = (32768U * (1UL << (msiclkrange + 1U))); + 8000aae: 2080 movs r0, #128 ; 0x80 + msiclkrange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE ) >> RCC_ICSCR_MSIRANGE_Pos; + 8000ab0: 685b ldr r3, [r3, #4] + sysclockfreq = (32768U * (1UL << (msiclkrange + 1U))); + 8000ab2: 0200 lsls r0, r0, #8 + msiclkrange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE ) >> RCC_ICSCR_MSIRANGE_Pos; + 8000ab4: 041b lsls r3, r3, #16 + 8000ab6: 0f5b lsrs r3, r3, #29 + sysclockfreq = (32768U * (1UL << (msiclkrange + 1U))); + 8000ab8: 3301 adds r3, #1 + 8000aba: 4098 lsls r0, r3 + return sysclockfreq; + 8000abc: e7d8 b.n 8000a70 + switch (tmpreg & RCC_CFGR_SWS) + 8000abe: 4805 ldr r0, [pc, #20] ; (8000ad4 ) + 8000ac0: e7d6 b.n 8000a70 + 8000ac2: 46c0 nop ; (mov r8, r8) + 8000ac4: 40021000 .word 0x40021000 + 8000ac8: ff48e500 .word 0xff48e500 + 8000acc: 00f42400 .word 0x00f42400 + 8000ad0: 08001618 .word 0x08001618 + 8000ad4: 007a1200 .word 0x007a1200 + 8000ad8: 003d0900 .word 0x003d0900 + +08000adc : +{ + 8000adc: b5f0 push {r4, r5, r6, r7, lr} + 8000ade: 0005 movs r5, r0 + 8000ae0: b087 sub sp, #28 + if(RCC_OscInitStruct == NULL) + 8000ae2: 2800 cmp r0, #0 + 8000ae4: d055 beq.n 8000b92 + sysclk_source = __HAL_RCC_GET_SYSCLK_SOURCE(); + 8000ae6: 230c movs r3, #12 + 8000ae8: 4cb6 ldr r4, [pc, #728] ; (8000dc4 ) + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) + 8000aea: 6802 ldr r2, [r0, #0] + sysclk_source = __HAL_RCC_GET_SYSCLK_SOURCE(); + 8000aec: 68e6 ldr r6, [r4, #12] + pll_config = __HAL_RCC_GET_PLL_OSCSOURCE(); + 8000aee: 68e7 ldr r7, [r4, #12] + sysclk_source = __HAL_RCC_GET_SYSCLK_SOURCE(); + 8000af0: 401e ands r6, r3 + pll_config = __HAL_RCC_GET_PLL_OSCSOURCE(); + 8000af2: 2380 movs r3, #128 ; 0x80 + 8000af4: 025b lsls r3, r3, #9 + 8000af6: 401f ands r7, r3 + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) + 8000af8: 07d2 lsls r2, r2, #31 + 8000afa: d43e bmi.n 8000b7a + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) + 8000afc: 682b ldr r3, [r5, #0] + 8000afe: 079b lsls r3, r3, #30 + 8000b00: d500 bpl.n 8000b04 + 8000b02: e087 b.n 8000c14 + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI) + 8000b04: 682b ldr r3, [r5, #0] + 8000b06: 06db lsls r3, r3, #27 + 8000b08: d529 bpl.n 8000b5e + if(sysclk_source == RCC_CFGR_SWS_MSI) + 8000b0a: 2e00 cmp r6, #0 + 8000b0c: d000 beq.n 8000b10 + 8000b0e: e0e0 b.n 8000cd2 + if((__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) != 0U) && (RCC_OscInitStruct->MSIState == RCC_MSI_OFF)) + 8000b10: 6823 ldr r3, [r4, #0] + 8000b12: 059b lsls r3, r3, #22 + 8000b14: d502 bpl.n 8000b1c + 8000b16: 69ab ldr r3, [r5, #24] + 8000b18: 2b00 cmp r3, #0 + 8000b1a: d03a beq.n 8000b92 + __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange); + 8000b1c: 6862 ldr r2, [r4, #4] + 8000b1e: 49aa ldr r1, [pc, #680] ; (8000dc8 ) + 8000b20: 6a2b ldr r3, [r5, #32] + 8000b22: 400a ands r2, r1 + 8000b24: 431a orrs r2, r3 + 8000b26: 6062 str r2, [r4, #4] + __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue); + 8000b28: 6861 ldr r1, [r4, #4] + 8000b2a: 69ea ldr r2, [r5, #28] + 8000b2c: 0209 lsls r1, r1, #8 + 8000b2e: 0a09 lsrs r1, r1, #8 + 8000b30: 0612 lsls r2, r2, #24 + 8000b32: 430a orrs r2, r1 + 8000b34: 6062 str r2, [r4, #4] + SystemCoreClock = (32768U * (1UL << ((RCC_OscInitStruct->MSIClockRange >> RCC_ICSCR_MSIRANGE_Pos) + 1U))) + 8000b36: 2280 movs r2, #128 ; 0x80 + 8000b38: 0b5b lsrs r3, r3, #13 + 8000b3a: 3301 adds r3, #1 + 8000b3c: 0212 lsls r2, r2, #8 + 8000b3e: 409a lsls r2, r3 + 8000b40: 0013 movs r3, r2 + >> AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)]; + 8000b42: 68e1 ldr r1, [r4, #12] + 8000b44: 060a lsls r2, r1, #24 + 8000b46: 49a1 ldr r1, [pc, #644] ; (8000dcc ) + 8000b48: 0f12 lsrs r2, r2, #28 + 8000b4a: 5c8a ldrb r2, [r1, r2] + 8000b4c: 40d3 lsrs r3, r2 + SystemCoreClock = (32768U * (1UL << ((RCC_OscInitStruct->MSIClockRange >> RCC_ICSCR_MSIRANGE_Pos) + 1U))) + 8000b4e: 4aa0 ldr r2, [pc, #640] ; (8000dd0 ) + 8000b50: 6013 str r3, [r2, #0] + status = HAL_InitTick (uwTickPrio); + 8000b52: 4ba0 ldr r3, [pc, #640] ; (8000dd4 ) + 8000b54: 6818 ldr r0, [r3, #0] + 8000b56: f7ff fed9 bl 800090c + if(status != HAL_OK) + 8000b5a: 2800 cmp r0, #0 + 8000b5c: d130 bne.n 8000bc0 + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) + 8000b5e: 682b ldr r3, [r5, #0] + 8000b60: 071b lsls r3, r3, #28 + 8000b62: d500 bpl.n 8000b66 + 8000b64: e0ec b.n 8000d40 + if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) + 8000b66: 682b ldr r3, [r5, #0] + 8000b68: 075b lsls r3, r3, #29 + 8000b6a: d500 bpl.n 8000b6e + 8000b6c: e10e b.n 8000d8c + if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) + 8000b6e: 6a6b ldr r3, [r5, #36] ; 0x24 + 8000b70: 2b00 cmp r3, #0 + 8000b72: d000 beq.n 8000b76 + 8000b74: e195 b.n 8000ea2 + return HAL_OK; + 8000b76: 2000 movs r0, #0 + 8000b78: e022 b.n 8000bc0 + if((sysclk_source == RCC_SYSCLKSOURCE_STATUS_HSE) + 8000b7a: 2e08 cmp r6, #8 + 8000b7c: d003 beq.n 8000b86 + || ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pll_config == RCC_PLLSOURCE_HSE))) + 8000b7e: 2e0c cmp r6, #12 + 8000b80: d109 bne.n 8000b96 + 8000b82: 2f00 cmp r7, #0 + 8000b84: d007 beq.n 8000b96 + if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) + 8000b86: 6823 ldr r3, [r4, #0] + 8000b88: 039b lsls r3, r3, #14 + 8000b8a: d5b7 bpl.n 8000afc + 8000b8c: 686b ldr r3, [r5, #4] + 8000b8e: 2b00 cmp r3, #0 + 8000b90: d1b4 bne.n 8000afc + return HAL_ERROR; + 8000b92: 2001 movs r0, #1 + 8000b94: e014 b.n 8000bc0 + __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); + 8000b96: 686a ldr r2, [r5, #4] + 8000b98: 429a cmp r2, r3 + 8000b9a: d113 bne.n 8000bc4 + 8000b9c: 6822 ldr r2, [r4, #0] + 8000b9e: 4313 orrs r3, r2 + 8000ba0: 6023 str r3, [r4, #0] + tickstart = HAL_GetTick(); + 8000ba2: f7ff fef7 bl 8000994 + 8000ba6: 9001 str r0, [sp, #4] + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U) + 8000ba8: 2280 movs r2, #128 ; 0x80 + 8000baa: 6823 ldr r3, [r4, #0] + 8000bac: 0292 lsls r2, r2, #10 + 8000bae: 4213 tst r3, r2 + 8000bb0: d1a4 bne.n 8000afc + if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) + 8000bb2: f7ff feef bl 8000994 + 8000bb6: 9b01 ldr r3, [sp, #4] + 8000bb8: 1ac0 subs r0, r0, r3 + 8000bba: 2864 cmp r0, #100 ; 0x64 + 8000bbc: d9f4 bls.n 8000ba8 + return HAL_TIMEOUT; + 8000bbe: 2003 movs r0, #3 +} + 8000bc0: b007 add sp, #28 + 8000bc2: bdf0 pop {r4, r5, r6, r7, pc} + __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); + 8000bc4: 21a0 movs r1, #160 ; 0xa0 + 8000bc6: 02c9 lsls r1, r1, #11 + 8000bc8: 428a cmp r2, r1 + 8000bca: d105 bne.n 8000bd8 + 8000bcc: 2280 movs r2, #128 ; 0x80 + 8000bce: 6821 ldr r1, [r4, #0] + 8000bd0: 02d2 lsls r2, r2, #11 + 8000bd2: 430a orrs r2, r1 + 8000bd4: 6022 str r2, [r4, #0] + 8000bd6: e7e1 b.n 8000b9c + 8000bd8: 6821 ldr r1, [r4, #0] + 8000bda: 487f ldr r0, [pc, #508] ; (8000dd8 ) + 8000bdc: 4001 ands r1, r0 + 8000bde: 6021 str r1, [r4, #0] + 8000be0: 6821 ldr r1, [r4, #0] + 8000be2: 400b ands r3, r1 + 8000be4: 9305 str r3, [sp, #20] + 8000be6: 9b05 ldr r3, [sp, #20] + 8000be8: 497c ldr r1, [pc, #496] ; (8000ddc ) + 8000bea: 6823 ldr r3, [r4, #0] + 8000bec: 400b ands r3, r1 + 8000bee: 6023 str r3, [r4, #0] + if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF) + 8000bf0: 2a00 cmp r2, #0 + 8000bf2: d1d6 bne.n 8000ba2 + tickstart = HAL_GetTick(); + 8000bf4: f7ff fece bl 8000994 + 8000bf8: 9001 str r0, [sp, #4] + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) + 8000bfa: 2280 movs r2, #128 ; 0x80 + 8000bfc: 6823 ldr r3, [r4, #0] + 8000bfe: 0292 lsls r2, r2, #10 + 8000c00: 4213 tst r3, r2 + 8000c02: d100 bne.n 8000c06 + 8000c04: e77a b.n 8000afc + if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) + 8000c06: f7ff fec5 bl 8000994 + 8000c0a: 9b01 ldr r3, [sp, #4] + 8000c0c: 1ac0 subs r0, r0, r3 + 8000c0e: 2864 cmp r0, #100 ; 0x64 + 8000c10: d9f3 bls.n 8000bfa + 8000c12: e7d4 b.n 8000bbe + if((hsi_state & RCC_HSI_OUTEN) != 0U) + 8000c14: 2220 movs r2, #32 + hsi_state = RCC_OscInitStruct->HSIState; + 8000c16: 68eb ldr r3, [r5, #12] + if((hsi_state & RCC_HSI_OUTEN) != 0U) + 8000c18: 4213 tst r3, r2 + 8000c1a: d003 beq.n 8000c24 + SET_BIT(RCC->CR, RCC_CR_HSIOUTEN); + 8000c1c: 6821 ldr r1, [r4, #0] + hsi_state &= ~RCC_CR_HSIOUTEN; + 8000c1e: 4393 bics r3, r2 + SET_BIT(RCC->CR, RCC_CR_HSIOUTEN); + 8000c20: 4311 orrs r1, r2 + 8000c22: 6021 str r1, [r4, #0] + if((sysclk_source == RCC_SYSCLKSOURCE_STATUS_HSI) + 8000c24: 2e04 cmp r6, #4 + 8000c26: d003 beq.n 8000c30 + || ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pll_config == RCC_PLLSOURCE_HSI))) + 8000c28: 2e0c cmp r6, #12 + 8000c2a: d124 bne.n 8000c76 + 8000c2c: 2f00 cmp r7, #0 + 8000c2e: d122 bne.n 8000c76 + if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (hsi_state == RCC_HSI_OFF)) + 8000c30: 6822 ldr r2, [r4, #0] + 8000c32: 0752 lsls r2, r2, #29 + 8000c34: d501 bpl.n 8000c3a + 8000c36: 2b00 cmp r3, #0 + 8000c38: d0ab beq.n 8000b92 + __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); + 8000c3a: 6861 ldr r1, [r4, #4] + 8000c3c: 692a ldr r2, [r5, #16] + 8000c3e: 4868 ldr r0, [pc, #416] ; (8000de0 ) + 8000c40: 0212 lsls r2, r2, #8 + 8000c42: 4001 ands r1, r0 + 8000c44: 430a orrs r2, r1 + __HAL_RCC_HSI_CONFIG(hsi_state); + 8000c46: 2109 movs r1, #9 + __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); + 8000c48: 6062 str r2, [r4, #4] + __HAL_RCC_HSI_CONFIG(hsi_state); + 8000c4a: 6822 ldr r2, [r4, #0] + 8000c4c: 438a bics r2, r1 + 8000c4e: 4313 orrs r3, r2 + 8000c50: 6023 str r3, [r4, #0] + SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_Pos]; + 8000c52: f7ff fefb bl 8000a4c + 8000c56: 68e3 ldr r3, [r4, #12] + 8000c58: 4a5c ldr r2, [pc, #368] ; (8000dcc ) + 8000c5a: 061b lsls r3, r3, #24 + 8000c5c: 0f1b lsrs r3, r3, #28 + 8000c5e: 5cd3 ldrb r3, [r2, r3] + 8000c60: 40d8 lsrs r0, r3 + 8000c62: 4b5b ldr r3, [pc, #364] ; (8000dd0 ) + 8000c64: 6018 str r0, [r3, #0] + status = HAL_InitTick (uwTickPrio); + 8000c66: 4b5b ldr r3, [pc, #364] ; (8000dd4 ) + 8000c68: 6818 ldr r0, [r3, #0] + 8000c6a: f7ff fe4f bl 800090c + if(status != HAL_OK) + 8000c6e: 2800 cmp r0, #0 + 8000c70: d100 bne.n 8000c74 + 8000c72: e747 b.n 8000b04 + 8000c74: e7a4 b.n 8000bc0 + if(hsi_state != RCC_HSI_OFF) + 8000c76: 2b00 cmp r3, #0 + 8000c78: d019 beq.n 8000cae + __HAL_RCC_HSI_CONFIG(hsi_state); + 8000c7a: 2109 movs r1, #9 + 8000c7c: 6822 ldr r2, [r4, #0] + 8000c7e: 438a bics r2, r1 + 8000c80: 4313 orrs r3, r2 + 8000c82: 6023 str r3, [r4, #0] + tickstart = HAL_GetTick(); + 8000c84: f7ff fe86 bl 8000994 + 8000c88: 0007 movs r7, r0 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) + 8000c8a: 2204 movs r2, #4 + 8000c8c: 6823 ldr r3, [r4, #0] + 8000c8e: 4213 tst r3, r2 + 8000c90: d007 beq.n 8000ca2 + __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); + 8000c92: 6862 ldr r2, [r4, #4] + 8000c94: 692b ldr r3, [r5, #16] + 8000c96: 4952 ldr r1, [pc, #328] ; (8000de0 ) + 8000c98: 021b lsls r3, r3, #8 + 8000c9a: 400a ands r2, r1 + 8000c9c: 4313 orrs r3, r2 + 8000c9e: 6063 str r3, [r4, #4] + 8000ca0: e730 b.n 8000b04 + if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) + 8000ca2: f7ff fe77 bl 8000994 + 8000ca6: 1bc0 subs r0, r0, r7 + 8000ca8: 2802 cmp r0, #2 + 8000caa: d9ee bls.n 8000c8a + 8000cac: e787 b.n 8000bbe + __HAL_RCC_HSI_DISABLE(); + 8000cae: 2201 movs r2, #1 + 8000cb0: 6823 ldr r3, [r4, #0] + 8000cb2: 4393 bics r3, r2 + 8000cb4: 6023 str r3, [r4, #0] + tickstart = HAL_GetTick(); + 8000cb6: f7ff fe6d bl 8000994 + 8000cba: 0007 movs r7, r0 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) + 8000cbc: 2204 movs r2, #4 + 8000cbe: 6823 ldr r3, [r4, #0] + 8000cc0: 4213 tst r3, r2 + 8000cc2: d100 bne.n 8000cc6 + 8000cc4: e71e b.n 8000b04 + if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) + 8000cc6: f7ff fe65 bl 8000994 + 8000cca: 1bc0 subs r0, r0, r7 + 8000ccc: 2802 cmp r0, #2 + 8000cce: d9f5 bls.n 8000cbc + 8000cd0: e775 b.n 8000bbe + if(RCC_OscInitStruct->MSIState != RCC_MSI_OFF) + 8000cd2: 69ab ldr r3, [r5, #24] + 8000cd4: 2b00 cmp r3, #0 + 8000cd6: d020 beq.n 8000d1a + __HAL_RCC_MSI_ENABLE(); + 8000cd8: 2380 movs r3, #128 ; 0x80 + 8000cda: 6822 ldr r2, [r4, #0] + 8000cdc: 005b lsls r3, r3, #1 + 8000cde: 4313 orrs r3, r2 + 8000ce0: 6023 str r3, [r4, #0] + tickstart = HAL_GetTick(); + 8000ce2: f7ff fe57 bl 8000994 + 8000ce6: 0007 movs r7, r0 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) == 0U) + 8000ce8: 2280 movs r2, #128 ; 0x80 + 8000cea: 6823 ldr r3, [r4, #0] + 8000cec: 0092 lsls r2, r2, #2 + 8000cee: 4213 tst r3, r2 + 8000cf0: d00d beq.n 8000d0e + __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange); + 8000cf2: 6863 ldr r3, [r4, #4] + 8000cf4: 4a34 ldr r2, [pc, #208] ; (8000dc8 ) + 8000cf6: 4013 ands r3, r2 + 8000cf8: 6a2a ldr r2, [r5, #32] + 8000cfa: 4313 orrs r3, r2 + 8000cfc: 6063 str r3, [r4, #4] + __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue); + 8000cfe: 6862 ldr r2, [r4, #4] + 8000d00: 69eb ldr r3, [r5, #28] + 8000d02: 0212 lsls r2, r2, #8 + 8000d04: 061b lsls r3, r3, #24 + 8000d06: 0a12 lsrs r2, r2, #8 + 8000d08: 4313 orrs r3, r2 + 8000d0a: 6063 str r3, [r4, #4] + 8000d0c: e727 b.n 8000b5e + if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE) + 8000d0e: f7ff fe41 bl 8000994 + 8000d12: 1bc0 subs r0, r0, r7 + 8000d14: 2802 cmp r0, #2 + 8000d16: d9e7 bls.n 8000ce8 + 8000d18: e751 b.n 8000bbe + __HAL_RCC_MSI_DISABLE(); + 8000d1a: 6823 ldr r3, [r4, #0] + 8000d1c: 4a31 ldr r2, [pc, #196] ; (8000de4 ) + 8000d1e: 4013 ands r3, r2 + 8000d20: 6023 str r3, [r4, #0] + tickstart = HAL_GetTick(); + 8000d22: f7ff fe37 bl 8000994 + 8000d26: 0007 movs r7, r0 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) != 0U) + 8000d28: 2280 movs r2, #128 ; 0x80 + 8000d2a: 6823 ldr r3, [r4, #0] + 8000d2c: 0092 lsls r2, r2, #2 + 8000d2e: 4213 tst r3, r2 + 8000d30: d100 bne.n 8000d34 + 8000d32: e714 b.n 8000b5e + if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE) + 8000d34: f7ff fe2e bl 8000994 + 8000d38: 1bc0 subs r0, r0, r7 + 8000d3a: 2802 cmp r0, #2 + 8000d3c: d9f4 bls.n 8000d28 + 8000d3e: e73e b.n 8000bbe + if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF) + 8000d40: 696a ldr r2, [r5, #20] + 8000d42: 2301 movs r3, #1 + 8000d44: 2a00 cmp r2, #0 + 8000d46: d010 beq.n 8000d6a + __HAL_RCC_LSI_ENABLE(); + 8000d48: 6d22 ldr r2, [r4, #80] ; 0x50 + 8000d4a: 4313 orrs r3, r2 + 8000d4c: 6523 str r3, [r4, #80] ; 0x50 + tickstart = HAL_GetTick(); + 8000d4e: f7ff fe21 bl 8000994 + 8000d52: 0007 movs r7, r0 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == 0U) + 8000d54: 2202 movs r2, #2 + 8000d56: 6d23 ldr r3, [r4, #80] ; 0x50 + 8000d58: 4213 tst r3, r2 + 8000d5a: d000 beq.n 8000d5e + 8000d5c: e703 b.n 8000b66 + if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) + 8000d5e: f7ff fe19 bl 8000994 + 8000d62: 1bc0 subs r0, r0, r7 + 8000d64: 2802 cmp r0, #2 + 8000d66: d9f5 bls.n 8000d54 + 8000d68: e729 b.n 8000bbe + __HAL_RCC_LSI_DISABLE(); + 8000d6a: 6d22 ldr r2, [r4, #80] ; 0x50 + 8000d6c: 439a bics r2, r3 + 8000d6e: 6522 str r2, [r4, #80] ; 0x50 + tickstart = HAL_GetTick(); + 8000d70: f7ff fe10 bl 8000994 + 8000d74: 0007 movs r7, r0 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != 0U) + 8000d76: 2202 movs r2, #2 + 8000d78: 6d23 ldr r3, [r4, #80] ; 0x50 + 8000d7a: 4213 tst r3, r2 + 8000d7c: d100 bne.n 8000d80 + 8000d7e: e6f2 b.n 8000b66 + if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) + 8000d80: f7ff fe08 bl 8000994 + 8000d84: 1bc0 subs r0, r0, r7 + 8000d86: 2802 cmp r0, #2 + 8000d88: d9f5 bls.n 8000d76 + 8000d8a: e718 b.n 8000bbe + if(__HAL_RCC_PWR_IS_CLK_DISABLED()) + 8000d8c: 2380 movs r3, #128 ; 0x80 + FlagStatus pwrclkchanged = RESET; + 8000d8e: 2100 movs r1, #0 + if(__HAL_RCC_PWR_IS_CLK_DISABLED()) + 8000d90: 6ba2 ldr r2, [r4, #56] ; 0x38 + 8000d92: 055b lsls r3, r3, #21 + FlagStatus pwrclkchanged = RESET; + 8000d94: 9101 str r1, [sp, #4] + if(__HAL_RCC_PWR_IS_CLK_DISABLED()) + 8000d96: 421a tst r2, r3 + 8000d98: d104 bne.n 8000da4 + __HAL_RCC_PWR_CLK_ENABLE(); + 8000d9a: 6ba2 ldr r2, [r4, #56] ; 0x38 + 8000d9c: 4313 orrs r3, r2 + 8000d9e: 63a3 str r3, [r4, #56] ; 0x38 + pwrclkchanged = SET; + 8000da0: 2301 movs r3, #1 + 8000da2: 9301 str r3, [sp, #4] + if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) + 8000da4: 2280 movs r2, #128 ; 0x80 + 8000da6: 4f10 ldr r7, [pc, #64] ; (8000de8 ) + 8000da8: 0052 lsls r2, r2, #1 + 8000daa: 683b ldr r3, [r7, #0] + 8000dac: 4213 tst r3, r2 + 8000dae: d01d beq.n 8000dec + __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); + 8000db0: 2280 movs r2, #128 ; 0x80 + 8000db2: 68ab ldr r3, [r5, #8] + 8000db4: 0052 lsls r2, r2, #1 + 8000db6: 4293 cmp r3, r2 + 8000db8: d12e bne.n 8000e18 + 8000dba: 6d22 ldr r2, [r4, #80] ; 0x50 + 8000dbc: 4313 orrs r3, r2 + 8000dbe: 6523 str r3, [r4, #80] ; 0x50 + 8000dc0: e04f b.n 8000e62 + 8000dc2: 46c0 nop ; (mov r8, r8) + 8000dc4: 40021000 .word 0x40021000 + 8000dc8: ffff1fff .word 0xffff1fff + 8000dcc: 08001600 .word 0x08001600 + 8000dd0: 20000000 .word 0x20000000 + 8000dd4: 20000008 .word 0x20000008 + 8000dd8: fffeffff .word 0xfffeffff + 8000ddc: fffbffff .word 0xfffbffff + 8000de0: ffffe0ff .word 0xffffe0ff + 8000de4: fffffeff .word 0xfffffeff + 8000de8: 40007000 .word 0x40007000 + SET_BIT(PWR->CR, PWR_CR_DBP); + 8000dec: 2280 movs r2, #128 ; 0x80 + 8000dee: 683b ldr r3, [r7, #0] + 8000df0: 0052 lsls r2, r2, #1 + 8000df2: 4313 orrs r3, r2 + 8000df4: 603b str r3, [r7, #0] + tickstart = HAL_GetTick(); + 8000df6: f7ff fdcd bl 8000994 + while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) + 8000dfa: 2380 movs r3, #128 ; 0x80 + 8000dfc: 005b lsls r3, r3, #1 + tickstart = HAL_GetTick(); + 8000dfe: 9002 str r0, [sp, #8] + while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) + 8000e00: 9303 str r3, [sp, #12] + 8000e02: 683b ldr r3, [r7, #0] + 8000e04: 9a03 ldr r2, [sp, #12] + 8000e06: 4213 tst r3, r2 + 8000e08: d1d2 bne.n 8000db0 + if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) + 8000e0a: f7ff fdc3 bl 8000994 + 8000e0e: 9b02 ldr r3, [sp, #8] + 8000e10: 1ac0 subs r0, r0, r3 + 8000e12: 2864 cmp r0, #100 ; 0x64 + 8000e14: d9f5 bls.n 8000e02 + 8000e16: e6d2 b.n 8000bbe + __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); + 8000e18: 2b00 cmp r3, #0 + 8000e1a: d116 bne.n 8000e4a + 8000e1c: 6d23 ldr r3, [r4, #80] ; 0x50 + 8000e1e: 4a51 ldr r2, [pc, #324] ; (8000f64 ) + 8000e20: 4013 ands r3, r2 + 8000e22: 6523 str r3, [r4, #80] ; 0x50 + 8000e24: 6d23 ldr r3, [r4, #80] ; 0x50 + 8000e26: 4a50 ldr r2, [pc, #320] ; (8000f68 ) + 8000e28: 4013 ands r3, r2 + 8000e2a: 6523 str r3, [r4, #80] ; 0x50 + tickstart = HAL_GetTick(); + 8000e2c: f7ff fdb2 bl 8000994 + 8000e30: 0007 movs r7, r0 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != 0U) + 8000e32: 2280 movs r2, #128 ; 0x80 + 8000e34: 6d23 ldr r3, [r4, #80] ; 0x50 + 8000e36: 0092 lsls r2, r2, #2 + 8000e38: 4213 tst r3, r2 + 8000e3a: d01a beq.n 8000e72 + if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) + 8000e3c: f7ff fdaa bl 8000994 + 8000e40: 4b4a ldr r3, [pc, #296] ; (8000f6c ) + 8000e42: 1bc0 subs r0, r0, r7 + 8000e44: 4298 cmp r0, r3 + 8000e46: d9f4 bls.n 8000e32 + 8000e48: e6b9 b.n 8000bbe + __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); + 8000e4a: 21a0 movs r1, #160 ; 0xa0 + 8000e4c: 00c9 lsls r1, r1, #3 + 8000e4e: 428b cmp r3, r1 + 8000e50: d118 bne.n 8000e84 + 8000e52: 2380 movs r3, #128 ; 0x80 + 8000e54: 6d21 ldr r1, [r4, #80] ; 0x50 + 8000e56: 00db lsls r3, r3, #3 + 8000e58: 430b orrs r3, r1 + 8000e5a: 6523 str r3, [r4, #80] ; 0x50 + 8000e5c: 6d23 ldr r3, [r4, #80] ; 0x50 + 8000e5e: 431a orrs r2, r3 + 8000e60: 6522 str r2, [r4, #80] ; 0x50 + tickstart = HAL_GetTick(); + 8000e62: f7ff fd97 bl 8000994 + 8000e66: 0007 movs r7, r0 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U) + 8000e68: 2280 movs r2, #128 ; 0x80 + 8000e6a: 6d23 ldr r3, [r4, #80] ; 0x50 + 8000e6c: 0092 lsls r2, r2, #2 + 8000e6e: 4213 tst r3, r2 + 8000e70: d010 beq.n 8000e94 + if(pwrclkchanged == SET) + 8000e72: 9b01 ldr r3, [sp, #4] + 8000e74: 2b01 cmp r3, #1 + 8000e76: d000 beq.n 8000e7a + 8000e78: e679 b.n 8000b6e + __HAL_RCC_PWR_CLK_DISABLE(); + 8000e7a: 6ba3 ldr r3, [r4, #56] ; 0x38 + 8000e7c: 4a3c ldr r2, [pc, #240] ; (8000f70 ) + 8000e7e: 4013 ands r3, r2 + 8000e80: 63a3 str r3, [r4, #56] ; 0x38 + 8000e82: e674 b.n 8000b6e + __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); + 8000e84: 6d23 ldr r3, [r4, #80] ; 0x50 + 8000e86: 4a37 ldr r2, [pc, #220] ; (8000f64 ) + 8000e88: 4013 ands r3, r2 + 8000e8a: 6523 str r3, [r4, #80] ; 0x50 + 8000e8c: 6d23 ldr r3, [r4, #80] ; 0x50 + 8000e8e: 4a36 ldr r2, [pc, #216] ; (8000f68 ) + 8000e90: 4013 ands r3, r2 + 8000e92: e794 b.n 8000dbe + if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) + 8000e94: f7ff fd7e bl 8000994 + 8000e98: 4b34 ldr r3, [pc, #208] ; (8000f6c ) + 8000e9a: 1bc0 subs r0, r0, r7 + 8000e9c: 4298 cmp r0, r3 + 8000e9e: d9e3 bls.n 8000e68 + 8000ea0: e68d b.n 8000bbe + if(sysclk_source != RCC_SYSCLKSOURCE_STATUS_PLLCLK) + 8000ea2: 2e0c cmp r6, #12 + 8000ea4: d043 beq.n 8000f2e + if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) + 8000ea6: 4a33 ldr r2, [pc, #204] ; (8000f74 ) + 8000ea8: 2b02 cmp r3, #2 + 8000eaa: d12e bne.n 8000f0a + __HAL_RCC_PLL_DISABLE(); + 8000eac: 6823 ldr r3, [r4, #0] + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) + 8000eae: 2780 movs r7, #128 ; 0x80 + __HAL_RCC_PLL_DISABLE(); + 8000eb0: 4013 ands r3, r2 + 8000eb2: 6023 str r3, [r4, #0] + tickstart = HAL_GetTick(); + 8000eb4: f7ff fd6e bl 8000994 + 8000eb8: 0006 movs r6, r0 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) + 8000eba: 04bf lsls r7, r7, #18 + 8000ebc: 6823 ldr r3, [r4, #0] + 8000ebe: 423b tst r3, r7 + 8000ec0: d11d bne.n 8000efe + __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, + 8000ec2: 6ae9 ldr r1, [r5, #44] ; 0x2c + 8000ec4: 6aab ldr r3, [r5, #40] ; 0x28 + 8000ec6: 68e2 ldr r2, [r4, #12] + 8000ec8: 430b orrs r3, r1 + 8000eca: 492b ldr r1, [pc, #172] ; (8000f78 ) + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U) + 8000ecc: 2680 movs r6, #128 ; 0x80 + __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, + 8000ece: 400a ands r2, r1 + 8000ed0: 4313 orrs r3, r2 + 8000ed2: 6b2a ldr r2, [r5, #48] ; 0x30 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U) + 8000ed4: 04b6 lsls r6, r6, #18 + __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, + 8000ed6: 4313 orrs r3, r2 + 8000ed8: 60e3 str r3, [r4, #12] + __HAL_RCC_PLL_ENABLE(); + 8000eda: 2380 movs r3, #128 ; 0x80 + 8000edc: 6822 ldr r2, [r4, #0] + 8000ede: 045b lsls r3, r3, #17 + 8000ee0: 4313 orrs r3, r2 + 8000ee2: 6023 str r3, [r4, #0] + tickstart = HAL_GetTick(); + 8000ee4: f7ff fd56 bl 8000994 + 8000ee8: 0005 movs r5, r0 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U) + 8000eea: 6823 ldr r3, [r4, #0] + 8000eec: 4233 tst r3, r6 + 8000eee: d000 beq.n 8000ef2 + 8000ef0: e641 b.n 8000b76 + if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) + 8000ef2: f7ff fd4f bl 8000994 + 8000ef6: 1b40 subs r0, r0, r5 + 8000ef8: 2802 cmp r0, #2 + 8000efa: d9f6 bls.n 8000eea + 8000efc: e65f b.n 8000bbe + if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) + 8000efe: f7ff fd49 bl 8000994 + 8000f02: 1b80 subs r0, r0, r6 + 8000f04: 2802 cmp r0, #2 + 8000f06: d9d9 bls.n 8000ebc + 8000f08: e659 b.n 8000bbe + __HAL_RCC_PLL_DISABLE(); + 8000f0a: 6823 ldr r3, [r4, #0] + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) + 8000f0c: 2680 movs r6, #128 ; 0x80 + __HAL_RCC_PLL_DISABLE(); + 8000f0e: 4013 ands r3, r2 + 8000f10: 6023 str r3, [r4, #0] + tickstart = HAL_GetTick(); + 8000f12: f7ff fd3f bl 8000994 + 8000f16: 0005 movs r5, r0 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) + 8000f18: 04b6 lsls r6, r6, #18 + 8000f1a: 6823 ldr r3, [r4, #0] + 8000f1c: 4233 tst r3, r6 + 8000f1e: d100 bne.n 8000f22 + 8000f20: e629 b.n 8000b76 + if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) + 8000f22: f7ff fd37 bl 8000994 + 8000f26: 1b40 subs r0, r0, r5 + 8000f28: 2802 cmp r0, #2 + 8000f2a: d9f6 bls.n 8000f1a + 8000f2c: e647 b.n 8000bbe + return HAL_ERROR; + 8000f2e: 0018 movs r0, r3 + if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) + 8000f30: 2b01 cmp r3, #1 + 8000f32: d100 bne.n 8000f36 + 8000f34: e644 b.n 8000bc0 + if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || + 8000f36: 2280 movs r2, #128 ; 0x80 + pll_config = RCC->CFGR; + 8000f38: 68e3 ldr r3, [r4, #12] + if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || + 8000f3a: 6aa9 ldr r1, [r5, #40] ; 0x28 + 8000f3c: 0252 lsls r2, r2, #9 + 8000f3e: 401a ands r2, r3 + 8000f40: 428a cmp r2, r1 + 8000f42: d000 beq.n 8000f46 + 8000f44: e625 b.n 8000b92 + (READ_BIT(pll_config, RCC_CFGR_PLLMUL) != RCC_OscInitStruct->PLL.PLLMUL) || + 8000f46: 22f0 movs r2, #240 ; 0xf0 + if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || + 8000f48: 6ae9 ldr r1, [r5, #44] ; 0x2c + (READ_BIT(pll_config, RCC_CFGR_PLLMUL) != RCC_OscInitStruct->PLL.PLLMUL) || + 8000f4a: 0392 lsls r2, r2, #14 + 8000f4c: 401a ands r2, r3 + if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || + 8000f4e: 428a cmp r2, r1 + 8000f50: d000 beq.n 8000f54 + 8000f52: e61e b.n 8000b92 + (READ_BIT(pll_config, RCC_CFGR_PLLDIV) != RCC_OscInitStruct->PLL.PLLDIV)) + 8000f54: 22c0 movs r2, #192 ; 0xc0 + 8000f56: 0412 lsls r2, r2, #16 + 8000f58: 4013 ands r3, r2 + (READ_BIT(pll_config, RCC_CFGR_PLLMUL) != RCC_OscInitStruct->PLL.PLLMUL) || + 8000f5a: 6b2a ldr r2, [r5, #48] ; 0x30 + 8000f5c: 4293 cmp r3, r2 + 8000f5e: d100 bne.n 8000f62 + 8000f60: e609 b.n 8000b76 + 8000f62: e616 b.n 8000b92 + 8000f64: fffffeff .word 0xfffffeff + 8000f68: fffffbff .word 0xfffffbff + 8000f6c: 00001388 .word 0x00001388 + 8000f70: efffffff .word 0xefffffff + 8000f74: feffffff .word 0xfeffffff + 8000f78: ff02ffff .word 0xff02ffff + +08000f7c : +{ + 8000f7c: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr} + 8000f7e: 1e04 subs r4, r0, #0 + 8000f80: 9101 str r1, [sp, #4] + if(RCC_ClkInitStruct == NULL) + 8000f82: d101 bne.n 8000f88 + return HAL_ERROR; + 8000f84: 2001 movs r0, #1 +} + 8000f86: bdfe pop {r1, r2, r3, r4, r5, r6, r7, pc} + if(FLatency > __HAL_FLASH_GET_LATENCY()) + 8000f88: 2601 movs r6, #1 + 8000f8a: 4d5b ldr r5, [pc, #364] ; (80010f8 ) + 8000f8c: 9a01 ldr r2, [sp, #4] + 8000f8e: 682b ldr r3, [r5, #0] + 8000f90: 4033 ands r3, r6 + 8000f92: 4293 cmp r3, r2 + 8000f94: d331 bcc.n 8000ffa + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) + 8000f96: 6822 ldr r2, [r4, #0] + 8000f98: 0793 lsls r3, r2, #30 + 8000f9a: d443 bmi.n 8001024 + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) + 8000f9c: 07d3 lsls r3, r2, #31 + 8000f9e: d449 bmi.n 8001034 + if(FLatency < __HAL_FLASH_GET_LATENCY()) + 8000fa0: 2601 movs r6, #1 + 8000fa2: 682b ldr r3, [r5, #0] + 8000fa4: 9a01 ldr r2, [sp, #4] + 8000fa6: 4033 ands r3, r6 + 8000fa8: 4293 cmp r3, r2 + 8000faa: d909 bls.n 8000fc0 + __HAL_FLASH_SET_LATENCY(FLatency); + 8000fac: 682b ldr r3, [r5, #0] + 8000fae: 43b3 bics r3, r6 + 8000fb0: 602b str r3, [r5, #0] + tickstart = HAL_GetTick(); + 8000fb2: f7ff fcef bl 8000994 + 8000fb6: 0007 movs r7, r0 + while (__HAL_FLASH_GET_LATENCY() != FLatency) + 8000fb8: 682b ldr r3, [r5, #0] + 8000fba: 4233 tst r3, r6 + 8000fbc: d000 beq.n 8000fc0 + 8000fbe: e08c b.n 80010da + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) + 8000fc0: 6822 ldr r2, [r4, #0] + 8000fc2: 4d4e ldr r5, [pc, #312] ; (80010fc ) + 8000fc4: 0753 lsls r3, r2, #29 + 8000fc6: d500 bpl.n 8000fca + 8000fc8: e08f b.n 80010ea + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) + 8000fca: 0713 lsls r3, r2, #28 + 8000fcc: d506 bpl.n 8000fdc + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3)); + 8000fce: 68ea ldr r2, [r5, #12] + 8000fd0: 6923 ldr r3, [r4, #16] + 8000fd2: 494b ldr r1, [pc, #300] ; (8001100 ) + 8000fd4: 00db lsls r3, r3, #3 + 8000fd6: 400a ands r2, r1 + 8000fd8: 4313 orrs r3, r2 + 8000fda: 60eb str r3, [r5, #12] + SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_Pos]; + 8000fdc: f7ff fd36 bl 8000a4c + 8000fe0: 68eb ldr r3, [r5, #12] + 8000fe2: 4a48 ldr r2, [pc, #288] ; (8001104 ) + 8000fe4: 061b lsls r3, r3, #24 + 8000fe6: 0f1b lsrs r3, r3, #28 + 8000fe8: 5cd3 ldrb r3, [r2, r3] + 8000fea: 40d8 lsrs r0, r3 + 8000fec: 4b46 ldr r3, [pc, #280] ; (8001108 ) + 8000fee: 6018 str r0, [r3, #0] + status = HAL_InitTick(uwTickPrio); + 8000ff0: 4b46 ldr r3, [pc, #280] ; (800110c ) + 8000ff2: 6818 ldr r0, [r3, #0] + 8000ff4: f7ff fc8a bl 800090c + if(status != HAL_OK) + 8000ff8: e7c5 b.n 8000f86 + __HAL_FLASH_SET_LATENCY(FLatency); + 8000ffa: 682b ldr r3, [r5, #0] + 8000ffc: 9a01 ldr r2, [sp, #4] + 8000ffe: 43b3 bics r3, r6 + 8001000: 4313 orrs r3, r2 + 8001002: 602b str r3, [r5, #0] + tickstart = HAL_GetTick(); + 8001004: f7ff fcc6 bl 8000994 + 8001008: 0007 movs r7, r0 + while (__HAL_FLASH_GET_LATENCY() != FLatency) + 800100a: 682b ldr r3, [r5, #0] + 800100c: 9a01 ldr r2, [sp, #4] + 800100e: 4033 ands r3, r6 + 8001010: 4293 cmp r3, r2 + 8001012: d0c0 beq.n 8000f96 + if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) + 8001014: f7ff fcbe bl 8000994 + 8001018: 4b3d ldr r3, [pc, #244] ; (8001110 ) + 800101a: 1bc0 subs r0, r0, r7 + 800101c: 4298 cmp r0, r3 + 800101e: d9f4 bls.n 800100a + return HAL_TIMEOUT; + 8001020: 2003 movs r0, #3 + 8001022: e7b0 b.n 8000f86 + MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); + 8001024: 20f0 movs r0, #240 ; 0xf0 + 8001026: 4935 ldr r1, [pc, #212] ; (80010fc ) + 8001028: 68cb ldr r3, [r1, #12] + 800102a: 4383 bics r3, r0 + 800102c: 68a0 ldr r0, [r4, #8] + 800102e: 4303 orrs r3, r0 + 8001030: 60cb str r3, [r1, #12] + 8001032: e7b3 b.n 8000f9c + if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) + 8001034: 4e31 ldr r6, [pc, #196] ; (80010fc ) + 8001036: 6862 ldr r2, [r4, #4] + if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U) + 8001038: 6833 ldr r3, [r6, #0] + if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) + 800103a: 2a02 cmp r2, #2 + 800103c: d118 bne.n 8001070 + if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U) + 800103e: 039b lsls r3, r3, #14 + 8001040: d5a0 bpl.n 8000f84 + __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource); + 8001042: 2103 movs r1, #3 + 8001044: 68f3 ldr r3, [r6, #12] + 8001046: 438b bics r3, r1 + 8001048: 4313 orrs r3, r2 + 800104a: 60f3 str r3, [r6, #12] + tickstart = HAL_GetTick(); + 800104c: f7ff fca2 bl 8000994 + if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) + 8001050: 6863 ldr r3, [r4, #4] + tickstart = HAL_GetTick(); + 8001052: 0007 movs r7, r0 + if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) + 8001054: 2b02 cmp r3, #2 + 8001056: d118 bne.n 800108a + while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE) + 8001058: 220c movs r2, #12 + 800105a: 68f3 ldr r3, [r6, #12] + 800105c: 4013 ands r3, r2 + 800105e: 2b08 cmp r3, #8 + 8001060: d09e beq.n 8000fa0 + if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) + 8001062: f7ff fc97 bl 8000994 + 8001066: 4b2a ldr r3, [pc, #168] ; (8001110 ) + 8001068: 1bc0 subs r0, r0, r7 + 800106a: 4298 cmp r0, r3 + 800106c: d9f4 bls.n 8001058 + 800106e: e7d7 b.n 8001020 + else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) + 8001070: 2a03 cmp r2, #3 + 8001072: d102 bne.n 800107a + if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U) + 8001074: 019b lsls r3, r3, #6 + 8001076: d4e4 bmi.n 8001042 + 8001078: e784 b.n 8000f84 + else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI) + 800107a: 2a01 cmp r2, #1 + 800107c: d102 bne.n 8001084 + if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) + 800107e: 075b lsls r3, r3, #29 + 8001080: d4df bmi.n 8001042 + 8001082: e77f b.n 8000f84 + if(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) == 0U) + 8001084: 059b lsls r3, r3, #22 + 8001086: d4dc bmi.n 8001042 + 8001088: e77c b.n 8000f84 + else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) + 800108a: 2b03 cmp r3, #3 + 800108c: d10b bne.n 80010a6 + while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) + 800108e: 220c movs r2, #12 + 8001090: 68f3 ldr r3, [r6, #12] + 8001092: 4013 ands r3, r2 + 8001094: 4293 cmp r3, r2 + 8001096: d083 beq.n 8000fa0 + if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) + 8001098: f7ff fc7c bl 8000994 + 800109c: 4b1c ldr r3, [pc, #112] ; (8001110 ) + 800109e: 1bc0 subs r0, r0, r7 + 80010a0: 4298 cmp r0, r3 + 80010a2: d9f4 bls.n 800108e + 80010a4: e7bc b.n 8001020 + else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI) + 80010a6: 2b01 cmp r3, #1 + 80010a8: d011 beq.n 80010ce + while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_MSI) + 80010aa: 220c movs r2, #12 + 80010ac: 68f3 ldr r3, [r6, #12] + 80010ae: 4213 tst r3, r2 + 80010b0: d100 bne.n 80010b4 + 80010b2: e775 b.n 8000fa0 + if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) + 80010b4: f7ff fc6e bl 8000994 + 80010b8: 4b15 ldr r3, [pc, #84] ; (8001110 ) + 80010ba: 1bc0 subs r0, r0, r7 + 80010bc: 4298 cmp r0, r3 + 80010be: d9f4 bls.n 80010aa + 80010c0: e7ae b.n 8001020 + if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) + 80010c2: f7ff fc67 bl 8000994 + 80010c6: 4b12 ldr r3, [pc, #72] ; (8001110 ) + 80010c8: 1bc0 subs r0, r0, r7 + 80010ca: 4298 cmp r0, r3 + 80010cc: d8a8 bhi.n 8001020 + while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI) + 80010ce: 220c movs r2, #12 + 80010d0: 68f3 ldr r3, [r6, #12] + 80010d2: 4013 ands r3, r2 + 80010d4: 2b04 cmp r3, #4 + 80010d6: d1f4 bne.n 80010c2 + 80010d8: e762 b.n 8000fa0 + if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) + 80010da: f7ff fc5b bl 8000994 + 80010de: 4b0c ldr r3, [pc, #48] ; (8001110 ) + 80010e0: 1bc0 subs r0, r0, r7 + 80010e2: 4298 cmp r0, r3 + 80010e4: d800 bhi.n 80010e8 + 80010e6: e767 b.n 8000fb8 + 80010e8: e79a b.n 8001020 + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider); + 80010ea: 68eb ldr r3, [r5, #12] + 80010ec: 4909 ldr r1, [pc, #36] ; (8001114 ) + 80010ee: 400b ands r3, r1 + 80010f0: 68e1 ldr r1, [r4, #12] + 80010f2: 430b orrs r3, r1 + 80010f4: 60eb str r3, [r5, #12] + 80010f6: e768 b.n 8000fca + 80010f8: 40022000 .word 0x40022000 + 80010fc: 40021000 .word 0x40021000 + 8001100: ffffc7ff .word 0xffffc7ff + 8001104: 08001600 .word 0x08001600 + 8001108: 20000000 .word 0x20000000 + 800110c: 20000008 .word 0x20000008 + 8001110: 00001388 .word 0x00001388 + 8001114: fffff8ff .word 0xfffff8ff + +08001118 : + + /* Check the parameters */ + assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); + + /*------------------------------- RTC/LCD Configuration ------------------------*/ + if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) + 8001118: 6803 ldr r3, [r0, #0] +{ + 800111a: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr} + 800111c: 0005 movs r5, r0 + if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) + 800111e: 069b lsls r3, r3, #26 + 8001120: d53d bpl.n 800119e +#endif /* LCD */ + + /* As soon as function is called to change RTC clock source, activation of the + power domain is done. */ + /* Requires to enable write access to Backup Domain of necessary */ + if(__HAL_RCC_PWR_IS_CLK_DISABLED()) + 8001122: 2380 movs r3, #128 ; 0x80 + FlagStatus pwrclkchanged = RESET; + 8001124: 2100 movs r1, #0 + if(__HAL_RCC_PWR_IS_CLK_DISABLED()) + 8001126: 4c50 ldr r4, [pc, #320] ; (8001268 ) + 8001128: 055b lsls r3, r3, #21 + 800112a: 6ba2 ldr r2, [r4, #56] ; 0x38 + FlagStatus pwrclkchanged = RESET; + 800112c: 9100 str r1, [sp, #0] + if(__HAL_RCC_PWR_IS_CLK_DISABLED()) + 800112e: 421a tst r2, r3 + 8001130: d104 bne.n 800113c + { + __HAL_RCC_PWR_CLK_ENABLE(); + 8001132: 6ba2 ldr r2, [r4, #56] ; 0x38 + 8001134: 4313 orrs r3, r2 + 8001136: 63a3 str r3, [r4, #56] ; 0x38 + pwrclkchanged = SET; + 8001138: 2301 movs r3, #1 + 800113a: 9300 str r3, [sp, #0] + } + + if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) + 800113c: 2780 movs r7, #128 ; 0x80 + 800113e: 4e4b ldr r6, [pc, #300] ; (800126c ) + 8001140: 007f lsls r7, r7, #1 + 8001142: 6833 ldr r3, [r6, #0] + 8001144: 423b tst r3, r7 + 8001146: d051 beq.n 80011ec + } + } + + /* Check if user wants to change HSE RTC prescaler whereas HSE is enabled */ + temp_reg = (RCC->CR & RCC_CR_RTCPRE); + if ((temp_reg != (PeriphClkInit->RTCClockSelection & RCC_CR_RTCPRE)) + 8001148: 686b ldr r3, [r5, #4] + 800114a: 22c0 movs r2, #192 ; 0xc0 + 800114c: 20c0 movs r0, #192 ; 0xc0 + 800114e: 001e movs r6, r3 + temp_reg = (RCC->CR & RCC_CR_RTCPRE); + 8001150: 6821 ldr r1, [r4, #0] + if ((temp_reg != (PeriphClkInit->RTCClockSelection & RCC_CR_RTCPRE)) + 8001152: 0292 lsls r2, r2, #10 + 8001154: 0380 lsls r0, r0, #14 + 8001156: 0017 movs r7, r2 + 8001158: 4016 ands r6, r2 + 800115a: 4003 ands r3, r0 + temp_reg = (RCC->CR & RCC_CR_RTCPRE); + 800115c: 4001 ands r1, r0 + if ((temp_reg != (PeriphClkInit->RTCClockSelection & RCC_CR_RTCPRE)) + 800115e: 428b cmp r3, r1 + 8001160: d155 bne.n 800120e + } + } + } + + /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */ + temp_reg = (RCC->CSR & RCC_CSR_RTCSEL); + 8001162: 6d23 ldr r3, [r4, #80] ; 0x50 + 8001164: 001a movs r2, r3 + 8001166: 403a ands r2, r7 + + if((temp_reg != 0x00000000U) && (((temp_reg != (PeriphClkInit->RTCClockSelection & RCC_CSR_RTCSEL)) \ + 8001168: 423b tst r3, r7 + 800116a: d157 bne.n 800121c + return HAL_TIMEOUT; + } + } + } + } + __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); + 800116c: 6869 ldr r1, [r5, #4] + 800116e: 23c0 movs r3, #192 ; 0xc0 + 8001170: 000a movs r2, r1 + 8001172: 029b lsls r3, r3, #10 + 8001174: 401a ands r2, r3 + 8001176: 429a cmp r2, r3 + 8001178: d107 bne.n 800118a + 800117a: 6823 ldr r3, [r4, #0] + 800117c: 483c ldr r0, [pc, #240] ; (8001270 ) + 800117e: 4003 ands r3, r0 + 8001180: 20c0 movs r0, #192 ; 0xc0 + 8001182: 0380 lsls r0, r0, #14 + 8001184: 4001 ands r1, r0 + 8001186: 430b orrs r3, r1 + 8001188: 6023 str r3, [r4, #0] + 800118a: 6d23 ldr r3, [r4, #80] ; 0x50 + 800118c: 431a orrs r2, r3 + + /* Require to disable power clock if necessary */ + if(pwrclkchanged == SET) + 800118e: 9b00 ldr r3, [sp, #0] + __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); + 8001190: 6522 str r2, [r4, #80] ; 0x50 + if(pwrclkchanged == SET) + 8001192: 2b01 cmp r3, #1 + 8001194: d103 bne.n 800119e + { + __HAL_RCC_PWR_CLK_DISABLE(); + 8001196: 6ba3 ldr r3, [r4, #56] ; 0x38 + 8001198: 4a36 ldr r2, [pc, #216] ; (8001274 ) + 800119a: 4013 ands r3, r2 + 800119c: 63a3 str r3, [r4, #56] ; 0x38 + __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection); + } +#endif /* RCC_CCIPR_USART1SEL */ + + /*----------------------------- USART2 Configuration --------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) + 800119e: 682a ldr r2, [r5, #0] + 80011a0: 0793 lsls r3, r2, #30 + 80011a2: d506 bpl.n 80011b2 + { + /* Check the parameters */ + assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection)); + + /* Configure the USART2 clock source */ + __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection); + 80011a4: 200c movs r0, #12 + 80011a6: 4930 ldr r1, [pc, #192] ; (8001268 ) + 80011a8: 6ccb ldr r3, [r1, #76] ; 0x4c + 80011aa: 4383 bics r3, r0 + 80011ac: 68a8 ldr r0, [r5, #8] + 80011ae: 4303 orrs r3, r0 + 80011b0: 64cb str r3, [r1, #76] ; 0x4c + } + + /*------------------------------ LPUART1 Configuration ------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) + 80011b2: 0753 lsls r3, r2, #29 + 80011b4: d506 bpl.n 80011c4 + { + /* Check the parameters */ + assert_param(IS_RCC_LPUART1CLKSOURCE(PeriphClkInit->Lpuart1ClockSelection)); + + /* Configure the LPUAR1 clock source */ + __HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection); + 80011b6: 492c ldr r1, [pc, #176] ; (8001268 ) + 80011b8: 482f ldr r0, [pc, #188] ; (8001278 ) + 80011ba: 6ccb ldr r3, [r1, #76] ; 0x4c + 80011bc: 4003 ands r3, r0 + 80011be: 68e8 ldr r0, [r5, #12] + 80011c0: 4303 orrs r3, r0 + 80011c2: 64cb str r3, [r1, #76] ; 0x4c + } + + /*------------------------------ I2C1 Configuration ------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) + 80011c4: 0713 lsls r3, r2, #28 + 80011c6: d506 bpl.n 80011d6 + { + /* Check the parameters */ + assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection)); + + /* Configure the I2C1 clock source */ + __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection); + 80011c8: 4927 ldr r1, [pc, #156] ; (8001268 ) + 80011ca: 482c ldr r0, [pc, #176] ; (800127c ) + 80011cc: 6ccb ldr r3, [r1, #76] ; 0x4c + 80011ce: 4003 ands r3, r0 + 80011d0: 6928 ldr r0, [r5, #16] + 80011d2: 4303 orrs r3, r0 + 80011d4: 64cb str r3, [r1, #76] ; 0x4c + { + assert_param(IS_RCC_LPTIMCLK(PeriphClkInit->LptimClockSelection)); + __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->LptimClockSelection); + } + + return HAL_OK; + 80011d6: 2000 movs r0, #0 + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == (RCC_PERIPHCLK_LPTIM1)) + 80011d8: 0613 lsls r3, r2, #24 + 80011da: d517 bpl.n 800120c + __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->LptimClockSelection); + 80011dc: 4a22 ldr r2, [pc, #136] ; (8001268 ) + 80011de: 4928 ldr r1, [pc, #160] ; (8001280 ) + 80011e0: 6cd3 ldr r3, [r2, #76] ; 0x4c + 80011e2: 400b ands r3, r1 + 80011e4: 6969 ldr r1, [r5, #20] + 80011e6: 430b orrs r3, r1 + 80011e8: 64d3 str r3, [r2, #76] ; 0x4c + 80011ea: e00f b.n 800120c + SET_BIT(PWR->CR, PWR_CR_DBP); + 80011ec: 6833 ldr r3, [r6, #0] + 80011ee: 433b orrs r3, r7 + 80011f0: 6033 str r3, [r6, #0] + tickstart = HAL_GetTick(); + 80011f2: f7ff fbcf bl 8000994 + 80011f6: 9001 str r0, [sp, #4] + while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) + 80011f8: 6833 ldr r3, [r6, #0] + 80011fa: 423b tst r3, r7 + 80011fc: d1a4 bne.n 8001148 + if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) + 80011fe: f7ff fbc9 bl 8000994 + 8001202: 9b01 ldr r3, [sp, #4] + 8001204: 1ac0 subs r0, r0, r3 + 8001206: 2864 cmp r0, #100 ; 0x64 + 8001208: d9f6 bls.n 80011f8 + return HAL_TIMEOUT; + 800120a: 2003 movs r0, #3 +} + 800120c: bdfe pop {r1, r2, r3, r4, r5, r6, r7, pc} + if ((PeriphClkInit->RTCClockSelection & RCC_CSR_RTCSEL) == RCC_CSR_RTCSEL_HSE) + 800120e: 4296 cmp r6, r2 + 8001210: d1a7 bne.n 8001162 + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) + 8001212: 6823 ldr r3, [r4, #0] + return HAL_ERROR; + 8001214: 2001 movs r0, #1 + if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) + 8001216: 039b lsls r3, r3, #14 + 8001218: d5a3 bpl.n 8001162 + 800121a: e7f7 b.n 800120c + if((temp_reg != 0x00000000U) && (((temp_reg != (PeriphClkInit->RTCClockSelection & RCC_CSR_RTCSEL)) \ + 800121c: 42b2 cmp r2, r6 + 800121e: d0a5 beq.n 800116c + && (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) + 8001220: 682b ldr r3, [r5, #0] + 8001222: 069b lsls r3, r3, #26 + 8001224: d5a2 bpl.n 800116c + __HAL_RCC_BACKUPRESET_FORCE(); + 8001226: 2280 movs r2, #128 ; 0x80 + temp_reg = (RCC->CSR & ~(RCC_CSR_RTCSEL)); + 8001228: 6d21 ldr r1, [r4, #80] ; 0x50 + __HAL_RCC_BACKUPRESET_FORCE(); + 800122a: 6d20 ldr r0, [r4, #80] ; 0x50 + 800122c: 0312 lsls r2, r2, #12 + 800122e: 4302 orrs r2, r0 + 8001230: 6522 str r2, [r4, #80] ; 0x50 + __HAL_RCC_BACKUPRESET_RELEASE(); + 8001232: 6d22 ldr r2, [r4, #80] ; 0x50 + temp_reg = (RCC->CSR & ~(RCC_CSR_RTCSEL)); + 8001234: 4b13 ldr r3, [pc, #76] ; (8001284 ) + __HAL_RCC_BACKUPRESET_RELEASE(); + 8001236: 4814 ldr r0, [pc, #80] ; (8001288 ) + temp_reg = (RCC->CSR & ~(RCC_CSR_RTCSEL)); + 8001238: 400b ands r3, r1 + __HAL_RCC_BACKUPRESET_RELEASE(); + 800123a: 4002 ands r2, r0 + 800123c: 6522 str r2, [r4, #80] ; 0x50 + RCC->CSR = temp_reg; + 800123e: 6523 str r3, [r4, #80] ; 0x50 + if (HAL_IS_BIT_SET(temp_reg, RCC_CSR_LSEON)) + 8001240: 05cb lsls r3, r1, #23 + 8001242: d400 bmi.n 8001246 + 8001244: e792 b.n 800116c + tickstart = HAL_GetTick(); + 8001246: f7ff fba5 bl 8000994 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U) + 800124a: 2780 movs r7, #128 ; 0x80 + tickstart = HAL_GetTick(); + 800124c: 0006 movs r6, r0 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U) + 800124e: 00bf lsls r7, r7, #2 + 8001250: 6d23 ldr r3, [r4, #80] ; 0x50 + 8001252: 423b tst r3, r7 + 8001254: d000 beq.n 8001258 + 8001256: e789 b.n 800116c + if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) + 8001258: f7ff fb9c bl 8000994 + 800125c: 4b0b ldr r3, [pc, #44] ; (800128c ) + 800125e: 1b80 subs r0, r0, r6 + 8001260: 4298 cmp r0, r3 + 8001262: d9f5 bls.n 8001250 + 8001264: e7d1 b.n 800120a + 8001266: 46c0 nop ; (mov r8, r8) + 8001268: 40021000 .word 0x40021000 + 800126c: 40007000 .word 0x40007000 + 8001270: ffcfffff .word 0xffcfffff + 8001274: efffffff .word 0xefffffff + 8001278: fffff3ff .word 0xfffff3ff + 800127c: ffffcfff .word 0xffffcfff + 8001280: fff3ffff .word 0xfff3ffff + 8001284: fffcffff .word 0xfffcffff + 8001288: fff7ffff .word 0xfff7ffff + 800128c: 00001388 .word 0x00001388 + +08001290 : + * @retval An ErrorStatus enumeration value: + * - SUCCESS: GPIO registers are initialized according to GPIO_InitStruct content + * - ERROR: Not applicable + */ +ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct) +{ + 8001290: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr} + uint32_t pinpos = 0x00000000U; + 8001292: 2300 movs r3, #0 +{ + 8001294: 0002 movs r2, r0 + /* ------------------------- Configure the port pins ---------------- */ + /* Initialize pinpos on first pin set */ + /* pinpos = 0; useless as already done in default initialization */ + + /* Configure the port pins */ + while (((GPIO_InitStruct->Pin) >> pinpos) != 0x00000000U) + 8001296: 680c ldr r4, [r1, #0] + } + + /* Pin Mode configuration */ + LL_GPIO_SetPinMode(GPIOx, currentpin, GPIO_InitStruct->Mode); + } + pinpos++; + 8001298: 9300 str r3, [sp, #0] + while (((GPIO_InitStruct->Pin) >> pinpos) != 0x00000000U) + 800129a: 0020 movs r0, r4 + 800129c: 9b00 ldr r3, [sp, #0] + 800129e: 40d8 lsrs r0, r3 + 80012a0: d100 bne.n 80012a4 + } + + + return (SUCCESS); +} + 80012a2: bdfe pop {r1, r2, r3, r4, r5, r6, r7, pc} + currentpin = (GPIO_InitStruct->Pin) & (0x00000001U << pinpos); + 80012a4: 2001 movs r0, #1 + 80012a6: 9b00 ldr r3, [sp, #0] + 80012a8: 4098 lsls r0, r3 + 80012aa: 0023 movs r3, r4 + 80012ac: 4003 ands r3, r0 + if (currentpin) + 80012ae: 4204 tst r4, r0 + 80012b0: d031 beq.n 8001316 + if ((GPIO_InitStruct->Mode == LL_GPIO_MODE_OUTPUT) || (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE)) + 80012b2: 6848 ldr r0, [r1, #4] + 80012b4: 2503 movs r5, #3 + 80012b6: 9001 str r0, [sp, #4] + 80012b8: 0018 movs r0, r3 + 80012ba: 4358 muls r0, r3 + 80012bc: 4345 muls r5, r0 + 80012be: 9e01 ldr r6, [sp, #4] + 80012c0: 43ed mvns r5, r5 + 80012c2: 1e77 subs r7, r6, #1 + 80012c4: 2f01 cmp r7, #1 + 80012c6: d80b bhi.n 80012e0 + MODIFY_REG(GPIOx->OSPEEDR, ((Pin * Pin) * GPIO_OSPEEDER_OSPEED0), ((Pin * Pin) * Speed)); + 80012c8: 688f ldr r7, [r1, #8] + 80012ca: 6896 ldr r6, [r2, #8] + 80012cc: 4347 muls r7, r0 + 80012ce: 402e ands r6, r5 + 80012d0: 4337 orrs r7, r6 + 80012d2: 6097 str r7, [r2, #8] + MODIFY_REG(GPIOx->OTYPER, PinMask, (PinMask * OutputType)); + 80012d4: 6857 ldr r7, [r2, #4] + 80012d6: 68ce ldr r6, [r1, #12] + 80012d8: 43a7 bics r7, r4 + 80012da: 4374 muls r4, r6 + 80012dc: 433c orrs r4, r7 + 80012de: 6054 str r4, [r2, #4] + MODIFY_REG(GPIOx->PUPDR, ((Pin * Pin) * GPIO_PUPDR_PUPD0), ((Pin * Pin) * Pull)); + 80012e0: 690c ldr r4, [r1, #16] + 80012e2: 68d7 ldr r7, [r2, #12] + 80012e4: 4344 muls r4, r0 + 80012e6: 402f ands r7, r5 + 80012e8: 433c orrs r4, r7 + 80012ea: 60d4 str r4, [r2, #12] + if (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE) + 80012ec: 9c01 ldr r4, [sp, #4] + 80012ee: 2c02 cmp r4, #2 + 80012f0: d10b bne.n 800130a + if (currentpin < LL_GPIO_PIN_8) + 80012f2: 694f ldr r7, [r1, #20] + 80012f4: 2bff cmp r3, #255 ; 0xff + 80012f6: d811 bhi.n 800131c + MODIFY_REG(GPIOx->AFR[0], ((((Pin * Pin) * Pin) * Pin) * GPIO_AFRL_AFSEL0), + 80012f8: 0003 movs r3, r0 + 80012fa: 260f movs r6, #15 + 80012fc: 4343 muls r3, r0 + 80012fe: 435e muls r6, r3 + 8001300: 437b muls r3, r7 + 8001302: 6a14 ldr r4, [r2, #32] + 8001304: 43b4 bics r4, r6 + 8001306: 431c orrs r4, r3 + 8001308: 6214 str r4, [r2, #32] + MODIFY_REG(GPIOx->MODER, ((Pin * Pin) * GPIO_MODER_MODE0), ((Pin * Pin) * Mode)); + 800130a: 6813 ldr r3, [r2, #0] + 800130c: 401d ands r5, r3 + 800130e: 9b01 ldr r3, [sp, #4] + 8001310: 4358 muls r0, r3 + 8001312: 4305 orrs r5, r0 + 8001314: 6015 str r5, [r2, #0] + pinpos++; + 8001316: 9b00 ldr r3, [sp, #0] + 8001318: 3301 adds r3, #1 + 800131a: e7bc b.n 8001296 + MODIFY_REG(GPIOx->AFR[1], (((((Pin >> 8U) * (Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U)) * GPIO_AFRH_AFSEL8), + 800131c: 260f movs r6, #15 + 800131e: 0a1b lsrs r3, r3, #8 + 8001320: 435b muls r3, r3 + 8001322: 435b muls r3, r3 + 8001324: 435e muls r6, r3 + 8001326: 437b muls r3, r7 + 8001328: 6a54 ldr r4, [r2, #36] ; 0x24 + 800132a: 43b4 bics r4, r6 + 800132c: 431c orrs r4, r3 + 800132e: 6254 str r4, [r2, #36] ; 0x24 +} + 8001330: e7eb b.n 800130a + ... + +08001334 : + CLEAR_BIT(I2Cx->CR1, I2C_CR1_PE); + 8001334: 2201 movs r2, #1 + 8001336: 6803 ldr r3, [r0, #0] + * @retval An ErrorStatus enumeration value: + * - SUCCESS: I2C registers are initialized + * - ERROR: Not applicable + */ +ErrorStatus LL_I2C_Init(I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct) +{ + 8001338: b530 push {r4, r5, lr} + 800133a: 4393 bics r3, r2 + 800133c: 6003 str r3, [r0, #0] + MODIFY_REG(I2Cx->CR1, I2C_CR1_ANFOFF | I2C_CR1_DNF, AnalogFilter | (DigitalFilter << I2C_CR1_DNF_Pos)); + 800133e: 68cb ldr r3, [r1, #12] + 8001340: 688d ldr r5, [r1, #8] + 8001342: 021b lsls r3, r3, #8 + 8001344: 6804 ldr r4, [r0, #0] + 8001346: 432b orrs r3, r5 + 8001348: 4d14 ldr r5, [pc, #80] ; (800139c ) + 800134a: 402c ands r4, r5 + 800134c: 4323 orrs r3, r4 + 800134e: 6003 str r3, [r0, #0] + WRITE_REG(I2Cx->TIMINGR, Timing); + 8001350: 684b ldr r3, [r1, #4] + * Disable, Configure and Enable I2Cx device own address 1 with parameters : + * - OwnAddress1: I2C_OAR1_OA1[9:0] bits + * - OwnAddrSize: I2C_OAR1_OA1MODE bit + */ + LL_I2C_DisableOwnAddress1(I2Cx); + LL_I2C_SetOwnAddress1(I2Cx, I2C_InitStruct->OwnAddress1, I2C_InitStruct->OwnAddrSize); + 8001352: 690d ldr r5, [r1, #16] + 8001354: 6103 str r3, [r0, #16] + SET_BIT(I2Cx->CR1, I2C_CR1_PE); + 8001356: 6803 ldr r3, [r0, #0] + 8001358: 431a orrs r2, r3 + 800135a: 6002 str r2, [r0, #0] + CLEAR_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN); + 800135c: 6882 ldr r2, [r0, #8] + 800135e: 4b10 ldr r3, [pc, #64] ; (80013a0 ) + 8001360: 401a ands r2, r3 + 8001362: 6082 str r2, [r0, #8] + MODIFY_REG(I2Cx->OAR1, I2C_OAR1_OA1 | I2C_OAR1_OA1MODE, OwnAddress1 | OwnAddrSize); + 8001364: 6884 ldr r4, [r0, #8] + 8001366: 698a ldr r2, [r1, #24] + 8001368: 0ae4 lsrs r4, r4, #11 + 800136a: 02e4 lsls r4, r4, #11 + 800136c: 432a orrs r2, r5 + 800136e: 4322 orrs r2, r4 + 8001370: 6082 str r2, [r0, #8] + + /* OwnAdress1 == 0 is reserved for General Call address */ + if (I2C_InitStruct->OwnAddress1 != 0U) + 8001372: 001c movs r4, r3 + 8001374: 2d00 cmp r5, #0 + 8001376: d004 beq.n 8001382 + SET_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN); + 8001378: 2380 movs r3, #128 ; 0x80 + 800137a: 6882 ldr r2, [r0, #8] + 800137c: 021b lsls r3, r3, #8 + 800137e: 4313 orrs r3, r2 + 8001380: 6083 str r3, [r0, #8] + MODIFY_REG(I2Cx->CR1, I2C_CR1_SMBHEN | I2C_CR1_SMBDEN, PeripheralMode); + 8001382: 6802 ldr r2, [r0, #0] + 8001384: 4b07 ldr r3, [pc, #28] ; (80013a4 ) + 8001386: 401a ands r2, r3 + 8001388: 680b ldr r3, [r1, #0] + 800138a: 431a orrs r2, r3 + 800138c: 6002 str r2, [r0, #0] + * @arg @ref LL_I2C_NACK + * @retval None + */ +__STATIC_INLINE void LL_I2C_AcknowledgeNextData(I2C_TypeDef *I2Cx, uint32_t TypeAcknowledge) +{ + MODIFY_REG(I2Cx->CR2, I2C_CR2_NACK, TypeAcknowledge); + 800138e: 6843 ldr r3, [r0, #4] + 8001390: 694a ldr r2, [r1, #20] + 8001392: 4023 ands r3, r4 + 8001394: 4313 orrs r3, r2 + 8001396: 6043 str r3, [r0, #4] + * - TypeAcknowledge: I2C_CR2_NACK bit + */ + LL_I2C_AcknowledgeNextData(I2Cx, I2C_InitStruct->TypeAcknowledge); + + return SUCCESS; +} + 8001398: 2000 movs r0, #0 + 800139a: bd30 pop {r4, r5, pc} + 800139c: ffffe0ff .word 0xffffe0ff + 80013a0: ffff7fff .word 0xffff7fff + 80013a4: ffcfffff .word 0xffcfffff + +080013a8 : + return ((READ_BIT(LPUARTx->CR1, USART_CR1_UE) == (USART_CR1_UE)) ? 1UL : 0UL); + 80013a8: 6802 ldr r2, [r0, #0] + * @retval An ErrorStatus enumeration value: + * - SUCCESS: LPUART registers are initialized according to LPUART_InitStruct content + * - ERROR: Problem occurred during LPUART Registers initialization + */ +ErrorStatus LL_LPUART_Init(USART_TypeDef *LPUARTx, LL_LPUART_InitTypeDef *LPUART_InitStruct) +{ + 80013aa: b5f8 push {r3, r4, r5, r6, r7, lr} + 80013ac: 2301 movs r3, #1 + 80013ae: 0015 movs r5, r2 + 80013b0: 0004 movs r4, r0 + 80013b2: 000e movs r6, r1 + 80013b4: 401d ands r5, r3 + assert_param(IS_LL_LPUART_DIRECTION(LPUART_InitStruct->TransferDirection)); + assert_param(IS_LL_LPUART_HWCONTROL(LPUART_InitStruct->HardwareFlowControl)); + + /* LPUART needs to be in disabled state, in order to be able to configure some bits in + CRx registers. Otherwise (LPUART not in Disabled state) => return ERROR */ + if (LL_LPUART_IsEnabled(LPUARTx) == 0U) + 80013b6: 421a tst r2, r3 + 80013b8: d001 beq.n 80013be + ErrorStatus status = ERROR; + 80013ba: 2001 movs r0, #1 + } + + } + + return (status); +} + 80013bc: bdf8 pop {r3, r4, r5, r6, r7, pc} + MODIFY_REG(LPUARTx->CR1, + 80013be: 684b ldr r3, [r1, #4] + 80013c0: 68c9 ldr r1, [r1, #12] + 80013c2: 6802 ldr r2, [r0, #0] + 80013c4: 430b orrs r3, r1 + 80013c6: 6931 ldr r1, [r6, #16] + 80013c8: 430b orrs r3, r1 + 80013ca: 4913 ldr r1, [pc, #76] ; (8001418 ) + 80013cc: 400a ands r2, r1 + 80013ce: 4313 orrs r3, r2 + 80013d0: 6003 str r3, [r0, #0] + MODIFY_REG(LPUARTx->CR2, USART_CR2_STOP, StopBits); + 80013d2: 6843 ldr r3, [r0, #4] + 80013d4: 4a11 ldr r2, [pc, #68] ; (800141c ) + 80013d6: 4013 ands r3, r2 + 80013d8: 68b2 ldr r2, [r6, #8] + 80013da: 4313 orrs r3, r2 + 80013dc: 6043 str r3, [r0, #4] + MODIFY_REG(LPUARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE, HardwareFlowControl); + 80013de: 6883 ldr r3, [r0, #8] + 80013e0: 4a0f ldr r2, [pc, #60] ; (8001420 ) + 80013e2: 4013 ands r3, r2 + 80013e4: 6972 ldr r2, [r6, #20] + 80013e6: 4313 orrs r3, r2 + 80013e8: 6083 str r3, [r0, #8] + periphclk = LL_RCC_GetLPUARTClockFreq(LL_RCC_LPUART1_CLKSOURCE); + 80013ea: 20c0 movs r0, #192 ; 0xc0 + 80013ec: 0100 lsls r0, r0, #4 + 80013ee: f000 f899 bl 8001524 + if ((periphclk != LL_RCC_PERIPH_FREQUENCY_NO) + 80013f2: 2800 cmp r0, #0 + 80013f4: d0e1 beq.n 80013ba + && (LPUART_InitStruct->BaudRate != 0U)) + 80013f6: 6832 ldr r2, [r6, #0] + 80013f8: 2a00 cmp r2, #0 + 80013fa: d0de beq.n 80013ba + LPUARTx->BRR = __LL_LPUART_DIV(PeriphClk, BaudRate); + 80013fc: 0029 movs r1, r5 + 80013fe: 0e07 lsrs r7, r0, #24 + 8001400: 0206 lsls r6, r0, #8 + 8001402: 0850 lsrs r0, r2, #1 + 8001404: 1980 adds r0, r0, r6 + 8001406: 4179 adcs r1, r7 + 8001408: 002b movs r3, r5 + 800140a: f7fe ff09 bl 8000220 <__aeabi_uldivmod> + 800140e: 0300 lsls r0, r0, #12 + 8001410: 0b00 lsrs r0, r0, #12 + 8001412: 60e0 str r0, [r4, #12] + status = SUCCESS; + 8001414: 0028 movs r0, r5 +} + 8001416: e7d1 b.n 80013bc + 8001418: efffe9f3 .word 0xefffe9f3 + 800141c: ffffcfff .word 0xffffcfff + 8001420: fffffcff .word 0xfffffcff + +08001424 : + * @rmtoll CR HSIRDY LL_RCC_HSI_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void) +{ + return ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) == RCC_CR_HSIRDY) ? 1UL : 0UL); + 8001424: 4b02 ldr r3, [pc, #8] ; (8001430 ) + 8001426: 6818 ldr r0, [r3, #0] + 8001428: 0740 lsls r0, r0, #29 + 800142a: 0fc0 lsrs r0, r0, #31 +} + 800142c: 4770 bx lr + 800142e: 46c0 nop ; (mov r8, r8) + 8001430: 40021000 .word 0x40021000 + +08001434 : + * @rmtoll CR HSIDIVF LL_RCC_IsActiveFlag_HSIDIV + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIDIV(void) +{ + return ((READ_BIT(RCC->CR, RCC_CR_HSIDIVF) == RCC_CR_HSIDIVF) ? 1UL : 0UL); + 8001434: 4b02 ldr r3, [pc, #8] ; (8001440 ) + 8001436: 6818 ldr r0, [r3, #0] + 8001438: 06c0 lsls r0, r0, #27 + 800143a: 0fc0 lsrs r0, r0, #31 +} + 800143c: 4770 bx lr + 800143e: 46c0 nop ; (mov r8, r8) + 8001440: 40021000 .word 0x40021000 + +08001444 : + return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE)); + 8001444: 4b03 ldr r3, [pc, #12] ; (8001454 ) + * @retval HCLK clock frequency (in Hz) + */ +uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency) +{ + /* HCLK clock frequency */ + return __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, LL_RCC_GetAHBPrescaler()); + 8001446: 4a04 ldr r2, [pc, #16] ; (8001458 ) + 8001448: 68db ldr r3, [r3, #12] + 800144a: 061b lsls r3, r3, #24 + 800144c: 0f1b lsrs r3, r3, #28 + 800144e: 5cd3 ldrb r3, [r2, r3] + 8001450: 40d8 lsrs r0, r3 +} + 8001452: 4770 bx lr + 8001454: 40021000 .word 0x40021000 + 8001458: 08001600 .word 0x08001600 + +0800145c : + return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1)); + 800145c: 4b03 ldr r3, [pc, #12] ; (800146c ) + * @retval PCLK1 clock frequency (in Hz) + */ +uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency) +{ + /* PCLK1 clock frequency */ + return __LL_RCC_CALC_PCLK1_FREQ(HCLK_Frequency, LL_RCC_GetAPB1Prescaler()); + 800145e: 4a04 ldr r2, [pc, #16] ; (8001470 ) + 8001460: 68db ldr r3, [r3, #12] + 8001462: 055b lsls r3, r3, #21 + 8001464: 0f5b lsrs r3, r3, #29 + 8001466: 5cd3 ldrb r3, [r2, r3] + 8001468: 40d8 lsrs r0, r3 +} + 800146a: 4770 bx lr + 800146c: 40021000 .word 0x40021000 + 8001470: 08001610 .word 0x08001610 + +08001474 : +/** + * @brief Return PLL clock frequency used for system domain + * @retval PLL clock frequency (in Hz) + */ +uint32_t RCC_PLL_GetFreqDomain_SYS(void) +{ + 8001474: b510 push {r4, lr} + return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC)); + 8001476: 4c0e ldr r4, [pc, #56] ; (80014b0 ) + 8001478: 68e3 ldr r3, [r4, #12] + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL divider) * PLL Multiplicator */ + + /* Get PLL source */ + pllsource = LL_RCC_PLL_GetMainSource(); + + switch (pllsource) + 800147a: 03db lsls r3, r3, #15 + 800147c: d415 bmi.n 80014aa + { + case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ + if (LL_RCC_IsActiveFlag_HSIDIV() != 0U) + 800147e: f7ff ffd9 bl 8001434 + { + pllinputfreq = (HSI_VALUE >> 2U); + } + else + { + pllinputfreq = HSI_VALUE; + 8001482: 1e43 subs r3, r0, #1 + 8001484: 4198 sbcs r0, r3 + 8001486: 4b0b ldr r3, [pc, #44] ; (80014b4 ) + 8001488: 4240 negs r0, r0 + 800148a: 4018 ands r0, r3 + 800148c: 4b0a ldr r3, [pc, #40] ; (80014b8 ) + 800148e: 18c0 adds r0, r0, r3 + return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLMUL)); + 8001490: 68e3 ldr r3, [r4, #12] + + default: /* HSE used as PLL clock source */ + pllinputfreq = HSE_VALUE; + break; + } + return __LL_RCC_CALC_PLLCLK_FREQ(pllinputfreq, LL_RCC_PLL_GetMultiplicator(), LL_RCC_PLL_GetDivider()); + 8001492: 4a0a ldr r2, [pc, #40] ; (80014bc ) + return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLDIV)); + 8001494: 68e1 ldr r1, [r4, #12] + 8001496: 029b lsls r3, r3, #10 + 8001498: 0f1b lsrs r3, r3, #28 + 800149a: 5cd3 ldrb r3, [r2, r3] + 800149c: 0209 lsls r1, r1, #8 + 800149e: 0f89 lsrs r1, r1, #30 + 80014a0: 4358 muls r0, r3 + 80014a2: 3101 adds r1, #1 + 80014a4: f7fe fe30 bl 8000108 <__udivsi3> +} + 80014a8: bd10 pop {r4, pc} + pllinputfreq = HSE_VALUE; + 80014aa: 4805 ldr r0, [pc, #20] ; (80014c0 ) + 80014ac: e7f0 b.n 8001490 + 80014ae: 46c0 nop ; (mov r8, r8) + 80014b0: 40021000 .word 0x40021000 + 80014b4: ff48e500 .word 0xff48e500 + 80014b8: 00f42400 .word 0x00f42400 + 80014bc: 08001618 .word 0x08001618 + 80014c0: 007a1200 .word 0x007a1200 + +080014c4 : + return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS)); + 80014c4: 210c movs r1, #12 + 80014c6: 4a13 ldr r2, [pc, #76] ; (8001514 ) +{ + 80014c8: b510 push {r4, lr} + 80014ca: 68d3 ldr r3, [r2, #12] + 80014cc: 400b ands r3, r1 + 80014ce: 0011 movs r1, r2 + switch (LL_RCC_GetSysClkSource()) + 80014d0: 2b08 cmp r3, #8 + 80014d2: d01d beq.n 8001510 + 80014d4: d805 bhi.n 80014e2 + 80014d6: 2b00 cmp r3, #0 + 80014d8: d008 beq.n 80014ec + 80014da: 2b04 cmp r3, #4 + 80014dc: d00e beq.n 80014fc + return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_MSIRANGE)); + 80014de: 684b ldr r3, [r1, #4] + 80014e0: e005 b.n 80014ee + 80014e2: 2b0c cmp r3, #12 + 80014e4: d1fb bne.n 80014de + frequency = RCC_PLL_GetFreqDomain_SYS(); + 80014e6: f7ff ffc5 bl 8001474 + break; + 80014ea: e010 b.n 800150e + 80014ec: 6853 ldr r3, [r2, #4] + frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_GetRange()); + 80014ee: 2080 movs r0, #128 ; 0x80 + 80014f0: 041b lsls r3, r3, #16 + 80014f2: 0f5b lsrs r3, r3, #29 + 80014f4: 3301 adds r3, #1 + 80014f6: 0200 lsls r0, r0, #8 + 80014f8: 4098 lsls r0, r3 + return frequency; + 80014fa: e008 b.n 800150e + if (LL_RCC_IsActiveFlag_HSIDIV() != 0U) + 80014fc: f7ff ff9a bl 8001434 + frequency = HSI_VALUE; + 8001500: 1e43 subs r3, r0, #1 + 8001502: 4198 sbcs r0, r3 + 8001504: 4b04 ldr r3, [pc, #16] ; (8001518 ) + 8001506: 4240 negs r0, r0 + 8001508: 4018 ands r0, r3 + 800150a: 4b04 ldr r3, [pc, #16] ; (800151c ) + 800150c: 18c0 adds r0, r0, r3 +} + 800150e: bd10 pop {r4, pc} + switch (LL_RCC_GetSysClkSource()) + 8001510: 4803 ldr r0, [pc, #12] ; (8001520 ) + 8001512: e7fc b.n 800150e + 8001514: 40021000 .word 0x40021000 + 8001518: ff48e500 .word 0xff48e500 + 800151c: 00f42400 .word 0x00f42400 + 8001520: 007a1200 .word 0x007a1200 + +08001524 : + return (uint32_t)(READ_BIT(RCC->CCIPR, LPUARTx)); + 8001524: 4a17 ldr r2, [pc, #92] ; (8001584 ) +{ + 8001526: b510 push {r4, lr} + 8001528: 6cd3 ldr r3, [r2, #76] ; 0x4c + 800152a: 4018 ands r0, r3 + switch (LL_RCC_GetLPUARTClockSource(LPUARTxSource)) + 800152c: 2380 movs r3, #128 ; 0x80 + 800152e: 011b lsls r3, r3, #4 + 8001530: 4298 cmp r0, r3 + 8001532: d00a beq.n 800154a + 8001534: 23c0 movs r3, #192 ; 0xc0 + 8001536: 011b lsls r3, r3, #4 + 8001538: 4298 cmp r0, r3 + 800153a: d014 beq.n 8001566 + 800153c: 2380 movs r3, #128 ; 0x80 + 800153e: 00db lsls r3, r3, #3 + 8001540: 4298 cmp r0, r3 + 8001542: d115 bne.n 8001570 + lpuart_frequency = RCC_GetSystemClockFreq(); + 8001544: f7ff ffbe bl 80014c4 +} + 8001548: bd10 pop {r4, pc} + if (LL_RCC_HSI_IsReady() != 0U) + 800154a: f7ff ff6b bl 8001424 + 800154e: 2800 cmp r0, #0 + 8001550: d00c beq.n 800156c + if (LL_RCC_IsActiveFlag_HSIDIV() != 0U) + 8001552: f7ff ff6f bl 8001434 + lpuart_frequency = HSI_VALUE; + 8001556: 1e43 subs r3, r0, #1 + 8001558: 4198 sbcs r0, r3 + 800155a: 4b0b ldr r3, [pc, #44] ; (8001588 ) + 800155c: 4240 negs r0, r0 + 800155e: 4018 ands r0, r3 + 8001560: 4b0a ldr r3, [pc, #40] ; (800158c ) + 8001562: 18c0 adds r0, r0, r3 + 8001564: e7f0 b.n 8001548 + return ((READ_BIT(RCC->CSR, RCC_CSR_LSERDY) == RCC_CSR_LSERDY) ? 1UL : 0UL); + 8001566: 6d13 ldr r3, [r2, #80] ; 0x50 + 8001568: 059b lsls r3, r3, #22 + 800156a: d408 bmi.n 800157e + uint32_t lpuart_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + 800156c: 2000 movs r0, #0 + 800156e: e7eb b.n 8001548 + lpuart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); + 8001570: f7ff ffa8 bl 80014c4 + 8001574: f7ff ff66 bl 8001444 + 8001578: f7ff ff70 bl 800145c + break; + 800157c: e7e4 b.n 8001548 + lpuart_frequency = LSE_VALUE; + 800157e: 2080 movs r0, #128 ; 0x80 + 8001580: 0200 lsls r0, r0, #8 + return lpuart_frequency; + 8001582: e7e1 b.n 8001548 + 8001584: 40021000 .word 0x40021000 + 8001588: ff48e500 .word 0xff48e500 + 800158c: 00f42400 .word 0x00f42400 + +08001590 <__libc_init_array>: + 8001590: b570 push {r4, r5, r6, lr} + 8001592: 2600 movs r6, #0 + 8001594: 4d0c ldr r5, [pc, #48] ; (80015c8 <__libc_init_array+0x38>) + 8001596: 4c0d ldr r4, [pc, #52] ; (80015cc <__libc_init_array+0x3c>) + 8001598: 1b64 subs r4, r4, r5 + 800159a: 10a4 asrs r4, r4, #2 + 800159c: 42a6 cmp r6, r4 + 800159e: d109 bne.n 80015b4 <__libc_init_array+0x24> + 80015a0: 2600 movs r6, #0 + 80015a2: f000 f821 bl 80015e8 <_init> + 80015a6: 4d0a ldr r5, [pc, #40] ; (80015d0 <__libc_init_array+0x40>) + 80015a8: 4c0a ldr r4, [pc, #40] ; (80015d4 <__libc_init_array+0x44>) + 80015aa: 1b64 subs r4, r4, r5 + 80015ac: 10a4 asrs r4, r4, #2 + 80015ae: 42a6 cmp r6, r4 + 80015b0: d105 bne.n 80015be <__libc_init_array+0x2e> + 80015b2: bd70 pop {r4, r5, r6, pc} + 80015b4: 00b3 lsls r3, r6, #2 + 80015b6: 58eb ldr r3, [r5, r3] + 80015b8: 4798 blx r3 + 80015ba: 3601 adds r6, #1 + 80015bc: e7ee b.n 800159c <__libc_init_array+0xc> + 80015be: 00b3 lsls r3, r6, #2 + 80015c0: 58eb ldr r3, [r5, r3] + 80015c2: 4798 blx r3 + 80015c4: 3601 adds r6, #1 + 80015c6: e7f2 b.n 80015ae <__libc_init_array+0x1e> + 80015c8: 0800162c .word 0x0800162c + 80015cc: 0800162c .word 0x0800162c + 80015d0: 0800162c .word 0x0800162c + 80015d4: 08001630 .word 0x08001630 + +080015d8 : + 80015d8: 0003 movs r3, r0 + 80015da: 1882 adds r2, r0, r2 + 80015dc: 4293 cmp r3, r2 + 80015de: d100 bne.n 80015e2 + 80015e0: 4770 bx lr + 80015e2: 7019 strb r1, [r3, #0] + 80015e4: 3301 adds r3, #1 + 80015e6: e7f9 b.n 80015dc + +080015e8 <_init>: + 80015e8: b5f8 push {r3, r4, r5, r6, r7, lr} + 80015ea: 46c0 nop ; (mov r8, r8) + 80015ec: bcf8 pop {r3, r4, r5, r6, r7} + 80015ee: bc08 pop {r3} + 80015f0: 469e mov lr, r3 + 80015f2: 4770 bx lr + +080015f4 <_fini>: + 80015f4: b5f8 push {r3, r4, r5, r6, r7, lr} + 80015f6: 46c0 nop ; (mov r8, r8) + 80015f8: bcf8 pop {r3, r4, r5, r6, r7} + 80015fa: bc08 pop {r3} + 80015fc: 469e mov lr, r3 + 80015fe: 4770 bx lr diff --git a/fw/Debug/iaq_wired_sensor.map b/fw/Debug/iaq_wired_sensor.map new file mode 100644 index 0000000..37ea287 --- /dev/null +++ b/fw/Debug/iaq_wired_sensor.map @@ -0,0 +1,3631 @@ +Archive member included to satisfy reference by file (symbol) + +/opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-errno.o) + Core/Src/syscalls.o (__errno) +/opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-exit.o) + /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/crt0.o (exit) +/opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-impure.o) + /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-exit.o) (_global_impure_ptr) +/opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-init.o) + /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/crt0.o (__libc_init_array) +/opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-memset.o) + /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/crt0.o (memset) +/opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_thumb1_case_uqi.o) + Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o (__gnu_thumb1_case_uqi) +/opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_udivsi3.o) + Core/Src/system_stm32l0xx.o (__aeabi_uidiv) +/opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_divsi3.o) + Core/Src/system_stm32l0xx.o (__aeabi_idiv) +/opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_dvmd_tls.o) + /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_udivsi3.o) (__aeabi_idiv0) +/opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_aeabi_ldivmod.o) + Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o (__aeabi_ldivmod) +/opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_aeabi_uldivmod.o) + Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o (__aeabi_uldivmod) +/opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_muldi3.o) + Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o (__aeabi_lmul) +/opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_udivmoddi4.o) + /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_aeabi_uldivmod.o) (__udivmoddi4) +/opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(bpabi.o) + /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_aeabi_ldivmod.o) (__gnu_ldivmod_helper) +/opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_clzdi2.o) + /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_udivmoddi4.o) (__clzdi2) +/opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_divdi3.o) + /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(bpabi.o) (__divdi3) +/opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_clzsi2.o) + /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_clzdi2.o) (__clzsi2) + +Allocating common symbols +Common symbol size file + +uwTick 0x4 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o +pFlash 0x18 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + +Discarded input sections + + .text 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crti.o + .data 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crti.o + .bss 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crti.o + .data 0x0000000000000000 0x4 /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crtbegin.o + .text 0x0000000000000000 0x80 /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/crt0.o + .data 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/crt0.o + .bss 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/crt0.o + .ARM.extab 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/crt0.o + .ARM.exidx 0x0000000000000000 0x10 /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/crt0.o + .ARM.attributes + 0x0000000000000000 0x1b /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/crt0.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .text 0x0000000000000000 0x0 Core/Src/main.o + .data 0x0000000000000000 0x0 Core/Src/main.o + .bss 0x0000000000000000 0x0 Core/Src/main.o + .text.Error_Handler + 0x0000000000000000 0x4 Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/stm32l0xx_hal_msp.o + .group 0x0000000000000000 0xc Core/Src/stm32l0xx_hal_msp.o + .group 0x0000000000000000 0xc Core/Src/stm32l0xx_hal_msp.o + .group 0x0000000000000000 0xc Core/Src/stm32l0xx_hal_msp.o + .group 0x0000000000000000 0xc Core/Src/stm32l0xx_hal_msp.o + .group 0x0000000000000000 0xc Core/Src/stm32l0xx_hal_msp.o + .group 0x0000000000000000 0xc Core/Src/stm32l0xx_hal_msp.o + .group 0x0000000000000000 0xc Core/Src/stm32l0xx_hal_msp.o + .group 0x0000000000000000 0xc Core/Src/stm32l0xx_hal_msp.o + .group 0x0000000000000000 0xc Core/Src/stm32l0xx_hal_msp.o + .group 0x0000000000000000 0xc Core/Src/stm32l0xx_hal_msp.o + .group 0x0000000000000000 0xc Core/Src/stm32l0xx_hal_msp.o + .group 0x0000000000000000 0xc Core/Src/stm32l0xx_hal_msp.o + .group 0x0000000000000000 0xc Core/Src/stm32l0xx_hal_msp.o + .group 0x0000000000000000 0xc Core/Src/stm32l0xx_hal_msp.o + .group 0x0000000000000000 0xc Core/Src/stm32l0xx_hal_msp.o + .group 0x0000000000000000 0xc Core/Src/stm32l0xx_hal_msp.o + .group 0x0000000000000000 0xc Core/Src/stm32l0xx_hal_msp.o + .group 0x0000000000000000 0xc Core/Src/stm32l0xx_hal_msp.o + .group 0x0000000000000000 0xc Core/Src/stm32l0xx_hal_msp.o + .group 0x0000000000000000 0xc Core/Src/stm32l0xx_hal_msp.o + .group 0x0000000000000000 0xc Core/Src/stm32l0xx_hal_msp.o + .group 0x0000000000000000 0xc Core/Src/stm32l0xx_hal_msp.o + .group 0x0000000000000000 0xc Core/Src/stm32l0xx_hal_msp.o + .group 0x0000000000000000 0xc Core/Src/stm32l0xx_hal_msp.o + .group 0x0000000000000000 0xc Core/Src/stm32l0xx_hal_msp.o + .group 0x0000000000000000 0xc Core/Src/stm32l0xx_hal_msp.o + .group 0x0000000000000000 0xc Core/Src/stm32l0xx_hal_msp.o + .group 0x0000000000000000 0xc Core/Src/stm32l0xx_hal_msp.o + .group 0x0000000000000000 0xc Core/Src/stm32l0xx_hal_msp.o + .group 0x0000000000000000 0xc Core/Src/stm32l0xx_hal_msp.o + .group 0x0000000000000000 0xc Core/Src/stm32l0xx_hal_msp.o + .group 0x0000000000000000 0xc Core/Src/stm32l0xx_hal_msp.o + .group 0x0000000000000000 0xc Core/Src/stm32l0xx_hal_msp.o + .group 0x0000000000000000 0xc Core/Src/stm32l0xx_hal_msp.o + .group 0x0000000000000000 0xc Core/Src/stm32l0xx_hal_msp.o + .group 0x0000000000000000 0xc Core/Src/stm32l0xx_hal_msp.o + .group 0x0000000000000000 0xc Core/Src/stm32l0xx_hal_msp.o + .group 0x0000000000000000 0xc Core/Src/stm32l0xx_hal_msp.o + .group 0x0000000000000000 0xc Core/Src/stm32l0xx_hal_msp.o + .group 0x0000000000000000 0xc Core/Src/stm32l0xx_hal_msp.o + .group 0x0000000000000000 0xc Core/Src/stm32l0xx_hal_msp.o + .group 0x0000000000000000 0xc Core/Src/stm32l0xx_hal_msp.o + .group 0x0000000000000000 0xc Core/Src/stm32l0xx_hal_msp.o + .group 0x0000000000000000 0xc Core/Src/stm32l0xx_hal_msp.o + .group 0x0000000000000000 0xc Core/Src/stm32l0xx_hal_msp.o + .text 0x0000000000000000 0x0 Core/Src/stm32l0xx_hal_msp.o + .data 0x0000000000000000 0x0 Core/Src/stm32l0xx_hal_msp.o + .bss 0x0000000000000000 0x0 Core/Src/stm32l0xx_hal_msp.o + .debug_macro 0x0000000000000000 0xa8a Core/Src/stm32l0xx_hal_msp.o + .debug_macro 0x0000000000000000 0x119 Core/Src/stm32l0xx_hal_msp.o + .debug_macro 0x0000000000000000 0x2e Core/Src/stm32l0xx_hal_msp.o + .debug_macro 0x0000000000000000 0x28 Core/Src/stm32l0xx_hal_msp.o + .debug_macro 0x0000000000000000 0x22 Core/Src/stm32l0xx_hal_msp.o + .debug_macro 0x0000000000000000 0x8e Core/Src/stm32l0xx_hal_msp.o + .debug_macro 0x0000000000000000 0x51 Core/Src/stm32l0xx_hal_msp.o + .debug_macro 0x0000000000000000 0x103 Core/Src/stm32l0xx_hal_msp.o + .debug_macro 0x0000000000000000 0x6a Core/Src/stm32l0xx_hal_msp.o + .debug_macro 0x0000000000000000 0x1df Core/Src/stm32l0xx_hal_msp.o + .debug_macro 0x0000000000000000 0x1c Core/Src/stm32l0xx_hal_msp.o + .debug_macro 0x0000000000000000 0x22 Core/Src/stm32l0xx_hal_msp.o + .debug_macro 0x0000000000000000 0xb5 Core/Src/stm32l0xx_hal_msp.o + .debug_macro 0x0000000000000000 0x3ad Core/Src/stm32l0xx_hal_msp.o + .debug_macro 0x0000000000000000 0x7b9c Core/Src/stm32l0xx_hal_msp.o + .debug_macro 0x0000000000000000 0x3c Core/Src/stm32l0xx_hal_msp.o + .debug_macro 0x0000000000000000 0x352b Core/Src/stm32l0xx_hal_msp.o + .debug_macro 0x0000000000000000 0x174 Core/Src/stm32l0xx_hal_msp.o + .debug_macro 0x0000000000000000 0x5b Core/Src/stm32l0xx_hal_msp.o + .debug_macro 0x0000000000000000 0x899 Core/Src/stm32l0xx_hal_msp.o + .debug_macro 0x0000000000000000 0x42e Core/Src/stm32l0xx_hal_msp.o + .debug_macro 0x0000000000000000 0x182 Core/Src/stm32l0xx_hal_msp.o + .debug_macro 0x0000000000000000 0x13f Core/Src/stm32l0xx_hal_msp.o + .debug_macro 0x0000000000000000 0xf1 Core/Src/stm32l0xx_hal_msp.o + .debug_macro 0x0000000000000000 0x28e Core/Src/stm32l0xx_hal_msp.o + .debug_macro 0x0000000000000000 0x28 Core/Src/stm32l0xx_hal_msp.o + .debug_macro 0x0000000000000000 0x129 Core/Src/stm32l0xx_hal_msp.o + .debug_macro 0x0000000000000000 0x244 Core/Src/stm32l0xx_hal_msp.o + .debug_macro 0x0000000000000000 0x22c Core/Src/stm32l0xx_hal_msp.o + .debug_macro 0x0000000000000000 0x5b Core/Src/stm32l0xx_hal_msp.o + .debug_macro 0x0000000000000000 0xa5 Core/Src/stm32l0xx_hal_msp.o + .debug_macro 0x0000000000000000 0x187 Core/Src/stm32l0xx_hal_msp.o + .debug_macro 0x0000000000000000 0x16 Core/Src/stm32l0xx_hal_msp.o + .debug_macro 0x0000000000000000 0x11c Core/Src/stm32l0xx_hal_msp.o + .debug_macro 0x0000000000000000 0x285 Core/Src/stm32l0xx_hal_msp.o + .debug_macro 0x0000000000000000 0x246 Core/Src/stm32l0xx_hal_msp.o + .debug_macro 0x0000000000000000 0x229 Core/Src/stm32l0xx_hal_msp.o + .debug_macro 0x0000000000000000 0x3b4 Core/Src/stm32l0xx_hal_msp.o + .debug_macro 0x0000000000000000 0x13d Core/Src/stm32l0xx_hal_msp.o + .debug_macro 0x0000000000000000 0x12d Core/Src/stm32l0xx_hal_msp.o + .debug_macro 0x0000000000000000 0x109 Core/Src/stm32l0xx_hal_msp.o + .debug_macro 0x0000000000000000 0xa7 Core/Src/stm32l0xx_hal_msp.o + .debug_macro 0x0000000000000000 0x16 Core/Src/stm32l0xx_hal_msp.o + .debug_macro 0x0000000000000000 0x2a Core/Src/stm32l0xx_hal_msp.o + .debug_macro 0x0000000000000000 0xdb Core/Src/stm32l0xx_hal_msp.o + .debug_macro 0x0000000000000000 0x28 Core/Src/stm32l0xx_hal_msp.o + .group 0x0000000000000000 0xc Core/Src/stm32l0xx_it.o + .group 0x0000000000000000 0xc Core/Src/stm32l0xx_it.o + .group 0x0000000000000000 0xc Core/Src/stm32l0xx_it.o + .group 0x0000000000000000 0xc Core/Src/stm32l0xx_it.o + .group 0x0000000000000000 0xc Core/Src/stm32l0xx_it.o + .group 0x0000000000000000 0xc Core/Src/stm32l0xx_it.o + .group 0x0000000000000000 0xc Core/Src/stm32l0xx_it.o + .group 0x0000000000000000 0xc Core/Src/stm32l0xx_it.o + .group 0x0000000000000000 0xc Core/Src/stm32l0xx_it.o + .group 0x0000000000000000 0xc Core/Src/stm32l0xx_it.o + .group 0x0000000000000000 0xc Core/Src/stm32l0xx_it.o + .group 0x0000000000000000 0xc Core/Src/stm32l0xx_it.o + .group 0x0000000000000000 0xc Core/Src/stm32l0xx_it.o + .group 0x0000000000000000 0xc Core/Src/stm32l0xx_it.o + .group 0x0000000000000000 0xc Core/Src/stm32l0xx_it.o + .group 0x0000000000000000 0xc Core/Src/stm32l0xx_it.o + .group 0x0000000000000000 0xc Core/Src/stm32l0xx_it.o + .group 0x0000000000000000 0xc Core/Src/stm32l0xx_it.o + .group 0x0000000000000000 0xc Core/Src/stm32l0xx_it.o + .group 0x0000000000000000 0xc Core/Src/stm32l0xx_it.o + .group 0x0000000000000000 0xc Core/Src/stm32l0xx_it.o + .group 0x0000000000000000 0xc Core/Src/stm32l0xx_it.o + .group 0x0000000000000000 0xc Core/Src/stm32l0xx_it.o + .group 0x0000000000000000 0xc Core/Src/stm32l0xx_it.o + .group 0x0000000000000000 0xc Core/Src/stm32l0xx_it.o + .group 0x0000000000000000 0xc Core/Src/stm32l0xx_it.o + .group 0x0000000000000000 0xc Core/Src/stm32l0xx_it.o + .group 0x0000000000000000 0xc Core/Src/stm32l0xx_it.o + .group 0x0000000000000000 0xc Core/Src/stm32l0xx_it.o + .group 0x0000000000000000 0xc Core/Src/stm32l0xx_it.o + .group 0x0000000000000000 0xc Core/Src/stm32l0xx_it.o + .group 0x0000000000000000 0xc Core/Src/stm32l0xx_it.o + .group 0x0000000000000000 0xc Core/Src/stm32l0xx_it.o + .group 0x0000000000000000 0xc Core/Src/stm32l0xx_it.o + .group 0x0000000000000000 0xc Core/Src/stm32l0xx_it.o + .group 0x0000000000000000 0xc Core/Src/stm32l0xx_it.o + .group 0x0000000000000000 0xc Core/Src/stm32l0xx_it.o + .group 0x0000000000000000 0xc Core/Src/stm32l0xx_it.o + .group 0x0000000000000000 0xc Core/Src/stm32l0xx_it.o + .group 0x0000000000000000 0xc Core/Src/stm32l0xx_it.o + .group 0x0000000000000000 0xc Core/Src/stm32l0xx_it.o + .group 0x0000000000000000 0xc Core/Src/stm32l0xx_it.o + .group 0x0000000000000000 0xc Core/Src/stm32l0xx_it.o + .group 0x0000000000000000 0xc Core/Src/stm32l0xx_it.o + .group 0x0000000000000000 0xc Core/Src/stm32l0xx_it.o + .group 0x0000000000000000 0xc Core/Src/stm32l0xx_it.o + .text 0x0000000000000000 0x0 Core/Src/stm32l0xx_it.o + .data 0x0000000000000000 0x0 Core/Src/stm32l0xx_it.o + .bss 0x0000000000000000 0x0 Core/Src/stm32l0xx_it.o + .debug_macro 0x0000000000000000 0xa8a Core/Src/stm32l0xx_it.o + .debug_macro 0x0000000000000000 0x119 Core/Src/stm32l0xx_it.o + .debug_macro 0x0000000000000000 0x2e Core/Src/stm32l0xx_it.o + .debug_macro 0x0000000000000000 0x28 Core/Src/stm32l0xx_it.o + .debug_macro 0x0000000000000000 0x22 Core/Src/stm32l0xx_it.o + .debug_macro 0x0000000000000000 0x8e Core/Src/stm32l0xx_it.o + .debug_macro 0x0000000000000000 0x51 Core/Src/stm32l0xx_it.o + .debug_macro 0x0000000000000000 0x103 Core/Src/stm32l0xx_it.o + .debug_macro 0x0000000000000000 0x6a Core/Src/stm32l0xx_it.o + .debug_macro 0x0000000000000000 0x1df Core/Src/stm32l0xx_it.o + .debug_macro 0x0000000000000000 0x1c Core/Src/stm32l0xx_it.o + .debug_macro 0x0000000000000000 0x22 Core/Src/stm32l0xx_it.o + .debug_macro 0x0000000000000000 0xb5 Core/Src/stm32l0xx_it.o + .debug_macro 0x0000000000000000 0x3ad Core/Src/stm32l0xx_it.o + .debug_macro 0x0000000000000000 0x7b9c Core/Src/stm32l0xx_it.o + .debug_macro 0x0000000000000000 0x3c Core/Src/stm32l0xx_it.o + .debug_macro 0x0000000000000000 0x352b Core/Src/stm32l0xx_it.o + .debug_macro 0x0000000000000000 0x174 Core/Src/stm32l0xx_it.o + .debug_macro 0x0000000000000000 0x5b Core/Src/stm32l0xx_it.o + .debug_macro 0x0000000000000000 0x899 Core/Src/stm32l0xx_it.o + .debug_macro 0x0000000000000000 0x42e Core/Src/stm32l0xx_it.o + .debug_macro 0x0000000000000000 0x182 Core/Src/stm32l0xx_it.o + .debug_macro 0x0000000000000000 0x13f Core/Src/stm32l0xx_it.o + .debug_macro 0x0000000000000000 0xf1 Core/Src/stm32l0xx_it.o + .debug_macro 0x0000000000000000 0x28e Core/Src/stm32l0xx_it.o + .debug_macro 0x0000000000000000 0x28 Core/Src/stm32l0xx_it.o + .debug_macro 0x0000000000000000 0x129 Core/Src/stm32l0xx_it.o + .debug_macro 0x0000000000000000 0x244 Core/Src/stm32l0xx_it.o + .debug_macro 0x0000000000000000 0x22c Core/Src/stm32l0xx_it.o + .debug_macro 0x0000000000000000 0x5b Core/Src/stm32l0xx_it.o + .debug_macro 0x0000000000000000 0xa5 Core/Src/stm32l0xx_it.o + .debug_macro 0x0000000000000000 0x187 Core/Src/stm32l0xx_it.o + .debug_macro 0x0000000000000000 0x16 Core/Src/stm32l0xx_it.o + .debug_macro 0x0000000000000000 0x11c Core/Src/stm32l0xx_it.o + .debug_macro 0x0000000000000000 0x285 Core/Src/stm32l0xx_it.o + .debug_macro 0x0000000000000000 0x246 Core/Src/stm32l0xx_it.o + .debug_macro 0x0000000000000000 0x229 Core/Src/stm32l0xx_it.o + .debug_macro 0x0000000000000000 0x3b4 Core/Src/stm32l0xx_it.o + .debug_macro 0x0000000000000000 0x13d Core/Src/stm32l0xx_it.o + .debug_macro 0x0000000000000000 0x12d Core/Src/stm32l0xx_it.o + .debug_macro 0x0000000000000000 0x109 Core/Src/stm32l0xx_it.o + .debug_macro 0x0000000000000000 0xa7 Core/Src/stm32l0xx_it.o + .debug_macro 0x0000000000000000 0x16 Core/Src/stm32l0xx_it.o + .debug_macro 0x0000000000000000 0x2a Core/Src/stm32l0xx_it.o + .debug_macro 0x0000000000000000 0xdb Core/Src/stm32l0xx_it.o + .debug_macro 0x0000000000000000 0x28 Core/Src/stm32l0xx_it.o + .group 0x0000000000000000 0xc Core/Src/syscalls.o + .group 0x0000000000000000 0xc Core/Src/syscalls.o + .group 0x0000000000000000 0xc Core/Src/syscalls.o + .group 0x0000000000000000 0xc Core/Src/syscalls.o + .group 0x0000000000000000 0xc Core/Src/syscalls.o + .group 0x0000000000000000 0xc Core/Src/syscalls.o + .group 0x0000000000000000 0xc Core/Src/syscalls.o + .group 0x0000000000000000 0xc Core/Src/syscalls.o + .group 0x0000000000000000 0xc Core/Src/syscalls.o + .group 0x0000000000000000 0xc Core/Src/syscalls.o + .group 0x0000000000000000 0xc Core/Src/syscalls.o + .group 0x0000000000000000 0xc Core/Src/syscalls.o + .group 0x0000000000000000 0xc Core/Src/syscalls.o + .group 0x0000000000000000 0xc Core/Src/syscalls.o + .group 0x0000000000000000 0xc Core/Src/syscalls.o + .group 0x0000000000000000 0xc Core/Src/syscalls.o + .group 0x0000000000000000 0xc Core/Src/syscalls.o + .group 0x0000000000000000 0xc Core/Src/syscalls.o + .group 0x0000000000000000 0xc Core/Src/syscalls.o + .group 0x0000000000000000 0xc Core/Src/syscalls.o + .group 0x0000000000000000 0xc Core/Src/syscalls.o + .group 0x0000000000000000 0xc Core/Src/syscalls.o + .group 0x0000000000000000 0xc Core/Src/syscalls.o + .group 0x0000000000000000 0xc Core/Src/syscalls.o + .group 0x0000000000000000 0xc Core/Src/syscalls.o + .group 0x0000000000000000 0xc Core/Src/syscalls.o + .group 0x0000000000000000 0xc Core/Src/syscalls.o + .group 0x0000000000000000 0xc Core/Src/syscalls.o + .group 0x0000000000000000 0xc Core/Src/syscalls.o + .group 0x0000000000000000 0xc Core/Src/syscalls.o + .group 0x0000000000000000 0xc Core/Src/syscalls.o + .group 0x0000000000000000 0xc Core/Src/syscalls.o + .group 0x0000000000000000 0xc Core/Src/syscalls.o + .group 0x0000000000000000 0xc Core/Src/syscalls.o + .group 0x0000000000000000 0xc Core/Src/syscalls.o + .group 0x0000000000000000 0xc Core/Src/syscalls.o + .group 0x0000000000000000 0xc Core/Src/syscalls.o + .group 0x0000000000000000 0xc Core/Src/syscalls.o + .group 0x0000000000000000 0xc Core/Src/syscalls.o + .group 0x0000000000000000 0xc Core/Src/syscalls.o + .group 0x0000000000000000 0xc Core/Src/syscalls.o + .group 0x0000000000000000 0xc Core/Src/syscalls.o + .group 0x0000000000000000 0xc Core/Src/syscalls.o + .group 0x0000000000000000 0xc Core/Src/syscalls.o + .group 0x0000000000000000 0xc Core/Src/syscalls.o + .group 0x0000000000000000 0xc Core/Src/syscalls.o + .group 0x0000000000000000 0xc Core/Src/syscalls.o + .text 0x0000000000000000 0x0 Core/Src/syscalls.o + .data 0x0000000000000000 0x0 Core/Src/syscalls.o + .bss 0x0000000000000000 0x0 Core/Src/syscalls.o + .text.initialise_monitor_handles + 0x0000000000000000 0x2 Core/Src/syscalls.o + .text._getpid 0x0000000000000000 0x4 Core/Src/syscalls.o + .text._kill 0x0000000000000000 0x10 Core/Src/syscalls.o + .text._exit 0x0000000000000000 0xc Core/Src/syscalls.o + .text._read 0x0000000000000000 0x1a Core/Src/syscalls.o + .text._write 0x0000000000000000 0x1a Core/Src/syscalls.o + .text._close 0x0000000000000000 0x6 Core/Src/syscalls.o + .text._fstat 0x0000000000000000 0xa Core/Src/syscalls.o + .text._isatty 0x0000000000000000 0x4 Core/Src/syscalls.o + .text._lseek 0x0000000000000000 0x4 Core/Src/syscalls.o + .text._open 0x0000000000000000 0xa Core/Src/syscalls.o + .text._wait 0x0000000000000000 0x10 Core/Src/syscalls.o + .text._unlink 0x0000000000000000 0x10 Core/Src/syscalls.o + .text._times 0x0000000000000000 0x6 Core/Src/syscalls.o + .text._stat 0x0000000000000000 0xa Core/Src/syscalls.o + .text._link 0x0000000000000000 0x10 Core/Src/syscalls.o + .text._fork 0x0000000000000000 0x10 Core/Src/syscalls.o + .text._execve 0x0000000000000000 0x10 Core/Src/syscalls.o + .bss.__env 0x0000000000000000 0x4 Core/Src/syscalls.o + .data.environ 0x0000000000000000 0x4 Core/Src/syscalls.o + .debug_info 0x0000000000000000 0x10e8 Core/Src/syscalls.o + .debug_abbrev 0x0000000000000000 0x2fe Core/Src/syscalls.o + .debug_loc 0x0000000000000000 0x491 Core/Src/syscalls.o + .debug_aranges + 0x0000000000000000 0xa8 Core/Src/syscalls.o + .debug_ranges 0x0000000000000000 0xb0 Core/Src/syscalls.o + .debug_macro 0x0000000000000000 0x24c Core/Src/syscalls.o + .debug_macro 0x0000000000000000 0xa8a Core/Src/syscalls.o + .debug_macro 0x0000000000000000 0x22 Core/Src/syscalls.o + .debug_macro 0x0000000000000000 0x4c Core/Src/syscalls.o + .debug_macro 0x0000000000000000 0x18 Core/Src/syscalls.o + .debug_macro 0x0000000000000000 0x94 Core/Src/syscalls.o + .debug_macro 0x0000000000000000 0x3c Core/Src/syscalls.o + .debug_macro 0x0000000000000000 0x34 Core/Src/syscalls.o + .debug_macro 0x0000000000000000 0x57 Core/Src/syscalls.o + .debug_macro 0x0000000000000000 0x174 Core/Src/syscalls.o + .debug_macro 0x0000000000000000 0x339 Core/Src/syscalls.o + .debug_macro 0x0000000000000000 0x16 Core/Src/syscalls.o + .debug_macro 0x0000000000000000 0x43 Core/Src/syscalls.o + .debug_macro 0x0000000000000000 0x34 Core/Src/syscalls.o + .debug_macro 0x0000000000000000 0x10 Core/Src/syscalls.o + .debug_macro 0x0000000000000000 0x58 Core/Src/syscalls.o + .debug_macro 0x0000000000000000 0x71 Core/Src/syscalls.o + .debug_macro 0x0000000000000000 0x1c Core/Src/syscalls.o + .debug_macro 0x0000000000000000 0x12a Core/Src/syscalls.o + .debug_macro 0x0000000000000000 0x10 Core/Src/syscalls.o + .debug_macro 0x0000000000000000 0x35 Core/Src/syscalls.o + .debug_macro 0x0000000000000000 0x10 Core/Src/syscalls.o + .debug_macro 0x0000000000000000 0x10 Core/Src/syscalls.o + .debug_macro 0x0000000000000000 0x10 Core/Src/syscalls.o + .debug_macro 0x0000000000000000 0x6a Core/Src/syscalls.o + .debug_macro 0x0000000000000000 0x1c Core/Src/syscalls.o + .debug_macro 0x0000000000000000 0x52 Core/Src/syscalls.o + .debug_macro 0x0000000000000000 0x22 Core/Src/syscalls.o + .debug_macro 0x0000000000000000 0x10 Core/Src/syscalls.o + .debug_macro 0x0000000000000000 0x40 Core/Src/syscalls.o + .debug_macro 0x0000000000000000 0xd5 Core/Src/syscalls.o + .debug_macro 0x0000000000000000 0x1c Core/Src/syscalls.o + .debug_macro 0x0000000000000000 0x3d Core/Src/syscalls.o + .debug_macro 0x0000000000000000 0x35 Core/Src/syscalls.o + .debug_macro 0x0000000000000000 0x12c Core/Src/syscalls.o + .debug_macro 0x0000000000000000 0x16 Core/Src/syscalls.o + .debug_macro 0x0000000000000000 0x16 Core/Src/syscalls.o + .debug_macro 0x0000000000000000 0x29 Core/Src/syscalls.o + .debug_macro 0x0000000000000000 0x10 Core/Src/syscalls.o + .debug_macro 0x0000000000000000 0x241 Core/Src/syscalls.o + .debug_macro 0x0000000000000000 0x1c Core/Src/syscalls.o + .debug_macro 0x0000000000000000 0x10 Core/Src/syscalls.o + .debug_macro 0x0000000000000000 0x10 Core/Src/syscalls.o + .debug_macro 0x0000000000000000 0x16 Core/Src/syscalls.o + .debug_macro 0x0000000000000000 0x145 Core/Src/syscalls.o + .debug_macro 0x0000000000000000 0x189 Core/Src/syscalls.o + .debug_macro 0x0000000000000000 0x16 Core/Src/syscalls.o + .debug_macro 0x0000000000000000 0xce Core/Src/syscalls.o + .debug_line 0x0000000000000000 0x8a5 Core/Src/syscalls.o + .debug_str 0x0000000000000000 0x8e55 Core/Src/syscalls.o + .comment 0x0000000000000000 0x54 Core/Src/syscalls.o + .debug_frame 0x0000000000000000 0x184 Core/Src/syscalls.o + .ARM.attributes + 0x0000000000000000 0x2c Core/Src/syscalls.o + .group 0x0000000000000000 0xc Core/Src/sysmem.o + .group 0x0000000000000000 0xc Core/Src/sysmem.o + .group 0x0000000000000000 0xc Core/Src/sysmem.o + .group 0x0000000000000000 0xc Core/Src/sysmem.o + .group 0x0000000000000000 0xc Core/Src/sysmem.o + .group 0x0000000000000000 0xc Core/Src/sysmem.o + .group 0x0000000000000000 0xc Core/Src/sysmem.o + .group 0x0000000000000000 0xc Core/Src/sysmem.o + .group 0x0000000000000000 0xc Core/Src/sysmem.o + .group 0x0000000000000000 0xc Core/Src/sysmem.o + .group 0x0000000000000000 0xc Core/Src/sysmem.o + .group 0x0000000000000000 0xc Core/Src/sysmem.o + .group 0x0000000000000000 0xc Core/Src/sysmem.o + .group 0x0000000000000000 0xc Core/Src/sysmem.o + .group 0x0000000000000000 0xc Core/Src/sysmem.o + .group 0x0000000000000000 0xc Core/Src/sysmem.o + .group 0x0000000000000000 0xc Core/Src/sysmem.o + .group 0x0000000000000000 0xc Core/Src/sysmem.o + .group 0x0000000000000000 0xc Core/Src/sysmem.o + .group 0x0000000000000000 0xc Core/Src/sysmem.o + .group 0x0000000000000000 0xc Core/Src/sysmem.o + .group 0x0000000000000000 0xc Core/Src/sysmem.o + .text 0x0000000000000000 0x0 Core/Src/sysmem.o + .data 0x0000000000000000 0x0 Core/Src/sysmem.o + .bss 0x0000000000000000 0x0 Core/Src/sysmem.o + .text._sbrk 0x0000000000000000 0x40 Core/Src/sysmem.o + .bss.__sbrk_heap_end + 0x0000000000000000 0x4 Core/Src/sysmem.o + .debug_info 0x0000000000000000 0xa4e Core/Src/sysmem.o + .debug_abbrev 0x0000000000000000 0x1f4 Core/Src/sysmem.o + .debug_loc 0x0000000000000000 0x69 Core/Src/sysmem.o + .debug_aranges + 0x0000000000000000 0x20 Core/Src/sysmem.o + .debug_ranges 0x0000000000000000 0x10 Core/Src/sysmem.o + .debug_macro 0x0000000000000000 0xff Core/Src/sysmem.o + .debug_macro 0x0000000000000000 0xa8a Core/Src/sysmem.o + .debug_macro 0x0000000000000000 0x10 Core/Src/sysmem.o + .debug_macro 0x0000000000000000 0x22 Core/Src/sysmem.o + .debug_macro 0x0000000000000000 0x4c Core/Src/sysmem.o + .debug_macro 0x0000000000000000 0x18 Core/Src/sysmem.o + .debug_macro 0x0000000000000000 0x94 Core/Src/sysmem.o + .debug_macro 0x0000000000000000 0x3c Core/Src/sysmem.o + .debug_macro 0x0000000000000000 0x34 Core/Src/sysmem.o + .debug_macro 0x0000000000000000 0x174 Core/Src/sysmem.o + .debug_macro 0x0000000000000000 0x16 Core/Src/sysmem.o + .debug_macro 0x0000000000000000 0x43 Core/Src/sysmem.o + .debug_macro 0x0000000000000000 0x57 Core/Src/sysmem.o + .debug_macro 0x0000000000000000 0x34 Core/Src/sysmem.o + .debug_macro 0x0000000000000000 0x10 Core/Src/sysmem.o + .debug_macro 0x0000000000000000 0x58 Core/Src/sysmem.o + .debug_macro 0x0000000000000000 0x71 Core/Src/sysmem.o + .debug_macro 0x0000000000000000 0x1c Core/Src/sysmem.o + .debug_macro 0x0000000000000000 0x12a Core/Src/sysmem.o + .debug_macro 0x0000000000000000 0x23b Core/Src/sysmem.o + .debug_macro 0x0000000000000000 0x103 Core/Src/sysmem.o + .debug_macro 0x0000000000000000 0x6a Core/Src/sysmem.o + .debug_macro 0x0000000000000000 0x1df Core/Src/sysmem.o + .debug_line 0x0000000000000000 0x4f9 Core/Src/sysmem.o + .debug_str 0x0000000000000000 0x6204 Core/Src/sysmem.o + .comment 0x0000000000000000 0x54 Core/Src/sysmem.o + .debug_frame 0x0000000000000000 0x28 Core/Src/sysmem.o + .ARM.attributes + 0x0000000000000000 0x2c Core/Src/sysmem.o + .group 0x0000000000000000 0xc Core/Src/system_stm32l0xx.o + .group 0x0000000000000000 0xc Core/Src/system_stm32l0xx.o + .group 0x0000000000000000 0xc Core/Src/system_stm32l0xx.o + .group 0x0000000000000000 0xc Core/Src/system_stm32l0xx.o + .group 0x0000000000000000 0xc Core/Src/system_stm32l0xx.o + .group 0x0000000000000000 0xc Core/Src/system_stm32l0xx.o + .group 0x0000000000000000 0xc Core/Src/system_stm32l0xx.o + .group 0x0000000000000000 0xc Core/Src/system_stm32l0xx.o + .group 0x0000000000000000 0xc Core/Src/system_stm32l0xx.o + .group 0x0000000000000000 0xc Core/Src/system_stm32l0xx.o + .group 0x0000000000000000 0xc Core/Src/system_stm32l0xx.o + .group 0x0000000000000000 0xc Core/Src/system_stm32l0xx.o + .group 0x0000000000000000 0xc Core/Src/system_stm32l0xx.o + .group 0x0000000000000000 0xc Core/Src/system_stm32l0xx.o + .group 0x0000000000000000 0xc Core/Src/system_stm32l0xx.o + .group 0x0000000000000000 0xc Core/Src/system_stm32l0xx.o + .group 0x0000000000000000 0xc Core/Src/system_stm32l0xx.o + .group 0x0000000000000000 0xc Core/Src/system_stm32l0xx.o + .group 0x0000000000000000 0xc Core/Src/system_stm32l0xx.o + .group 0x0000000000000000 0xc Core/Src/system_stm32l0xx.o + .group 0x0000000000000000 0xc Core/Src/system_stm32l0xx.o + .group 0x0000000000000000 0xc Core/Src/system_stm32l0xx.o + .group 0x0000000000000000 0xc Core/Src/system_stm32l0xx.o + .group 0x0000000000000000 0xc Core/Src/system_stm32l0xx.o + .group 0x0000000000000000 0xc Core/Src/system_stm32l0xx.o + .group 0x0000000000000000 0xc Core/Src/system_stm32l0xx.o + .group 0x0000000000000000 0xc Core/Src/system_stm32l0xx.o + .group 0x0000000000000000 0xc Core/Src/system_stm32l0xx.o + .group 0x0000000000000000 0xc Core/Src/system_stm32l0xx.o + .group 0x0000000000000000 0xc Core/Src/system_stm32l0xx.o + .group 0x0000000000000000 0xc Core/Src/system_stm32l0xx.o + .group 0x0000000000000000 0xc Core/Src/system_stm32l0xx.o + .group 0x0000000000000000 0xc Core/Src/system_stm32l0xx.o + .group 0x0000000000000000 0xc Core/Src/system_stm32l0xx.o + .text 0x0000000000000000 0x0 Core/Src/system_stm32l0xx.o + .data 0x0000000000000000 0x0 Core/Src/system_stm32l0xx.o + .bss 0x0000000000000000 0x0 Core/Src/system_stm32l0xx.o + .text.SystemCoreClockUpdate + 0x0000000000000000 0x9c Core/Src/system_stm32l0xx.o + .debug_macro 0x0000000000000000 0xa8a Core/Src/system_stm32l0xx.o + .debug_macro 0x0000000000000000 0x2e Core/Src/system_stm32l0xx.o + .debug_macro 0x0000000000000000 0x28 Core/Src/system_stm32l0xx.o + .debug_macro 0x0000000000000000 0x22 Core/Src/system_stm32l0xx.o + .debug_macro 0x0000000000000000 0x8e Core/Src/system_stm32l0xx.o + .debug_macro 0x0000000000000000 0x51 Core/Src/system_stm32l0xx.o + .debug_macro 0x0000000000000000 0x103 Core/Src/system_stm32l0xx.o + .debug_macro 0x0000000000000000 0x6a Core/Src/system_stm32l0xx.o + .debug_macro 0x0000000000000000 0x1df Core/Src/system_stm32l0xx.o + .debug_macro 0x0000000000000000 0x1c Core/Src/system_stm32l0xx.o + .debug_macro 0x0000000000000000 0x22 Core/Src/system_stm32l0xx.o + .debug_macro 0x0000000000000000 0xb5 Core/Src/system_stm32l0xx.o + .debug_macro 0x0000000000000000 0x3ad Core/Src/system_stm32l0xx.o + .debug_macro 0x0000000000000000 0x7b9c Core/Src/system_stm32l0xx.o + .debug_macro 0x0000000000000000 0x3c Core/Src/system_stm32l0xx.o + .debug_macro 0x0000000000000000 0x119 Core/Src/system_stm32l0xx.o + .debug_macro 0x0000000000000000 0x352b Core/Src/system_stm32l0xx.o + .debug_macro 0x0000000000000000 0x174 Core/Src/system_stm32l0xx.o + .debug_macro 0x0000000000000000 0x5b Core/Src/system_stm32l0xx.o + .debug_macro 0x0000000000000000 0x899 Core/Src/system_stm32l0xx.o + .debug_macro 0x0000000000000000 0x42e Core/Src/system_stm32l0xx.o + .debug_macro 0x0000000000000000 0x182 Core/Src/system_stm32l0xx.o + .debug_macro 0x0000000000000000 0x13f Core/Src/system_stm32l0xx.o + .debug_macro 0x0000000000000000 0xf1 Core/Src/system_stm32l0xx.o + .debug_macro 0x0000000000000000 0x28e Core/Src/system_stm32l0xx.o + .debug_macro 0x0000000000000000 0x28 Core/Src/system_stm32l0xx.o + .debug_macro 0x0000000000000000 0x129 Core/Src/system_stm32l0xx.o + .debug_macro 0x0000000000000000 0x244 Core/Src/system_stm32l0xx.o + .debug_macro 0x0000000000000000 0x22c Core/Src/system_stm32l0xx.o + .debug_macro 0x0000000000000000 0x5b Core/Src/system_stm32l0xx.o + .debug_macro 0x0000000000000000 0xa5 Core/Src/system_stm32l0xx.o + .debug_macro 0x0000000000000000 0x187 Core/Src/system_stm32l0xx.o + .debug_macro 0x0000000000000000 0x16 Core/Src/system_stm32l0xx.o + .debug_macro 0x0000000000000000 0x11c Core/Src/system_stm32l0xx.o + .text 0x0000000000000000 0x14 Core/Startup/startup_stm32l011f4ux.o + .data 0x0000000000000000 0x0 Core/Startup/startup_stm32l011f4ux.o + .bss 0x0000000000000000 0x0 Core/Startup/startup_stm32l011f4ux.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .text 0x0000000000000000 0x0 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .data 0x0000000000000000 0x0 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .bss 0x0000000000000000 0x0 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .text.HAL_MspInit + 0x0000000000000000 0x2 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .text.HAL_MspDeInit + 0x0000000000000000 0x2 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .text.HAL_DeInit + 0x0000000000000000 0x28 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .text.HAL_GetTickPrio + 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .text.HAL_SetTickFreq + 0x0000000000000000 0x28 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .text.HAL_GetTickFreq + 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .text.HAL_SuspendTick + 0x0000000000000000 0x10 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .text.HAL_ResumeTick + 0x0000000000000000 0x10 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .text.HAL_GetHalVersion + 0x0000000000000000 0x8 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .text.HAL_GetREVID + 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .text.HAL_GetDEVID + 0x0000000000000000 0x10 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .text.HAL_GetUIDw0 + 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .text.HAL_GetUIDw1 + 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .text.HAL_GetUIDw2 + 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .text.HAL_DBGMCU_EnableDBGSleepMode + 0x0000000000000000 0x10 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .text.HAL_DBGMCU_DisableDBGSleepMode + 0x0000000000000000 0x10 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .text.HAL_DBGMCU_EnableDBGStopMode + 0x0000000000000000 0x10 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .text.HAL_DBGMCU_DisableDBGStopMode + 0x0000000000000000 0x10 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .text.HAL_DBGMCU_EnableDBGStandbyMode + 0x0000000000000000 0x10 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .text.HAL_DBGMCU_DisableDBGStandbyMode + 0x0000000000000000 0x10 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .text.HAL_DBGMCU_DBG_EnableLowPowerConfig + 0x0000000000000000 0x10 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .text.HAL_DBGMCU_DBG_DisableLowPowerConfig + 0x0000000000000000 0x10 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .text.HAL_SYSCFG_GetBootMode + 0x0000000000000000 0x10 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .text.HAL_SYSCFG_VREFINT_OutputSelect + 0x0000000000000000 0x18 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .text.HAL_SYSCFG_Enable_Lock_VREFINT + 0x0000000000000000 0x14 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .text.HAL_SYSCFG_Disable_Lock_VREFINT + 0x0000000000000000 0x10 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .debug_macro 0x0000000000000000 0xa8a Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .debug_macro 0x0000000000000000 0x119 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .debug_macro 0x0000000000000000 0x2e Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .debug_macro 0x0000000000000000 0x28 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .debug_macro 0x0000000000000000 0x22 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .debug_macro 0x0000000000000000 0x8e Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .debug_macro 0x0000000000000000 0x51 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .debug_macro 0x0000000000000000 0x103 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .debug_macro 0x0000000000000000 0x6a Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .debug_macro 0x0000000000000000 0x1df Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .debug_macro 0x0000000000000000 0x1c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .debug_macro 0x0000000000000000 0x22 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .debug_macro 0x0000000000000000 0xb5 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .debug_macro 0x0000000000000000 0x3ad Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .debug_macro 0x0000000000000000 0x7b9c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .debug_macro 0x0000000000000000 0x3c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .debug_macro 0x0000000000000000 0x352b Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .debug_macro 0x0000000000000000 0x174 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .debug_macro 0x0000000000000000 0x5b Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .debug_macro 0x0000000000000000 0x899 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .debug_macro 0x0000000000000000 0x42e Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .debug_macro 0x0000000000000000 0x182 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .debug_macro 0x0000000000000000 0x13f Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .debug_macro 0x0000000000000000 0xf1 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .debug_macro 0x0000000000000000 0x28e Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .debug_macro 0x0000000000000000 0x28 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .debug_macro 0x0000000000000000 0x129 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .debug_macro 0x0000000000000000 0x244 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .debug_macro 0x0000000000000000 0x22c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .debug_macro 0x0000000000000000 0x5b Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .debug_macro 0x0000000000000000 0xa5 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .debug_macro 0x0000000000000000 0x187 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .debug_macro 0x0000000000000000 0x16 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .debug_macro 0x0000000000000000 0x11c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .text 0x0000000000000000 0x0 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .data 0x0000000000000000 0x0 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .bss 0x0000000000000000 0x0 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .text.HAL_NVIC_EnableIRQ + 0x0000000000000000 0x18 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .text.HAL_NVIC_DisableIRQ + 0x0000000000000000 0x20 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .text.HAL_NVIC_SystemReset + 0x0000000000000000 0x1c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .text.HAL_NVIC_GetPriority + 0x0000000000000000 0x3c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .text.HAL_NVIC_SetPendingIRQ + 0x0000000000000000 0x18 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .text.HAL_NVIC_GetPendingIRQ + 0x0000000000000000 0x1c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .text.HAL_NVIC_ClearPendingIRQ + 0x0000000000000000 0x1c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .text.HAL_SYSTICK_CLKSourceConfig + 0x0000000000000000 0x1c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .text.HAL_SYSTICK_Callback + 0x0000000000000000 0x2 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .text.HAL_SYSTICK_IRQHandler + 0x0000000000000000 0x8 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .debug_macro 0x0000000000000000 0xa8a Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x119 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x2e Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x28 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x22 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x8e Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x51 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x103 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x6a Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x1df Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x1c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x22 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .debug_macro 0x0000000000000000 0xb5 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x3ad Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x7b9c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x3c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x352b Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x174 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x5b Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x899 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x42e Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x182 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x13f Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .debug_macro 0x0000000000000000 0xf1 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x28e Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x28 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x129 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x244 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x22c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x5b Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .debug_macro 0x0000000000000000 0xa5 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x187 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x16 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x11c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .text 0x0000000000000000 0x0 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .data 0x0000000000000000 0x0 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .bss 0x0000000000000000 0x0 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .text.HAL_DMA_Init + 0x0000000000000000 0x88 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .text.HAL_DMA_DeInit + 0x0000000000000000 0x60 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .text.HAL_DMA_Start + 0x0000000000000000 0x64 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .text.HAL_DMA_Start_IT + 0x0000000000000000 0x80 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .text.HAL_DMA_Abort + 0x0000000000000000 0x40 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .text.HAL_DMA_Abort_IT + 0x0000000000000000 0x4a Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .text.HAL_DMA_PollForTransfer + 0x0000000000000000 0xc4 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .text.HAL_DMA_IRQHandler + 0x0000000000000000 0x96 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .text.HAL_DMA_RegisterCallback + 0x0000000000000000 0x40 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .text.HAL_DMA_UnRegisterCallback + 0x0000000000000000 0x4e Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .text.HAL_DMA_GetState + 0x0000000000000000 0x8 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .text.HAL_DMA_GetError + 0x0000000000000000 0x4 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .debug_info 0x0000000000000000 0x962 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .debug_abbrev 0x0000000000000000 0x23f Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .debug_loc 0x0000000000000000 0x853 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .debug_aranges + 0x0000000000000000 0x78 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .debug_ranges 0x0000000000000000 0xc8 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .debug_macro 0x0000000000000000 0x197 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .debug_macro 0x0000000000000000 0xa8a Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .debug_macro 0x0000000000000000 0x119 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .debug_macro 0x0000000000000000 0x2e Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .debug_macro 0x0000000000000000 0x28 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .debug_macro 0x0000000000000000 0x22 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .debug_macro 0x0000000000000000 0x8e Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .debug_macro 0x0000000000000000 0x51 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .debug_macro 0x0000000000000000 0x103 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .debug_macro 0x0000000000000000 0x6a Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .debug_macro 0x0000000000000000 0x1df Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .debug_macro 0x0000000000000000 0x1c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .debug_macro 0x0000000000000000 0x22 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .debug_macro 0x0000000000000000 0xb5 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .debug_macro 0x0000000000000000 0x3ad Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .debug_macro 0x0000000000000000 0x7b9c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .debug_macro 0x0000000000000000 0x3c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .debug_macro 0x0000000000000000 0x352b Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .debug_macro 0x0000000000000000 0x174 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .debug_macro 0x0000000000000000 0x5b Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .debug_macro 0x0000000000000000 0x899 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .debug_macro 0x0000000000000000 0x42e Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .debug_macro 0x0000000000000000 0x182 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .debug_macro 0x0000000000000000 0x13f Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .debug_macro 0x0000000000000000 0xf1 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .debug_macro 0x0000000000000000 0x28e Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .debug_macro 0x0000000000000000 0x28 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .debug_macro 0x0000000000000000 0x129 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .debug_macro 0x0000000000000000 0x244 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .debug_macro 0x0000000000000000 0x22c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .debug_macro 0x0000000000000000 0x5b Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .debug_macro 0x0000000000000000 0xa5 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .debug_macro 0x0000000000000000 0x187 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .debug_macro 0x0000000000000000 0x16 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .debug_macro 0x0000000000000000 0x11c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .debug_line 0x0000000000000000 0xeed Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .debug_str 0x0000000000000000 0x5ac2d Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .comment 0x0000000000000000 0x54 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .debug_frame 0x0000000000000000 0x164 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .ARM.attributes + 0x0000000000000000 0x2c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .text 0x0000000000000000 0x0 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .data 0x0000000000000000 0x0 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .bss 0x0000000000000000 0x0 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .text.HAL_EXTI_SetConfigLine + 0x0000000000000000 0xa4 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .text.HAL_EXTI_GetConfigLine + 0x0000000000000000 0x8c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .text.HAL_EXTI_ClearConfigLine + 0x0000000000000000 0x64 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .text.HAL_EXTI_RegisterCallback + 0x0000000000000000 0xe Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .text.HAL_EXTI_GetHandle + 0x0000000000000000 0xe Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .text.HAL_EXTI_IRQHandler + 0x0000000000000000 0x24 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .text.HAL_EXTI_GetPending + 0x0000000000000000 0x18 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .text.HAL_EXTI_ClearPending + 0x0000000000000000 0x14 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .text.HAL_EXTI_GenerateSWI + 0x0000000000000000 0x14 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .debug_info 0x0000000000000000 0x6b2 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .debug_abbrev 0x0000000000000000 0x210 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .debug_loc 0x0000000000000000 0x3ce Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .debug_aranges + 0x0000000000000000 0x60 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .debug_ranges 0x0000000000000000 0x50 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .debug_macro 0x0000000000000000 0x197 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .debug_macro 0x0000000000000000 0xa8a Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .debug_macro 0x0000000000000000 0x119 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .debug_macro 0x0000000000000000 0x2e Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .debug_macro 0x0000000000000000 0x28 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .debug_macro 0x0000000000000000 0x22 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .debug_macro 0x0000000000000000 0x8e Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .debug_macro 0x0000000000000000 0x51 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .debug_macro 0x0000000000000000 0x103 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .debug_macro 0x0000000000000000 0x6a Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .debug_macro 0x0000000000000000 0x1df Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .debug_macro 0x0000000000000000 0x1c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .debug_macro 0x0000000000000000 0x22 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .debug_macro 0x0000000000000000 0xb5 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .debug_macro 0x0000000000000000 0x3ad Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .debug_macro 0x0000000000000000 0x7b9c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .debug_macro 0x0000000000000000 0x3c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .debug_macro 0x0000000000000000 0x352b Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .debug_macro 0x0000000000000000 0x174 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .debug_macro 0x0000000000000000 0x5b Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .debug_macro 0x0000000000000000 0x899 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .debug_macro 0x0000000000000000 0x42e Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .debug_macro 0x0000000000000000 0x182 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .debug_macro 0x0000000000000000 0x13f Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .debug_macro 0x0000000000000000 0xf1 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .debug_macro 0x0000000000000000 0x28e Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .debug_macro 0x0000000000000000 0x28 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .debug_macro 0x0000000000000000 0x129 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .debug_macro 0x0000000000000000 0x244 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .debug_macro 0x0000000000000000 0x22c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .debug_macro 0x0000000000000000 0x5b Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .debug_macro 0x0000000000000000 0xa5 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .debug_macro 0x0000000000000000 0x187 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .debug_macro 0x0000000000000000 0x16 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .debug_macro 0x0000000000000000 0x11c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .debug_line 0x0000000000000000 0xa69 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .debug_str 0x0000000000000000 0x5a9fd Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .comment 0x0000000000000000 0x54 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .debug_frame 0x0000000000000000 0xd0 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .ARM.attributes + 0x0000000000000000 0x2c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .text 0x0000000000000000 0x0 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .data 0x0000000000000000 0x0 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .bss 0x0000000000000000 0x0 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .text.FLASH_SetErrorCode + 0x0000000000000000 0xac Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .text.HAL_FLASH_Program_IT + 0x0000000000000000 0x38 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .text.HAL_FLASH_EndOfOperationCallback + 0x0000000000000000 0x2 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .text.HAL_FLASH_OperationErrorCallback + 0x0000000000000000 0x2 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .text.HAL_FLASH_IRQHandler + 0x0000000000000000 0xe0 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .text.HAL_FLASH_Unlock + 0x0000000000000000 0x68 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .text.HAL_FLASH_Lock + 0x0000000000000000 0x1c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .text.HAL_FLASH_OB_Unlock + 0x0000000000000000 0x44 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .text.HAL_FLASH_OB_Lock + 0x0000000000000000 0x14 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .text.HAL_FLASH_GetError + 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .text.FLASH_WaitForLastOperation + 0x0000000000000000 0x78 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .text.HAL_FLASH_Program + 0x0000000000000000 0x38 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .text.HAL_FLASH_OB_Launch + 0x0000000000000000 0x20 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .debug_info 0x0000000000000000 0x7a9 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .debug_abbrev 0x0000000000000000 0x32d Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .debug_loc 0x0000000000000000 0x2f6 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .debug_aranges + 0x0000000000000000 0x78 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .debug_ranges 0x0000000000000000 0x68 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .debug_macro 0x0000000000000000 0x198 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .debug_macro 0x0000000000000000 0xa8a Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .debug_macro 0x0000000000000000 0x119 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .debug_macro 0x0000000000000000 0x2e Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .debug_macro 0x0000000000000000 0x28 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .debug_macro 0x0000000000000000 0x22 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .debug_macro 0x0000000000000000 0x8e Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .debug_macro 0x0000000000000000 0x51 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .debug_macro 0x0000000000000000 0x103 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .debug_macro 0x0000000000000000 0x6a Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .debug_macro 0x0000000000000000 0x1df Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .debug_macro 0x0000000000000000 0x1c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .debug_macro 0x0000000000000000 0x22 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .debug_macro 0x0000000000000000 0xb5 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .debug_macro 0x0000000000000000 0x3ad Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .debug_macro 0x0000000000000000 0x7b9c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .debug_macro 0x0000000000000000 0x3c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .debug_macro 0x0000000000000000 0x352b Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .debug_macro 0x0000000000000000 0x174 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .debug_macro 0x0000000000000000 0x5b Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .debug_macro 0x0000000000000000 0x899 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .debug_macro 0x0000000000000000 0x42e Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .debug_macro 0x0000000000000000 0x182 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .debug_macro 0x0000000000000000 0x13f Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .debug_macro 0x0000000000000000 0xf1 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .debug_macro 0x0000000000000000 0x28e Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .debug_macro 0x0000000000000000 0x28 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .debug_macro 0x0000000000000000 0x129 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .debug_macro 0x0000000000000000 0x244 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .debug_macro 0x0000000000000000 0x22c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .debug_macro 0x0000000000000000 0x5b Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .debug_macro 0x0000000000000000 0xa5 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .debug_macro 0x0000000000000000 0x187 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .debug_macro 0x0000000000000000 0x16 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .debug_macro 0x0000000000000000 0x11c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .debug_line 0x0000000000000000 0xc3e Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .debug_str 0x0000000000000000 0x5aab3 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .comment 0x0000000000000000 0x54 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .debug_frame 0x0000000000000000 0x12c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .ARM.attributes + 0x0000000000000000 0x2c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + COMMON 0x0000000000000000 0x18 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .text 0x0000000000000000 0x0 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .data 0x0000000000000000 0x0 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .bss 0x0000000000000000 0x0 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .text.FLASH_OB_ProtectedSectorsConfig + 0x0000000000000000 0x58 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .text.HAL_FLASHEx_OBProgram + 0x0000000000000000 0x114 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .text.HAL_FLASHEx_OBGetConfig + 0x0000000000000000 0x38 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .text.HAL_FLASHEx_AdvOBProgram + 0x0000000000000000 0x16 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .text.HAL_FLASHEx_AdvOBGetConfig + 0x0000000000000000 0x18 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .text.HAL_FLASHEx_OB_SelectPCROP + 0x0000000000000000 0x38 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .text.HAL_FLASHEx_OB_DeSelectPCROP + 0x0000000000000000 0x34 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .text.HAL_FLASHEx_DATAEEPROM_Unlock + 0x0000000000000000 0x30 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .text.HAL_FLASHEx_DATAEEPROM_Lock + 0x0000000000000000 0x14 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .text.HAL_FLASHEx_DATAEEPROM_Erase + 0x0000000000000000 0x24 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .text.HAL_FLASHEx_DATAEEPROM_Program + 0x0000000000000000 0x54 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .text.HAL_FLASHEx_DATAEEPROM_EnableFixedTimeProgram + 0x0000000000000000 0x14 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .text.HAL_FLASHEx_DATAEEPROM_DisableFixedTimeProgram + 0x0000000000000000 0x14 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .text.FLASH_PageErase + 0x0000000000000000 0x2c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .text.HAL_FLASHEx_Erase + 0x0000000000000000 0x78 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .text.HAL_FLASHEx_Erase_IT + 0x0000000000000000 0x58 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .debug_info 0x0000000000000000 0xeeb Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .debug_abbrev 0x0000000000000000 0x334 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .debug_loc 0x0000000000000000 0xb91 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .debug_aranges + 0x0000000000000000 0x98 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .debug_ranges 0x0000000000000000 0x108 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x197 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0xa8a Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x119 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x2e Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x28 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x22 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x8e Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x51 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x103 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x6a Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x1df Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x1c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x22 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0xb5 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x3ad Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x7b9c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x3c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x352b Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x174 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x5b Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x899 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x42e Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x182 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x13f Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0xf1 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x28e Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x28 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x129 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x244 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x22c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x5b Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0xa5 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x187 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x16 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x11c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .debug_line 0x0000000000000000 0xf45 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .debug_str 0x0000000000000000 0x5ad91 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .comment 0x0000000000000000 0x54 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .debug_frame 0x0000000000000000 0x18c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .ARM.attributes + 0x0000000000000000 0x2c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .text 0x0000000000000000 0x0 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .data 0x0000000000000000 0x0 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .bss 0x0000000000000000 0x0 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .RamFunc 0x0000000000000000 0x1b4 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .debug_info 0x0000000000000000 0x4a6 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .debug_abbrev 0x0000000000000000 0x1e2 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .debug_loc 0x0000000000000000 0x18e Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .debug_aranges + 0x0000000000000000 0x40 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .debug_ranges 0x0000000000000000 0x48 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .debug_macro 0x0000000000000000 0x197 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .debug_macro 0x0000000000000000 0xa8a Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .debug_macro 0x0000000000000000 0x119 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .debug_macro 0x0000000000000000 0x2e Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .debug_macro 0x0000000000000000 0x28 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .debug_macro 0x0000000000000000 0x22 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .debug_macro 0x0000000000000000 0x8e Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .debug_macro 0x0000000000000000 0x51 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .debug_macro 0x0000000000000000 0x103 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .debug_macro 0x0000000000000000 0x6a Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .debug_macro 0x0000000000000000 0x1df Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .debug_macro 0x0000000000000000 0x1c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .debug_macro 0x0000000000000000 0x22 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .debug_macro 0x0000000000000000 0xb5 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .debug_macro 0x0000000000000000 0x3ad Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .debug_macro 0x0000000000000000 0x7b9c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .debug_macro 0x0000000000000000 0x3c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .debug_macro 0x0000000000000000 0x352b Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .debug_macro 0x0000000000000000 0x174 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .debug_macro 0x0000000000000000 0x5b Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .debug_macro 0x0000000000000000 0x899 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .debug_macro 0x0000000000000000 0x42e Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .debug_macro 0x0000000000000000 0x182 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .debug_macro 0x0000000000000000 0x13f Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .debug_macro 0x0000000000000000 0xf1 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .debug_macro 0x0000000000000000 0x28e Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .debug_macro 0x0000000000000000 0x28 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .debug_macro 0x0000000000000000 0x129 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .debug_macro 0x0000000000000000 0x244 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .debug_macro 0x0000000000000000 0x22c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .debug_macro 0x0000000000000000 0x5b Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .debug_macro 0x0000000000000000 0xa5 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .debug_macro 0x0000000000000000 0x187 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .debug_macro 0x0000000000000000 0x16 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .debug_macro 0x0000000000000000 0x11c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .debug_line 0x0000000000000000 0x890 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .debug_str 0x0000000000000000 0x5a9e2 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .comment 0x0000000000000000 0x54 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .debug_frame 0x0000000000000000 0x78 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .ARM.attributes + 0x0000000000000000 0x2c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .text 0x0000000000000000 0x0 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .data 0x0000000000000000 0x0 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .bss 0x0000000000000000 0x0 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .text.HAL_GPIO_Init + 0x0000000000000000 0x150 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .text.HAL_GPIO_DeInit + 0x0000000000000000 0xd0 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .text.HAL_GPIO_ReadPin + 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .text.HAL_GPIO_WritePin + 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .text.HAL_GPIO_TogglePin + 0x0000000000000000 0x10 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .text.HAL_GPIO_LockPin + 0x0000000000000000 0x28 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .text.HAL_GPIO_EXTI_Callback + 0x0000000000000000 0x2 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .text.HAL_GPIO_EXTI_IRQHandler + 0x0000000000000000 0x18 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .debug_info 0x0000000000000000 0x7cd Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .debug_abbrev 0x0000000000000000 0x205 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .debug_loc 0x0000000000000000 0x3c6 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .debug_aranges + 0x0000000000000000 0x58 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .debug_ranges 0x0000000000000000 0x48 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x1cf Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .debug_macro 0x0000000000000000 0xa8a Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x119 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x2e Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x28 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x22 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x8e Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x51 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x103 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x6a Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x1df Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x1c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x22 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .debug_macro 0x0000000000000000 0xb5 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x3ad Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x7b9c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x3c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x352b Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x174 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x5b Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x899 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x42e Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x182 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x13f Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .debug_macro 0x0000000000000000 0xf1 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x28e Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x28 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x129 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x244 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x22c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x5b Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .debug_macro 0x0000000000000000 0xa5 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x187 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x16 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x11c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .debug_line 0x0000000000000000 0xb06 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .debug_str 0x0000000000000000 0x5ab14 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .comment 0x0000000000000000 0x54 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .debug_frame 0x0000000000000000 0xbc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .ARM.attributes + 0x0000000000000000 0x2c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text 0x0000000000000000 0x0 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .data 0x0000000000000000 0x0 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .bss 0x0000000000000000 0x0 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.I2C_Flush_TXDR + 0x0000000000000000 0x1c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.I2C_TransferConfig + 0x0000000000000000 0x28 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.I2C_Enable_IRQ + 0x0000000000000000 0x60 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.I2C_Disable_IRQ + 0x0000000000000000 0x48 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.I2C_ConvertOtherXferOptions + 0x0000000000000000 0x1c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.I2C_IsAcknowledgeFailed + 0x0000000000000000 0x7c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.I2C_WaitOnRXNEFlagUntilTimeout + 0x0000000000000000 0x80 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.I2C_WaitOnSTOPFlagUntilTimeout + 0x0000000000000000 0x50 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.I2C_WaitOnFlagUntilTimeout + 0x0000000000000000 0x50 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.I2C_WaitOnTXISFlagUntilTimeout + 0x0000000000000000 0x54 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.I2C_RequestMemoryWrite + 0x0000000000000000 0x68 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.I2C_RequestMemoryRead + 0x0000000000000000 0x64 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.HAL_I2C_MspInit + 0x0000000000000000 0x2 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.HAL_I2C_Init + 0x0000000000000000 0xac Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.HAL_I2C_MspDeInit + 0x0000000000000000 0x2 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.HAL_I2C_DeInit + 0x0000000000000000 0x34 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.HAL_I2C_Master_Transmit + 0x0000000000000000 0x124 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.HAL_I2C_Master_Receive + 0x0000000000000000 0x124 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.HAL_I2C_Slave_Transmit + 0x0000000000000000 0x150 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.HAL_I2C_Slave_Receive + 0x0000000000000000 0x154 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.HAL_I2C_Master_Transmit_IT + 0x0000000000000000 0x98 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.HAL_I2C_Master_Receive_IT + 0x0000000000000000 0x98 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.HAL_I2C_Slave_Transmit_IT + 0x0000000000000000 0x5c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.HAL_I2C_Slave_Receive_IT + 0x0000000000000000 0x5c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.HAL_I2C_Master_Transmit_DMA + 0x0000000000000000 0x13c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.HAL_I2C_Master_Receive_DMA + 0x0000000000000000 0x13c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.HAL_I2C_Slave_Transmit_DMA + 0x0000000000000000 0xe0 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.HAL_I2C_Slave_Receive_DMA + 0x0000000000000000 0xe4 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.HAL_I2C_Mem_Write + 0x0000000000000000 0x174 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.HAL_I2C_Mem_Read + 0x0000000000000000 0x188 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.HAL_I2C_Mem_Write_IT + 0x0000000000000000 0xdc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.HAL_I2C_Mem_Read_IT + 0x0000000000000000 0xe0 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.HAL_I2C_Mem_Write_DMA + 0x0000000000000000 0x150 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.HAL_I2C_Mem_Read_DMA + 0x0000000000000000 0x154 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.HAL_I2C_IsDeviceReady + 0x0000000000000000 0x148 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.HAL_I2C_Master_Seq_Transmit_IT + 0x0000000000000000 0xac Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.HAL_I2C_Master_Seq_Transmit_DMA + 0x0000000000000000 0x154 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.HAL_I2C_Master_Seq_Receive_IT + 0x0000000000000000 0xac Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.HAL_I2C_Master_Seq_Receive_DMA + 0x0000000000000000 0x154 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.HAL_I2C_Slave_Seq_Transmit_IT + 0x0000000000000000 0xd4 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.HAL_I2C_Slave_Seq_Transmit_DMA + 0x0000000000000000 0x180 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.HAL_I2C_Slave_Seq_Receive_IT + 0x0000000000000000 0xdc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.HAL_I2C_Slave_Seq_Receive_DMA + 0x0000000000000000 0x188 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.HAL_I2C_EnableListen_IT + 0x0000000000000000 0x28 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.HAL_I2C_DisableListen_IT + 0x0000000000000000 0x34 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.HAL_I2C_Master_Abort_IT + 0x0000000000000000 0x70 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.HAL_I2C_EV_IRQHandler + 0x0000000000000000 0x12 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.HAL_I2C_MasterTxCpltCallback + 0x0000000000000000 0x2 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.HAL_I2C_MasterRxCpltCallback + 0x0000000000000000 0x2 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.I2C_ITMasterSeqCplt + 0x0000000000000000 0x48 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.HAL_I2C_SlaveTxCpltCallback + 0x0000000000000000 0x2 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.HAL_I2C_SlaveRxCpltCallback + 0x0000000000000000 0x2 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.I2C_ITSlaveSeqCplt + 0x0000000000000000 0x84 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.I2C_DMASlaveTransmitCplt + 0x0000000000000000 0x24 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.I2C_DMASlaveReceiveCplt + 0x0000000000000000 0x30 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.HAL_I2C_AddrCallback + 0x0000000000000000 0x2 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.I2C_ITAddrCplt.isra.0 + 0x0000000000000000 0x9a Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.HAL_I2C_ListenCpltCallback + 0x0000000000000000 0x2 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.I2C_ITListenCplt + 0x0000000000000000 0x6c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.HAL_I2C_MemTxCpltCallback + 0x0000000000000000 0x2 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.HAL_I2C_MemRxCpltCallback + 0x0000000000000000 0x2 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.HAL_I2C_ErrorCallback + 0x0000000000000000 0x2 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.HAL_I2C_AbortCpltCallback + 0x0000000000000000 0x2 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.I2C_TreatErrorCallback + 0x0000000000000000 0x2a Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.I2C_ITError + 0x0000000000000000 0xf4 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.I2C_ITSlaveCplt + 0x0000000000000000 0x138 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.I2C_Slave_ISR_IT + 0x0000000000000000 0x130 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.I2C_ITMasterCplt + 0x0000000000000000 0xe4 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.I2C_Master_ISR_IT + 0x0000000000000000 0x140 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.I2C_Slave_ISR_DMA + 0x0000000000000000 0x10c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.I2C_Master_ISR_DMA + 0x0000000000000000 0x120 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.I2C_DMAError + 0x0000000000000000 0x18 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.I2C_DMAMasterTransmitCplt + 0x0000000000000000 0x50 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.I2C_DMAMasterReceiveCplt + 0x0000000000000000 0x54 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.HAL_I2C_ER_IRQHandler + 0x0000000000000000 0x62 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.I2C_DMAAbort + 0x0000000000000000 0x1e Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.HAL_I2C_GetState + 0x0000000000000000 0x8 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.HAL_I2C_GetMode + 0x0000000000000000 0x8 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .text.HAL_I2C_GetError + 0x0000000000000000 0x4 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .debug_info 0x0000000000000000 0x3f91 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .debug_abbrev 0x0000000000000000 0x3a9 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .debug_loc 0x0000000000000000 0x405b Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .debug_aranges + 0x0000000000000000 0x240 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .debug_ranges 0x0000000000000000 0x2a8 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .debug_macro 0x0000000000000000 0x25c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .debug_macro 0x0000000000000000 0xa8a Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .debug_macro 0x0000000000000000 0x119 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .debug_macro 0x0000000000000000 0x2e Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .debug_macro 0x0000000000000000 0x28 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .debug_macro 0x0000000000000000 0x22 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .debug_macro 0x0000000000000000 0x8e Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .debug_macro 0x0000000000000000 0x51 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .debug_macro 0x0000000000000000 0x103 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .debug_macro 0x0000000000000000 0x6a Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .debug_macro 0x0000000000000000 0x1df Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .debug_macro 0x0000000000000000 0x1c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .debug_macro 0x0000000000000000 0x22 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .debug_macro 0x0000000000000000 0xb5 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .debug_macro 0x0000000000000000 0x3ad Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .debug_macro 0x0000000000000000 0x7b9c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .debug_macro 0x0000000000000000 0x3c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .debug_macro 0x0000000000000000 0x352b Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .debug_macro 0x0000000000000000 0x174 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .debug_macro 0x0000000000000000 0x5b Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .debug_macro 0x0000000000000000 0x899 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .debug_macro 0x0000000000000000 0x42e Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .debug_macro 0x0000000000000000 0x182 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .debug_macro 0x0000000000000000 0x13f Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .debug_macro 0x0000000000000000 0xf1 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .debug_macro 0x0000000000000000 0x28e Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .debug_macro 0x0000000000000000 0x28 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .debug_macro 0x0000000000000000 0x129 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .debug_macro 0x0000000000000000 0x244 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .debug_macro 0x0000000000000000 0x22c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .debug_macro 0x0000000000000000 0x5b Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .debug_macro 0x0000000000000000 0xa5 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .debug_macro 0x0000000000000000 0x187 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .debug_macro 0x0000000000000000 0x16 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .debug_macro 0x0000000000000000 0x11c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .debug_line 0x0000000000000000 0x511e Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .debug_str 0x0000000000000000 0x5bb19 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .comment 0x0000000000000000 0x54 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .debug_frame 0x0000000000000000 0x884 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .ARM.attributes + 0x0000000000000000 0x2c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .text 0x0000000000000000 0x0 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .data 0x0000000000000000 0x0 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .bss 0x0000000000000000 0x0 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .text.HAL_I2CEx_ConfigAnalogFilter + 0x0000000000000000 0x4c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .text.HAL_I2CEx_ConfigDigitalFilter + 0x0000000000000000 0x48 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .text.HAL_I2CEx_EnableWakeUp + 0x0000000000000000 0x42 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .text.HAL_I2CEx_DisableWakeUp + 0x0000000000000000 0x44 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .text.HAL_I2CEx_EnableFastModePlus + 0x0000000000000000 0x1c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .text.HAL_I2CEx_DisableFastModePlus + 0x0000000000000000 0x1c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .debug_info 0x0000000000000000 0x9e2 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .debug_abbrev 0x0000000000000000 0x1da Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .debug_loc 0x0000000000000000 0x1b0 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .debug_aranges + 0x0000000000000000 0x48 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .debug_ranges 0x0000000000000000 0x38 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .debug_macro 0x0000000000000000 0x197 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .debug_macro 0x0000000000000000 0xa8a Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .debug_macro 0x0000000000000000 0x119 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .debug_macro 0x0000000000000000 0x2e Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .debug_macro 0x0000000000000000 0x28 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .debug_macro 0x0000000000000000 0x22 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .debug_macro 0x0000000000000000 0x8e Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .debug_macro 0x0000000000000000 0x51 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .debug_macro 0x0000000000000000 0x103 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .debug_macro 0x0000000000000000 0x6a Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .debug_macro 0x0000000000000000 0x1df Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .debug_macro 0x0000000000000000 0x1c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .debug_macro 0x0000000000000000 0x22 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .debug_macro 0x0000000000000000 0xb5 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .debug_macro 0x0000000000000000 0x3ad Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .debug_macro 0x0000000000000000 0x7b9c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .debug_macro 0x0000000000000000 0x3c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .debug_macro 0x0000000000000000 0x352b Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .debug_macro 0x0000000000000000 0x174 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .debug_macro 0x0000000000000000 0x5b Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .debug_macro 0x0000000000000000 0x899 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .debug_macro 0x0000000000000000 0x42e Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .debug_macro 0x0000000000000000 0x182 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .debug_macro 0x0000000000000000 0x13f Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .debug_macro 0x0000000000000000 0xf1 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .debug_macro 0x0000000000000000 0x28e Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .debug_macro 0x0000000000000000 0x28 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .debug_macro 0x0000000000000000 0x129 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .debug_macro 0x0000000000000000 0x244 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .debug_macro 0x0000000000000000 0x22c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .debug_macro 0x0000000000000000 0x5b Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .debug_macro 0x0000000000000000 0xa5 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .debug_macro 0x0000000000000000 0x187 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .debug_macro 0x0000000000000000 0x16 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .debug_macro 0x0000000000000000 0x11c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .debug_line 0x0000000000000000 0x9b2 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .debug_str 0x0000000000000000 0x5ae1f Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .comment 0x0000000000000000 0x54 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .debug_frame 0x0000000000000000 0xa8 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .ARM.attributes + 0x0000000000000000 0x2c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .text 0x0000000000000000 0x0 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .data 0x0000000000000000 0x0 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .bss 0x0000000000000000 0x0 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .text.HAL_PWR_DeInit + 0x0000000000000000 0x20 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .text.HAL_PWR_EnableBkUpAccess + 0x0000000000000000 0x14 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .text.HAL_PWR_DisableBkUpAccess + 0x0000000000000000 0x14 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .text.HAL_PWR_ConfigPVD + 0x0000000000000000 0x74 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .text.HAL_PWR_EnablePVD + 0x0000000000000000 0x10 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .text.HAL_PWR_DisablePVD + 0x0000000000000000 0x10 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .text.HAL_PWR_EnableWakeUpPin + 0x0000000000000000 0x10 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .text.HAL_PWR_DisableWakeUpPin + 0x0000000000000000 0x10 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .text.HAL_PWR_EnterSLEEPMode + 0x0000000000000000 0x70 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .text.HAL_PWR_EnterSTOPMode + 0x0000000000000000 0x78 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .text.HAL_PWR_EnterSTANDBYMode + 0x0000000000000000 0x20 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .text.HAL_PWR_EnableSleepOnExit + 0x0000000000000000 0x10 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .text.HAL_PWR_DisableSleepOnExit + 0x0000000000000000 0x10 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .text.HAL_PWR_EnableSEVOnPend + 0x0000000000000000 0x10 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .text.HAL_PWR_DisableSEVOnPend + 0x0000000000000000 0x10 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .text.HAL_PWR_PVDCallback + 0x0000000000000000 0x2 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .text.HAL_PWR_PVD_IRQHandler + 0x0000000000000000 0x1c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .debug_info 0x0000000000000000 0x73f Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .debug_abbrev 0x0000000000000000 0x1b5 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .debug_loc 0x0000000000000000 0x1f9 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .debug_aranges + 0x0000000000000000 0xa0 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .debug_ranges 0x0000000000000000 0x90 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x1af Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .debug_macro 0x0000000000000000 0xa8a Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x119 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x2e Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x28 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x22 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x8e Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x51 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x103 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x6a Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x1df Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x1c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x22 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .debug_macro 0x0000000000000000 0xb5 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x3ad Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x7b9c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x3c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x352b Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x174 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x5b Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x899 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x42e Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x182 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x13f Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .debug_macro 0x0000000000000000 0xf1 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x28e Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x28 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x129 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x244 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x22c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x5b Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .debug_macro 0x0000000000000000 0xa5 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x187 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x16 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x11c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .debug_line 0x0000000000000000 0x9a2 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .debug_str 0x0000000000000000 0x5ab32 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .comment 0x0000000000000000 0x54 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .debug_frame 0x0000000000000000 0x14c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .ARM.attributes + 0x0000000000000000 0x2c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .text 0x0000000000000000 0x0 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .data 0x0000000000000000 0x0 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .bss 0x0000000000000000 0x0 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .text.HAL_PWREx_GetVoltageRange + 0x0000000000000000 0x10 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .text.HAL_PWREx_EnableFastWakeUp + 0x0000000000000000 0x14 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .text.HAL_PWREx_DisableFastWakeUp + 0x0000000000000000 0x14 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .text.HAL_PWREx_EnableUltraLowPower + 0x0000000000000000 0x14 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .text.HAL_PWREx_DisableUltraLowPower + 0x0000000000000000 0x14 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .text.HAL_PWREx_EnableLowPowerRunMode + 0x0000000000000000 0x1c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .text.HAL_PWREx_DisableLowPowerRunMode + 0x0000000000000000 0x50 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .debug_info 0x0000000000000000 0x27f Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .debug_abbrev 0x0000000000000000 0x135 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .debug_loc 0x0000000000000000 0x30 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .debug_aranges + 0x0000000000000000 0x50 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .debug_ranges 0x0000000000000000 0x40 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x19d Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0xa8a Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x119 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x2e Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x28 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x22 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x8e Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x51 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x103 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x6a Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x1df Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x1c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x22 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0xb5 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x3ad Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x7b9c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x3c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x352b Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x174 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x5b Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x899 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x42e Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x182 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x13f Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0xf1 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x28e Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x28 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x129 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x244 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x22c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x5b Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0xa5 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x187 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x16 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x11c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .debug_line 0x0000000000000000 0x78a Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .debug_str 0x0000000000000000 0x5a8f2 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .comment 0x0000000000000000 0x54 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .debug_frame 0x0000000000000000 0x88 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .ARM.attributes + 0x0000000000000000 0x2c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .text 0x0000000000000000 0x0 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .data 0x0000000000000000 0x0 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .bss 0x0000000000000000 0x0 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .text.HAL_RCC_DeInit + 0x0000000000000000 0xdc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .text.HAL_RCC_MCOConfig + 0x0000000000000000 0x74 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .text.HAL_RCC_GetHCLKFreq + 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .text.HAL_RCC_GetPCLK1Freq + 0x0000000000000000 0x20 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .text.HAL_RCC_GetPCLK2Freq + 0x0000000000000000 0x20 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .text.HAL_RCC_GetOscConfig + 0x0000000000000000 0xa4 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .text.HAL_RCC_GetClockConfig + 0x0000000000000000 0x40 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .debug_macro 0x0000000000000000 0xa8a Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x119 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x2e Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x28 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x22 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x8e Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x51 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x103 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x6a Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x1df Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x1c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x22 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .debug_macro 0x0000000000000000 0xb5 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x3ad Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x7b9c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x3c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x352b Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x174 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x5b Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x899 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x42e Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x182 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x13f Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .debug_macro 0x0000000000000000 0xf1 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x28e Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x28 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x129 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x244 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x22c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x5b Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .debug_macro 0x0000000000000000 0xa5 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x187 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x16 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x11c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .text 0x0000000000000000 0x0 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .data 0x0000000000000000 0x0 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .bss 0x0000000000000000 0x0 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .text.HAL_RCCEx_GetPeriphCLKConfig + 0x0000000000000000 0x4c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .text.HAL_RCCEx_GetPeriphCLKFreq + 0x0000000000000000 0x174 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .text.HAL_RCCEx_EnableLSECSS + 0x0000000000000000 0x14 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .text.HAL_RCCEx_DisableLSECSS + 0x0000000000000000 0x1c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .text.HAL_RCCEx_EnableLSECSS_IT + 0x0000000000000000 0x30 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .text.HAL_RCCEx_LSECSS_Callback + 0x0000000000000000 0x2 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .text.HAL_RCCEx_LSECSS_IRQHandler + 0x0000000000000000 0x18 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0xa8a Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x119 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x2e Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x28 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x22 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x8e Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x51 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x103 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x6a Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x1df Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x1c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x22 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0xb5 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x3ad Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x7b9c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x3c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x352b Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x174 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x5b Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x899 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x42e Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x182 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x13f Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0xf1 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x28e Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x28 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x129 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x244 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x22c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x5b Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0xa5 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x187 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x16 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x11c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .text 0x0000000000000000 0x0 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .data 0x0000000000000000 0x0 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .bss 0x0000000000000000 0x0 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .debug_info 0x0000000000000000 0x172 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .debug_abbrev 0x0000000000000000 0x9a Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .debug_aranges + 0x0000000000000000 0x18 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .debug_macro 0x0000000000000000 0x198 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .debug_macro 0x0000000000000000 0xa8a Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .debug_macro 0x0000000000000000 0x119 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .debug_macro 0x0000000000000000 0x2e Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .debug_macro 0x0000000000000000 0x28 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .debug_macro 0x0000000000000000 0x22 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .debug_macro 0x0000000000000000 0x8e Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .debug_macro 0x0000000000000000 0x51 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .debug_macro 0x0000000000000000 0x103 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .debug_macro 0x0000000000000000 0x6a Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .debug_macro 0x0000000000000000 0x1df Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .debug_macro 0x0000000000000000 0x1c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .debug_macro 0x0000000000000000 0x22 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .debug_macro 0x0000000000000000 0xb5 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .debug_macro 0x0000000000000000 0x3ad Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .debug_macro 0x0000000000000000 0x7b9c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .debug_macro 0x0000000000000000 0x3c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .debug_macro 0x0000000000000000 0x352b Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .debug_macro 0x0000000000000000 0x174 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .debug_macro 0x0000000000000000 0x5b Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .debug_macro 0x0000000000000000 0x899 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .debug_macro 0x0000000000000000 0x42e Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .debug_macro 0x0000000000000000 0x182 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .debug_macro 0x0000000000000000 0x13f Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .debug_macro 0x0000000000000000 0xf1 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .debug_macro 0x0000000000000000 0x28e Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .debug_macro 0x0000000000000000 0x28 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .debug_macro 0x0000000000000000 0x129 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .debug_macro 0x0000000000000000 0x244 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .debug_macro 0x0000000000000000 0x22c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .debug_macro 0x0000000000000000 0x5b Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .debug_macro 0x0000000000000000 0xa5 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .debug_macro 0x0000000000000000 0x187 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .debug_macro 0x0000000000000000 0x16 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .debug_macro 0x0000000000000000 0x11c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .debug_line 0x0000000000000000 0x65b Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .debug_str 0x0000000000000000 0x5a7ae Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .comment 0x0000000000000000 0x54 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .ARM.attributes + 0x0000000000000000 0x32 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .text 0x0000000000000000 0x0 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .data 0x0000000000000000 0x0 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .bss 0x0000000000000000 0x0 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .debug_info 0x0000000000000000 0x172 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .debug_abbrev 0x0000000000000000 0x9a Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .debug_aranges + 0x0000000000000000 0x18 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x197 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0xa8a Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x119 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x2e Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x28 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x22 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x8e Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x51 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x103 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x6a Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x1df Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x1c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x22 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0xb5 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x3ad Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x7b9c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x3c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x352b Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x174 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x5b Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x899 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x42e Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x182 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x13f Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0xf1 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x28e Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x28 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x129 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x244 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x22c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x5b Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0xa5 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x187 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x16 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x11c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .debug_line 0x0000000000000000 0x65e Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .debug_str 0x0000000000000000 0x5a7b1 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .comment 0x0000000000000000 0x54 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .ARM.attributes + 0x0000000000000000 0x32 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.o + .text 0x0000000000000000 0x0 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.o + .data 0x0000000000000000 0x0 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.o + .bss 0x0000000000000000 0x0 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.o + .text.LL_DMA_DeInit + 0x0000000000000000 0xc8 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.o + .text.LL_DMA_Init + 0x0000000000000000 0x64 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.o + .text.LL_DMA_StructInit + 0x0000000000000000 0x1a Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.o + .rodata.CHANNEL_OFFSET_TAB + 0x0000000000000000 0x5 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.o + .debug_info 0x0000000000000000 0x96b Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.o + .debug_abbrev 0x0000000000000000 0x2a9 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.o + .debug_loc 0x0000000000000000 0x3f7 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.o + .debug_aranges + 0x0000000000000000 0x30 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.o + .debug_ranges 0x0000000000000000 0x128 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.o + .debug_macro 0x0000000000000000 0x1f1 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.o + .debug_macro 0x0000000000000000 0xa8a Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.o + .debug_macro 0x0000000000000000 0x2e Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.o + .debug_macro 0x0000000000000000 0x28 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.o + .debug_macro 0x0000000000000000 0x22 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.o + .debug_macro 0x0000000000000000 0x8e Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.o + .debug_macro 0x0000000000000000 0x51 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.o + .debug_macro 0x0000000000000000 0x103 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.o + .debug_macro 0x0000000000000000 0x6a Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.o + .debug_macro 0x0000000000000000 0x1df Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.o + .debug_macro 0x0000000000000000 0x1c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.o + .debug_macro 0x0000000000000000 0x22 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.o + .debug_macro 0x0000000000000000 0xb5 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.o + .debug_macro 0x0000000000000000 0x3ad Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.o + .debug_macro 0x0000000000000000 0x7b9c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.o + .debug_macro 0x0000000000000000 0x3c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.o + .debug_macro 0x0000000000000000 0x119 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.o + .debug_macro 0x0000000000000000 0x352b Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.o + .debug_macro 0x0000000000000000 0x174 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.o + .debug_macro 0x0000000000000000 0x5b Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.o + .debug_macro 0x0000000000000000 0x899 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.o + .debug_macro 0x0000000000000000 0x42e Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.o + .debug_macro 0x0000000000000000 0x182 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.o + .debug_macro 0x0000000000000000 0x13f Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.o + .debug_macro 0x0000000000000000 0xf1 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.o + .debug_macro 0x0000000000000000 0x28e Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.o + .debug_macro 0x0000000000000000 0x28 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.o + .debug_macro 0x0000000000000000 0x129 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.o + .debug_macro 0x0000000000000000 0x244 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.o + .debug_macro 0x0000000000000000 0x22c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.o + .debug_macro 0x0000000000000000 0x5b Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.o + .debug_macro 0x0000000000000000 0xa5 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.o + .debug_macro 0x0000000000000000 0x187 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.o + .debug_macro 0x0000000000000000 0x16 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.o + .debug_macro 0x0000000000000000 0x11c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.o + .debug_macro 0x0000000000000000 0x27f Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.o + .debug_macro 0x0000000000000000 0xa7 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.o + .debug_line 0x0000000000000000 0x9f0 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.o + .debug_str 0x0000000000000000 0x5c727 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.o + .comment 0x0000000000000000 0x54 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.o + .debug_frame 0x0000000000000000 0x58 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.o + .ARM.attributes + 0x0000000000000000 0x2c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.o + .text 0x0000000000000000 0x0 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.o + .data 0x0000000000000000 0x0 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.o + .bss 0x0000000000000000 0x0 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.o + .text.LL_EXTI_DeInit + 0x0000000000000000 0x24 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.o + .text.LL_EXTI_Init + 0x0000000000000000 0xa0 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.o + .text.LL_EXTI_StructInit + 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.o + .debug_info 0x0000000000000000 0x559 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.o + .debug_abbrev 0x0000000000000000 0x1f1 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.o + .debug_loc 0x0000000000000000 0x12c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.o + .debug_aranges + 0x0000000000000000 0x30 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.o + .debug_ranges 0x0000000000000000 0x68 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.o + .debug_macro 0x0000000000000000 0x1be Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.o + .debug_macro 0x0000000000000000 0xa8a Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.o + .debug_macro 0x0000000000000000 0x2e Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.o + .debug_macro 0x0000000000000000 0x28 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.o + .debug_macro 0x0000000000000000 0x22 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.o + .debug_macro 0x0000000000000000 0x8e Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.o + .debug_macro 0x0000000000000000 0x51 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.o + .debug_macro 0x0000000000000000 0x103 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.o + .debug_macro 0x0000000000000000 0x6a Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.o + .debug_macro 0x0000000000000000 0x1df Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.o + .debug_macro 0x0000000000000000 0x1c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.o + .debug_macro 0x0000000000000000 0x22 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.o + .debug_macro 0x0000000000000000 0xb5 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.o + .debug_macro 0x0000000000000000 0x3ad Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.o + .debug_macro 0x0000000000000000 0x7b9c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.o + .debug_macro 0x0000000000000000 0x3c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.o + .debug_macro 0x0000000000000000 0x119 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.o + .debug_macro 0x0000000000000000 0x352b Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.o + .debug_macro 0x0000000000000000 0x174 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.o + .debug_macro 0x0000000000000000 0x5b Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.o + .debug_macro 0x0000000000000000 0x899 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.o + .debug_macro 0x0000000000000000 0x42e Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.o + .debug_macro 0x0000000000000000 0x182 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.o + .debug_macro 0x0000000000000000 0x13f Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.o + .debug_macro 0x0000000000000000 0xf1 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.o + .debug_macro 0x0000000000000000 0x28e Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.o + .debug_macro 0x0000000000000000 0x28 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.o + .debug_macro 0x0000000000000000 0x129 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.o + .debug_macro 0x0000000000000000 0x244 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.o + .debug_macro 0x0000000000000000 0x22c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.o + .debug_macro 0x0000000000000000 0x5b Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.o + .debug_macro 0x0000000000000000 0xa5 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.o + .debug_macro 0x0000000000000000 0x187 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.o + .debug_macro 0x0000000000000000 0x16 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.o + .debug_macro 0x0000000000000000 0x11c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.o + .debug_macro 0x0000000000000000 0x103 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.o + .debug_line 0x0000000000000000 0x851 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.o + .debug_str 0x0000000000000000 0x5b018 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.o + .comment 0x0000000000000000 0x54 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.o + .debug_frame 0x0000000000000000 0x48 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.o + .ARM.attributes + 0x0000000000000000 0x2c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.o + .text 0x0000000000000000 0x0 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.o + .data 0x0000000000000000 0x0 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.o + .bss 0x0000000000000000 0x0 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.o + .text.LL_GPIO_DeInit + 0x0000000000000000 0x48 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.o + .text.LL_GPIO_StructInit + 0x0000000000000000 0x18 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.o + .debug_macro 0x0000000000000000 0xa8a Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.o + .debug_macro 0x0000000000000000 0x2e Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.o + .debug_macro 0x0000000000000000 0x28 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.o + .debug_macro 0x0000000000000000 0x22 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.o + .debug_macro 0x0000000000000000 0x8e Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.o + .debug_macro 0x0000000000000000 0x51 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.o + .debug_macro 0x0000000000000000 0x103 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.o + .debug_macro 0x0000000000000000 0x6a Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.o + .debug_macro 0x0000000000000000 0x1df Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.o + .debug_macro 0x0000000000000000 0x1c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.o + .debug_macro 0x0000000000000000 0x22 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.o + .debug_macro 0x0000000000000000 0xb5 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.o + .debug_macro 0x0000000000000000 0x3ad Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.o + .debug_macro 0x0000000000000000 0x7b9c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.o + .debug_macro 0x0000000000000000 0x3c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.o + .debug_macro 0x0000000000000000 0x119 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.o + .debug_macro 0x0000000000000000 0x352b Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.o + .debug_macro 0x0000000000000000 0x174 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.o + .debug_macro 0x0000000000000000 0x5b Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.o + .debug_macro 0x0000000000000000 0x899 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.o + .debug_macro 0x0000000000000000 0x42e Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.o + .debug_macro 0x0000000000000000 0x182 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.o + .debug_macro 0x0000000000000000 0x13f Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.o + .debug_macro 0x0000000000000000 0xf1 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.o + .debug_macro 0x0000000000000000 0x28e Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.o + .debug_macro 0x0000000000000000 0x28 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.o + .debug_macro 0x0000000000000000 0x129 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.o + .debug_macro 0x0000000000000000 0x244 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.o + .debug_macro 0x0000000000000000 0x22c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.o + .debug_macro 0x0000000000000000 0x5b Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.o + .debug_macro 0x0000000000000000 0xa5 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.o + .debug_macro 0x0000000000000000 0x187 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.o + .debug_macro 0x0000000000000000 0x16 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.o + .debug_macro 0x0000000000000000 0x11c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.o + .debug_macro 0x0000000000000000 0xa7 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.o + .text 0x0000000000000000 0x0 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.o + .data 0x0000000000000000 0x0 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.o + .bss 0x0000000000000000 0x0 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.o + .text.LL_I2C_DeInit + 0x0000000000000000 0x30 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.o + .text.LL_I2C_StructInit + 0x0000000000000000 0x16 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.o + .debug_macro 0x0000000000000000 0xa8a Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.o + .debug_macro 0x0000000000000000 0x2e Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.o + .debug_macro 0x0000000000000000 0x28 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.o + .debug_macro 0x0000000000000000 0x22 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.o + .debug_macro 0x0000000000000000 0x8e Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.o + .debug_macro 0x0000000000000000 0x51 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.o + .debug_macro 0x0000000000000000 0x103 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.o + .debug_macro 0x0000000000000000 0x6a Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.o + .debug_macro 0x0000000000000000 0x1df Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.o + .debug_macro 0x0000000000000000 0x1c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.o + .debug_macro 0x0000000000000000 0x22 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.o + .debug_macro 0x0000000000000000 0xb5 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.o + .debug_macro 0x0000000000000000 0x3ad Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.o + .debug_macro 0x0000000000000000 0x7b9c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.o + .debug_macro 0x0000000000000000 0x3c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.o + .debug_macro 0x0000000000000000 0x119 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.o + .debug_macro 0x0000000000000000 0x352b Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.o + .debug_macro 0x0000000000000000 0x174 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.o + .debug_macro 0x0000000000000000 0x5b Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.o + .debug_macro 0x0000000000000000 0x899 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.o + .debug_macro 0x0000000000000000 0x42e Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.o + .debug_macro 0x0000000000000000 0x182 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.o + .debug_macro 0x0000000000000000 0x13f Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.o + .debug_macro 0x0000000000000000 0xf1 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.o + .debug_macro 0x0000000000000000 0x28e Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.o + .debug_macro 0x0000000000000000 0x28 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.o + .debug_macro 0x0000000000000000 0x129 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.o + .debug_macro 0x0000000000000000 0x244 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.o + .debug_macro 0x0000000000000000 0x22c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.o + .debug_macro 0x0000000000000000 0x5b Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.o + .debug_macro 0x0000000000000000 0xa5 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.o + .debug_macro 0x0000000000000000 0x187 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.o + .debug_macro 0x0000000000000000 0x16 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.o + .debug_macro 0x0000000000000000 0x11c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.o + .debug_macro 0x0000000000000000 0xa7 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.o + .text 0x0000000000000000 0x0 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.o + .data 0x0000000000000000 0x0 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.o + .bss 0x0000000000000000 0x0 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.o + .text.LL_LPUART_DeInit + 0x0000000000000000 0x30 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.o + .text.LL_LPUART_StructInit + 0x0000000000000000 0x16 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.o + .debug_macro 0x0000000000000000 0xa8a Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.o + .debug_macro 0x0000000000000000 0x2e Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.o + .debug_macro 0x0000000000000000 0x28 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.o + .debug_macro 0x0000000000000000 0x22 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.o + .debug_macro 0x0000000000000000 0x8e Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.o + .debug_macro 0x0000000000000000 0x51 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.o + .debug_macro 0x0000000000000000 0x103 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.o + .debug_macro 0x0000000000000000 0x6a Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.o + .debug_macro 0x0000000000000000 0x1df Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.o + .debug_macro 0x0000000000000000 0x1c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.o + .debug_macro 0x0000000000000000 0x22 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.o + .debug_macro 0x0000000000000000 0xb5 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.o + .debug_macro 0x0000000000000000 0x3ad Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.o + .debug_macro 0x0000000000000000 0x7b9c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.o + .debug_macro 0x0000000000000000 0x3c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.o + .debug_macro 0x0000000000000000 0x119 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.o + .debug_macro 0x0000000000000000 0x352b Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.o + .debug_macro 0x0000000000000000 0x174 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.o + .debug_macro 0x0000000000000000 0x5b Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.o + .debug_macro 0x0000000000000000 0x899 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.o + .debug_macro 0x0000000000000000 0x42e Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.o + .debug_macro 0x0000000000000000 0x182 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.o + .debug_macro 0x0000000000000000 0x13f Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.o + .debug_macro 0x0000000000000000 0xf1 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.o + .debug_macro 0x0000000000000000 0x28e Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.o + .debug_macro 0x0000000000000000 0x28 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.o + .debug_macro 0x0000000000000000 0x129 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.o + .debug_macro 0x0000000000000000 0x244 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.o + .debug_macro 0x0000000000000000 0x22c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.o + .debug_macro 0x0000000000000000 0x5b Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.o + .debug_macro 0x0000000000000000 0xa5 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.o + .debug_macro 0x0000000000000000 0x187 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.o + .debug_macro 0x0000000000000000 0x16 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.o + .debug_macro 0x0000000000000000 0x11c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.o + .debug_macro 0x0000000000000000 0x3b4 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.o + .debug_macro 0x0000000000000000 0xa7 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.o + .text 0x0000000000000000 0x0 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.o + .data 0x0000000000000000 0x0 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.o + .bss 0x0000000000000000 0x0 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.o + .text.LL_RCC_DeInit + 0x0000000000000000 0xb8 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.o + .text.RCC_GetPCLK2ClockFreq + 0x0000000000000000 0x18 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.o + .text.LL_RCC_GetSystemClocksFreq + 0x0000000000000000 0x20 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.o + .text.LL_RCC_GetUSARTClockFreq + 0x0000000000000000 0x7c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.o + .text.LL_RCC_GetI2CClockFreq + 0x0000000000000000 0x70 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.o + .text.LL_RCC_GetLPTIMClockFreq + 0x0000000000000000 0x78 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.o + .debug_macro 0x0000000000000000 0xa8a Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.o + .debug_macro 0x0000000000000000 0x2e Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.o + .debug_macro 0x0000000000000000 0x28 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.o + .debug_macro 0x0000000000000000 0x22 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.o + .debug_macro 0x0000000000000000 0x8e Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.o + .debug_macro 0x0000000000000000 0x51 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.o + .debug_macro 0x0000000000000000 0x103 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.o + .debug_macro 0x0000000000000000 0x6a Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.o + .debug_macro 0x0000000000000000 0x1df Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.o + .debug_macro 0x0000000000000000 0x1c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.o + .debug_macro 0x0000000000000000 0x22 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.o + .debug_macro 0x0000000000000000 0xb5 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.o + .debug_macro 0x0000000000000000 0x3ad Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.o + .debug_macro 0x0000000000000000 0x7b9c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.o + .debug_macro 0x0000000000000000 0x3c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.o + .debug_macro 0x0000000000000000 0x119 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.o + .debug_macro 0x0000000000000000 0x352b Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.o + .debug_macro 0x0000000000000000 0x174 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.o + .debug_macro 0x0000000000000000 0x5b Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.o + .debug_macro 0x0000000000000000 0x899 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.o + .debug_macro 0x0000000000000000 0x42e Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.o + .debug_macro 0x0000000000000000 0x182 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.o + .debug_macro 0x0000000000000000 0x13f Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.o + .debug_macro 0x0000000000000000 0xf1 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.o + .debug_macro 0x0000000000000000 0x28e Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.o + .debug_macro 0x0000000000000000 0x28 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.o + .debug_macro 0x0000000000000000 0x129 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.o + .debug_macro 0x0000000000000000 0x244 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.o + .debug_macro 0x0000000000000000 0x22c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.o + .debug_macro 0x0000000000000000 0x5b Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.o + .debug_macro 0x0000000000000000 0xa5 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.o + .debug_macro 0x0000000000000000 0x187 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.o + .debug_macro 0x0000000000000000 0x16 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.o + .debug_macro 0x0000000000000000 0x11c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.o + .group 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.o + .text 0x0000000000000000 0x0 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.o + .data 0x0000000000000000 0x0 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.o + .bss 0x0000000000000000 0x0 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.o + .text.LL_Init1msTick + 0x0000000000000000 0x20 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.o + .text.LL_mDelay + 0x0000000000000000 0x2c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.o + .text.LL_SetSystemCoreClock + 0x0000000000000000 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.o + .text.LL_SetFlashLatency + 0x0000000000000000 0x74 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.o + .text.UTILS_EnablePLLAndSwitchSystem + 0x0000000000000000 0x9c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.o + .text.LL_PLL_ConfigSystemClock_HSI + 0x0000000000000000 0x60 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.o + .text.LL_PLL_ConfigSystemClock_HSE + 0x0000000000000000 0x80 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.o + .debug_info 0x0000000000000000 0xce9 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.o + .debug_abbrev 0x0000000000000000 0x391 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.o + .debug_loc 0x0000000000000000 0x743 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.o + .debug_aranges + 0x0000000000000000 0x50 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.o + .debug_ranges 0x0000000000000000 0x2c0 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.o + .debug_macro 0x0000000000000000 0x23f Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.o + .debug_macro 0x0000000000000000 0xa8a Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.o + .debug_macro 0x0000000000000000 0x2e Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.o + .debug_macro 0x0000000000000000 0x28 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.o + .debug_macro 0x0000000000000000 0x22 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.o + .debug_macro 0x0000000000000000 0x8e Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.o + .debug_macro 0x0000000000000000 0x51 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.o + .debug_macro 0x0000000000000000 0x103 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.o + .debug_macro 0x0000000000000000 0x6a Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.o + .debug_macro 0x0000000000000000 0x1df Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.o + .debug_macro 0x0000000000000000 0x1c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.o + .debug_macro 0x0000000000000000 0x22 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.o + .debug_macro 0x0000000000000000 0xb5 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.o + .debug_macro 0x0000000000000000 0x3ad Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.o + .debug_macro 0x0000000000000000 0x7b9c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.o + .debug_macro 0x0000000000000000 0x3c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.o + .debug_macro 0x0000000000000000 0x119 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.o + .debug_macro 0x0000000000000000 0x352b Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.o + .debug_macro 0x0000000000000000 0x174 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.o + .debug_macro 0x0000000000000000 0x5b Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.o + .debug_macro 0x0000000000000000 0x899 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.o + .debug_macro 0x0000000000000000 0x42e Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.o + .debug_macro 0x0000000000000000 0x182 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.o + .debug_macro 0x0000000000000000 0x13f Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.o + .debug_macro 0x0000000000000000 0xf1 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.o + .debug_macro 0x0000000000000000 0x28e Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.o + .debug_macro 0x0000000000000000 0x28 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.o + .debug_macro 0x0000000000000000 0x129 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.o + .debug_macro 0x0000000000000000 0x244 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.o + .debug_macro 0x0000000000000000 0x22c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.o + .debug_macro 0x0000000000000000 0x5b Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.o + .debug_macro 0x0000000000000000 0xa5 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.o + .debug_macro 0x0000000000000000 0x187 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.o + .debug_macro 0x0000000000000000 0x16 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.o + .debug_macro 0x0000000000000000 0x11c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.o + .debug_macro 0x0000000000000000 0x3ae Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.o + .debug_macro 0x0000000000000000 0x2a Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.o + .debug_macro 0x0000000000000000 0x13d Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.o + .debug_macro 0x0000000000000000 0xdb Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.o + .debug_line 0x0000000000000000 0xd70 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.o + .debug_str 0x0000000000000000 0x5dd57 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.o + .comment 0x0000000000000000 0x54 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.o + .debug_frame 0x0000000000000000 0xc0 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.o + .ARM.attributes + 0x0000000000000000 0x2c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.o + .text 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-errno.o) + .data 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-errno.o) + .bss 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-errno.o) + .text.__errno 0x0000000000000000 0xc /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-errno.o) + .debug_frame 0x0000000000000000 0x20 /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-errno.o) + .ARM.attributes + 0x0000000000000000 0x2c /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-errno.o) + .text 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-exit.o) + .data 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-exit.o) + .bss 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-exit.o) + .text.exit 0x0000000000000000 0x2c /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-exit.o) + .debug_frame 0x0000000000000000 0x28 /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-exit.o) + .ARM.attributes + 0x0000000000000000 0x2c /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-exit.o) + .text 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-impure.o) + .data 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-impure.o) + .bss 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-impure.o) + .data._impure_ptr + 0x0000000000000000 0x4 /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-impure.o) + .data.impure_data + 0x0000000000000000 0x60 /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-impure.o) + .rodata._global_impure_ptr + 0x0000000000000000 0x4 /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-impure.o) + .ARM.attributes + 0x0000000000000000 0x2c /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-impure.o) + .text 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-init.o) + .data 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-init.o) + .bss 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-init.o) + .text 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-memset.o) + .data 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-memset.o) + .bss 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-memset.o) + .text 0x0000000000000000 0x14 /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_thumb1_case_uqi.o) + .data 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_thumb1_case_uqi.o) + .bss 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_thumb1_case_uqi.o) + .ARM.attributes + 0x0000000000000000 0x1e /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_thumb1_case_uqi.o) + .data 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_udivsi3.o) + .bss 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_udivsi3.o) + .text 0x0000000000000000 0x1d4 /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_divsi3.o) + .data 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_divsi3.o) + .bss 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_divsi3.o) + .debug_frame 0x0000000000000000 0x20 /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_divsi3.o) + .ARM.attributes + 0x0000000000000000 0x1e /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_divsi3.o) + .data 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_dvmd_tls.o) + .bss 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_dvmd_tls.o) + .text 0x0000000000000000 0x48 /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_aeabi_ldivmod.o) + .data 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_aeabi_ldivmod.o) + .bss 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_aeabi_ldivmod.o) + .ARM.attributes + 0x0000000000000000 0x1e /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_aeabi_ldivmod.o) + .data 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_aeabi_uldivmod.o) + .bss 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_aeabi_uldivmod.o) + .data 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_muldi3.o) + .bss 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_muldi3.o) + .data 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_udivmoddi4.o) + .bss 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_udivmoddi4.o) + .ARM.extab 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_udivmoddi4.o) + .text 0x0000000000000000 0x3c /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(bpabi.o) + .data 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(bpabi.o) + .bss 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(bpabi.o) + .debug_frame 0x0000000000000000 0x38 /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(bpabi.o) + .ARM.attributes + 0x0000000000000000 0x2c /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(bpabi.o) + .data 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_clzdi2.o) + .bss 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_clzdi2.o) + .text 0x0000000000000000 0x1cc /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_divdi3.o) + .data 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_divdi3.o) + .bss 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_divdi3.o) + .ARM.extab 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_divdi3.o) + .ARM.exidx 0x0000000000000000 0x8 /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_divdi3.o) + .debug_frame 0x0000000000000000 0x3c /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_divdi3.o) + .ARM.attributes + 0x0000000000000000 0x2c /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_divdi3.o) + .data 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_clzsi2.o) + .bss 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_clzsi2.o) + .text 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crtend.o + .data 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crtend.o + .bss 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crtend.o + .eh_frame 0x0000000000000000 0x4 /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crtend.o + .ARM.attributes + 0x0000000000000000 0x2c /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crtend.o + .text 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crtn.o + .data 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crtn.o + .bss 0x0000000000000000 0x0 /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crtn.o + +Memory Configuration + +Name Origin Length Attributes +RAM 0x0000000020000000 0x0000000000000800 xrw +FLASH 0x0000000008000000 0x0000000000004000 xr +*default* 0x0000000000000000 0xffffffffffffffff + +Linker script and memory map + +LOAD /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crti.o +LOAD /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crtbegin.o +LOAD /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/crt0.o +LOAD Core/Src/main.o +LOAD Core/Src/stm32l0xx_hal_msp.o +LOAD Core/Src/stm32l0xx_it.o +LOAD Core/Src/syscalls.o +LOAD Core/Src/sysmem.o +LOAD Core/Src/system_stm32l0xx.o +LOAD Core/Startup/startup_stm32l011f4ux.o +LOAD Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o +LOAD Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o +LOAD Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o +LOAD Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o +LOAD Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o +LOAD Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o +LOAD Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o +LOAD Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o +LOAD Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o +LOAD Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o +LOAD Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o +LOAD Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o +LOAD Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o +LOAD Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o +LOAD Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o +LOAD Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o +LOAD Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.o +LOAD Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.o +LOAD Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.o +LOAD Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.o +LOAD Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.o +LOAD Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.o +LOAD Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.o +START GROUP +LOAD /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a +LOAD /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libm.a +END GROUP +START GROUP +LOAD /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a +LOAD /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a +END GROUP +START GROUP +LOAD /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a +LOAD /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a +LOAD /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libnosys.a +END GROUP +START GROUP +LOAD /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a +LOAD /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a +LOAD /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libnosys.a +END GROUP +LOAD /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crtend.o +LOAD /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crtn.o + 0x0000000020000800 _estack = (ORIGIN (RAM) + LENGTH (RAM)) + 0x0000000000000200 _Min_Heap_Size = 0x200 + 0x0000000000000400 _Min_Stack_Size = 0x400 + +.isr_vector 0x0000000008000000 0xc0 + 0x0000000008000000 . = ALIGN (0x4) + *(.isr_vector) + .isr_vector 0x0000000008000000 0xc0 Core/Startup/startup_stm32l011f4ux.o + 0x0000000008000000 g_pfnVectors + 0x00000000080000c0 . = ALIGN (0x4) + +.text 0x00000000080000c0 0x1540 + 0x00000000080000c0 . = ALIGN (0x4) + *(.text) + .text 0x00000000080000c0 0x48 /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crtbegin.o + .text 0x0000000008000108 0x114 /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_udivsi3.o) + 0x0000000008000108 __udivsi3 + 0x0000000008000108 __aeabi_uidiv + 0x0000000008000214 __aeabi_uidivmod + .text 0x000000000800021c 0x4 /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_dvmd_tls.o) + 0x000000000800021c __aeabi_ldiv0 + 0x000000000800021c __aeabi_idiv0 + .text 0x0000000008000220 0x40 /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_aeabi_uldivmod.o) + 0x0000000008000220 __aeabi_uldivmod + .text 0x0000000008000260 0x50 /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_muldi3.o) + 0x0000000008000260 __aeabi_lmul + 0x0000000008000260 __muldi3 + .text 0x00000000080002b0 0x198 /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_udivmoddi4.o) + 0x00000000080002b0 __udivmoddi4 + .text 0x0000000008000448 0x18 /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_clzdi2.o) + 0x0000000008000448 __clzdi2 + .text 0x0000000008000460 0x3c /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_clzsi2.o) + 0x0000000008000460 __clzsi2 + *(.text*) + .text.LL_IOP_GRP1_EnableClock + 0x000000000800049c 0x1c Core/Src/main.o + .text.SystemClock_Config + 0x00000000080004b8 0x90 Core/Src/main.o + 0x00000000080004b8 SystemClock_Config + .text.startup.main + 0x0000000008000548 0x310 Core/Src/main.o + 0x0000000008000548 main + .text.HAL_MspInit + 0x0000000008000858 0x1c Core/Src/stm32l0xx_hal_msp.o + 0x0000000008000858 HAL_MspInit + .text.NMI_Handler + 0x0000000008000874 0x2 Core/Src/stm32l0xx_it.o + 0x0000000008000874 NMI_Handler + .text.HardFault_Handler + 0x0000000008000876 0x2 Core/Src/stm32l0xx_it.o + 0x0000000008000876 HardFault_Handler + .text.SVC_Handler + 0x0000000008000878 0x2 Core/Src/stm32l0xx_it.o + 0x0000000008000878 SVC_Handler + .text.PendSV_Handler + 0x000000000800087a 0x2 Core/Src/stm32l0xx_it.o + 0x000000000800087a PendSV_Handler + .text.SysTick_Handler + 0x000000000800087c 0x8 Core/Src/stm32l0xx_it.o + 0x000000000800087c SysTick_Handler + .text.DMA1_Channel2_3_IRQHandler + 0x0000000008000884 0x2 Core/Src/stm32l0xx_it.o + 0x0000000008000884 DMA1_Channel2_3_IRQHandler + .text.SystemInit + 0x0000000008000886 0x2 Core/Src/system_stm32l0xx.o + 0x0000000008000886 SystemInit + .text.Reset_Handler + 0x0000000008000888 0x80 Core/Startup/startup_stm32l011f4ux.o + 0x0000000008000888 Reset_Handler + .text.Default_Handler + 0x0000000008000908 0x2 Core/Startup/startup_stm32l011f4ux.o + 0x0000000008000908 ADC1_COMP_IRQHandler + 0x0000000008000908 PVD_IRQHandler + 0x0000000008000908 I2C1_IRQHandler + 0x0000000008000908 SPI1_IRQHandler + 0x0000000008000908 EXTI2_3_IRQHandler + 0x0000000008000908 RTC_IRQHandler + 0x0000000008000908 EXTI4_15_IRQHandler + 0x0000000008000908 RCC_IRQHandler + 0x0000000008000908 DMA1_Channel1_IRQHandler + 0x0000000008000908 Default_Handler + 0x0000000008000908 DMA1_Channel4_5_IRQHandler + 0x0000000008000908 EXTI0_1_IRQHandler + 0x0000000008000908 TIM21_IRQHandler + 0x0000000008000908 WWDG_IRQHandler + 0x0000000008000908 LPUART1_IRQHandler + 0x0000000008000908 TIM2_IRQHandler + 0x0000000008000908 USART2_IRQHandler + 0x0000000008000908 FLASH_IRQHandler + 0x0000000008000908 LPTIM1_IRQHandler + *fill* 0x000000000800090a 0x2 + .text.HAL_InitTick + 0x000000000800090c 0x48 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + 0x000000000800090c HAL_InitTick + .text.HAL_Init + 0x0000000008000954 0x28 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + 0x0000000008000954 HAL_Init + .text.HAL_IncTick + 0x000000000800097c 0x18 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + 0x000000000800097c HAL_IncTick + .text.HAL_GetTick + 0x0000000008000994 0xc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + 0x0000000008000994 HAL_GetTick + .text.HAL_Delay + 0x00000000080009a0 0x24 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + 0x00000000080009a0 HAL_Delay + .text.HAL_NVIC_SetPriority + 0x00000000080009c4 0x54 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + 0x00000000080009c4 HAL_NVIC_SetPriority + .text.HAL_SYSTICK_Config + 0x0000000008000a18 0x34 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + 0x0000000008000a18 HAL_SYSTICK_Config + .text.HAL_RCC_GetSysClockFreq + 0x0000000008000a4c 0x90 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + 0x0000000008000a4c HAL_RCC_GetSysClockFreq + .text.HAL_RCC_OscConfig + 0x0000000008000adc 0x4a0 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + 0x0000000008000adc HAL_RCC_OscConfig + .text.HAL_RCC_ClockConfig + 0x0000000008000f7c 0x19c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + 0x0000000008000f7c HAL_RCC_ClockConfig + .text.HAL_RCCEx_PeriphCLKConfig + 0x0000000008001118 0x178 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + 0x0000000008001118 HAL_RCCEx_PeriphCLKConfig + .text.LL_GPIO_Init + 0x0000000008001290 0xa2 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.o + 0x0000000008001290 LL_GPIO_Init + *fill* 0x0000000008001332 0x2 + .text.LL_I2C_Init + 0x0000000008001334 0x74 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.o + 0x0000000008001334 LL_I2C_Init + .text.LL_LPUART_Init + 0x00000000080013a8 0x7c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.o + 0x00000000080013a8 LL_LPUART_Init + .text.LL_RCC_HSI_IsReady + 0x0000000008001424 0x10 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.o + .text.LL_RCC_IsActiveFlag_HSIDIV + 0x0000000008001434 0x10 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.o + .text.RCC_GetHCLKClockFreq + 0x0000000008001444 0x18 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.o + 0x0000000008001444 RCC_GetHCLKClockFreq + .text.RCC_GetPCLK1ClockFreq + 0x000000000800145c 0x18 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.o + 0x000000000800145c RCC_GetPCLK1ClockFreq + .text.RCC_PLL_GetFreqDomain_SYS + 0x0000000008001474 0x50 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.o + 0x0000000008001474 RCC_PLL_GetFreqDomain_SYS + .text.RCC_GetSystemClockFreq + 0x00000000080014c4 0x60 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.o + 0x00000000080014c4 RCC_GetSystemClockFreq + .text.LL_RCC_GetLPUARTClockFreq + 0x0000000008001524 0x6c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.o + 0x0000000008001524 LL_RCC_GetLPUARTClockFreq + .text.__libc_init_array + 0x0000000008001590 0x48 /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-init.o) + 0x0000000008001590 __libc_init_array + .text.memset 0x00000000080015d8 0x10 /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-memset.o) + 0x00000000080015d8 memset + *(.glue_7) + .glue_7 0x00000000080015e8 0x0 linker stubs + *(.glue_7t) + .glue_7t 0x00000000080015e8 0x0 linker stubs + *(.eh_frame) + .eh_frame 0x00000000080015e8 0x0 /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crtbegin.o + *(.init) + .init 0x00000000080015e8 0x4 /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crti.o + 0x00000000080015e8 _init + .init 0x00000000080015ec 0x8 /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crtn.o + *(.fini) + .fini 0x00000000080015f4 0x4 /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crti.o + 0x00000000080015f4 _fini + .fini 0x00000000080015f8 0x8 /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crtn.o + 0x0000000008001600 . = ALIGN (0x4) + 0x0000000008001600 _etext = . + +.vfp11_veneer 0x0000000008001600 0x0 + .vfp11_veneer 0x0000000008001600 0x0 linker stubs + +.v4_bx 0x0000000008001600 0x0 + .v4_bx 0x0000000008001600 0x0 linker stubs + +.iplt 0x0000000008001600 0x0 + .iplt 0x0000000008001600 0x0 /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crtbegin.o + +.rodata 0x0000000008001600 0x24 + 0x0000000008001600 . = ALIGN (0x4) + *(.rodata) + *(.rodata*) + .rodata.AHBPrescTable + 0x0000000008001600 0x10 Core/Src/system_stm32l0xx.o + 0x0000000008001600 AHBPrescTable + .rodata.APBPrescTable + 0x0000000008001610 0x8 Core/Src/system_stm32l0xx.o + 0x0000000008001610 APBPrescTable + .rodata.PLLMulTable + 0x0000000008001618 0x9 Core/Src/system_stm32l0xx.o + 0x0000000008001618 PLLMulTable + 0x0000000008001624 . = ALIGN (0x4) + *fill* 0x0000000008001621 0x3 + +.ARM.extab 0x0000000008001624 0x0 + 0x0000000008001624 . = ALIGN (0x4) + *(.ARM.extab* .gnu.linkonce.armextab.*) + 0x0000000008001624 . = ALIGN (0x4) + +.ARM 0x0000000008001624 0x8 + 0x0000000008001624 . = ALIGN (0x4) + 0x0000000008001624 __exidx_start = . + *(.ARM.exidx*) + .ARM.exidx 0x0000000008001624 0x8 /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_udivmoddi4.o) + 0x000000000800162c __exidx_end = . + 0x000000000800162c . = ALIGN (0x4) + +.rel.dyn 0x000000000800162c 0x0 + .rel.iplt 0x000000000800162c 0x0 /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crtbegin.o + +.preinit_array 0x000000000800162c 0x0 + 0x000000000800162c . = ALIGN (0x4) + 0x000000000800162c PROVIDE (__preinit_array_start = .) + *(.preinit_array*) + 0x000000000800162c PROVIDE (__preinit_array_end = .) + 0x000000000800162c . = ALIGN (0x4) + +.init_array 0x000000000800162c 0x4 + 0x000000000800162c . = ALIGN (0x4) + 0x000000000800162c PROVIDE (__init_array_start = .) + *(SORT_BY_NAME(.init_array.*)) + *(.init_array*) + .init_array 0x000000000800162c 0x4 /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crtbegin.o + 0x0000000008001630 PROVIDE (__init_array_end = .) + 0x0000000008001630 . = ALIGN (0x4) + +.fini_array 0x0000000008001630 0x4 + 0x0000000008001630 . = ALIGN (0x4) + [!provide] PROVIDE (__fini_array_start = .) + *(SORT_BY_NAME(.fini_array.*)) + *(.fini_array*) + .fini_array 0x0000000008001630 0x4 /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crtbegin.o + [!provide] PROVIDE (__fini_array_end = .) + 0x0000000008001634 . = ALIGN (0x4) + 0x0000000008001634 _sidata = LOADADDR (.data) + +.data 0x0000000020000000 0xc load address 0x0000000008001634 + 0x0000000020000000 . = ALIGN (0x4) + 0x0000000020000000 _sdata = . + *(.data) + *(.data*) + .data.SystemCoreClock + 0x0000000020000000 0x4 Core/Src/system_stm32l0xx.o + 0x0000000020000000 SystemCoreClock + .data.uwTickFreq + 0x0000000020000004 0x1 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + 0x0000000020000004 uwTickFreq + *fill* 0x0000000020000005 0x3 + .data.uwTickPrio + 0x0000000020000008 0x4 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + 0x0000000020000008 uwTickPrio + *(.RamFunc) + *(.RamFunc*) + 0x000000002000000c . = ALIGN (0x4) + 0x000000002000000c _edata = . + +.igot.plt 0x000000002000000c 0x0 load address 0x0000000008001640 + .igot.plt 0x000000002000000c 0x0 /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crtbegin.o + 0x000000002000000c . = ALIGN (0x4) + +.bss 0x000000002000000c 0x20 load address 0x0000000008001640 + 0x000000002000000c _sbss = . + 0x000000002000000c __bss_start__ = _sbss + *(.bss) + .bss 0x000000002000000c 0x1c /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crtbegin.o + *(.bss*) + *(COMMON) + COMMON 0x0000000020000028 0x4 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + 0x0000000020000028 uwTick + 0x000000002000002c . = ALIGN (0x4) + 0x000000002000002c _ebss = . + 0x000000002000002c __bss_end__ = _ebss + +._user_heap_stack + 0x000000002000002c 0x604 load address 0x0000000008001640 + 0x0000000020000030 . = ALIGN (0x8) + *fill* 0x000000002000002c 0x4 + [!provide] PROVIDE (end = .) + 0x0000000020000030 PROVIDE (_end = .) + 0x0000000020000230 . = (. + _Min_Heap_Size) + *fill* 0x0000000020000030 0x200 + 0x0000000020000630 . = (. + _Min_Stack_Size) + *fill* 0x0000000020000230 0x400 + 0x0000000020000630 . = ALIGN (0x8) + +/DISCARD/ + libc.a(*) + libm.a(*) + libgcc.a(*) + +.ARM.attributes + 0x0000000000000000 0x28 + *(.ARM.attributes) + .ARM.attributes + 0x0000000000000000 0x1e /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crti.o + .ARM.attributes + 0x000000000000001e 0x2c /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crtbegin.o + .ARM.attributes + 0x000000000000004a 0x2c Core/Src/main.o + .ARM.attributes + 0x0000000000000076 0x2c Core/Src/stm32l0xx_hal_msp.o + .ARM.attributes + 0x00000000000000a2 0x2c Core/Src/stm32l0xx_it.o + .ARM.attributes + 0x00000000000000ce 0x2c Core/Src/system_stm32l0xx.o + .ARM.attributes + 0x00000000000000fa 0x22 Core/Startup/startup_stm32l011f4ux.o + .ARM.attributes + 0x000000000000011c 0x2c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .ARM.attributes + 0x0000000000000148 0x2c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .ARM.attributes + 0x0000000000000174 0x2c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .ARM.attributes + 0x00000000000001a0 0x2c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .ARM.attributes + 0x00000000000001cc 0x2c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.o + .ARM.attributes + 0x00000000000001f8 0x2c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.o + .ARM.attributes + 0x0000000000000224 0x2c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.o + .ARM.attributes + 0x0000000000000250 0x2c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.o + .ARM.attributes + 0x000000000000027c 0x2c /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-init.o) + .ARM.attributes + 0x00000000000002a8 0x2c /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-memset.o) + .ARM.attributes + 0x00000000000002d4 0x1e /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_udivsi3.o) + .ARM.attributes + 0x00000000000002f2 0x1e /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_dvmd_tls.o) + .ARM.attributes + 0x0000000000000310 0x1e /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_aeabi_uldivmod.o) + .ARM.attributes + 0x000000000000032e 0x2c /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_muldi3.o) + .ARM.attributes + 0x000000000000035a 0x2c /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_udivmoddi4.o) + .ARM.attributes + 0x0000000000000386 0x1e /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_clzdi2.o) + .ARM.attributes + 0x00000000000003a4 0x1e /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_clzsi2.o) + .ARM.attributes + 0x00000000000003c2 0x1e /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crtn.o +OUTPUT(iaq_wired_sensor.elf elf32-littlearm) +LOAD linker stubs +LOAD /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc.a +LOAD /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libm.a +LOAD /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a + +.debug_info 0x0000000000000000 0x6c2d + .debug_info 0x0000000000000000 0x1b86 Core/Src/main.o + .debug_info 0x0000000000001b86 0x2f0 Core/Src/stm32l0xx_hal_msp.o + .debug_info 0x0000000000001e76 0x21a Core/Src/stm32l0xx_it.o + .debug_info 0x0000000000002090 0x37c Core/Src/system_stm32l0xx.o + .debug_info 0x000000000000240c 0x22 Core/Startup/startup_stm32l011f4ux.o + .debug_info 0x000000000000242e 0x989 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .debug_info 0x0000000000002db7 0x961 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .debug_info 0x0000000000003718 0xc7e Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .debug_info 0x0000000000004396 0x607 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .debug_info 0x000000000000499d 0x85a Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.o + .debug_info 0x00000000000051f7 0x831 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.o + .debug_info 0x0000000000005a28 0x6fb Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.o + .debug_info 0x0000000000006123 0xb0a Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.o + +.debug_abbrev 0x0000000000000000 0x1b63 + .debug_abbrev 0x0000000000000000 0x3be Core/Src/main.o + .debug_abbrev 0x00000000000003be 0x109 Core/Src/stm32l0xx_hal_msp.o + .debug_abbrev 0x00000000000004c7 0x137 Core/Src/stm32l0xx_it.o + .debug_abbrev 0x00000000000005fe 0x14b Core/Src/system_stm32l0xx.o + .debug_abbrev 0x0000000000000749 0x12 Core/Startup/startup_stm32l011f4ux.o + .debug_abbrev 0x000000000000075b 0x2d4 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .debug_abbrev 0x0000000000000a2f 0x28d Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .debug_abbrev 0x0000000000000cbc 0x2f4 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .debug_abbrev 0x0000000000000fb0 0x212 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .debug_abbrev 0x00000000000011c2 0x226 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.o + .debug_abbrev 0x00000000000013e8 0x1fd Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.o + .debug_abbrev 0x00000000000015e5 0x249 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.o + .debug_abbrev 0x000000000000182e 0x335 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.o + +.debug_loc 0x0000000000000000 0x2331 + .debug_loc 0x0000000000000000 0x60f Core/Src/main.o + .debug_loc 0x000000000000060f 0x178 Core/Src/system_stm32l0xx.o + .debug_loc 0x0000000000000787 0x13e Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .debug_loc 0x00000000000008c5 0x44f Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .debug_loc 0x0000000000000d14 0x6fa Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .debug_loc 0x000000000000140e 0x377 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .debug_loc 0x0000000000001785 0x333 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.o + .debug_loc 0x0000000000001ab8 0x1f3 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.o + .debug_loc 0x0000000000001cab 0x21e Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.o + .debug_loc 0x0000000000001ec9 0x468 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.o + +.debug_aranges 0x0000000000000000 0x430 + .debug_aranges + 0x0000000000000000 0x38 Core/Src/main.o + .debug_aranges + 0x0000000000000038 0x20 Core/Src/stm32l0xx_hal_msp.o + .debug_aranges + 0x0000000000000058 0x38 Core/Src/stm32l0xx_it.o + .debug_aranges + 0x0000000000000090 0x28 Core/Src/system_stm32l0xx.o + .debug_aranges + 0x00000000000000b8 0x28 Core/Startup/startup_stm32l011f4ux.o + .debug_aranges + 0x00000000000000e0 0x108 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .debug_aranges + 0x00000000000001e8 0x78 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .debug_aranges + 0x0000000000000260 0x68 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .debug_aranges + 0x00000000000002c8 0x58 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .debug_aranges + 0x0000000000000320 0x30 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.o + .debug_aranges + 0x0000000000000350 0x30 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.o + .debug_aranges + 0x0000000000000380 0x30 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.o + .debug_aranges + 0x00000000000003b0 0x80 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.o + +.debug_ranges 0x0000000000000000 0xa18 + .debug_ranges 0x0000000000000000 0x3c0 Core/Src/main.o + .debug_ranges 0x00000000000003c0 0x10 Core/Src/stm32l0xx_hal_msp.o + .debug_ranges 0x00000000000003d0 0x28 Core/Src/stm32l0xx_it.o + .debug_ranges 0x00000000000003f8 0x18 Core/Src/system_stm32l0xx.o + .debug_ranges 0x0000000000000410 0x20 Core/Startup/startup_stm32l011f4ux.o + .debug_ranges 0x0000000000000430 0xf8 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .debug_ranges 0x0000000000000528 0x100 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .debug_ranges 0x0000000000000628 0xa0 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .debug_ranges 0x00000000000006c8 0x48 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .debug_ranges 0x0000000000000710 0x38 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.o + .debug_ranges 0x0000000000000748 0x68 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.o + .debug_ranges 0x00000000000007b0 0x58 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.o + .debug_ranges 0x0000000000000808 0x210 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.o + +.debug_macro 0x0000000000000000 0x1133a + .debug_macro 0x0000000000000000 0x209 Core/Src/main.o + .debug_macro 0x0000000000000209 0xa8a Core/Src/main.o + .debug_macro 0x0000000000000c93 0x119 Core/Src/main.o + .debug_macro 0x0000000000000dac 0x2e Core/Src/main.o + .debug_macro 0x0000000000000dda 0x28 Core/Src/main.o + .debug_macro 0x0000000000000e02 0x22 Core/Src/main.o + .debug_macro 0x0000000000000e24 0x8e Core/Src/main.o + .debug_macro 0x0000000000000eb2 0x51 Core/Src/main.o + .debug_macro 0x0000000000000f03 0x103 Core/Src/main.o + .debug_macro 0x0000000000001006 0x6a Core/Src/main.o + .debug_macro 0x0000000000001070 0x1df Core/Src/main.o + .debug_macro 0x000000000000124f 0x1c Core/Src/main.o + .debug_macro 0x000000000000126b 0x22 Core/Src/main.o + .debug_macro 0x000000000000128d 0xb5 Core/Src/main.o + .debug_macro 0x0000000000001342 0x3ad Core/Src/main.o + .debug_macro 0x00000000000016ef 0x7b9c Core/Src/main.o + .debug_macro 0x000000000000928b 0x3c Core/Src/main.o + .debug_macro 0x00000000000092c7 0x352b Core/Src/main.o + .debug_macro 0x000000000000c7f2 0x174 Core/Src/main.o + .debug_macro 0x000000000000c966 0x5b Core/Src/main.o + .debug_macro 0x000000000000c9c1 0x899 Core/Src/main.o + .debug_macro 0x000000000000d25a 0x42e Core/Src/main.o + .debug_macro 0x000000000000d688 0x182 Core/Src/main.o + .debug_macro 0x000000000000d80a 0x13f Core/Src/main.o + .debug_macro 0x000000000000d949 0xf1 Core/Src/main.o + .debug_macro 0x000000000000da3a 0x28e Core/Src/main.o + .debug_macro 0x000000000000dcc8 0x28 Core/Src/main.o + .debug_macro 0x000000000000dcf0 0x129 Core/Src/main.o + .debug_macro 0x000000000000de19 0x244 Core/Src/main.o + .debug_macro 0x000000000000e05d 0x22c Core/Src/main.o + .debug_macro 0x000000000000e289 0x5b Core/Src/main.o + .debug_macro 0x000000000000e2e4 0xa5 Core/Src/main.o + .debug_macro 0x000000000000e389 0x187 Core/Src/main.o + .debug_macro 0x000000000000e510 0x16 Core/Src/main.o + .debug_macro 0x000000000000e526 0x11c Core/Src/main.o + .debug_macro 0x000000000000e642 0x285 Core/Src/main.o + .debug_macro 0x000000000000e8c7 0x246 Core/Src/main.o + .debug_macro 0x000000000000eb0d 0x229 Core/Src/main.o + .debug_macro 0x000000000000ed36 0x3b4 Core/Src/main.o + .debug_macro 0x000000000000f0ea 0x13d Core/Src/main.o + .debug_macro 0x000000000000f227 0x12d Core/Src/main.o + .debug_macro 0x000000000000f354 0x109 Core/Src/main.o + .debug_macro 0x000000000000f45d 0xa7 Core/Src/main.o + .debug_macro 0x000000000000f504 0x16 Core/Src/main.o + .debug_macro 0x000000000000f51a 0x2a Core/Src/main.o + .debug_macro 0x000000000000f544 0xdb Core/Src/main.o + .debug_macro 0x000000000000f61f 0x28 Core/Src/main.o + .debug_macro 0x000000000000f647 0x209 Core/Src/stm32l0xx_hal_msp.o + .debug_macro 0x000000000000f850 0x213 Core/Src/stm32l0xx_it.o + .debug_macro 0x000000000000fa63 0x197 Core/Src/system_stm32l0xx.o + .debug_macro 0x000000000000fbfa 0x1bb Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .debug_macro 0x000000000000fdb5 0x197 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .debug_macro 0x000000000000ff4c 0x1bb Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .debug_macro 0x0000000000010107 0x197 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .debug_macro 0x000000000001029e 0x1d9 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.o + .debug_macro 0x0000000000010477 0x127 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.o + .debug_macro 0x000000000001059e 0x1d9 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.o + .debug_macro 0x0000000000010777 0x240 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.o + .debug_macro 0x00000000000109b7 0x1ee Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.o + .debug_macro 0x0000000000010ba5 0x223 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.o + .debug_macro 0x0000000000010dc8 0x1c4 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.o + .debug_macro 0x0000000000010f8c 0x3ae Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.o + +.debug_line 0x0000000000000000 0x7f60 + .debug_line 0x0000000000000000 0xfbb Core/Src/main.o + .debug_line 0x0000000000000fbb 0x770 Core/Src/stm32l0xx_hal_msp.o + .debug_line 0x000000000000172b 0x7d5 Core/Src/stm32l0xx_it.o + .debug_line 0x0000000000001f00 0x758 Core/Src/system_stm32l0xx.o + .debug_line 0x0000000000002658 0x9b Core/Startup/startup_stm32l011f4ux.o + .debug_line 0x00000000000026f3 0xaff Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .debug_line 0x00000000000031f2 0x9dc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .debug_line 0x0000000000003bce 0x1249 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .debug_line 0x0000000000004e17 0xb28 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .debug_line 0x000000000000593f 0x881 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.o + .debug_line 0x00000000000061c0 0x843 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.o + .debug_line 0x0000000000006a03 0x82c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.o + .debug_line 0x000000000000722f 0xd31 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.o + +.debug_str 0x0000000000000000 0x62aa3 + .debug_str 0x0000000000000000 0x60caf Core/Src/main.o + 0x61704 (size before relaxing) + .debug_str 0x0000000000060caf 0x2c Core/Src/stm32l0xx_hal_msp.o + 0x60cd1 (size before relaxing) + .debug_str 0x0000000000060cdb 0x9d Core/Src/stm32l0xx_it.o + 0x60caa (size before relaxing) + .debug_str 0x0000000000060d78 0x61 Core/Src/system_stm32l0xx.o + 0x5a86f (size before relaxing) + .debug_str 0x0000000000060dd9 0x36 Core/Startup/startup_stm32l011f4ux.o + 0x92 (size before relaxing) + .debug_str 0x0000000000060e0f 0x426 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + 0x5aeb3 (size before relaxing) + .debug_str 0x0000000000061235 0x146 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + 0x5aba3 (size before relaxing) + .debug_str 0x000000000006137b 0x243 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + 0x5ace7 (size before relaxing) + .debug_str 0x00000000000615be 0x133 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + 0x5aaab (size before relaxing) + .debug_str 0x00000000000616f1 0x545 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.o + 0x5b971 (size before relaxing) + .debug_str 0x0000000000061c36 0x3ef Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.o + 0x5c0e6 (size before relaxing) + .debug_str 0x0000000000062025 0x50c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.o + 0x5d75c (size before relaxing) + .debug_str 0x0000000000062531 0x572 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.o + 0x5c666 (size before relaxing) + +.comment 0x0000000000000000 0x53 + .comment 0x0000000000000000 0x53 Core/Src/main.o + 0x54 (size before relaxing) + .comment 0x0000000000000053 0x54 Core/Src/stm32l0xx_hal_msp.o + .comment 0x0000000000000053 0x54 Core/Src/stm32l0xx_it.o + .comment 0x0000000000000053 0x54 Core/Src/system_stm32l0xx.o + .comment 0x0000000000000053 0x54 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .comment 0x0000000000000053 0x54 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .comment 0x0000000000000053 0x54 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .comment 0x0000000000000053 0x54 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .comment 0x0000000000000053 0x54 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.o + .comment 0x0000000000000053 0x54 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.o + .comment 0x0000000000000053 0x54 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.o + .comment 0x0000000000000053 0x54 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.o + +.debug_frame 0x0000000000000000 0x91c + .debug_frame 0x0000000000000000 0x6c Core/Src/main.o + .debug_frame 0x000000000000006c 0x20 Core/Src/stm32l0xx_hal_msp.o + .debug_frame 0x000000000000008c 0x78 Core/Src/stm32l0xx_it.o + .debug_frame 0x0000000000000104 0x3c Core/Src/system_stm32l0xx.o + .debug_frame 0x0000000000000140 0x234 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o + .debug_frame 0x0000000000000374 0xe4 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o + .debug_frame 0x0000000000000458 0x118 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o + .debug_frame 0x0000000000000570 0xbc Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o + .debug_frame 0x000000000000062c 0x54 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.o + .debug_frame 0x0000000000000680 0x4c Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.o + .debug_frame 0x00000000000006cc 0x50 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.o + .debug_frame 0x000000000000071c 0x124 Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.o + .debug_frame 0x0000000000000840 0x2c /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-init.o) + .debug_frame 0x000000000000086c 0x20 /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-memset.o) + .debug_frame 0x000000000000088c 0x20 /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_udivsi3.o) + .debug_frame 0x00000000000008ac 0x34 /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_muldi3.o) + .debug_frame 0x00000000000008e0 0x3c /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_udivmoddi4.o) diff --git a/fw/Debug/makefile b/fw/Debug/makefile new file mode 100644 index 0000000..7d54beb --- /dev/null +++ b/fw/Debug/makefile @@ -0,0 +1,101 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (9-2020-q2-update) +################################################################################ + +-include ../makefile.init + +RM := rm -rf + +# All of the sources participating in the build are defined here +-include sources.mk +-include Drivers/STM32L0xx_HAL_Driver/Src/subdir.mk +-include Core/Startup/subdir.mk +-include Core/Src/subdir.mk +-include subdir.mk +-include objects.mk + +ifneq ($(MAKECMDGOALS),clean) +ifneq ($(strip $(S_DEPS)),) +-include $(S_DEPS) +endif +ifneq ($(strip $(S_UPPER_DEPS)),) +-include $(S_UPPER_DEPS) +endif +ifneq ($(strip $(C_DEPS)),) +-include $(C_DEPS) +endif +endif + +-include ../makefile.defs + +OPTIONAL_TOOL_DEPS := \ +$(wildcard ../makefile.defs) \ +$(wildcard ../makefile.init) \ +$(wildcard ../makefile.targets) \ + + +BUILD_ARTIFACT_NAME := iaq_wired_sensor +BUILD_ARTIFACT_EXTENSION := elf +BUILD_ARTIFACT_PREFIX := +BUILD_ARTIFACT := $(BUILD_ARTIFACT_PREFIX)$(BUILD_ARTIFACT_NAME).$(BUILD_ARTIFACT_EXTENSION) + +# Add inputs and outputs from these tool invocations to the build variables +EXECUTABLES += \ +iaq_wired_sensor.elf \ + +SIZE_OUTPUT += \ +default.size.stdout \ + +OBJDUMP_LIST += \ +iaq_wired_sensor.list \ + +OBJCOPY_BIN += \ +iaq_wired_sensor.bin \ + + +# All Target +all: main-build + +# Main-build Target +main-build: iaq_wired_sensor.elf secondary-outputs + +# Tool invocations +iaq_wired_sensor.elf: $(OBJS) $(USER_OBJS) /home/david/Personal/Projects/HDIoT/Smart_Household/Wired_Sensors/iaq_wired_sensor/fw/STM32L011F4UX_FLASH.ld makefile objects.list $(OPTIONAL_TOOL_DEPS) + arm-none-eabi-gcc -o "iaq_wired_sensor.elf" @"objects.list" $(USER_OBJS) $(LIBS) -mcpu=cortex-m0plus -T"/home/david/Personal/Projects/HDIoT/Smart_Household/Wired_Sensors/iaq_wired_sensor/fw/STM32L011F4UX_FLASH.ld" --specs=nosys.specs -Wl,-Map="iaq_wired_sensor.map" -Wl,--gc-sections -static --specs=nano.specs -mfloat-abi=soft -mthumb -Wl,--start-group -lc -lm -Wl,--end-group + @echo 'Finished building target: $@' + @echo ' ' + +default.size.stdout: $(EXECUTABLES) makefile objects.list $(OPTIONAL_TOOL_DEPS) + arm-none-eabi-size $(EXECUTABLES) + @echo 'Finished building: $@' + @echo ' ' + +iaq_wired_sensor.list: $(EXECUTABLES) makefile objects.list $(OPTIONAL_TOOL_DEPS) + arm-none-eabi-objdump -h -S $(EXECUTABLES) > "iaq_wired_sensor.list" + @echo 'Finished building: $@' + @echo ' ' + +iaq_wired_sensor.bin: $(EXECUTABLES) makefile objects.list $(OPTIONAL_TOOL_DEPS) + arm-none-eabi-objcopy -O binary $(EXECUTABLES) "iaq_wired_sensor.bin" + @echo 'Finished building: $@' + @echo ' ' + +# Other Targets +clean: + -$(RM) * + -@echo ' ' + +secondary-outputs: $(SIZE_OUTPUT) $(OBJDUMP_LIST) $(OBJCOPY_BIN) + +fail-specified-linker-script-missing: + @echo 'Error: Cannot find the specified linker script. Check the linker settings in the build configuration.' + @exit 2 + +warn-no-linker-script-specified: + @echo 'Warning: No linker script specified. Check the linker settings in the build configuration.' + +.PHONY: all clean dependents fail-specified-linker-script-missing warn-no-linker-script-specified +.SECONDARY: + +-include ../makefile.targets diff --git a/fw/Debug/objects.list b/fw/Debug/objects.list new file mode 100644 index 0000000..ac9feea --- /dev/null +++ b/fw/Debug/objects.list @@ -0,0 +1,30 @@ +"Core/Src/main.o" +"Core/Src/stm32l0xx_hal_msp.o" +"Core/Src/stm32l0xx_it.o" +"Core/Src/syscalls.o" +"Core/Src/sysmem.o" +"Core/Src/system_stm32l0xx.o" +"Core/Startup/startup_stm32l011f4ux.o" +"Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o" +"Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o" +"Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_dma.o" +"Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_exti.o" +"Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash.o" +"Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ex.o" +"Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_flash_ramfunc.o" +"Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o" +"Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o" +"Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o" +"Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr.o" +"Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_pwr_ex.o" +"Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o" +"Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o" +"Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o" +"Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o" +"Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.o" +"Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.o" +"Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.o" +"Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.o" +"Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.o" +"Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.o" +"Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.o" diff --git a/fw/Debug/objects.mk b/fw/Debug/objects.mk new file mode 100644 index 0000000..e12976d --- /dev/null +++ b/fw/Debug/objects.mk @@ -0,0 +1,9 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (9-2020-q2-update) +################################################################################ + +USER_OBJS := + +LIBS := + diff --git a/fw/Debug/sources.mk b/fw/Debug/sources.mk new file mode 100644 index 0000000..a511ac3 --- /dev/null +++ b/fw/Debug/sources.mk @@ -0,0 +1,26 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (9-2020-q2-update) +################################################################################ + +ELF_SRCS := +OBJ_SRCS := +S_SRCS := +C_SRCS := +S_UPPER_SRCS := +O_SRCS := +SIZE_OUTPUT := +OBJDUMP_LIST := +EXECUTABLES := +OBJS := +S_DEPS := +S_UPPER_DEPS := +C_DEPS := +OBJCOPY_BIN := + +# Every subdirectory with source files must be described here +SUBDIRS := \ +Core/Src \ +Core/Startup \ +Drivers/STM32L0xx_HAL_Driver/Src \ + diff --git a/fw/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h b/fw/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h deleted file mode 100644 index a4063c5..0000000 --- a/fw/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart.h +++ /dev/null @@ -1,1588 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l0xx_hal_uart.h - * @author MCD Application Team - * @brief Header file of UART HAL module. - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef STM32L0xx_HAL_UART_H -#define STM32L0xx_HAL_UART_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l0xx_hal_def.h" - -/** @addtogroup STM32L0xx_HAL_Driver - * @{ - */ - -/** @addtogroup UART - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup UART_Exported_Types UART Exported Types - * @{ - */ - -/** - * @brief UART Init Structure definition - */ -typedef struct -{ - uint32_t BaudRate; /*!< This member configures the UART communication baud rate. - The baud rate register is computed using the following formula: - LPUART: - ======= - Baud Rate Register = ((256 * lpuart_ker_ck) / ((huart->Init.BaudRate))) - where lpuart_ker_ck is the UART input clock - UART: - ===== - - If oversampling is 16 or in LIN mode, - Baud Rate Register = ((uart_ker_ck) / ((huart->Init.BaudRate))) - - If oversampling is 8, - Baud Rate Register[15:4] = ((2 * uart_ker_ck) / ((huart->Init.BaudRate)))[15:4] - Baud Rate Register[3] = 0 - Baud Rate Register[2:0] = (((2 * uart_ker_ck) / ((huart->Init.BaudRate)))[3:0]) >> 1 - where uart_ker_ck is the UART input clock */ - - uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. - This parameter can be a value of @ref UARTEx_Word_Length. */ - - uint32_t StopBits; /*!< Specifies the number of stop bits transmitted. - This parameter can be a value of @ref UART_Stop_Bits. */ - - uint32_t Parity; /*!< Specifies the parity mode. - This parameter can be a value of @ref UART_Parity - @note When parity is enabled, the computed parity is inserted - at the MSB position of the transmitted data (9th bit when - the word length is set to 9 data bits; 8th bit when the - word length is set to 8 data bits). */ - - uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled. - This parameter can be a value of @ref UART_Mode. */ - - uint32_t HwFlowCtl; /*!< Specifies whether the hardware flow control mode is enabled - or disabled. - This parameter can be a value of @ref UART_Hardware_Flow_Control. */ - - uint32_t OverSampling; /*!< Specifies whether the Over sampling 8 is enabled or disabled, - to achieve higher speed (up to f_PCLK/8). - This parameter can be a value of @ref UART_Over_Sampling. */ - - uint32_t OneBitSampling; /*!< Specifies whether a single sample or three samples' majority vote is selected. - Selecting the single sample method increases the receiver tolerance to clock - deviations. This parameter can be a value of @ref UART_OneBit_Sampling. */ - - -} UART_InitTypeDef; - -/** - * @brief UART Advanced Features initialization structure definition - */ -typedef struct -{ - uint32_t AdvFeatureInit; /*!< Specifies which advanced UART features is initialized. Several - Advanced Features may be initialized at the same time . - This parameter can be a value of - @ref UART_Advanced_Features_Initialization_Type. */ - - uint32_t TxPinLevelInvert; /*!< Specifies whether the TX pin active level is inverted. - This parameter can be a value of @ref UART_Tx_Inv. */ - - uint32_t RxPinLevelInvert; /*!< Specifies whether the RX pin active level is inverted. - This parameter can be a value of @ref UART_Rx_Inv. */ - - uint32_t DataInvert; /*!< Specifies whether data are inverted (positive/direct logic - vs negative/inverted logic). - This parameter can be a value of @ref UART_Data_Inv. */ - - uint32_t Swap; /*!< Specifies whether TX and RX pins are swapped. - This parameter can be a value of @ref UART_Rx_Tx_Swap. */ - - uint32_t OverrunDisable; /*!< Specifies whether the reception overrun detection is disabled. - This parameter can be a value of @ref UART_Overrun_Disable. */ - - uint32_t DMADisableonRxError; /*!< Specifies whether the DMA is disabled in case of reception error. - This parameter can be a value of @ref UART_DMA_Disable_on_Rx_Error. */ - - uint32_t AutoBaudRateEnable; /*!< Specifies whether auto Baud rate detection is enabled. - This parameter can be a value of @ref UART_AutoBaudRate_Enable. */ - - uint32_t AutoBaudRateMode; /*!< If auto Baud rate detection is enabled, specifies how the rate - detection is carried out. - This parameter can be a value of @ref UART_AutoBaud_Rate_Mode. */ - - uint32_t MSBFirst; /*!< Specifies whether MSB is sent first on UART line. - This parameter can be a value of @ref UART_MSB_First. */ -} UART_AdvFeatureInitTypeDef; - -/** - * @brief HAL UART State definition - * @note HAL UART State value is a combination of 2 different substates: - * gState and RxState (see @ref UART_State_Definition). - * - gState contains UART state information related to global Handle management - * and also information related to Tx operations. - * gState value coding follow below described bitmap : - * b7-b6 Error information - * 00 : No Error - * 01 : (Not Used) - * 10 : Timeout - * 11 : Error - * b5 Peripheral initialization status - * 0 : Reset (Peripheral not initialized) - * 1 : Init done (Peripheral initialized. HAL UART Init function already called) - * b4-b3 (not used) - * xx : Should be set to 00 - * b2 Intrinsic process state - * 0 : Ready - * 1 : Busy (Peripheral busy with some configuration or internal operations) - * b1 (not used) - * x : Should be set to 0 - * b0 Tx state - * 0 : Ready (no Tx operation ongoing) - * 1 : Busy (Tx operation ongoing) - * - RxState contains information related to Rx operations. - * RxState value coding follow below described bitmap : - * b7-b6 (not used) - * xx : Should be set to 00 - * b5 Peripheral initialization status - * 0 : Reset (Peripheral not initialized) - * 1 : Init done (Peripheral initialized) - * b4-b2 (not used) - * xxx : Should be set to 000 - * b1 Rx state - * 0 : Ready (no Rx operation ongoing) - * 1 : Busy (Rx operation ongoing) - * b0 (not used) - * x : Should be set to 0. - */ -typedef uint32_t HAL_UART_StateTypeDef; - -/** - * @brief UART clock sources definition - */ -typedef enum -{ - UART_CLOCKSOURCE_PCLK1 = 0x00U, /*!< PCLK1 clock source */ - UART_CLOCKSOURCE_PCLK2 = 0x01U, /*!< PCLK2 clock source */ - UART_CLOCKSOURCE_HSI = 0x02U, /*!< HSI clock source */ - UART_CLOCKSOURCE_SYSCLK = 0x04U, /*!< SYSCLK clock source */ - UART_CLOCKSOURCE_LSE = 0x08U, /*!< LSE clock source */ - UART_CLOCKSOURCE_UNDEFINED = 0x10U /*!< Undefined clock source */ -} UART_ClockSourceTypeDef; - -/** - * @brief HAL UART Reception type definition - * @note HAL UART Reception type value aims to identify which type of Reception is ongoing. - * It is expected to admit following values : - * HAL_UART_RECEPTION_STANDARD = 0x00U, - * HAL_UART_RECEPTION_TOIDLE = 0x01U, - * HAL_UART_RECEPTION_TORTO = 0x02U, - * HAL_UART_RECEPTION_TOCHARMATCH = 0x03U, - */ -typedef uint32_t HAL_UART_RxTypeTypeDef; - -/** - * @brief UART handle Structure definition - */ -typedef struct __UART_HandleTypeDef -{ - USART_TypeDef *Instance; /*!< UART registers base address */ - - UART_InitTypeDef Init; /*!< UART communication parameters */ - - UART_AdvFeatureInitTypeDef AdvancedInit; /*!< UART Advanced Features initialization parameters */ - - uint8_t *pTxBuffPtr; /*!< Pointer to UART Tx transfer Buffer */ - - uint16_t TxXferSize; /*!< UART Tx Transfer size */ - - __IO uint16_t TxXferCount; /*!< UART Tx Transfer Counter */ - - uint8_t *pRxBuffPtr; /*!< Pointer to UART Rx transfer Buffer */ - - uint16_t RxXferSize; /*!< UART Rx Transfer size */ - - __IO uint16_t RxXferCount; /*!< UART Rx Transfer Counter */ - - uint16_t Mask; /*!< UART Rx RDR register mask */ - - __IO HAL_UART_RxTypeTypeDef ReceptionType; /*!< Type of ongoing reception */ - - void (*RxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Rx IRQ handler */ - - void (*TxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Tx IRQ handler */ - - DMA_HandleTypeDef *hdmatx; /*!< UART Tx DMA Handle parameters */ - - DMA_HandleTypeDef *hdmarx; /*!< UART Rx DMA Handle parameters */ - - HAL_LockTypeDef Lock; /*!< Locking object */ - - __IO HAL_UART_StateTypeDef gState; /*!< UART state information related to global Handle management - and also related to Tx operations. This parameter - can be a value of @ref HAL_UART_StateTypeDef */ - - __IO HAL_UART_StateTypeDef RxState; /*!< UART state information related to Rx operations. This - parameter can be a value of @ref HAL_UART_StateTypeDef */ - - __IO uint32_t ErrorCode; /*!< UART Error code */ - -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - void (* TxHalfCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Tx Half Complete Callback */ - void (* TxCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Tx Complete Callback */ - void (* RxHalfCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Rx Half Complete Callback */ - void (* RxCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Rx Complete Callback */ - void (* ErrorCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Error Callback */ - void (* AbortCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Complete Callback */ - void (* AbortTransmitCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Transmit Complete Callback */ - void (* AbortReceiveCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Receive Complete Callback */ - void (* WakeupCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Wakeup Callback */ - void (* RxEventCallback)(struct __UART_HandleTypeDef *huart, uint16_t Pos); /*!< UART Reception Event Callback */ - - void (* MspInitCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Msp Init callback */ - void (* MspDeInitCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Msp DeInit callback */ -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ - -} UART_HandleTypeDef; - -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) -/** - * @brief HAL UART Callback ID enumeration definition - */ -typedef enum -{ - HAL_UART_TX_HALFCOMPLETE_CB_ID = 0x00U, /*!< UART Tx Half Complete Callback ID */ - HAL_UART_TX_COMPLETE_CB_ID = 0x01U, /*!< UART Tx Complete Callback ID */ - HAL_UART_RX_HALFCOMPLETE_CB_ID = 0x02U, /*!< UART Rx Half Complete Callback ID */ - HAL_UART_RX_COMPLETE_CB_ID = 0x03U, /*!< UART Rx Complete Callback ID */ - HAL_UART_ERROR_CB_ID = 0x04U, /*!< UART Error Callback ID */ - HAL_UART_ABORT_COMPLETE_CB_ID = 0x05U, /*!< UART Abort Complete Callback ID */ - HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x06U, /*!< UART Abort Transmit Complete Callback ID */ - HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID = 0x07U, /*!< UART Abort Receive Complete Callback ID */ - HAL_UART_WAKEUP_CB_ID = 0x08U, /*!< UART Wakeup Callback ID */ - - HAL_UART_MSPINIT_CB_ID = 0x0BU, /*!< UART MspInit callback ID */ - HAL_UART_MSPDEINIT_CB_ID = 0x0CU /*!< UART MspDeInit callback ID */ - -} HAL_UART_CallbackIDTypeDef; - -/** - * @brief HAL UART Callback pointer definition - */ -typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer to an UART callback function */ -typedef void (*pUART_RxEventCallbackTypeDef)(struct __UART_HandleTypeDef *huart, uint16_t Pos); /*!< pointer to a UART Rx Event specific callback function */ - -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ - -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup UART_Exported_Constants UART Exported Constants - * @{ - */ - -/** @defgroup UART_State_Definition UART State Code Definition - * @{ - */ -#define HAL_UART_STATE_RESET 0x00000000U /*!< Peripheral is not initialized - Value is allowed for gState and RxState */ -#define HAL_UART_STATE_READY 0x00000020U /*!< Peripheral Initialized and ready for use - Value is allowed for gState and RxState */ -#define HAL_UART_STATE_BUSY 0x00000024U /*!< an internal process is ongoing - Value is allowed for gState only */ -#define HAL_UART_STATE_BUSY_TX 0x00000021U /*!< Data Transmission process is ongoing - Value is allowed for gState only */ -#define HAL_UART_STATE_BUSY_RX 0x00000022U /*!< Data Reception process is ongoing - Value is allowed for RxState only */ -#define HAL_UART_STATE_BUSY_TX_RX 0x00000023U /*!< Data Transmission and Reception process is ongoing - Not to be used for neither gState nor RxState.Value is result - of combination (Or) between gState and RxState values */ -#define HAL_UART_STATE_TIMEOUT 0x000000A0U /*!< Timeout state - Value is allowed for gState only */ -#define HAL_UART_STATE_ERROR 0x000000E0U /*!< Error - Value is allowed for gState only */ -/** - * @} - */ - -/** @defgroup UART_Error_Definition UART Error Definition - * @{ - */ -#define HAL_UART_ERROR_NONE (0x00000000U) /*!< No error */ -#define HAL_UART_ERROR_PE (0x00000001U) /*!< Parity error */ -#define HAL_UART_ERROR_NE (0x00000002U) /*!< Noise error */ -#define HAL_UART_ERROR_FE (0x00000004U) /*!< Frame error */ -#define HAL_UART_ERROR_ORE (0x00000008U) /*!< Overrun error */ -#define HAL_UART_ERROR_DMA (0x00000010U) /*!< DMA transfer error */ -#define HAL_UART_ERROR_RTO (0x00000020U) /*!< Receiver Timeout error */ - -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) -#define HAL_UART_ERROR_INVALID_CALLBACK (0x00000040U) /*!< Invalid Callback error */ -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ -/** - * @} - */ - -/** @defgroup UART_Stop_Bits UART Number of Stop Bits - * @{ - */ -#define UART_STOPBITS_0_5 USART_CR2_STOP_0 /*!< UART frame with 0.5 stop bit */ -#define UART_STOPBITS_1 0x00000000U /*!< UART frame with 1 stop bit */ -#define UART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1) /*!< UART frame with 1.5 stop bits */ -#define UART_STOPBITS_2 USART_CR2_STOP_1 /*!< UART frame with 2 stop bits */ -/** - * @} - */ - -/** @defgroup UART_Parity UART Parity - * @{ - */ -#define UART_PARITY_NONE 0x00000000U /*!< No parity */ -#define UART_PARITY_EVEN USART_CR1_PCE /*!< Even parity */ -#define UART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< Odd parity */ -/** - * @} - */ - -/** @defgroup UART_Hardware_Flow_Control UART Hardware Flow Control - * @{ - */ -#define UART_HWCONTROL_NONE 0x00000000U /*!< No hardware control */ -#define UART_HWCONTROL_RTS USART_CR3_RTSE /*!< Request To Send */ -#define UART_HWCONTROL_CTS USART_CR3_CTSE /*!< Clear To Send */ -#define UART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) /*!< Request and Clear To Send */ -/** - * @} - */ - -/** @defgroup UART_Mode UART Transfer Mode - * @{ - */ -#define UART_MODE_RX USART_CR1_RE /*!< RX mode */ -#define UART_MODE_TX USART_CR1_TE /*!< TX mode */ -#define UART_MODE_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< RX and TX mode */ -/** - * @} - */ - -/** @defgroup UART_State UART State - * @{ - */ -#define UART_STATE_DISABLE 0x00000000U /*!< UART disabled */ -#define UART_STATE_ENABLE USART_CR1_UE /*!< UART enabled */ -/** - * @} - */ - -/** @defgroup UART_Over_Sampling UART Over Sampling - * @{ - */ -#define UART_OVERSAMPLING_16 0x00000000U /*!< Oversampling by 16 */ -#define UART_OVERSAMPLING_8 USART_CR1_OVER8 /*!< Oversampling by 8 */ -/** - * @} - */ - -/** @defgroup UART_OneBit_Sampling UART One Bit Sampling Method - * @{ - */ -#define UART_ONE_BIT_SAMPLE_DISABLE 0x00000000U /*!< One-bit sampling disable */ -#define UART_ONE_BIT_SAMPLE_ENABLE USART_CR3_ONEBIT /*!< One-bit sampling enable */ -/** - * @} - */ - -/** @defgroup UART_AutoBaud_Rate_Mode UART Advanced Feature AutoBaud Rate Mode - * @{ - */ -#define UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT 0x00000000U /*!< Auto Baud rate detection - on start bit */ -#define UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE USART_CR2_ABRMODE_0 /*!< Auto Baud rate detection - on falling edge */ -#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME USART_CR2_ABRMODE_1 /*!< Auto Baud rate detection - on 0x7F frame detection */ -#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME USART_CR2_ABRMODE /*!< Auto Baud rate detection - on 0x55 frame detection */ -/** - * @} - */ - -/** @defgroup UART_Receiver_Timeout UART Receiver Timeout - * @{ - */ -#define UART_RECEIVER_TIMEOUT_DISABLE 0x00000000U /*!< UART Receiver Timeout disable */ -#define UART_RECEIVER_TIMEOUT_ENABLE USART_CR2_RTOEN /*!< UART Receiver Timeout enable */ -/** - * @} - */ - -/** @defgroup UART_LIN UART Local Interconnection Network mode - * @{ - */ -#define UART_LIN_DISABLE 0x00000000U /*!< Local Interconnect Network disable */ -#define UART_LIN_ENABLE USART_CR2_LINEN /*!< Local Interconnect Network enable */ -/** - * @} - */ - -/** @defgroup UART_LIN_Break_Detection UART LIN Break Detection - * @{ - */ -#define UART_LINBREAKDETECTLENGTH_10B 0x00000000U /*!< LIN 10-bit break detection length */ -#define UART_LINBREAKDETECTLENGTH_11B USART_CR2_LBDL /*!< LIN 11-bit break detection length */ -/** - * @} - */ - -/** @defgroup UART_DMA_Tx UART DMA Tx - * @{ - */ -#define UART_DMA_TX_DISABLE 0x00000000U /*!< UART DMA TX disabled */ -#define UART_DMA_TX_ENABLE USART_CR3_DMAT /*!< UART DMA TX enabled */ -/** - * @} - */ - -/** @defgroup UART_DMA_Rx UART DMA Rx - * @{ - */ -#define UART_DMA_RX_DISABLE 0x00000000U /*!< UART DMA RX disabled */ -#define UART_DMA_RX_ENABLE USART_CR3_DMAR /*!< UART DMA RX enabled */ -/** - * @} - */ - -/** @defgroup UART_Half_Duplex_Selection UART Half Duplex Selection - * @{ - */ -#define UART_HALF_DUPLEX_DISABLE 0x00000000U /*!< UART half-duplex disabled */ -#define UART_HALF_DUPLEX_ENABLE USART_CR3_HDSEL /*!< UART half-duplex enabled */ -/** - * @} - */ - -/** @defgroup UART_WakeUp_Methods UART WakeUp Methods - * @{ - */ -#define UART_WAKEUPMETHOD_IDLELINE 0x00000000U /*!< UART wake-up on idle line */ -#define UART_WAKEUPMETHOD_ADDRESSMARK USART_CR1_WAKE /*!< UART wake-up on address mark */ -/** - * @} - */ - -/** @defgroup UART_Request_Parameters UART Request Parameters - * @{ - */ -#define UART_AUTOBAUD_REQUEST USART_RQR_ABRRQ /*!< Auto-Baud Rate Request */ -#define UART_SENDBREAK_REQUEST USART_RQR_SBKRQ /*!< Send Break Request */ -#define UART_MUTE_MODE_REQUEST USART_RQR_MMRQ /*!< Mute Mode Request */ -#define UART_RXDATA_FLUSH_REQUEST USART_RQR_RXFRQ /*!< Receive Data flush Request */ -#define UART_TXDATA_FLUSH_REQUEST USART_RQR_TXFRQ /*!< Transmit data flush Request */ -/** - * @} - */ - -/** @defgroup UART_Advanced_Features_Initialization_Type UART Advanced Feature Initialization Type - * @{ - */ -#define UART_ADVFEATURE_NO_INIT 0x00000000U /*!< No advanced feature initialization */ -#define UART_ADVFEATURE_TXINVERT_INIT 0x00000001U /*!< TX pin active level inversion */ -#define UART_ADVFEATURE_RXINVERT_INIT 0x00000002U /*!< RX pin active level inversion */ -#define UART_ADVFEATURE_DATAINVERT_INIT 0x00000004U /*!< Binary data inversion */ -#define UART_ADVFEATURE_SWAP_INIT 0x00000008U /*!< TX/RX pins swap */ -#define UART_ADVFEATURE_RXOVERRUNDISABLE_INIT 0x00000010U /*!< RX overrun disable */ -#define UART_ADVFEATURE_DMADISABLEONERROR_INIT 0x00000020U /*!< DMA disable on Reception Error */ -#define UART_ADVFEATURE_AUTOBAUDRATE_INIT 0x00000040U /*!< Auto Baud rate detection initialization */ -#define UART_ADVFEATURE_MSBFIRST_INIT 0x00000080U /*!< Most significant bit sent/received first */ -/** - * @} - */ - -/** @defgroup UART_Tx_Inv UART Advanced Feature TX Pin Active Level Inversion - * @{ - */ -#define UART_ADVFEATURE_TXINV_DISABLE 0x00000000U /*!< TX pin active level inversion disable */ -#define UART_ADVFEATURE_TXINV_ENABLE USART_CR2_TXINV /*!< TX pin active level inversion enable */ -/** - * @} - */ - -/** @defgroup UART_Rx_Inv UART Advanced Feature RX Pin Active Level Inversion - * @{ - */ -#define UART_ADVFEATURE_RXINV_DISABLE 0x00000000U /*!< RX pin active level inversion disable */ -#define UART_ADVFEATURE_RXINV_ENABLE USART_CR2_RXINV /*!< RX pin active level inversion enable */ -/** - * @} - */ - -/** @defgroup UART_Data_Inv UART Advanced Feature Binary Data Inversion - * @{ - */ -#define UART_ADVFEATURE_DATAINV_DISABLE 0x00000000U /*!< Binary data inversion disable */ -#define UART_ADVFEATURE_DATAINV_ENABLE USART_CR2_DATAINV /*!< Binary data inversion enable */ -/** - * @} - */ - -/** @defgroup UART_Rx_Tx_Swap UART Advanced Feature RX TX Pins Swap - * @{ - */ -#define UART_ADVFEATURE_SWAP_DISABLE 0x00000000U /*!< TX/RX pins swap disable */ -#define UART_ADVFEATURE_SWAP_ENABLE USART_CR2_SWAP /*!< TX/RX pins swap enable */ -/** - * @} - */ - -/** @defgroup UART_Overrun_Disable UART Advanced Feature Overrun Disable - * @{ - */ -#define UART_ADVFEATURE_OVERRUN_ENABLE 0x00000000U /*!< RX overrun enable */ -#define UART_ADVFEATURE_OVERRUN_DISABLE USART_CR3_OVRDIS /*!< RX overrun disable */ -/** - * @} - */ - -/** @defgroup UART_AutoBaudRate_Enable UART Advanced Feature Auto BaudRate Enable - * @{ - */ -#define UART_ADVFEATURE_AUTOBAUDRATE_DISABLE 0x00000000U /*!< RX Auto Baud rate detection enable */ -#define UART_ADVFEATURE_AUTOBAUDRATE_ENABLE USART_CR2_ABREN /*!< RX Auto Baud rate detection disable */ -/** - * @} - */ - -/** @defgroup UART_DMA_Disable_on_Rx_Error UART Advanced Feature DMA Disable On Rx Error - * @{ - */ -#define UART_ADVFEATURE_DMA_ENABLEONRXERROR 0x00000000U /*!< DMA enable on Reception Error */ -#define UART_ADVFEATURE_DMA_DISABLEONRXERROR USART_CR3_DDRE /*!< DMA disable on Reception Error */ -/** - * @} - */ - -/** @defgroup UART_MSB_First UART Advanced Feature MSB First - * @{ - */ -#define UART_ADVFEATURE_MSBFIRST_DISABLE 0x00000000U /*!< Most significant bit sent/received - first disable */ -#define UART_ADVFEATURE_MSBFIRST_ENABLE USART_CR2_MSBFIRST /*!< Most significant bit sent/received - first enable */ -/** - * @} - */ - -/** @defgroup UART_Stop_Mode_Enable UART Advanced Feature Stop Mode Enable - * @{ - */ -#define UART_ADVFEATURE_STOPMODE_DISABLE 0x00000000U /*!< UART stop mode disable */ -#define UART_ADVFEATURE_STOPMODE_ENABLE USART_CR1_UESM /*!< UART stop mode enable */ -/** - * @} - */ - -/** @defgroup UART_Mute_Mode UART Advanced Feature Mute Mode Enable - * @{ - */ -#define UART_ADVFEATURE_MUTEMODE_DISABLE 0x00000000U /*!< UART mute mode disable */ -#define UART_ADVFEATURE_MUTEMODE_ENABLE USART_CR1_MME /*!< UART mute mode enable */ -/** - * @} - */ - -/** @defgroup UART_CR2_ADDRESS_LSB_POS UART Address-matching LSB Position In CR2 Register - * @{ - */ -#define UART_CR2_ADDRESS_LSB_POS 24U /*!< UART address-matching LSB position in CR2 register */ -/** - * @} - */ - -/** @defgroup UART_WakeUp_from_Stop_Selection UART WakeUp From Stop Selection - * @{ - */ -#define UART_WAKEUP_ON_ADDRESS 0x00000000U /*!< UART wake-up on address */ -#define UART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1 /*!< UART wake-up on start bit */ -#define UART_WAKEUP_ON_READDATA_NONEMPTY USART_CR3_WUS /*!< UART wake-up on receive data register - not empty or RXFIFO is not empty */ -/** - * @} - */ - -/** @defgroup UART_DriverEnable_Polarity UART DriverEnable Polarity - * @{ - */ -#define UART_DE_POLARITY_HIGH 0x00000000U /*!< Driver enable signal is active high */ -#define UART_DE_POLARITY_LOW USART_CR3_DEP /*!< Driver enable signal is active low */ -/** - * @} - */ - -/** @defgroup UART_CR1_DEAT_ADDRESS_LSB_POS UART Driver Enable Assertion Time LSB Position In CR1 Register - * @{ - */ -#define UART_CR1_DEAT_ADDRESS_LSB_POS 21U /*!< UART Driver Enable assertion time LSB - position in CR1 register */ -/** - * @} - */ - -/** @defgroup UART_CR1_DEDT_ADDRESS_LSB_POS UART Driver Enable DeAssertion Time LSB Position In CR1 Register - * @{ - */ -#define UART_CR1_DEDT_ADDRESS_LSB_POS 16U /*!< UART Driver Enable de-assertion time LSB - position in CR1 register */ -/** - * @} - */ - -/** @defgroup UART_Interruption_Mask UART Interruptions Flag Mask - * @{ - */ -#define UART_IT_MASK 0x001FU /*!< UART interruptions flags mask */ -/** - * @} - */ - -/** @defgroup UART_TimeOut_Value UART polling-based communications time-out value - * @{ - */ -#define HAL_UART_TIMEOUT_VALUE 0x1FFFFFFU /*!< UART polling-based communications time-out value */ -/** - * @} - */ - -/** @defgroup UART_Flags UART Status Flags - * Elements values convention: 0xXXXX - * - 0xXXXX : Flag mask in the ISR register - * @{ - */ -#define UART_FLAG_REACK USART_ISR_REACK /*!< UART receive enable acknowledge flag */ -#define UART_FLAG_TEACK USART_ISR_TEACK /*!< UART transmit enable acknowledge flag */ -#define UART_FLAG_WUF USART_ISR_WUF /*!< UART wake-up from stop mode flag */ -#define UART_FLAG_RWU USART_ISR_RWU /*!< UART receiver wake-up from mute mode flag */ -#define UART_FLAG_SBKF USART_ISR_SBKF /*!< UART send break flag */ -#define UART_FLAG_CMF USART_ISR_CMF /*!< UART character match flag */ -#define UART_FLAG_BUSY USART_ISR_BUSY /*!< UART busy flag */ -#define UART_FLAG_ABRF USART_ISR_ABRF /*!< UART auto Baud rate flag */ -#define UART_FLAG_ABRE USART_ISR_ABRE /*!< UART auto Baud rate error */ -#define UART_FLAG_RTOF USART_ISR_RTOF /*!< UART receiver timeout flag */ -#define UART_FLAG_CTS USART_ISR_CTS /*!< UART clear to send flag */ -#define UART_FLAG_CTSIF USART_ISR_CTSIF /*!< UART clear to send interrupt flag */ -#define UART_FLAG_LBDF USART_ISR_LBDF /*!< UART LIN break detection flag */ -#define UART_FLAG_TXE USART_ISR_TXE /*!< UART transmit data register empty */ -#define UART_FLAG_TC USART_ISR_TC /*!< UART transmission complete */ -#define UART_FLAG_RXNE USART_ISR_RXNE /*!< UART read data register not empty */ -#define UART_FLAG_IDLE USART_ISR_IDLE /*!< UART idle flag */ -#define UART_FLAG_ORE USART_ISR_ORE /*!< UART overrun error */ -#define UART_FLAG_NE USART_ISR_NE /*!< UART noise error */ -#define UART_FLAG_FE USART_ISR_FE /*!< UART frame error */ -#define UART_FLAG_PE USART_ISR_PE /*!< UART parity error */ -/** - * @} - */ - -/** @defgroup UART_Interrupt_definition UART Interrupts Definition - * Elements values convention: 000ZZZZZ0XXYYYYYb - * - YYYYY : Interrupt source position in the XX register (5bits) - * - XX : Interrupt source register (2bits) - * - 01: CR1 register - * - 10: CR2 register - * - 11: CR3 register - * - ZZZZZ : Flag position in the ISR register(5bits) - * Elements values convention: 000000000XXYYYYYb - * - YYYYY : Interrupt source position in the XX register (5bits) - * - XX : Interrupt source register (2bits) - * - 01: CR1 register - * - 10: CR2 register - * - 11: CR3 register - * Elements values convention: 0000ZZZZ00000000b - * - ZZZZ : Flag position in the ISR register(4bits) - * @{ - */ -#define UART_IT_PE 0x0028U /*!< UART parity error interruption */ -#define UART_IT_TXE 0x0727U /*!< UART transmit data register empty interruption */ -#define UART_IT_TC 0x0626U /*!< UART transmission complete interruption */ -#define UART_IT_RXNE 0x0525U /*!< UART read data register not empty interruption */ -#define UART_IT_IDLE 0x0424U /*!< UART idle interruption */ -#define UART_IT_LBD 0x0846U /*!< UART LIN break detection interruption */ -#define UART_IT_CTS 0x096AU /*!< UART CTS interruption */ -#define UART_IT_CM 0x112EU /*!< UART character match interruption */ -#define UART_IT_WUF 0x1476U /*!< UART wake-up from stop mode interruption */ -#define UART_IT_RTO 0x0B3AU /*!< UART receiver timeout interruption */ - -#define UART_IT_ERR 0x0060U /*!< UART error interruption */ - -#define UART_IT_ORE 0x0300U /*!< UART overrun error interruption */ -#define UART_IT_NE 0x0200U /*!< UART noise error interruption */ -#define UART_IT_FE 0x0100U /*!< UART frame error interruption */ -/** - * @} - */ - -/** @defgroup UART_IT_CLEAR_Flags UART Interruption Clear Flags - * @{ - */ -#define UART_CLEAR_PEF USART_ICR_PECF /*!< Parity Error Clear Flag */ -#define UART_CLEAR_FEF USART_ICR_FECF /*!< Framing Error Clear Flag */ -#define UART_CLEAR_NEF USART_ICR_NCF /*!< Noise Error detected Clear Flag */ -#define UART_CLEAR_OREF USART_ICR_ORECF /*!< Overrun Error Clear Flag */ -#define UART_CLEAR_IDLEF USART_ICR_IDLECF /*!< IDLE line detected Clear Flag */ -#define UART_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */ -#define UART_CLEAR_LBDF USART_ICR_LBDCF /*!< LIN Break Detection Clear Flag */ -#define UART_CLEAR_CTSF USART_ICR_CTSCF /*!< CTS Interrupt Clear Flag */ -#define UART_CLEAR_CMF USART_ICR_CMCF /*!< Character Match Clear Flag */ -#define UART_CLEAR_WUF USART_ICR_WUCF /*!< Wake Up from stop mode Clear Flag */ -#define UART_CLEAR_RTOF USART_ICR_RTOCF /*!< UART receiver timeout clear flag */ -/** - * @} - */ - -/** @defgroup UART_RECEPTION_TYPE_Values UART Reception type values - * @{ - */ -#define HAL_UART_RECEPTION_STANDARD (0x00000000U) /*!< Standard reception */ -#define HAL_UART_RECEPTION_TOIDLE (0x00000001U) /*!< Reception till completion or IDLE event */ -#define HAL_UART_RECEPTION_TORTO (0x00000002U) /*!< Reception till completion or RTO event */ -#define HAL_UART_RECEPTION_TOCHARMATCH (0x00000003U) /*!< Reception till completion or CM event */ -/** - * @} - */ - -/** - * @} - */ - -/* Exported macros -----------------------------------------------------------*/ -/** @defgroup UART_Exported_Macros UART Exported Macros - * @{ - */ - -/** @brief Reset UART handle states. - * @param __HANDLE__ UART handle. - * @retval None - */ -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) -#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) do{ \ - (__HANDLE__)->gState = HAL_UART_STATE_RESET; \ - (__HANDLE__)->RxState = HAL_UART_STATE_RESET; \ - (__HANDLE__)->MspInitCallback = NULL; \ - (__HANDLE__)->MspDeInitCallback = NULL; \ - } while(0U) -#else -#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) do{ \ - (__HANDLE__)->gState = HAL_UART_STATE_RESET; \ - (__HANDLE__)->RxState = HAL_UART_STATE_RESET; \ - } while(0U) -#endif /*USE_HAL_UART_REGISTER_CALLBACKS */ - -/** @brief Flush the UART Data registers. - * @param __HANDLE__ specifies the UART Handle. - * @retval None - */ -#define __HAL_UART_FLUSH_DRREGISTER(__HANDLE__) \ - do{ \ - SET_BIT((__HANDLE__)->Instance->RQR, UART_RXDATA_FLUSH_REQUEST); \ - SET_BIT((__HANDLE__)->Instance->RQR, UART_TXDATA_FLUSH_REQUEST); \ - } while(0U) - -/** @brief Clear the specified UART pending flag. - * @param __HANDLE__ specifies the UART Handle. - * @param __FLAG__ specifies the flag to check. - * This parameter can be any combination of the following values: - * @arg @ref UART_CLEAR_PEF Parity Error Clear Flag - * @arg @ref UART_CLEAR_FEF Framing Error Clear Flag - * @arg @ref UART_CLEAR_NEF Noise detected Clear Flag - * @arg @ref UART_CLEAR_OREF Overrun Error Clear Flag - * @arg @ref UART_CLEAR_IDLEF IDLE line detected Clear Flag - * @arg @ref UART_CLEAR_TCF Transmission Complete Clear Flag - * @arg @ref UART_CLEAR_RTOF Receiver Timeout clear flag - * @arg @ref UART_CLEAR_LBDF LIN Break Detection Clear Flag - * @arg @ref UART_CLEAR_CTSF CTS Interrupt Clear Flag - * @arg @ref UART_CLEAR_CMF Character Match Clear Flag - * @arg @ref UART_CLEAR_WUF Wake Up from stop mode Clear Flag - * @retval None - */ -#define __HAL_UART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) - -/** @brief Clear the UART PE pending flag. - * @param __HANDLE__ specifies the UART Handle. - * @retval None - */ -#define __HAL_UART_CLEAR_PEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_PEF) - -/** @brief Clear the UART FE pending flag. - * @param __HANDLE__ specifies the UART Handle. - * @retval None - */ -#define __HAL_UART_CLEAR_FEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_FEF) - -/** @brief Clear the UART NE pending flag. - * @param __HANDLE__ specifies the UART Handle. - * @retval None - */ -#define __HAL_UART_CLEAR_NEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_NEF) - -/** @brief Clear the UART ORE pending flag. - * @param __HANDLE__ specifies the UART Handle. - * @retval None - */ -#define __HAL_UART_CLEAR_OREFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_OREF) - -/** @brief Clear the UART IDLE pending flag. - * @param __HANDLE__ specifies the UART Handle. - * @retval None - */ -#define __HAL_UART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_IDLEF) - - -/** @brief Check whether the specified UART flag is set or not. - * @param __HANDLE__ specifies the UART Handle. - * @param __FLAG__ specifies the flag to check. - * This parameter can be one of the following values: - * @arg @ref UART_FLAG_REACK Receive enable acknowledge flag - * @arg @ref UART_FLAG_TEACK Transmit enable acknowledge flag - * @arg @ref UART_FLAG_WUF Wake up from stop mode flag - * @arg @ref UART_FLAG_RWU Receiver wake up flag (if the UART in mute mode) - * @arg @ref UART_FLAG_SBKF Send Break flag - * @arg @ref UART_FLAG_CMF Character match flag - * @arg @ref UART_FLAG_BUSY Busy flag - * @arg @ref UART_FLAG_ABRF Auto Baud rate detection flag - * @arg @ref UART_FLAG_ABRE Auto Baud rate detection error flag - * @arg @ref UART_FLAG_CTS CTS Change flag - * @arg @ref UART_FLAG_LBDF LIN Break detection flag - * @arg @ref UART_FLAG_TXE Transmit data register empty flag - * @arg @ref UART_FLAG_TC Transmission Complete flag - * @arg @ref UART_FLAG_RXNE Receive data register not empty flag - * @arg @ref UART_FLAG_RTOF Receiver Timeout flag - * @arg @ref UART_FLAG_IDLE Idle Line detection flag - * @arg @ref UART_FLAG_ORE Overrun Error flag - * @arg @ref UART_FLAG_NE Noise Error flag - * @arg @ref UART_FLAG_FE Framing Error flag - * @arg @ref UART_FLAG_PE Parity Error flag - * @retval The new state of __FLAG__ (TRUE or FALSE). - */ -#define __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__)) - -/** @brief Enable the specified UART interrupt. - * @param __HANDLE__ specifies the UART Handle. - * @param __INTERRUPT__ specifies the UART interrupt source to enable. - * This parameter can be one of the following values: - * @arg @ref UART_IT_WUF Wakeup from stop mode interrupt - * @arg @ref UART_IT_CM Character match interrupt - * @arg @ref UART_IT_CTS CTS change interrupt - * @arg @ref UART_IT_LBD LIN Break detection interrupt - * @arg @ref UART_IT_TXE Transmit Data Register empty interrupt - * @arg @ref UART_IT_TC Transmission complete interrupt - * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt - * @arg @ref UART_IT_RTO Receive Timeout interrupt - * @arg @ref UART_IT_IDLE Idle line detection interrupt - * @arg @ref UART_IT_PE Parity Error interrupt - * @arg @ref UART_IT_ERR Error interrupt (frame error, noise error, overrun error) - * @retval None - */ -#define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__) (\ - ((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)?\ - ((__HANDLE__)->Instance->CR1 |= (1U <<\ - ((__INTERRUPT__) & UART_IT_MASK))): \ - ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)?\ - ((__HANDLE__)->Instance->CR2 |= (1U <<\ - ((__INTERRUPT__) & UART_IT_MASK))): \ - ((__HANDLE__)->Instance->CR3 |= (1U <<\ - ((__INTERRUPT__) & UART_IT_MASK)))) - -/** @brief Disable the specified UART interrupt. - * @param __HANDLE__ specifies the UART Handle. - * @param __INTERRUPT__ specifies the UART interrupt source to disable. - * This parameter can be one of the following values: - * @arg @ref UART_IT_WUF Wakeup from stop mode interrupt - * @arg @ref UART_IT_CM Character match interrupt - * @arg @ref UART_IT_CTS CTS change interrupt - * @arg @ref UART_IT_LBD LIN Break detection interrupt - * @arg @ref UART_IT_TXE Transmit Data Register empty interrupt - * @arg @ref UART_IT_TC Transmission complete interrupt - * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt - * @arg @ref UART_IT_RTO Receive Timeout interrupt - * @arg @ref UART_IT_IDLE Idle line detection interrupt - * @arg @ref UART_IT_PE Parity Error interrupt - * @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error) - * @retval None - */ -#define __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__) (\ - ((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)?\ - ((__HANDLE__)->Instance->CR1 &= ~ (1U <<\ - ((__INTERRUPT__) & UART_IT_MASK))): \ - ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)?\ - ((__HANDLE__)->Instance->CR2 &= ~ (1U <<\ - ((__INTERRUPT__) & UART_IT_MASK))): \ - ((__HANDLE__)->Instance->CR3 &= ~ (1U <<\ - ((__INTERRUPT__) & UART_IT_MASK)))) - -/** @brief Check whether the specified UART interrupt has occurred or not. - * @param __HANDLE__ specifies the UART Handle. - * @param __INTERRUPT__ specifies the UART interrupt to check. - * This parameter can be one of the following values: - * @arg @ref UART_IT_WUF Wakeup from stop mode interrupt - * @arg @ref UART_IT_CM Character match interrupt - * @arg @ref UART_IT_CTS CTS change interrupt - * @arg @ref UART_IT_LBD LIN Break detection interrupt - * @arg @ref UART_IT_TXE Transmit Data Register empty interrupt - * @arg @ref UART_IT_TC Transmission complete interrupt - * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt - * @arg @ref UART_IT_RTO Receive Timeout interrupt - * @arg @ref UART_IT_IDLE Idle line detection interrupt - * @arg @ref UART_IT_PE Parity Error interrupt - * @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error) - * @retval The new state of __INTERRUPT__ (SET or RESET). - */ -#define __HAL_UART_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR\ - & (1U << ((__INTERRUPT__)>> 8U))) != RESET) ? SET : RESET) - -/** @brief Check whether the specified UART interrupt source is enabled or not. - * @param __HANDLE__ specifies the UART Handle. - * @param __INTERRUPT__ specifies the UART interrupt source to check. - * This parameter can be one of the following values: - * @arg @ref UART_IT_WUF Wakeup from stop mode interrupt - * @arg @ref UART_IT_CM Character match interrupt - * @arg @ref UART_IT_CTS CTS change interrupt - * @arg @ref UART_IT_LBD LIN Break detection interrupt - * @arg @ref UART_IT_TXE Transmit Data Register empty interrupt - * @arg @ref UART_IT_TC Transmission complete interrupt - * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt - * @arg @ref UART_IT_RTO Receive Timeout interrupt - * @arg @ref UART_IT_IDLE Idle line detection interrupt - * @arg @ref UART_IT_PE Parity Error interrupt - * @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error) - * @retval The new state of __INTERRUPT__ (SET or RESET). - */ -#define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U) ?\ - (__HANDLE__)->Instance->CR1 : \ - (((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U) ?\ - (__HANDLE__)->Instance->CR2 : \ - (__HANDLE__)->Instance->CR3)) & (1U <<\ - (((uint16_t)(__INTERRUPT__)) &\ - UART_IT_MASK))) != RESET) ? SET : RESET) - -/** @brief Clear the specified UART ISR flag, in setting the proper ICR register flag. - * @param __HANDLE__ specifies the UART Handle. - * @param __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set - * to clear the corresponding interrupt - * This parameter can be one of the following values: - * @arg @ref UART_CLEAR_PEF Parity Error Clear Flag - * @arg @ref UART_CLEAR_FEF Framing Error Clear Flag - * @arg @ref UART_CLEAR_NEF Noise detected Clear Flag - * @arg @ref UART_CLEAR_OREF Overrun Error Clear Flag - * @arg @ref UART_CLEAR_IDLEF IDLE line detected Clear Flag - * @arg @ref UART_CLEAR_RTOF Receiver timeout clear flag - * @arg @ref UART_CLEAR_TCF Transmission Complete Clear Flag - * @arg @ref UART_CLEAR_LBDF LIN Break Detection Clear Flag - * @arg @ref UART_CLEAR_CTSF CTS Interrupt Clear Flag - * @arg @ref UART_CLEAR_CMF Character Match Clear Flag - * @arg @ref UART_CLEAR_WUF Wake Up from stop mode Clear Flag - * @retval None - */ -#define __HAL_UART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__)) - -/** @brief Set a specific UART request flag. - * @param __HANDLE__ specifies the UART Handle. - * @param __REQ__ specifies the request flag to set - * This parameter can be one of the following values: - * @arg @ref UART_AUTOBAUD_REQUEST Auto-Baud Rate Request - * @arg @ref UART_SENDBREAK_REQUEST Send Break Request - * @arg @ref UART_MUTE_MODE_REQUEST Mute Mode Request - * @arg @ref UART_RXDATA_FLUSH_REQUEST Receive Data flush Request - * @arg @ref UART_TXDATA_FLUSH_REQUEST Transmit data flush Request - * @retval None - */ -#define __HAL_UART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__)) - -/** @brief Enable the UART one bit sample method. - * @param __HANDLE__ specifies the UART Handle. - * @retval None - */ -#define __HAL_UART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT) - -/** @brief Disable the UART one bit sample method. - * @param __HANDLE__ specifies the UART Handle. - * @retval None - */ -#define __HAL_UART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= ~USART_CR3_ONEBIT) - -/** @brief Enable UART. - * @param __HANDLE__ specifies the UART Handle. - * @retval None - */ -#define __HAL_UART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE) - -/** @brief Disable UART. - * @param __HANDLE__ specifies the UART Handle. - * @retval None - */ -#define __HAL_UART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE) - -/** @brief Enable CTS flow control. - * @note This macro allows to enable CTS hardware flow control for a given UART instance, - * without need to call HAL_UART_Init() function. - * As involving direct access to UART registers, usage of this macro should be fully endorsed by user. - * @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need - * for USART instance Deinit/Init, following conditions for macro call should be fulfilled : - * - UART instance should have already been initialised (through call of HAL_UART_Init() ) - * - macro could only be called when corresponding UART instance is disabled - * (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable - * macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). - * @param __HANDLE__ specifies the UART Handle. - * @retval None - */ -#define __HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__) \ - do{ \ - SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \ - (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_CTSE; \ - } while(0U) - -/** @brief Disable CTS flow control. - * @note This macro allows to disable CTS hardware flow control for a given UART instance, - * without need to call HAL_UART_Init() function. - * As involving direct access to UART registers, usage of this macro should be fully endorsed by user. - * @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need - * for USART instance Deinit/Init, following conditions for macro call should be fulfilled : - * - UART instance should have already been initialised (through call of HAL_UART_Init() ) - * - macro could only be called when corresponding UART instance is disabled - * (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable - * macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). - * @param __HANDLE__ specifies the UART Handle. - * @retval None - */ -#define __HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__) \ - do{ \ - CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \ - (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_CTSE); \ - } while(0U) - -/** @brief Enable RTS flow control. - * @note This macro allows to enable RTS hardware flow control for a given UART instance, - * without need to call HAL_UART_Init() function. - * As involving direct access to UART registers, usage of this macro should be fully endorsed by user. - * @note As macro is expected to be used for modifying RTS Hw flow control feature activation, without need - * for USART instance Deinit/Init, following conditions for macro call should be fulfilled : - * - UART instance should have already been initialised (through call of HAL_UART_Init() ) - * - macro could only be called when corresponding UART instance is disabled - * (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable - * macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). - * @param __HANDLE__ specifies the UART Handle. - * @retval None - */ -#define __HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__) \ - do{ \ - SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); \ - (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_RTSE; \ - } while(0U) - -/** @brief Disable RTS flow control. - * @note This macro allows to disable RTS hardware flow control for a given UART instance, - * without need to call HAL_UART_Init() function. - * As involving direct access to UART registers, usage of this macro should be fully endorsed by user. - * @note As macro is expected to be used for modifying RTS Hw flow control feature activation, without need - * for USART instance Deinit/Init, following conditions for macro call should be fulfilled : - * - UART instance should have already been initialised (through call of HAL_UART_Init() ) - * - macro could only be called when corresponding UART instance is disabled - * (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable - * macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). - * @param __HANDLE__ specifies the UART Handle. - * @retval None - */ -#define __HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__) \ - do{ \ - CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE);\ - (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_RTSE); \ - } while(0U) -/** - * @} - */ - -/* Private macros --------------------------------------------------------*/ -/** @defgroup UART_Private_Macros UART Private Macros - * @{ - */ - -/** @brief BRR division operation to set BRR register with LPUART. - * @param __PCLK__ LPUART clock. - * @param __BAUD__ Baud rate set by the user. - * @retval Division result - */ -#define UART_DIV_LPUART(__PCLK__, __BAUD__) (((((uint64_t)(__PCLK__)*256U)) + ((__BAUD__)/2U)) / (__BAUD__)) - -/** @brief BRR division operation to set BRR register in 8-bit oversampling mode. - * @param __PCLK__ UART clock. - * @param __BAUD__ Baud rate set by the user. - * @retval Division result - */ -#define UART_DIV_SAMPLING8(__PCLK__, __BAUD__) ((((__PCLK__)*2U) + ((__BAUD__)/2U)) / (__BAUD__)) - -/** @brief BRR division operation to set BRR register in 16-bit oversampling mode. - * @param __PCLK__ UART clock. - * @param __BAUD__ Baud rate set by the user. - * @retval Division result - */ -#define UART_DIV_SAMPLING16(__PCLK__, __BAUD__) (((__PCLK__) + ((__BAUD__)/2U)) / (__BAUD__)) - -/** @brief Check whether or not UART instance is Low Power UART. - * @param __HANDLE__ specifies the UART Handle. - * @retval SET (instance is LPUART) or RESET (instance isn't LPUART) - */ -#define UART_INSTANCE_LOWPOWER(__HANDLE__) (IS_LPUART_INSTANCE((__HANDLE__)->Instance)) - -/** @brief Check UART Baud rate. - * @param __BAUDRATE__ Baudrate specified by the user. - * The maximum Baud Rate is derived from the maximum clock on L0 (i.e. 32 MHz) - * divided by the smallest oversampling used on the USART (i.e. 8) - * @retval SET (__BAUDRATE__ is valid) or RESET (__BAUDRATE__ is invalid) - */ -#define IS_UART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 4000001U) - -/** @brief Check UART assertion time. - * @param __TIME__ 5-bit value assertion time. - * @retval Test result (TRUE or FALSE). - */ -#define IS_UART_ASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1FU) - -/** @brief Check UART deassertion time. - * @param __TIME__ 5-bit value deassertion time. - * @retval Test result (TRUE or FALSE). - */ -#define IS_UART_DEASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1FU) - -/** - * @brief Ensure that UART frame number of stop bits is valid. - * @param __STOPBITS__ UART frame number of stop bits. - * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid) - */ -#define IS_UART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == UART_STOPBITS_0_5) || \ - ((__STOPBITS__) == UART_STOPBITS_1) || \ - ((__STOPBITS__) == UART_STOPBITS_1_5) || \ - ((__STOPBITS__) == UART_STOPBITS_2)) - -/** - * @brief Ensure that LPUART frame number of stop bits is valid. - * @param __STOPBITS__ LPUART frame number of stop bits. - * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid) - */ -#define IS_LPUART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == UART_STOPBITS_1) || \ - ((__STOPBITS__) == UART_STOPBITS_2)) - -/** - * @brief Ensure that UART frame parity is valid. - * @param __PARITY__ UART frame parity. - * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid) - */ -#define IS_UART_PARITY(__PARITY__) (((__PARITY__) == UART_PARITY_NONE) || \ - ((__PARITY__) == UART_PARITY_EVEN) || \ - ((__PARITY__) == UART_PARITY_ODD)) - -/** - * @brief Ensure that UART hardware flow control is valid. - * @param __CONTROL__ UART hardware flow control. - * @retval SET (__CONTROL__ is valid) or RESET (__CONTROL__ is invalid) - */ -#define IS_UART_HARDWARE_FLOW_CONTROL(__CONTROL__)\ - (((__CONTROL__) == UART_HWCONTROL_NONE) || \ - ((__CONTROL__) == UART_HWCONTROL_RTS) || \ - ((__CONTROL__) == UART_HWCONTROL_CTS) || \ - ((__CONTROL__) == UART_HWCONTROL_RTS_CTS)) - -/** - * @brief Ensure that UART communication mode is valid. - * @param __MODE__ UART communication mode. - * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) - */ -#define IS_UART_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(UART_MODE_TX_RX)))) == 0x00U) && ((__MODE__) != 0x00U)) - -/** - * @brief Ensure that UART state is valid. - * @param __STATE__ UART state. - * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid) - */ -#define IS_UART_STATE(__STATE__) (((__STATE__) == UART_STATE_DISABLE) || \ - ((__STATE__) == UART_STATE_ENABLE)) - -/** - * @brief Ensure that UART oversampling is valid. - * @param __SAMPLING__ UART oversampling. - * @retval SET (__SAMPLING__ is valid) or RESET (__SAMPLING__ is invalid) - */ -#define IS_UART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == UART_OVERSAMPLING_16) || \ - ((__SAMPLING__) == UART_OVERSAMPLING_8)) - -/** - * @brief Ensure that UART frame sampling is valid. - * @param __ONEBIT__ UART frame sampling. - * @retval SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid) - */ -#define IS_UART_ONE_BIT_SAMPLE(__ONEBIT__) (((__ONEBIT__) == UART_ONE_BIT_SAMPLE_DISABLE) || \ - ((__ONEBIT__) == UART_ONE_BIT_SAMPLE_ENABLE)) - -/** - * @brief Ensure that UART auto Baud rate detection mode is valid. - * @param __MODE__ UART auto Baud rate detection mode. - * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) - */ -#define IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(__MODE__) (((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT) || \ - ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE) || \ - ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME) || \ - ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME)) - -/** - * @brief Ensure that UART receiver timeout setting is valid. - * @param __TIMEOUT__ UART receiver timeout setting. - * @retval SET (__TIMEOUT__ is valid) or RESET (__TIMEOUT__ is invalid) - */ -#define IS_UART_RECEIVER_TIMEOUT(__TIMEOUT__) (((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_DISABLE) || \ - ((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_ENABLE)) - -/** @brief Check the receiver timeout value. - * @note The maximum UART receiver timeout value is 0xFFFFFF. - * @param __TIMEOUTVALUE__ receiver timeout value. - * @retval Test result (TRUE or FALSE) - */ -#define IS_UART_RECEIVER_TIMEOUT_VALUE(__TIMEOUTVALUE__) ((__TIMEOUTVALUE__) <= 0xFFFFFFU) - -/** - * @brief Ensure that UART LIN state is valid. - * @param __LIN__ UART LIN state. - * @retval SET (__LIN__ is valid) or RESET (__LIN__ is invalid) - */ -#define IS_UART_LIN(__LIN__) (((__LIN__) == UART_LIN_DISABLE) || \ - ((__LIN__) == UART_LIN_ENABLE)) - -/** - * @brief Ensure that UART LIN break detection length is valid. - * @param __LENGTH__ UART LIN break detection length. - * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid) - */ -#define IS_UART_LIN_BREAK_DETECT_LENGTH(__LENGTH__) (((__LENGTH__) == UART_LINBREAKDETECTLENGTH_10B) || \ - ((__LENGTH__) == UART_LINBREAKDETECTLENGTH_11B)) - -/** - * @brief Ensure that UART DMA TX state is valid. - * @param __DMATX__ UART DMA TX state. - * @retval SET (__DMATX__ is valid) or RESET (__DMATX__ is invalid) - */ -#define IS_UART_DMA_TX(__DMATX__) (((__DMATX__) == UART_DMA_TX_DISABLE) || \ - ((__DMATX__) == UART_DMA_TX_ENABLE)) - -/** - * @brief Ensure that UART DMA RX state is valid. - * @param __DMARX__ UART DMA RX state. - * @retval SET (__DMARX__ is valid) or RESET (__DMARX__ is invalid) - */ -#define IS_UART_DMA_RX(__DMARX__) (((__DMARX__) == UART_DMA_RX_DISABLE) || \ - ((__DMARX__) == UART_DMA_RX_ENABLE)) - -/** - * @brief Ensure that UART half-duplex state is valid. - * @param __HDSEL__ UART half-duplex state. - * @retval SET (__HDSEL__ is valid) or RESET (__HDSEL__ is invalid) - */ -#define IS_UART_HALF_DUPLEX(__HDSEL__) (((__HDSEL__) == UART_HALF_DUPLEX_DISABLE) || \ - ((__HDSEL__) == UART_HALF_DUPLEX_ENABLE)) - -/** - * @brief Ensure that UART wake-up method is valid. - * @param __WAKEUP__ UART wake-up method . - * @retval SET (__WAKEUP__ is valid) or RESET (__WAKEUP__ is invalid) - */ -#define IS_UART_WAKEUPMETHOD(__WAKEUP__) (((__WAKEUP__) == UART_WAKEUPMETHOD_IDLELINE) || \ - ((__WAKEUP__) == UART_WAKEUPMETHOD_ADDRESSMARK)) - -/** - * @brief Ensure that UART request parameter is valid. - * @param __PARAM__ UART request parameter. - * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid) - */ -#define IS_UART_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == UART_AUTOBAUD_REQUEST) || \ - ((__PARAM__) == UART_SENDBREAK_REQUEST) || \ - ((__PARAM__) == UART_MUTE_MODE_REQUEST) || \ - ((__PARAM__) == UART_RXDATA_FLUSH_REQUEST) || \ - ((__PARAM__) == UART_TXDATA_FLUSH_REQUEST)) - -/** - * @brief Ensure that UART advanced features initialization is valid. - * @param __INIT__ UART advanced features initialization. - * @retval SET (__INIT__ is valid) or RESET (__INIT__ is invalid) - */ -#define IS_UART_ADVFEATURE_INIT(__INIT__) ((__INIT__) <= (UART_ADVFEATURE_NO_INIT | \ - UART_ADVFEATURE_TXINVERT_INIT | \ - UART_ADVFEATURE_RXINVERT_INIT | \ - UART_ADVFEATURE_DATAINVERT_INIT | \ - UART_ADVFEATURE_SWAP_INIT | \ - UART_ADVFEATURE_RXOVERRUNDISABLE_INIT | \ - UART_ADVFEATURE_DMADISABLEONERROR_INIT | \ - UART_ADVFEATURE_AUTOBAUDRATE_INIT | \ - UART_ADVFEATURE_MSBFIRST_INIT)) - -/** - * @brief Ensure that UART frame TX inversion setting is valid. - * @param __TXINV__ UART frame TX inversion setting. - * @retval SET (__TXINV__ is valid) or RESET (__TXINV__ is invalid) - */ -#define IS_UART_ADVFEATURE_TXINV(__TXINV__) (((__TXINV__) == UART_ADVFEATURE_TXINV_DISABLE) || \ - ((__TXINV__) == UART_ADVFEATURE_TXINV_ENABLE)) - -/** - * @brief Ensure that UART frame RX inversion setting is valid. - * @param __RXINV__ UART frame RX inversion setting. - * @retval SET (__RXINV__ is valid) or RESET (__RXINV__ is invalid) - */ -#define IS_UART_ADVFEATURE_RXINV(__RXINV__) (((__RXINV__) == UART_ADVFEATURE_RXINV_DISABLE) || \ - ((__RXINV__) == UART_ADVFEATURE_RXINV_ENABLE)) - -/** - * @brief Ensure that UART frame data inversion setting is valid. - * @param __DATAINV__ UART frame data inversion setting. - * @retval SET (__DATAINV__ is valid) or RESET (__DATAINV__ is invalid) - */ -#define IS_UART_ADVFEATURE_DATAINV(__DATAINV__) (((__DATAINV__) == UART_ADVFEATURE_DATAINV_DISABLE) || \ - ((__DATAINV__) == UART_ADVFEATURE_DATAINV_ENABLE)) - -/** - * @brief Ensure that UART frame RX/TX pins swap setting is valid. - * @param __SWAP__ UART frame RX/TX pins swap setting. - * @retval SET (__SWAP__ is valid) or RESET (__SWAP__ is invalid) - */ -#define IS_UART_ADVFEATURE_SWAP(__SWAP__) (((__SWAP__) == UART_ADVFEATURE_SWAP_DISABLE) || \ - ((__SWAP__) == UART_ADVFEATURE_SWAP_ENABLE)) - -/** - * @brief Ensure that UART frame overrun setting is valid. - * @param __OVERRUN__ UART frame overrun setting. - * @retval SET (__OVERRUN__ is valid) or RESET (__OVERRUN__ is invalid) - */ -#define IS_UART_OVERRUN(__OVERRUN__) (((__OVERRUN__) == UART_ADVFEATURE_OVERRUN_ENABLE) || \ - ((__OVERRUN__) == UART_ADVFEATURE_OVERRUN_DISABLE)) - -/** - * @brief Ensure that UART auto Baud rate state is valid. - * @param __AUTOBAUDRATE__ UART auto Baud rate state. - * @retval SET (__AUTOBAUDRATE__ is valid) or RESET (__AUTOBAUDRATE__ is invalid) - */ -#define IS_UART_ADVFEATURE_AUTOBAUDRATE(__AUTOBAUDRATE__) (((__AUTOBAUDRATE__) == \ - UART_ADVFEATURE_AUTOBAUDRATE_DISABLE) || \ - ((__AUTOBAUDRATE__) == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)) - -/** - * @brief Ensure that UART DMA enabling or disabling on error setting is valid. - * @param __DMA__ UART DMA enabling or disabling on error setting. - * @retval SET (__DMA__ is valid) or RESET (__DMA__ is invalid) - */ -#define IS_UART_ADVFEATURE_DMAONRXERROR(__DMA__) (((__DMA__) == UART_ADVFEATURE_DMA_ENABLEONRXERROR) || \ - ((__DMA__) == UART_ADVFEATURE_DMA_DISABLEONRXERROR)) - -/** - * @brief Ensure that UART frame MSB first setting is valid. - * @param __MSBFIRST__ UART frame MSB first setting. - * @retval SET (__MSBFIRST__ is valid) or RESET (__MSBFIRST__ is invalid) - */ -#define IS_UART_ADVFEATURE_MSBFIRST(__MSBFIRST__) (((__MSBFIRST__) == UART_ADVFEATURE_MSBFIRST_DISABLE) || \ - ((__MSBFIRST__) == UART_ADVFEATURE_MSBFIRST_ENABLE)) - -/** - * @brief Ensure that UART stop mode state is valid. - * @param __STOPMODE__ UART stop mode state. - * @retval SET (__STOPMODE__ is valid) or RESET (__STOPMODE__ is invalid) - */ -#define IS_UART_ADVFEATURE_STOPMODE(__STOPMODE__) (((__STOPMODE__) == UART_ADVFEATURE_STOPMODE_DISABLE) || \ - ((__STOPMODE__) == UART_ADVFEATURE_STOPMODE_ENABLE)) - -/** - * @brief Ensure that UART mute mode state is valid. - * @param __MUTE__ UART mute mode state. - * @retval SET (__MUTE__ is valid) or RESET (__MUTE__ is invalid) - */ -#define IS_UART_MUTE_MODE(__MUTE__) (((__MUTE__) == UART_ADVFEATURE_MUTEMODE_DISABLE) || \ - ((__MUTE__) == UART_ADVFEATURE_MUTEMODE_ENABLE)) - -/** - * @brief Ensure that UART wake-up selection is valid. - * @param __WAKE__ UART wake-up selection. - * @retval SET (__WAKE__ is valid) or RESET (__WAKE__ is invalid) - */ -#define IS_UART_WAKEUP_SELECTION(__WAKE__) (((__WAKE__) == UART_WAKEUP_ON_ADDRESS) || \ - ((__WAKE__) == UART_WAKEUP_ON_STARTBIT) || \ - ((__WAKE__) == UART_WAKEUP_ON_READDATA_NONEMPTY)) - -/** - * @brief Ensure that UART driver enable polarity is valid. - * @param __POLARITY__ UART driver enable polarity. - * @retval SET (__POLARITY__ is valid) or RESET (__POLARITY__ is invalid) - */ -#define IS_UART_DE_POLARITY(__POLARITY__) (((__POLARITY__) == UART_DE_POLARITY_HIGH) || \ - ((__POLARITY__) == UART_DE_POLARITY_LOW)) - - -/** - * @} - */ - -/* Include UART HAL Extended module */ -#include "stm32l0xx_hal_uart_ex.h" - - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup UART_Exported_Functions UART Exported Functions - * @{ - */ - -/** @addtogroup UART_Exported_Functions_Group1 Initialization and de-initialization functions - * @{ - */ - -/* Initialization and de-initialization functions ****************************/ -HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart); -HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart); -HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength); -HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod); -HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart); -void HAL_UART_MspInit(UART_HandleTypeDef *huart); -void HAL_UART_MspDeInit(UART_HandleTypeDef *huart); - -/* Callbacks Register/UnRegister functions ***********************************/ -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) -HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID, - pUART_CallbackTypeDef pCallback); -HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID); - -HAL_StatusTypeDef HAL_UART_RegisterRxEventCallback(UART_HandleTypeDef *huart, pUART_RxEventCallbackTypeDef pCallback); -HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart); -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ - -/** - * @} - */ - -/** @addtogroup UART_Exported_Functions_Group2 IO operation functions - * @{ - */ - -/* IO operation functions *****************************************************/ -HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart); -HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart); -HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart); -/* Transfer Abort functions */ -HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart); -HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart); -HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart); -HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart); -HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart); -HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart); - -void HAL_UART_IRQHandler(UART_HandleTypeDef *huart); -void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart); -void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart); -void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart); -void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart); -void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart); -void HAL_UART_AbortCpltCallback(UART_HandleTypeDef *huart); -void HAL_UART_AbortTransmitCpltCallback(UART_HandleTypeDef *huart); -void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart); - -void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size); - -/** - * @} - */ - -/** @addtogroup UART_Exported_Functions_Group3 Peripheral Control functions - * @{ - */ - -/* Peripheral Control functions ************************************************/ -void HAL_UART_ReceiverTimeout_Config(UART_HandleTypeDef *huart, uint32_t TimeoutValue); -HAL_StatusTypeDef HAL_UART_EnableReceiverTimeout(UART_HandleTypeDef *huart); -HAL_StatusTypeDef HAL_UART_DisableReceiverTimeout(UART_HandleTypeDef *huart); - -HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart); -HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart); -HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart); -void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart); -HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart); -HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart); - -/** - * @} - */ - -/** @addtogroup UART_Exported_Functions_Group4 Peripheral State and Error functions - * @{ - */ - -/* Peripheral State and Errors functions **************************************************/ -HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart); -uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart); - -/** - * @} - */ - -/** - * @} - */ - -/* Private functions -----------------------------------------------------------*/ -/** @addtogroup UART_Private_Functions UART Private Functions - * @{ - */ -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) -void UART_InitCallbacksToDefault(UART_HandleTypeDef *huart); -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ -HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart); -HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart); -HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, - uint32_t Tickstart, uint32_t Timeout); -void UART_AdvFeatureConfig(UART_HandleTypeDef *huart); -HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* STM32L0xx_HAL_UART_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/fw/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h b/fw/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h deleted file mode 100644 index 40914ba..0000000 --- a/fw/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_hal_uart_ex.h +++ /dev/null @@ -1,452 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l0xx_hal_uart_ex.h - * @author MCD Application Team - * @brief Header file of UART HAL Extended module. - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef STM32L0xx_HAL_UART_EX_H -#define STM32L0xx_HAL_UART_EX_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l0xx_hal_def.h" - -/** @addtogroup STM32L0xx_HAL_Driver - * @{ - */ - -/** @addtogroup UARTEx - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup UARTEx_Exported_Types UARTEx Exported Types - * @{ - */ - -/** - * @brief UART wake up from stop mode parameters - */ -typedef struct -{ - uint32_t WakeUpEvent; /*!< Specifies which event will activate the Wakeup from Stop mode flag (WUF). - This parameter can be a value of @ref UART_WakeUp_from_Stop_Selection. - If set to UART_WAKEUP_ON_ADDRESS, the two other fields below must - be filled up. */ - - uint16_t AddressLength; /*!< Specifies whether the address is 4 or 7-bit long. - This parameter can be a value of @ref UARTEx_WakeUp_Address_Length. */ - - uint8_t Address; /*!< UART/USART node address (7-bit long max). */ -} UART_WakeUpTypeDef; - -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup UARTEx_Exported_Constants UARTEx Exported Constants - * @{ - */ - -/** @defgroup UARTEx_Word_Length UARTEx Word Length - * @{ - */ -#define UART_WORDLENGTH_7B USART_CR1_M1 /*!< 7-bit long UART frame */ -#define UART_WORDLENGTH_8B 0x00000000U /*!< 8-bit long UART frame */ -#define UART_WORDLENGTH_9B USART_CR1_M0 /*!< 9-bit long UART frame */ -/** - * @} - */ - -/** @defgroup UARTEx_WakeUp_Address_Length UARTEx WakeUp Address Length - * @{ - */ -#define UART_ADDRESS_DETECT_4B 0x00000000U /*!< 4-bit long wake-up address */ -#define UART_ADDRESS_DETECT_7B USART_CR2_ADDM7 /*!< 7-bit long wake-up address */ -/** - * @} - */ - -/** - * @} - */ - -/* Exported macros -----------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup UARTEx_Exported_Functions - * @{ - */ - -/** @addtogroup UARTEx_Exported_Functions_Group1 - * @{ - */ - -/* Initialization and de-initialization functions ****************************/ -HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, - uint32_t DeassertionTime); - -/** - * @} - */ - -/** @addtogroup UARTEx_Exported_Functions_Group2 - * @{ - */ - -void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart); - -/** - * @} - */ - -/** @addtogroup UARTEx_Exported_Functions_Group3 - * @{ - */ - -/* Peripheral Control functions **********************************************/ -HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection); -HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart); -HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart); - -HAL_StatusTypeDef HAL_UARTEx_EnableClockStopMode(UART_HandleTypeDef *huart); -HAL_StatusTypeDef HAL_UARTEx_DisableClockStopMode(UART_HandleTypeDef *huart); - -HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength); - - -HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint16_t *RxLen, uint32_t Timeout); -HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); - - -/** - * @} - */ - -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/** @defgroup UARTEx_Private_Macros UARTEx Private Macros - * @{ - */ - -/** @brief Report the UART clock source. - * @param __HANDLE__ specifies the UART Handle. - * @param __CLOCKSOURCE__ output variable. - * @retval UART clocking source, written in __CLOCKSOURCE__. - */ -#if defined (STM32L031xx) || defined (STM32L041xx) || defined (STM32L011xx) || defined (STM32L021xx) || defined (STM32L010xB) || defined (STM32L010x8) || defined (STM32L010x6) || defined (STM32L010x4) -#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ - do { \ - if((__HANDLE__)->Instance == USART2) \ - { \ - switch(__HAL_RCC_GET_USART2_SOURCE()) \ - { \ - case RCC_USART2CLKSOURCE_PCLK1: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ - break; \ - case RCC_USART2CLKSOURCE_HSI: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ - break; \ - case RCC_USART2CLKSOURCE_SYSCLK: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ - break; \ - case RCC_USART2CLKSOURCE_LSE: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ - break; \ - default: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ - break; \ - } \ - } \ - else if((__HANDLE__)->Instance == LPUART1) \ - { \ - switch(__HAL_RCC_GET_LPUART1_SOURCE()) \ - { \ - case RCC_LPUART1CLKSOURCE_PCLK1: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ - break; \ - case RCC_LPUART1CLKSOURCE_HSI: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ - break; \ - case RCC_LPUART1CLKSOURCE_SYSCLK: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ - break; \ - case RCC_LPUART1CLKSOURCE_LSE: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ - break; \ - default: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ - break; \ - } \ - } \ - else \ - { \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ - } \ - } while(0) - -#elif defined (STM32L051xx) || defined (STM32L052xx) || defined (STM32L053xx) || defined (STM32L062xx) || defined (STM32L063xx) - -#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ - do { \ - if((__HANDLE__)->Instance == USART1) \ - { \ - switch(__HAL_RCC_GET_USART1_SOURCE()) \ - { \ - case RCC_USART1CLKSOURCE_PCLK2: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK2; \ - break; \ - case RCC_USART1CLKSOURCE_HSI: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ - break; \ - case RCC_USART1CLKSOURCE_SYSCLK: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ - break; \ - case RCC_USART1CLKSOURCE_LSE: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ - break; \ - default: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ - break; \ - } \ - } \ - else if((__HANDLE__)->Instance == USART2) \ - { \ - switch(__HAL_RCC_GET_USART2_SOURCE()) \ - { \ - case RCC_USART2CLKSOURCE_PCLK1: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ - break; \ - case RCC_USART2CLKSOURCE_HSI: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ - break; \ - case RCC_USART2CLKSOURCE_SYSCLK: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ - break; \ - case RCC_USART2CLKSOURCE_LSE: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ - break; \ - default: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ - break; \ - } \ - } \ - else if((__HANDLE__)->Instance == LPUART1) \ - { \ - switch(__HAL_RCC_GET_LPUART1_SOURCE()) \ - { \ - case RCC_LPUART1CLKSOURCE_PCLK1: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ - break; \ - case RCC_LPUART1CLKSOURCE_HSI: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ - break; \ - case RCC_LPUART1CLKSOURCE_SYSCLK: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ - break; \ - case RCC_LPUART1CLKSOURCE_LSE: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ - break; \ - default: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ - break; \ - } \ - } \ - else \ - { \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ - } \ - } while(0) - -#else - -#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ - do { \ - if((__HANDLE__)->Instance == USART1) \ - { \ - switch(__HAL_RCC_GET_USART1_SOURCE()) \ - { \ - case RCC_USART1CLKSOURCE_PCLK2: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK2; \ - break; \ - case RCC_USART1CLKSOURCE_HSI: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ - break; \ - case RCC_USART1CLKSOURCE_SYSCLK: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ - break; \ - case RCC_USART1CLKSOURCE_LSE: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ - break; \ - default: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ - break; \ - } \ - } \ - else if((__HANDLE__)->Instance == USART2) \ - { \ - switch(__HAL_RCC_GET_USART2_SOURCE()) \ - { \ - case RCC_USART2CLKSOURCE_PCLK1: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ - break; \ - case RCC_USART2CLKSOURCE_HSI: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ - break; \ - case RCC_USART2CLKSOURCE_SYSCLK: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ - break; \ - case RCC_USART2CLKSOURCE_LSE: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ - break; \ - default: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ - break; \ - } \ - } \ - else if((__HANDLE__)->Instance == USART4) \ - { \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ - } \ - else if((__HANDLE__)->Instance == USART5) \ - { \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ - } \ - else if((__HANDLE__)->Instance == LPUART1) \ - { \ - switch(__HAL_RCC_GET_LPUART1_SOURCE()) \ - { \ - case RCC_LPUART1CLKSOURCE_PCLK1: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ - break; \ - case RCC_LPUART1CLKSOURCE_HSI: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ - break; \ - case RCC_LPUART1CLKSOURCE_SYSCLK: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ - break; \ - case RCC_LPUART1CLKSOURCE_LSE: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ - break; \ - default: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ - break; \ - } \ - } \ - else \ - { \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ - } \ - } while(0) -#endif /* (STM32L031xx) || (STM32L041xx) || (STM32L011xx) || (STM32L021xx) || (STM32L010xB) || (STM32L010x8) || (STM32L010x6) || (STM32L010x4)*/ - - -/** @brief Report the UART mask to apply to retrieve the received data - * according to the word length and to the parity bits activation. - * @note If PCE = 1, the parity bit is not included in the data extracted - * by the reception API(). - * This masking operation is not carried out in the case of - * DMA transfers. - * @param __HANDLE__ specifies the UART Handle. - * @retval None, the mask to apply to UART RDR register is stored in (__HANDLE__)->Mask field. - */ -#define UART_MASK_COMPUTATION(__HANDLE__) \ - do { \ - if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_9B) \ - { \ - if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \ - { \ - (__HANDLE__)->Mask = 0x01FFU ; \ - } \ - else \ - { \ - (__HANDLE__)->Mask = 0x00FFU ; \ - } \ - } \ - else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_8B) \ - { \ - if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \ - { \ - (__HANDLE__)->Mask = 0x00FFU ; \ - } \ - else \ - { \ - (__HANDLE__)->Mask = 0x007FU ; \ - } \ - } \ - else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_7B) \ - { \ - if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \ - { \ - (__HANDLE__)->Mask = 0x007FU ; \ - } \ - else \ - { \ - (__HANDLE__)->Mask = 0x003FU ; \ - } \ - } \ - else \ - { \ - (__HANDLE__)->Mask = 0x0000U; \ - } \ - } while(0U) - -/** - * @brief Ensure that UART frame length is valid. - * @param __LENGTH__ UART frame length. - * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid) - */ -#define IS_UART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == UART_WORDLENGTH_7B) || \ - ((__LENGTH__) == UART_WORDLENGTH_8B) || \ - ((__LENGTH__) == UART_WORDLENGTH_9B)) - -/** - * @brief Ensure that UART wake-up address length is valid. - * @param __ADDRESS__ UART wake-up address length. - * @retval SET (__ADDRESS__ is valid) or RESET (__ADDRESS__ is invalid) - */ -#define IS_UART_ADDRESSLENGTH_DETECT(__ADDRESS__) (((__ADDRESS__) == UART_ADDRESS_DETECT_4B) || \ - ((__ADDRESS__) == UART_ADDRESS_DETECT_7B)) - -/** - * @} - */ - -/* Private functions ---------------------------------------------------------*/ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* STM32L0xx_HAL_UART_EX_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/fw/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h b/fw/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h new file mode 100644 index 0000000..4d82663 --- /dev/null +++ b/fw/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h @@ -0,0 +1,1171 @@ +/** + ****************************************************************************** + * @file stm32l0xx_ll_bus.h + * @author MCD Application Team + * @brief Header file of BUS LL module. + + @verbatim + ##### RCC Limitations ##### + ============================================================================== + [..] + A delay between an RCC peripheral clock enable and the effective peripheral + enabling should be taken into account in order to manage the peripheral read/write + from/to registers. + (+) This delay depends on the peripheral mapping. + (++) AHB & APB peripherals, 1 dummy read is necessary + + [..] + Workarounds: + (#) For AHB & APB peripherals, a dummy read to the peripheral register has been + inserted in each LL_{BUS}_GRP{x}_EnableClock() function. + + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright(c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32L0xx_LL_BUS_H +#define __STM32L0xx_LL_BUS_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l0xx.h" + +/** @addtogroup STM32L0xx_LL_Driver + * @{ + */ + +#if defined(RCC) + +/** @defgroup BUS_LL BUS + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ + +/* Private macros ------------------------------------------------------------*/ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup BUS_LL_Exported_Constants BUS Exported Constants + * @{ + */ + +/** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH + * @{ + */ +#define LL_AHB1_GRP1_PERIPH_ALL 0xFFFFFFFFU +#define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHBENR_DMA1EN /*!< DMA1 clock enable */ +#define LL_AHB1_GRP1_PERIPH_MIF RCC_AHBENR_MIFEN /*!< MIF clock enable */ +#define LL_AHB1_GRP1_PERIPH_SRAM RCC_AHBSMENR_SRAMSMEN /*!< Sleep Mode SRAM clock enable */ +#define LL_AHB1_GRP1_PERIPH_CRC RCC_AHBENR_CRCEN /*!< CRC clock enable */ +#if defined(TSC) +#define LL_AHB1_GRP1_PERIPH_TSC RCC_AHBENR_TSCEN /*!< TSC clock enable */ +#endif /*TSC*/ +#if defined(RNG) +#define LL_AHB1_GRP1_PERIPH_RNG RCC_AHBENR_RNGEN /*!< RNG clock enable */ +#endif /*RNG*/ +#if defined(AES) +#define LL_AHB1_GRP1_PERIPH_CRYP RCC_AHBENR_CRYPEN /*!< CRYP clock enable */ +#endif /*AES*/ +/** + * @} + */ + + +/** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH + * @{ + */ +#define LL_APB1_GRP1_PERIPH_ALL 0xFFFFFFFFU +#define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR_TIM2EN /*!< TIM2 clock enable */ +#if defined(TIM3) +#define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR_TIM3EN /*!< TIM3 clock enable */ +#endif +#if defined(TIM6) +#define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1ENR_TIM6EN /*!< TIM6 clock enable */ +#endif +#if defined(TIM7) +#define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR_TIM7EN /*!< TIM7 clock enable */ +#endif +#if defined(LCD) +#define LL_APB1_GRP1_PERIPH_LCD RCC_APB1ENR_LCDEN /*!< LCD clock enable */ +#endif /*LCD*/ +#define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR_WWDGEN /*!< WWDG clock enable */ +#if defined(SPI2) +#define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR_SPI2EN /*!< SPI2 clock enable */ +#endif +#define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR_USART2EN /*!< USART2 clock enable */ +#define LL_APB1_GRP1_PERIPH_LPUART1 RCC_APB1ENR_LPUART1EN /*!< LPUART1 clock enable */ +#if defined(USART4) +#define LL_APB1_GRP1_PERIPH_USART4 RCC_APB1ENR_USART4EN /*!< USART4 clock enable */ +#endif +#if defined(USART5) +#define LL_APB1_GRP1_PERIPH_USART5 RCC_APB1ENR_USART5EN /*!< USART5 clock enable */ +#endif +#define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR_I2C1EN /*!< I2C1 clock enable */ +#if defined(I2C2) +#define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR_I2C2EN /*!< I2C2 clock enable */ +#endif +#if defined(USB) +#define LL_APB1_GRP1_PERIPH_USB RCC_APB1ENR_USBEN /*!< USB clock enable */ +#endif /*USB*/ +#if defined(CRS) +#define LL_APB1_GRP1_PERIPH_CRS RCC_APB1ENR_CRSEN /*!< CRS clock enable */ +#endif /*CRS*/ +#define LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR_PWREN /*!< PWR clock enable */ +#if defined(DAC) +#define LL_APB1_GRP1_PERIPH_DAC1 RCC_APB1ENR_DACEN /*!< DAC clock enable */ +#endif +#if defined(I2C3) +#define LL_APB1_GRP1_PERIPH_I2C3 RCC_APB1ENR_I2C3EN /*!< I2C3 clock enable */ +#endif +#define LL_APB1_GRP1_PERIPH_LPTIM1 RCC_APB1ENR_LPTIM1EN /*!< LPTIM1 clock enable */ +/** + * @} + */ + + + + +/** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH APB2 GRP1 PERIPH + * @{ + */ +#define LL_APB2_GRP1_PERIPH_ALL 0xFFFFFFFFU +#define LL_APB2_GRP1_PERIPH_SYSCFG RCC_APB2ENR_SYSCFGEN /*!< SYSCFG clock enable */ +#define LL_APB2_GRP1_PERIPH_TIM21 RCC_APB2ENR_TIM21EN /*!< TIM21 clock enable */ +#if defined(TIM22) +#define LL_APB2_GRP1_PERIPH_TIM22 RCC_APB2ENR_TIM22EN /*!< TIM22 clock enable */ +#endif +#define LL_APB2_GRP1_PERIPH_FW RCC_APB2ENR_FWEN /*!< FireWall clock enable */ +#define LL_APB2_GRP1_PERIPH_ADC1 RCC_APB2ENR_ADC1EN /*!< ADC1 clock enable */ +#define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN /*!< SPI1 clock enable */ +#if defined(USART1) +#define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN /*!< USART1 clock enable */ +#endif +#define LL_APB2_GRP1_PERIPH_DBGMCU RCC_APB2ENR_DBGMCUEN /*!< DBGMCU clock enable */ + +/** + * @} + */ + + + +/** @defgroup BUS_LL_EC_IOP_GRP1_PERIPH IOP GRP1 PERIPH + * @{ + */ +#define LL_IOP_GRP1_PERIPH_ALL 0xFFFFFFFFU +#define LL_IOP_GRP1_PERIPH_GPIOA RCC_IOPENR_GPIOAEN /*!< GPIO port A control */ +#define LL_IOP_GRP1_PERIPH_GPIOB RCC_IOPENR_GPIOBEN /*!< GPIO port B control */ +#define LL_IOP_GRP1_PERIPH_GPIOC RCC_IOPENR_GPIOCEN /*!< GPIO port C control */ +#if defined(GPIOD) +#define LL_IOP_GRP1_PERIPH_GPIOD RCC_IOPENR_GPIODEN /*!< GPIO port D control */ +#endif /*GPIOD*/ +#if defined(GPIOE) +#define LL_IOP_GRP1_PERIPH_GPIOE RCC_IOPENR_GPIOEEN /*!< GPIO port H control */ +#endif /*GPIOE*/ +#if defined(GPIOH) +#define LL_IOP_GRP1_PERIPH_GPIOH RCC_IOPENR_GPIOHEN /*!< GPIO port H control */ +#endif /*GPIOH*/ +/** + * @} + */ + + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +/** @defgroup BUS_LL_Exported_Functions BUS Exported Functions + * @{ + */ + +/** @defgroup BUS_LL_EF_AHB1 AHB1 + * @{ + */ + +/** + * @brief Enable AHB1 peripherals clock. + * @rmtoll AHBENR DMAEN LL_AHB1_GRP1_EnableClock\n + * AHBENR MIFEN LL_AHB1_GRP1_EnableClock\n + * AHBENR CRCEN LL_AHB1_GRP1_EnableClock\n + * AHBENR TSCEN LL_AHB1_GRP1_EnableClock\n + * AHBENR RNGEN LL_AHB1_GRP1_EnableClock\n + * AHBENR CRYPEN LL_AHB1_GRP1_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_MIF + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->AHBENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->AHBENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if AHB1 peripheral clock is enabled or not + * @rmtoll AHBENR DMAEN LL_AHB1_GRP1_IsEnabledClock\n + * AHBENR MIFEN LL_AHB1_GRP1_IsEnabledClock\n + * AHBENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n + * AHBENR TSCEN LL_AHB1_GRP1_IsEnabledClock\n + * AHBENR RNGEN LL_AHB1_GRP1_IsEnabledClock\n + * AHBENR CRYPEN LL_AHB1_GRP1_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_MIF + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*) + * + * (*) value not defined in all devices. + * @retval State of Periphs (1 or 0). +*/ +__STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC->AHBENR, Periphs) == (Periphs)) ? 1UL : 0UL); +} + +/** + * @brief Disable AHB1 peripherals clock. + * @rmtoll AHBENR DMAEN LL_AHB1_GRP1_DisableClock\n + * AHBENR MIFEN LL_AHB1_GRP1_DisableClock\n + * AHBENR CRCEN LL_AHB1_GRP1_DisableClock\n + * AHBENR TSCEN LL_AHB1_GRP1_DisableClock\n + * AHBENR RNGEN LL_AHB1_GRP1_DisableClock\n + * AHBENR CRYPEN LL_AHB1_GRP1_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_MIF + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHBENR, Periphs); +} + +/** + * @brief Force AHB1 peripherals reset. + * @rmtoll AHBRSTR DMARST LL_AHB1_GRP1_ForceReset\n + * AHBRSTR MIFRST LL_AHB1_GRP1_ForceReset\n + * AHBRSTR CRCRST LL_AHB1_GRP1_ForceReset\n + * AHBRSTR TSCRST LL_AHB1_GRP1_ForceReset\n + * AHBRSTR RNGRST LL_AHB1_GRP1_ForceReset\n + * AHBRSTR CRYPRST LL_AHB1_GRP1_ForceReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_ALL + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_MIF + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs) +{ + SET_BIT(RCC->AHBRSTR, Periphs); +} + +/** + * @brief Release AHB1 peripherals reset. + * @rmtoll AHBRSTR DMARST LL_AHB1_GRP1_ReleaseReset\n + * AHBRSTR MIFRST LL_AHB1_GRP1_ReleaseReset\n + * AHBRSTR CRCRST LL_AHB1_GRP1_ReleaseReset\n + * AHBRSTR TSCRST LL_AHB1_GRP1_ReleaseReset\n + * AHBRSTR RNGRST LL_AHB1_GRP1_ReleaseReset\n + * AHBRSTR CRYPRST LL_AHB1_GRP1_ReleaseReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_ALL + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_MIF + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHBRSTR, Periphs); +} + +/** + * @brief Enable AHB1 peripherals clock during Low Power (Sleep) mode. + * @rmtoll AHBSMENR DMASMEN LL_AHB1_GRP1_EnableClockSleep\n + * AHBSMENR MIFSMEN LL_AHB1_GRP1_EnableClockSleep\n + * AHBSMENR SRAMSMEN LL_AHB1_GRP1_EnableClockSleep\n + * AHBSMENR CRCSMEN LL_AHB1_GRP1_EnableClockSleep\n + * AHBSMENR TSCSMEN LL_AHB1_GRP1_EnableClockSleep\n + * AHBSMENR RNGSMEN LL_AHB1_GRP1_EnableClockSleep\n + * AHBSMENR CRYPSMEN LL_AHB1_GRP1_EnableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_MIF + * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB1_GRP1_EnableClockSleep(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->AHBSMENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->AHBSMENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Disable AHB1 peripherals clock during Low Power (Sleep) mode. + * @rmtoll AHBSMENR DMASMEN LL_AHB1_GRP1_DisableClockSleep\n + * AHBSMENR MIFSMEN LL_AHB1_GRP1_DisableClockSleep\n + * AHBSMENR SRAMSMEN LL_AHB1_GRP1_DisableClockSleep\n + * AHBSMENR CRCSMEN LL_AHB1_GRP1_DisableClockSleep\n + * AHBSMENR TSCSMEN LL_AHB1_GRP1_DisableClockSleep\n + * AHBSMENR RNGSMEN LL_AHB1_GRP1_DisableClockSleep\n + * AHBSMENR CRYPSMEN LL_AHB1_GRP1_DisableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_MIF + * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB1_GRP1_DisableClockSleep(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHBSMENR, Periphs); +} + +/** + * @} + */ + +/** @defgroup BUS_LL_EF_APB1 APB1 + * @{ + */ + +/** + * @brief Enable APB1 peripherals clock. + * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_EnableClock\n + * APB1ENR TIM3EN LL_APB1_GRP1_EnableClock\n + * APB1ENR TIM6EN LL_APB1_GRP1_EnableClock\n + * APB1ENR TIM7EN LL_APB1_GRP1_EnableClock\n + * APB1ENR LCDEN LL_APB1_GRP1_EnableClock\n + * APB1ENR WWDGEN LL_APB1_GRP1_EnableClock\n + * APB1ENR SPI2EN LL_APB1_GRP1_EnableClock\n + * APB1ENR USART2EN LL_APB1_GRP1_EnableClock\n + * APB1ENR LPUART1EN LL_APB1_GRP1_EnableClock\n + * APB1ENR USART4EN LL_APB1_GRP1_EnableClock\n + * APB1ENR USART5EN LL_APB1_GRP1_EnableClock\n + * APB1ENR I2C1EN LL_APB1_GRP1_EnableClock\n + * APB1ENR I2C2EN LL_APB1_GRP1_EnableClock\n + * APB1ENR USBEN LL_APB1_GRP1_EnableClock\n + * APB1ENR CRSEN LL_APB1_GRP1_EnableClock\n + * APB1ENR PWREN LL_APB1_GRP1_EnableClock\n + * APB1ENR DACEN LL_APB1_GRP1_EnableClock\n + * APB1ENR I2C3EN LL_APB1_GRP1_EnableClock\n + * APB1ENR LPTIM1EN LL_APB1_GRP1_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_LPUART1 + * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) + * @arg @ref LL_APB1_GRP1_PERIPH_PWR + * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->APB1ENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->APB1ENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if APB1 peripheral clock is enabled or not + * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR TIM3EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR TIM6EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR TIM7EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR LCDEN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR WWDGEN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR SPI2EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR USART2EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR LPUART1EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR USART4EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR USART5EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR I2C1EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR I2C2EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR USBEN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR CRSEN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR PWREN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR DACEN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR I2C3EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR LPTIM1EN LL_APB1_GRP1_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_LPUART1 + * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) + * @arg @ref LL_APB1_GRP1_PERIPH_PWR + * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + * + * (*) value not defined in all devices. + * @retval State of Periphs (1 or 0). +*/ +__STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC->APB1ENR, Periphs) == (Periphs)) ? 1UL : 0UL); +} + +/** + * @brief Disable APB1 peripherals clock. + * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_DisableClock\n + * APB1ENR TIM3EN LL_APB1_GRP1_DisableClock\n + * APB1ENR TIM6EN LL_APB1_GRP1_DisableClock\n + * APB1ENR TIM7EN LL_APB1_GRP1_DisableClock\n + * APB1ENR LCDEN LL_APB1_GRP1_DisableClock\n + * APB1ENR WWDGEN LL_APB1_GRP1_DisableClock\n + * APB1ENR SPI2EN LL_APB1_GRP1_DisableClock\n + * APB1ENR USART2EN LL_APB1_GRP1_DisableClock\n + * APB1ENR LPUART1EN LL_APB1_GRP1_DisableClock\n + * APB1ENR USART4EN LL_APB1_GRP1_DisableClock\n + * APB1ENR USART5EN LL_APB1_GRP1_DisableClock\n + * APB1ENR I2C1EN LL_APB1_GRP1_DisableClock\n + * APB1ENR I2C2EN LL_APB1_GRP1_DisableClock\n + * APB1ENR USBEN LL_APB1_GRP1_DisableClock\n + * APB1ENR CRSEN LL_APB1_GRP1_DisableClock\n + * APB1ENR PWREN LL_APB1_GRP1_DisableClock\n + * APB1ENR DACEN LL_APB1_GRP1_DisableClock\n + * APB1ENR I2C3EN LL_APB1_GRP1_DisableClock\n + * APB1ENR LPTIM1EN LL_APB1_GRP1_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_LPUART1 + * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) + * @arg @ref LL_APB1_GRP1_PERIPH_PWR + * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB1ENR, Periphs); +} + +/** + * @brief Force APB1 peripherals reset. + * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR TIM3RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR TIM6RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR TIM7RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR LCDRST LL_APB1_GRP1_ForceReset\n + * APB1RSTR WWDGRST LL_APB1_GRP1_ForceReset\n + * APB1RSTR SPI2RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR USART2RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR LPUART1RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR USART4RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR USART5RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR I2C1RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR I2C2RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR USBRST LL_APB1_GRP1_ForceReset\n + * APB1RSTR CRSRST LL_APB1_GRP1_ForceReset\n + * APB1RSTR PWRRST LL_APB1_GRP1_ForceReset\n + * APB1RSTR DACRST LL_APB1_GRP1_ForceReset\n + * APB1RSTR I2C3RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR LPTIM1RST LL_APB1_GRP1_ForceReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_ALL + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_LPUART1 + * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) + * @arg @ref LL_APB1_GRP1_PERIPH_PWR + * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs) +{ + SET_BIT(RCC->APB1RSTR, Periphs); +} + +/** + * @brief Release APB1 peripherals reset. + * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR TIM3RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR TIM6RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR TIM7RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR LCDRST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR WWDGRST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR SPI2RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR USART2RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR LPUART1RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR USART4RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR USART5RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR I2C1RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR I2C2RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR USBRST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR CRSRST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR PWRRST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR DACRST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR I2C3RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR LPTIM1RST LL_APB1_GRP1_ReleaseReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_ALL + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_LPUART1 + * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) + * @arg @ref LL_APB1_GRP1_PERIPH_PWR + * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB1RSTR, Periphs); +} + +/** + * @brief Enable APB1 peripherals clock during Low Power (Sleep) mode. + * @rmtoll APB1SMENR TIM2SMEN LL_APB1_GRP1_EnableClockSleep\n + * APB1SMENR TIM3SMEN LL_APB1_GRP1_EnableClockSleep\n + * APB1SMENR TIM6SMEN LL_APB1_GRP1_EnableClockSleep\n + * APB1SMENR TIM7SMEN LL_APB1_GRP1_EnableClockSleep\n + * APB1SMENR LCDSMEN LL_APB1_GRP1_EnableClockSleep\n + * APB1SMENR WWDGSMEN LL_APB1_GRP1_EnableClockSleep\n + * APB1SMENR SPI2SMEN LL_APB1_GRP1_EnableClockSleep\n + * APB1SMENR USART2SMEN LL_APB1_GRP1_EnableClockSleep\n + * APB1SMENR LPUART1SMEN LL_APB1_GRP1_EnableClockSleep\n + * APB1SMENR USART4SMEN LL_APB1_GRP1_EnableClockSleep\n + * APB1SMENR USART5SMEN LL_APB1_GRP1_EnableClockSleep\n + * APB1SMENR I2C1SMEN LL_APB1_GRP1_EnableClockSleep\n + * APB1SMENR I2C2SMEN LL_APB1_GRP1_EnableClockSleep\n + * APB1SMENR USBSMEN LL_APB1_GRP1_EnableClockSleep\n + * APB1SMENR CRSSMEN LL_APB1_GRP1_EnableClockSleep\n + * APB1SMENR PWRSMEN LL_APB1_GRP1_EnableClockSleep\n + * APB1SMENR DACSMEN LL_APB1_GRP1_EnableClockSleep\n + * APB1SMENR I2C3SMEN LL_APB1_GRP1_EnableClockSleep\n + * APB1SMENR LPTIM1SMEN LL_APB1_GRP1_EnableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_LPUART1 + * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) + * @arg @ref LL_APB1_GRP1_PERIPH_PWR + * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB1_GRP1_EnableClockSleep(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->APB1SMENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->APB1SMENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Disable APB1 peripherals clock during Low Power (Sleep) mode. + * @rmtoll APB1SMENR TIM2SMEN LL_APB1_GRP1_DisableClockSleep\n + * APB1SMENR TIM3SMEN LL_APB1_GRP1_DisableClockSleep\n + * APB1SMENR TIM6SMEN LL_APB1_GRP1_DisableClockSleep\n + * APB1SMENR TIM7SMEN LL_APB1_GRP1_DisableClockSleep\n + * APB1SMENR LCDSMEN LL_APB1_GRP1_DisableClockSleep\n + * APB1SMENR WWDGSMEN LL_APB1_GRP1_DisableClockSleep\n + * APB1SMENR SPI2SMEN LL_APB1_GRP1_DisableClockSleep\n + * APB1SMENR USART2SMEN LL_APB1_GRP1_DisableClockSleep\n + * APB1SMENR LPUART1SMEN LL_APB1_GRP1_DisableClockSleep\n + * APB1SMENR USART4SMEN LL_APB1_GRP1_DisableClockSleep\n + * APB1SMENR USART5SMEN LL_APB1_GRP1_DisableClockSleep\n + * APB1SMENR I2C1SMEN LL_APB1_GRP1_DisableClockSleep\n + * APB1SMENR I2C2SMEN LL_APB1_GRP1_DisableClockSleep\n + * APB1SMENR USBSMEN LL_APB1_GRP1_DisableClockSleep\n + * APB1SMENR CRSSMEN LL_APB1_GRP1_DisableClockSleep\n + * APB1SMENR PWRSMEN LL_APB1_GRP1_DisableClockSleep\n + * APB1SMENR DACSMEN LL_APB1_GRP1_DisableClockSleep\n + * APB1SMENR I2C3SMEN LL_APB1_GRP1_DisableClockSleep\n + * APB1SMENR LPTIM1SMEN LL_APB1_GRP1_DisableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_LPUART1 + * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) + * @arg @ref LL_APB1_GRP1_PERIPH_PWR + * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB1_GRP1_DisableClockSleep(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB1SMENR, Periphs); +} + +/** + * @} + */ + +/** @defgroup BUS_LL_EF_APB2 APB2 + * @{ + */ + +/** + * @brief Enable APB2 peripherals clock. + * @rmtoll APB2ENR SYSCFGEN LL_APB2_GRP1_EnableClock\n + * APB2ENR TIM21EN LL_APB2_GRP1_EnableClock\n + * APB2ENR TIM22EN LL_APB2_GRP1_EnableClock\n + * APB2ENR FWEN LL_APB2_GRP1_EnableClock\n + * APB2ENR ADCEN LL_APB2_GRP1_EnableClock\n + * APB2ENR SPI1EN LL_APB2_GRP1_EnableClock\n + * APB2ENR USART1EN LL_APB2_GRP1_EnableClock\n + * APB2ENR DBGEN LL_APB2_GRP1_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG + * @arg @ref LL_APB2_GRP1_PERIPH_TIM21 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM22 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_FW + * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DBGMCU + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->APB2ENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->APB2ENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if APB2 peripheral clock is enabled or not + * @rmtoll APB2ENR SYSCFGEN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR TIM21EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR TIM22EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR FWEN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR ADCEN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR SPI1EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR USART1EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR DBGEN LL_APB2_GRP1_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG + * @arg @ref LL_APB2_GRP1_PERIPH_TIM21 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM22 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_FW + * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DBGMCU + * + * (*) value not defined in all devices. + * @retval State of Periphs (1 or 0). +*/ +__STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC->APB2ENR, Periphs) == (Periphs)) ? 1UL : 0UL); +} + +/** + * @brief Disable APB2 peripherals clock. + * @rmtoll APB2ENR SYSCFGEN LL_APB2_GRP1_DisableClock\n + * APB2ENR TIM21EN LL_APB2_GRP1_DisableClock\n + * APB2ENR TIM22EN LL_APB2_GRP1_DisableClock\n + * APB2ENR FWEN LL_APB2_GRP1_DisableClock\n + * APB2ENR ADCEN LL_APB2_GRP1_DisableClock\n + * APB2ENR SPI1EN LL_APB2_GRP1_DisableClock\n + * APB2ENR USART1EN LL_APB2_GRP1_DisableClock\n + * APB2ENR DBGEN LL_APB2_GRP1_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG + * @arg @ref LL_APB2_GRP1_PERIPH_TIM21 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM22 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_FW + * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DBGMCU + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB2ENR, Periphs); +} + +/** + * @brief Force APB2 peripherals reset. + * @rmtoll APB2RSTR SYSCFGRST LL_APB2_GRP1_ForceReset\n + * APB2RSTR TIM21RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR TIM22RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR ADCRST LL_APB2_GRP1_ForceReset\n + * APB2RSTR SPI1RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR USART1RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR DBGRST LL_APB2_GRP1_ForceReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_ALL + * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG + * @arg @ref LL_APB2_GRP1_PERIPH_TIM21 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM22 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DBGMCU + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs) +{ + SET_BIT(RCC->APB2RSTR, Periphs); +} + +/** + * @brief Release APB2 peripherals reset. + * @rmtoll APB2RSTR SYSCFGRST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR TIM21RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR TIM22RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR ADCRST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR SPI1RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR USART1RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR DBGRST LL_APB2_GRP1_ReleaseReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_ALL + * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG + * @arg @ref LL_APB2_GRP1_PERIPH_TIM21 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM22 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DBGMCU + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB2RSTR, Periphs); +} + +/** + * @brief Enable APB2 peripherals clock during Low Power (Sleep) mode. + * @rmtoll APB2SMENR SYSCFGSMEN LL_APB2_GRP1_EnableClockSleep\n + * APB2SMENR TIM21SMEN LL_APB2_GRP1_EnableClockSleep\n + * APB2SMENR TIM22SMEN LL_APB2_GRP1_EnableClockSleep\n + * APB2SMENR ADCSMEN LL_APB2_GRP1_EnableClockSleep\n + * APB2SMENR SPI1SMEN LL_APB2_GRP1_EnableClockSleep\n + * APB2SMENR USART1SMEN LL_APB2_GRP1_EnableClockSleep\n + * APB2SMENR DBGSMEN LL_APB2_GRP1_EnableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG + * @arg @ref LL_APB2_GRP1_PERIPH_TIM21 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM22 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DBGMCU + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB2_GRP1_EnableClockSleep(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->APB2SMENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->APB2SMENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Disable APB2 peripherals clock during Low Power (Sleep) mode. + * @rmtoll APB2SMENR SYSCFGSMEN LL_APB2_GRP1_DisableClockSleep\n + * APB2SMENR TIM21SMEN LL_APB2_GRP1_DisableClockSleep\n + * APB2SMENR TIM22SMEN LL_APB2_GRP1_DisableClockSleep\n + * APB2SMENR ADCSMEN LL_APB2_GRP1_DisableClockSleep\n + * APB2SMENR SPI1SMEN LL_APB2_GRP1_DisableClockSleep\n + * APB2SMENR USART1SMEN LL_APB2_GRP1_DisableClockSleep\n + * APB2SMENR DBGSMEN LL_APB2_GRP1_DisableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG + * @arg @ref LL_APB2_GRP1_PERIPH_TIM21 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM22 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DBGMCU + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB2_GRP1_DisableClockSleep(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB2SMENR, Periphs); +} + +/** + * @} + */ +/** @defgroup BUS_LL_EF_IOP IOP + * @{ + */ + +/** + * @brief Enable IOP peripherals clock. + * @rmtoll IOPENR GPIOAEN LL_IOP_GRP1_EnableClock\n + * IOPENR GPIOBEN LL_IOP_GRP1_EnableClock\n + * IOPENR GPIOCEN LL_IOP_GRP1_EnableClock\n + * IOPENR GPIODEN LL_IOP_GRP1_EnableClock\n + * IOPENR GPIOEEN LL_IOP_GRP1_EnableClock\n + * IOPENR GPIOHEN LL_IOP_GRP1_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_IOP_GRP1_PERIPH_GPIOA + * @arg @ref LL_IOP_GRP1_PERIPH_GPIOB + * @arg @ref LL_IOP_GRP1_PERIPH_GPIOC + * @arg @ref LL_IOP_GRP1_PERIPH_GPIOD (*) + * @arg @ref LL_IOP_GRP1_PERIPH_GPIOE (*) + * @arg @ref LL_IOP_GRP1_PERIPH_GPIOH (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_IOP_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->IOPENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->IOPENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if IOP peripheral clock is enabled or not + * @rmtoll IOPENR GPIOAEN LL_IOP_GRP1_IsEnabledClock\n + * IOPENR GPIOBEN LL_IOP_GRP1_IsEnabledClock\n + * IOPENR GPIOCEN LL_IOP_GRP1_IsEnabledClock\n + * IOPENR GPIODEN LL_IOP_GRP1_IsEnabledClock\n + * IOPENR GPIOEEN LL_IOP_GRP1_IsEnabledClock\n + * IOPENR GPIOHEN LL_IOP_GRP1_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_IOP_GRP1_PERIPH_GPIOA + * @arg @ref LL_IOP_GRP1_PERIPH_GPIOB + * @arg @ref LL_IOP_GRP1_PERIPH_GPIOC + * @arg @ref LL_IOP_GRP1_PERIPH_GPIOD (*) + * @arg @ref LL_IOP_GRP1_PERIPH_GPIOE (*) + * @arg @ref LL_IOP_GRP1_PERIPH_GPIOH (*) + * + * (*) value not defined in all devices. + * @retval State of Periphs (1 or 0). +*/ +__STATIC_INLINE uint32_t LL_IOP_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC->IOPENR, Periphs) == (Periphs)) ? 1UL : 0UL); +} + +/** + * @brief Disable IOP peripherals clock. + * @rmtoll IOPENR GPIOAEN LL_IOP_GRP1_DisableClock\n + * IOPENR GPIOBEN LL_IOP_GRP1_DisableClock\n + * IOPENR GPIOCEN LL_IOP_GRP1_DisableClock\n + * IOPENR GPIODEN LL_IOP_GRP1_DisableClock\n + * IOPENR GPIOEEN LL_IOP_GRP1_DisableClock\n + * IOPENR GPIOHEN LL_IOP_GRP1_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_IOP_GRP1_PERIPH_GPIOA + * @arg @ref LL_IOP_GRP1_PERIPH_GPIOB + * @arg @ref LL_IOP_GRP1_PERIPH_GPIOC + * @arg @ref LL_IOP_GRP1_PERIPH_GPIOD (*) + * @arg @ref LL_IOP_GRP1_PERIPH_GPIOE (*) + * @arg @ref LL_IOP_GRP1_PERIPH_GPIOH (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_IOP_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC->IOPENR, Periphs); +} + +/** + * @brief Disable IOP peripherals clock. + * @rmtoll IOPRSTR GPIOASMEN LL_IOP_GRP1_ForceReset\n + * IOPRSTR GPIOBSMEN LL_IOP_GRP1_ForceReset\n + * IOPRSTR GPIOCSMEN LL_IOP_GRP1_ForceReset\n + * IOPRSTR GPIODSMEN LL_IOP_GRP1_ForceReset\n + * IOPRSTR GPIOESMEN LL_IOP_GRP1_ForceReset\n + * IOPRSTR GPIOHSMEN LL_IOP_GRP1_ForceReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_IOP_GRP1_PERIPH_ALL + * @arg @ref LL_IOP_GRP1_PERIPH_GPIOA + * @arg @ref LL_IOP_GRP1_PERIPH_GPIOB + * @arg @ref LL_IOP_GRP1_PERIPH_GPIOC + * @arg @ref LL_IOP_GRP1_PERIPH_GPIOD (*) + * @arg @ref LL_IOP_GRP1_PERIPH_GPIOE (*) + * @arg @ref LL_IOP_GRP1_PERIPH_GPIOH (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_IOP_GRP1_ForceReset(uint32_t Periphs) +{ + SET_BIT(RCC->IOPRSTR, Periphs); +} + +/** + * @brief Release IOP peripherals reset. + * @rmtoll IOPRSTR GPIOASMEN LL_IOP_GRP1_ReleaseReset\n + * IOPRSTR GPIOBSMEN LL_IOP_GRP1_ReleaseReset\n + * IOPRSTR GPIOCSMEN LL_IOP_GRP1_ReleaseReset\n + * IOPRSTR GPIODSMEN LL_IOP_GRP1_ReleaseReset\n + * IOPRSTR GPIOESMEN LL_IOP_GRP1_ReleaseReset\n + * IOPRSTR GPIOHSMEN LL_IOP_GRP1_ReleaseReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_IOP_GRP1_PERIPH_ALL + * @arg @ref LL_IOP_GRP1_PERIPH_GPIOA + * @arg @ref LL_IOP_GRP1_PERIPH_GPIOB + * @arg @ref LL_IOP_GRP1_PERIPH_GPIOC + * @arg @ref LL_IOP_GRP1_PERIPH_GPIOD (*) + * @arg @ref LL_IOP_GRP1_PERIPH_GPIOE (*) + * @arg @ref LL_IOP_GRP1_PERIPH_GPIOH (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_IOP_GRP1_ReleaseReset(uint32_t Periphs) +{ + CLEAR_BIT(RCC->IOPRSTR, Periphs); +} + +/** + * @brief Enable IOP peripherals clock during Low Power (Sleep) mode. + * @rmtoll IOPSMENR GPIOARST LL_IOP_GRP1_EnableClockSleep\n + * IOPSMENR GPIOBRST LL_IOP_GRP1_EnableClockSleep\n + * IOPSMENR GPIOCRST LL_IOP_GRP1_EnableClockSleep\n + * IOPSMENR GPIODRST LL_IOP_GRP1_EnableClockSleep\n + * IOPSMENR GPIOERST LL_IOP_GRP1_EnableClockSleep\n + * IOPSMENR GPIOHRST LL_IOP_GRP1_EnableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_IOP_GRP1_PERIPH_GPIOA + * @arg @ref LL_IOP_GRP1_PERIPH_GPIOB + * @arg @ref LL_IOP_GRP1_PERIPH_GPIOC + * @arg @ref LL_IOP_GRP1_PERIPH_GPIOD (*) + * @arg @ref LL_IOP_GRP1_PERIPH_GPIOE (*) + * @arg @ref LL_IOP_GRP1_PERIPH_GPIOH (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_IOP_GRP1_EnableClockSleep(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->IOPSMENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->IOPSMENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Disable IOP peripherals clock during Low Power (Sleep) mode. + * @rmtoll IOPSMENR GPIOARST LL_IOP_GRP1_DisableClockSleep\n + * IOPSMENR GPIOBRST LL_IOP_GRP1_DisableClockSleep\n + * IOPSMENR GPIOCRST LL_IOP_GRP1_DisableClockSleep\n + * IOPSMENR GPIODRST LL_IOP_GRP1_DisableClockSleep\n + * IOPSMENR GPIOERST LL_IOP_GRP1_DisableClockSleep\n + * IOPSMENR GPIOHRST LL_IOP_GRP1_DisableClockSleep + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_IOP_GRP1_PERIPH_GPIOA + * @arg @ref LL_IOP_GRP1_PERIPH_GPIOB + * @arg @ref LL_IOP_GRP1_PERIPH_GPIOC + * @arg @ref LL_IOP_GRP1_PERIPH_GPIOD (*) + * @arg @ref LL_IOP_GRP1_PERIPH_GPIOE (*) + * @arg @ref LL_IOP_GRP1_PERIPH_GPIOH (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_IOP_GRP1_DisableClockSleep(uint32_t Periphs) +{ + CLEAR_BIT(RCC->IOPSMENR, Periphs); +} + +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined(RCC) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32L0xx_LL_BUS_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/fw/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h b/fw/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h new file mode 100644 index 0000000..cb015f3 --- /dev/null +++ b/fw/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h @@ -0,0 +1,590 @@ +/** + ****************************************************************************** + * @file stm32l0xx_ll_cortex.h + * @author MCD Application Team + * @brief Header file of CORTEX LL module. + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The LL CORTEX driver contains a set of generic APIs that can be + used by user: + (+) SYSTICK configuration used by @ref LL_mDelay and @ref LL_Init1msTick + functions + (+) Low power mode configuration (SCB register of Cortex-MCU) + (+) MPU API to configure and enable regions + (+) API to access to MCU info (CPUID register) + + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright(c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32L0xx_LL_CORTEX_H +#define __STM32L0xx_LL_CORTEX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l0xx.h" + +/** @addtogroup STM32L0xx_LL_Driver + * @{ + */ + +/** @defgroup CORTEX_LL CORTEX + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ + +/* Private macros ------------------------------------------------------------*/ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup CORTEX_LL_Exported_Constants CORTEX Exported Constants + * @{ + */ + +/** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source + * @{ + */ +#define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 (0x00000000U) /*!< AHB clock divided by 8 selected as SysTick clock source.*/ +#define LL_SYSTICK_CLKSOURCE_HCLK (SysTick_CTRL_CLKSOURCE_Msk) /*!< AHB clock selected as SysTick clock source. */ +/** + * @} + */ + +#if __MPU_PRESENT + +/** @defgroup CORTEX_LL_EC_CTRL_HFNMI_PRIVDEF MPU Control + * @{ + */ +#define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE (0x00000000U) /*!< Disable NMI and privileged SW access */ +#define LL_MPU_CTRL_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk /*!< Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers */ +#define LL_MPU_CTRL_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk /*!< Enable privileged software access to default memory map */ +#define LL_MPU_CTRL_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) /*!< Enable NMI and privileged SW access */ +/** + * @} + */ + +/** @defgroup CORTEX_LL_EC_REGION MPU Region Number + * @{ + */ +#define LL_MPU_REGION_NUMBER0 (0x00U) /*!< REGION Number 0 */ +#define LL_MPU_REGION_NUMBER1 (0x01U) /*!< REGION Number 1 */ +#define LL_MPU_REGION_NUMBER2 (0x02U) /*!< REGION Number 2 */ +#define LL_MPU_REGION_NUMBER3 (0x03U) /*!< REGION Number 3 */ +#define LL_MPU_REGION_NUMBER4 (0x04U) /*!< REGION Number 4 */ +#define LL_MPU_REGION_NUMBER5 (0x05U) /*!< REGION Number 5 */ +#define LL_MPU_REGION_NUMBER6 (0x06U) /*!< REGION Number 6 */ +#define LL_MPU_REGION_NUMBER7 (0x07U) /*!< REGION Number 7 */ +/** + * @} + */ + +/** @defgroup CORTEX_LL_EC_REGION_SIZE MPU Region Size + * @{ + */ +#define LL_MPU_REGION_SIZE_32B ((uint32_t)(0x04U << MPU_RASR_SIZE_Pos)) /*!< 32B Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_64B ((uint32_t)(0x05U << MPU_RASR_SIZE_Pos)) /*!< 64B Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_128B ((uint32_t)(0x06U << MPU_RASR_SIZE_Pos)) /*!< 128B Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_256B ((uint32_t)(0x07U << MPU_RASR_SIZE_Pos)) /*!< 256B Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_512B ((uint32_t)(0x08U << MPU_RASR_SIZE_Pos)) /*!< 512B Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_1KB ((uint32_t)(0x09U << MPU_RASR_SIZE_Pos)) /*!< 1KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_2KB ((uint32_t)(0x0AU << MPU_RASR_SIZE_Pos)) /*!< 2KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_4KB ((uint32_t)(0x0BU << MPU_RASR_SIZE_Pos)) /*!< 4KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_8KB ((uint32_t)(0x0CU << MPU_RASR_SIZE_Pos)) /*!< 8KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_16KB ((uint32_t)(0x0DU << MPU_RASR_SIZE_Pos)) /*!< 16KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_32KB ((uint32_t)(0x0EU << MPU_RASR_SIZE_Pos)) /*!< 32KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_64KB ((uint32_t)(0x0FU << MPU_RASR_SIZE_Pos)) /*!< 64KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_128KB ((uint32_t)(0x10U << MPU_RASR_SIZE_Pos)) /*!< 128KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_256KB ((uint32_t)(0x11U << MPU_RASR_SIZE_Pos)) /*!< 256KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_512KB ((uint32_t)(0x12U << MPU_RASR_SIZE_Pos)) /*!< 512KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_1MB ((uint32_t)(0x13U << MPU_RASR_SIZE_Pos)) /*!< 1MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_2MB ((uint32_t)(0x14U << MPU_RASR_SIZE_Pos)) /*!< 2MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_4MB ((uint32_t)(0x15U << MPU_RASR_SIZE_Pos)) /*!< 4MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_8MB ((uint32_t)(0x16U << MPU_RASR_SIZE_Pos)) /*!< 8MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_16MB ((uint32_t)(0x17U << MPU_RASR_SIZE_Pos)) /*!< 16MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_32MB ((uint32_t)(0x18U << MPU_RASR_SIZE_Pos)) /*!< 32MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_64MB ((uint32_t)(0x19U << MPU_RASR_SIZE_Pos)) /*!< 64MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_128MB ((uint32_t)(0x1AU << MPU_RASR_SIZE_Pos)) /*!< 128MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_256MB ((uint32_t)(0x1BU << MPU_RASR_SIZE_Pos)) /*!< 256MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_512MB ((uint32_t)(0x1CU << MPU_RASR_SIZE_Pos)) /*!< 512MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_1GB ((uint32_t)(0x1DU << MPU_RASR_SIZE_Pos)) /*!< 1GB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_2GB ((uint32_t)(0x1EU << MPU_RASR_SIZE_Pos)) /*!< 2GB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_4GB ((uint32_t)(0x1FU << MPU_RASR_SIZE_Pos)) /*!< 4GB Size of the MPU protection region */ +/** + * @} + */ + +/** @defgroup CORTEX_LL_EC_REGION_PRIVILEDGES MPU Region Privileges + * @{ + */ +#define LL_MPU_REGION_NO_ACCESS ((uint32_t)(0x00U << MPU_RASR_AP_Pos)) /*!< No access*/ +#define LL_MPU_REGION_PRIV_RW ((uint32_t)(0x01U << MPU_RASR_AP_Pos)) /*!< RW privileged (privileged access only)*/ +#define LL_MPU_REGION_PRIV_RW_URO ((uint32_t)(0x02U << MPU_RASR_AP_Pos)) /*!< RW privileged - RO user (Write in a user program generates a fault) */ +#define LL_MPU_REGION_FULL_ACCESS ((uint32_t)(0x03U << MPU_RASR_AP_Pos)) /*!< RW privileged & user (Full access) */ +#define LL_MPU_REGION_PRIV_RO ((uint32_t)(0x05U << MPU_RASR_AP_Pos)) /*!< RO privileged (privileged read only)*/ +#define LL_MPU_REGION_PRIV_RO_URO ((uint32_t)(0x06U << MPU_RASR_AP_Pos)) /*!< RO privileged & user (read only) */ +/** + * @} + */ + +/** @defgroup CORTEX_LL_EC_TEX MPU TEX Level + * @{ + */ +#define LL_MPU_TEX_LEVEL0 ((uint32_t)(0x00U << MPU_RASR_TEX_Pos)) /*!< b000 for TEX bits */ +#define LL_MPU_TEX_LEVEL1 ((uint32_t)(0x01U << MPU_RASR_TEX_Pos)) /*!< b001 for TEX bits */ +#define LL_MPU_TEX_LEVEL2 ((uint32_t)(0x02U << MPU_RASR_TEX_Pos)) /*!< b010 for TEX bits */ +#define LL_MPU_TEX_LEVEL4 ((uint32_t)(0x04U << MPU_RASR_TEX_Pos)) /*!< b100 for TEX bits */ +/** + * @} + */ + +/** @defgroup CORTEX_LL_EC_INSTRUCTION_ACCESS MPU Instruction Access + * @{ + */ +#define LL_MPU_INSTRUCTION_ACCESS_ENABLE (0x00U) /*!< Instruction fetches enabled */ +#define LL_MPU_INSTRUCTION_ACCESS_DISABLE MPU_RASR_XN_Msk /*!< Instruction fetches disabled*/ +/** + * @} + */ + +/** @defgroup CORTEX_LL_EC_SHAREABLE_ACCESS MPU Shareable Access + * @{ + */ +#define LL_MPU_ACCESS_SHAREABLE MPU_RASR_S_Msk /*!< Shareable memory attribute */ +#define LL_MPU_ACCESS_NOT_SHAREABLE (0x00U) /*!< Not Shareable memory attribute */ +/** + * @} + */ + +/** @defgroup CORTEX_LL_EC_CACHEABLE_ACCESS MPU Cacheable Access + * @{ + */ +#define LL_MPU_ACCESS_CACHEABLE MPU_RASR_C_Msk /*!< Cacheable memory attribute */ +#define LL_MPU_ACCESS_NOT_CACHEABLE (0x00U) /*!< Not Cacheable memory attribute */ +/** + * @} + */ + +/** @defgroup CORTEX_LL_EC_BUFFERABLE_ACCESS MPU Bufferable Access + * @{ + */ +#define LL_MPU_ACCESS_BUFFERABLE MPU_RASR_B_Msk /*!< Bufferable memory attribute */ +#define LL_MPU_ACCESS_NOT_BUFFERABLE (0x00U) /*!< Not Bufferable memory attribute */ +/** + * @} + */ +#endif /* __MPU_PRESENT */ +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup CORTEX_LL_Exported_Functions CORTEX Exported Functions + * @{ + */ + +/** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK + * @{ + */ + +/** + * @brief This function checks if the Systick counter flag is active or not. + * @note It can be used in timeout function on application side. + * @rmtoll STK_CTRL COUNTFLAG LL_SYSTICK_IsActiveCounterFlag + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void) +{ + return ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk)); +} + +/** + * @brief Configures the SysTick clock source + * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_SetClkSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8 + * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK + * @retval None + */ +__STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source) +{ + if (Source == LL_SYSTICK_CLKSOURCE_HCLK) + { + SET_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK); + } + else + { + CLEAR_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK); + } +} + +/** + * @brief Get the SysTick clock source + * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_GetClkSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8 + * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK + */ +__STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void) +{ + return READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK); +} + +/** + * @brief Enable SysTick exception request + * @rmtoll STK_CTRL TICKINT LL_SYSTICK_EnableIT + * @retval None + */ +__STATIC_INLINE void LL_SYSTICK_EnableIT(void) +{ + SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); +} + +/** + * @brief Disable SysTick exception request + * @rmtoll STK_CTRL TICKINT LL_SYSTICK_DisableIT + * @retval None + */ +__STATIC_INLINE void LL_SYSTICK_DisableIT(void) +{ + CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); +} + +/** + * @brief Checks if the SYSTICK interrupt is enabled or disabled. + * @rmtoll STK_CTRL TICKINT LL_SYSTICK_IsEnabledIT + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void) +{ + return (READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk)); +} + +/** + * @} + */ + +/** @defgroup CORTEX_LL_EF_LOW_POWER_MODE LOW POWER MODE + * @{ + */ + +/** + * @brief Processor uses sleep as its low power mode + * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableSleep + * @retval None + */ +__STATIC_INLINE void LL_LPM_EnableSleep(void) +{ + /* Clear SLEEPDEEP bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); +} + +/** + * @brief Processor uses deep sleep as its low power mode + * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableDeepSleep + * @retval None + */ +__STATIC_INLINE void LL_LPM_EnableDeepSleep(void) +{ + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); +} + +/** + * @brief Configures sleep-on-exit when returning from Handler mode to Thread mode. + * @note Setting this bit to 1 enables an interrupt-driven application to avoid returning to an + * empty main application. + * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_EnableSleepOnExit + * @retval None + */ +__STATIC_INLINE void LL_LPM_EnableSleepOnExit(void) +{ + /* Set SLEEPONEXIT bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); +} + +/** + * @brief Do not sleep when returning to Thread mode. + * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_DisableSleepOnExit + * @retval None + */ +__STATIC_INLINE void LL_LPM_DisableSleepOnExit(void) +{ + /* Clear SLEEPONEXIT bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); +} + +/** + * @brief Enabled events and all interrupts, including disabled interrupts, can wakeup the + * processor. + * @rmtoll SCB_SCR SEVEONPEND LL_LPM_EnableEventOnPend + * @retval None + */ +__STATIC_INLINE void LL_LPM_EnableEventOnPend(void) +{ + /* Set SEVEONPEND bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); +} + +/** + * @brief Only enabled interrupts or events can wakeup the processor, disabled interrupts are + * excluded + * @rmtoll SCB_SCR SEVEONPEND LL_LPM_DisableEventOnPend + * @retval None + */ +__STATIC_INLINE void LL_LPM_DisableEventOnPend(void) +{ + /* Clear SEVEONPEND bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); +} + +/** + * @} + */ + +/** @defgroup CORTEX_LL_EF_MCU_INFO MCU INFO + * @{ + */ + +/** + * @brief Get Implementer code + * @rmtoll SCB_CPUID IMPLEMENTER LL_CPUID_GetImplementer + * @retval Value should be equal to 0x41 for ARM + */ +__STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void) +{ + return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos); +} + +/** + * @brief Get Variant number (The r value in the rnpn product revision identifier) + * @rmtoll SCB_CPUID VARIANT LL_CPUID_GetVariant + * @retval Value between 0 and 255 (0x0: revision 0) + */ +__STATIC_INLINE uint32_t LL_CPUID_GetVariant(void) +{ + return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos); +} + +/** + * @brief Get Architecture number + * @rmtoll SCB_CPUID ARCHITECTURE LL_CPUID_GetArchitecture + * @retval Value should be equal to 0xC for Cortex-M0+ devices + */ +__STATIC_INLINE uint32_t LL_CPUID_GetArchitecture(void) +{ + return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos); +} + +/** + * @brief Get Part number + * @rmtoll SCB_CPUID PARTNO LL_CPUID_GetParNo + * @retval Value should be equal to 0xC60 for Cortex-M0+ + */ +__STATIC_INLINE uint32_t LL_CPUID_GetParNo(void) +{ + return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos); +} + +/** + * @brief Get Revision number (The p value in the rnpn product revision identifier, indicates patch release) + * @rmtoll SCB_CPUID REVISION LL_CPUID_GetRevision + * @retval Value between 0 and 255 (0x1: patch 1) + */ +__STATIC_INLINE uint32_t LL_CPUID_GetRevision(void) +{ + return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos); +} + +/** + * @} + */ + +#if __MPU_PRESENT +/** @defgroup CORTEX_LL_EF_MPU MPU + * @{ + */ + +/** + * @brief Enable MPU with input options + * @rmtoll MPU_CTRL ENABLE LL_MPU_Enable + * @param Options This parameter can be one of the following values: + * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE + * @arg @ref LL_MPU_CTRL_HARDFAULT_NMI + * @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT + * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF + * @retval None + */ +__STATIC_INLINE void LL_MPU_Enable(uint32_t Options) +{ + /* Enable the MPU*/ + WRITE_REG(MPU->CTRL, (MPU_CTRL_ENABLE_Msk | Options)); + /* Ensure MPU settings take effects */ + __DSB(); + /* Sequence instruction fetches using update settings */ + __ISB(); +} + +/** + * @brief Disable MPU + * @rmtoll MPU_CTRL ENABLE LL_MPU_Disable + * @retval None + */ +__STATIC_INLINE void LL_MPU_Disable(void) +{ + /* Make sure outstanding transfers are done */ + __DMB(); + /* Disable MPU*/ + WRITE_REG(MPU->CTRL, 0U); +} + +/** + * @brief Check if MPU is enabled or not + * @rmtoll MPU_CTRL ENABLE LL_MPU_IsEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_MPU_IsEnabled(void) +{ + return (READ_BIT(MPU->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk)); +} + +/** + * @brief Enable a MPU region + * @rmtoll MPU_RASR ENABLE LL_MPU_EnableRegion + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @retval None + */ +__STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region) +{ + /* Set Region number */ + WRITE_REG(MPU->RNR, Region); + /* Enable the MPU region */ + SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk); +} + +/** + * @brief Configure and enable a region + * @rmtoll MPU_RNR REGION LL_MPU_ConfigRegion\n + * MPU_RBAR REGION LL_MPU_ConfigRegion\n + * MPU_RBAR ADDR LL_MPU_ConfigRegion\n + * MPU_RASR XN LL_MPU_ConfigRegion\n + * MPU_RASR AP LL_MPU_ConfigRegion\n + * MPU_RASR S LL_MPU_ConfigRegion\n + * MPU_RASR C LL_MPU_ConfigRegion\n + * MPU_RASR B LL_MPU_ConfigRegion\n + * MPU_RASR SIZE LL_MPU_ConfigRegion + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @param Address Value of region base address + * @param SubRegionDisable Sub-region disable value between Min_Data = 0x00 and Max_Data = 0xFF + * @param Attributes This parameter can be a combination of the following values: + * @arg @ref LL_MPU_REGION_SIZE_32B or @ref LL_MPU_REGION_SIZE_64B or @ref LL_MPU_REGION_SIZE_128B or @ref LL_MPU_REGION_SIZE_256B or @ref LL_MPU_REGION_SIZE_512B + * or @ref LL_MPU_REGION_SIZE_1KB or @ref LL_MPU_REGION_SIZE_2KB or @ref LL_MPU_REGION_SIZE_4KB or @ref LL_MPU_REGION_SIZE_8KB or @ref LL_MPU_REGION_SIZE_16KB + * or @ref LL_MPU_REGION_SIZE_32KB or @ref LL_MPU_REGION_SIZE_64KB or @ref LL_MPU_REGION_SIZE_128KB or @ref LL_MPU_REGION_SIZE_256KB or @ref LL_MPU_REGION_SIZE_512KB + * or @ref LL_MPU_REGION_SIZE_1MB or @ref LL_MPU_REGION_SIZE_2MB or @ref LL_MPU_REGION_SIZE_4MB or @ref LL_MPU_REGION_SIZE_8MB or @ref LL_MPU_REGION_SIZE_16MB + * or @ref LL_MPU_REGION_SIZE_32MB or @ref LL_MPU_REGION_SIZE_64MB or @ref LL_MPU_REGION_SIZE_128MB or @ref LL_MPU_REGION_SIZE_256MB or @ref LL_MPU_REGION_SIZE_512MB + * or @ref LL_MPU_REGION_SIZE_1GB or @ref LL_MPU_REGION_SIZE_2GB or @ref LL_MPU_REGION_SIZE_4GB + * @arg @ref LL_MPU_REGION_NO_ACCESS or @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_PRIV_RW_URO or @ref LL_MPU_REGION_FULL_ACCESS + * or @ref LL_MPU_REGION_PRIV_RO or @ref LL_MPU_REGION_PRIV_RO_URO + * @arg @ref LL_MPU_TEX_LEVEL0 or @ref LL_MPU_TEX_LEVEL1 or @ref LL_MPU_TEX_LEVEL2 or @ref LL_MPU_TEX_LEVEL4 + * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE + * @arg @ref LL_MPU_ACCESS_SHAREABLE or @ref LL_MPU_ACCESS_NOT_SHAREABLE + * @arg @ref LL_MPU_ACCESS_CACHEABLE or @ref LL_MPU_ACCESS_NOT_CACHEABLE + * @arg @ref LL_MPU_ACCESS_BUFFERABLE or @ref LL_MPU_ACCESS_NOT_BUFFERABLE + * @retval None + */ +__STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t SubRegionDisable, uint32_t Address, uint32_t Attributes) +{ + /* Set Region number */ + WRITE_REG(MPU->RNR, Region); + /* Set base address */ + WRITE_REG(MPU->RBAR, (Address & 0xFFFFFFE0U)); + /* Configure MPU */ + WRITE_REG(MPU->RASR, (MPU_RASR_ENABLE_Msk | Attributes | SubRegionDisable << MPU_RASR_SRD_Pos)); +} + +/** + * @brief Disable a region + * @rmtoll MPU_RNR REGION LL_MPU_DisableRegion\n + * MPU_RASR ENABLE LL_MPU_DisableRegion + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @retval None + */ +__STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region) +{ + /* Set Region number */ + WRITE_REG(MPU->RNR, Region); + /* Disable the MPU region */ + CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk); +} + +/** + * @} + */ + +#endif /* __MPU_PRESENT */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32L0xx_LL_CORTEX_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/fw/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_crs.h b/fw/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_crs.h new file mode 100644 index 0000000..8cfbd08 --- /dev/null +++ b/fw/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_crs.h @@ -0,0 +1,798 @@ +/** + ****************************************************************************** + * @file stm32l0xx_ll_crs.h + * @author MCD Application Team + * @brief Header file of CRS LL module. + ****************************************************************************** + * @attention + * + *

© Copyright(c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32L0xx_LL_CRS_H +#define __STM32L0xx_LL_CRS_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l0xx.h" + +/** @addtogroup STM32L0xx_LL_Driver + * @{ + */ + +#if defined(CRS) + +/** @defgroup CRS_LL CRS + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup CRS_LL_Private_Constants CRS Private Constants + * @{ + */ + +/* Defines used for the bit position in the register and perform offsets*/ +#define CRS_POSITION_TRIM (CRS_CR_TRIM_Pos) /* bit position in CR reg */ +#define CRS_POSITION_FECAP (CRS_ISR_FECAP_Pos) /* bit position in ISR reg */ +#define CRS_POSITION_FELIM (CRS_CFGR_FELIM_Pos) /* bit position in CFGR reg */ + + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup CRS_LL_Exported_Constants CRS Exported Constants + * @{ + */ + +/** @defgroup CRS_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_CRS_ReadReg function + * @{ + */ +#define LL_CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF +#define LL_CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF +#define LL_CRS_ISR_ERRF CRS_ISR_ERRF +#define LL_CRS_ISR_ESYNCF CRS_ISR_ESYNCF +#define LL_CRS_ISR_SYNCERR CRS_ISR_SYNCERR +#define LL_CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS +#define LL_CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF +/** + * @} + */ + +/** @defgroup CRS_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_CRS_ReadReg and LL_CRS_WriteReg functions + * @{ + */ +#define LL_CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE +#define LL_CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE +#define LL_CRS_CR_ERRIE CRS_CR_ERRIE +#define LL_CRS_CR_ESYNCIE CRS_CR_ESYNCIE +/** + * @} + */ + +/** @defgroup CRS_LL_EC_SYNC_DIV Synchronization Signal Divider + * @{ + */ +#define LL_CRS_SYNC_DIV_1 (0x00U) /*!< Synchro Signal not divided (default) */ +#define LL_CRS_SYNC_DIV_2 CRS_CFGR_SYNCDIV_0 /*!< Synchro Signal divided by 2 */ +#define LL_CRS_SYNC_DIV_4 CRS_CFGR_SYNCDIV_1 /*!< Synchro Signal divided by 4 */ +#define LL_CRS_SYNC_DIV_8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */ +#define LL_CRS_SYNC_DIV_16 CRS_CFGR_SYNCDIV_2 /*!< Synchro Signal divided by 16 */ +#define LL_CRS_SYNC_DIV_32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */ +#define LL_CRS_SYNC_DIV_64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */ +#define LL_CRS_SYNC_DIV_128 CRS_CFGR_SYNCDIV /*!< Synchro Signal divided by 128 */ +/** + * @} + */ + +/** @defgroup CRS_LL_EC_SYNC_SOURCE Synchronization Signal Source + * @{ + */ +#define LL_CRS_SYNC_SOURCE_GPIO (0x00U) /*!< Synchro Signal soucre GPIO */ +#define LL_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */ +#define LL_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF (default)*/ +/** + * @} + */ + +/** @defgroup CRS_LL_EC_SYNC_POLARITY Synchronization Signal Polarity + * @{ + */ +#define LL_CRS_SYNC_POLARITY_RISING (0x00U) /*!< Synchro Active on rising edge (default) */ +#define LL_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */ +/** + * @} + */ + +/** @defgroup CRS_LL_EC_FREQERRORDIR Frequency Error Direction + * @{ + */ +#define LL_CRS_FREQ_ERROR_DIR_UP (0x00U) /*!< Upcounting direction, the actual frequency is above the target */ +#define LL_CRS_FREQ_ERROR_DIR_DOWN CRS_ISR_FEDIR /*!< Downcounting direction, the actual frequency is below the target */ +/** + * @} + */ + +/** @defgroup CRS_LL_EC_DEFAULTVALUES Default Values + * @{ + */ +/** + * @brief Reset value of the RELOAD field + * @note The reset value of the RELOAD field corresponds to a target frequency of 48 MHz + * and a synchronization signal frequency of 1 kHz (SOF signal from USB) + */ +#define LL_CRS_RELOADVALUE_DEFAULT (0xBB7FU) + +/** + * @brief Reset value of Frequency error limit. + */ +#define LL_CRS_ERRORLIMIT_DEFAULT (0x22U) + +/** + * @brief Reset value of the HSI48 Calibration field + * @note The default value is 32, which corresponds to the middle of the trimming interval. + * The trimming step is around 67 kHz between two consecutive TRIM steps. + * A higher TRIM value corresponds to a higher output frequency + */ +#define LL_CRS_HSI48CALIBRATION_DEFAULT (0x20U) +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup CRS_LL_Exported_Macros CRS Exported Macros + * @{ + */ + +/** @defgroup CRS_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in CRS register + * @param __INSTANCE__ CRS Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_CRS_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in CRS register + * @param __INSTANCE__ CRS Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_CRS_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** @defgroup CRS_LL_EM_Exported_Macros_Calculate_Reload Exported_Macros_Calculate_Reload + * @{ + */ + +/** + * @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies + * @note The RELOAD value should be selected according to the ratio between + * the target frequency and the frequency of the synchronization source after + * prescaling. It is then decreased by one in order to reach the expected + * synchronization on the zero value. The formula is the following: + * RELOAD = (fTARGET / fSYNC) -1 + * @param __FTARGET__ Target frequency (value in Hz) + * @param __FSYNC__ Synchronization signal frequency (value in Hz) + * @retval Reload value (in Hz) + */ +#define __LL_CRS_CALC_CALCULATE_RELOADVALUE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup CRS_LL_Exported_Functions CRS Exported Functions + * @{ + */ + +/** @defgroup CRS_LL_EF_Configuration Configuration + * @{ + */ + +/** + * @brief Enable Frequency error counter + * @note When this bit is set, the CRS_CFGR register is write-protected and cannot be modified + * @rmtoll CR CEN LL_CRS_EnableFreqErrorCounter + * @retval None + */ +__STATIC_INLINE void LL_CRS_EnableFreqErrorCounter(void) +{ + SET_BIT(CRS->CR, CRS_CR_CEN); +} + +/** + * @brief Disable Frequency error counter + * @rmtoll CR CEN LL_CRS_DisableFreqErrorCounter + * @retval None + */ +__STATIC_INLINE void LL_CRS_DisableFreqErrorCounter(void) +{ + CLEAR_BIT(CRS->CR, CRS_CR_CEN); +} + +/** + * @brief Check if Frequency error counter is enabled or not + * @rmtoll CR CEN LL_CRS_IsEnabledFreqErrorCounter + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsEnabledFreqErrorCounter(void) +{ + return (READ_BIT(CRS->CR, CRS_CR_CEN) == (CRS_CR_CEN)); +} + +/** + * @brief Enable Automatic trimming counter + * @rmtoll CR AUTOTRIMEN LL_CRS_EnableAutoTrimming + * @retval None + */ +__STATIC_INLINE void LL_CRS_EnableAutoTrimming(void) +{ + SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN); +} + +/** + * @brief Disable Automatic trimming counter + * @rmtoll CR AUTOTRIMEN LL_CRS_DisableAutoTrimming + * @retval None + */ +__STATIC_INLINE void LL_CRS_DisableAutoTrimming(void) +{ + CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN); +} + +/** + * @brief Check if Automatic trimming is enabled or not + * @rmtoll CR AUTOTRIMEN LL_CRS_IsEnabledAutoTrimming + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsEnabledAutoTrimming(void) +{ + return (READ_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) == (CRS_CR_AUTOTRIMEN)); +} + +/** + * @brief Set HSI48 oscillator smooth trimming + * @note When the AUTOTRIMEN bit is set, this field is controlled by hardware and is read-only + * @rmtoll CR TRIM LL_CRS_SetHSI48SmoothTrimming + * @param Value a number between Min_Data = 0 and Max_Data = 63 + * @note Default value can be set thanks to @ref LL_CRS_HSI48CALIBRATION_DEFAULT + * @retval None + */ +__STATIC_INLINE void LL_CRS_SetHSI48SmoothTrimming(uint32_t Value) +{ + MODIFY_REG(CRS->CR, CRS_CR_TRIM, Value << CRS_POSITION_TRIM); +} + +/** + * @brief Get HSI48 oscillator smooth trimming + * @rmtoll CR TRIM LL_CRS_GetHSI48SmoothTrimming + * @retval a number between Min_Data = 0 and Max_Data = 63 + */ +__STATIC_INLINE uint32_t LL_CRS_GetHSI48SmoothTrimming(void) +{ + return (uint32_t)(READ_BIT(CRS->CR, CRS_CR_TRIM) >> CRS_POSITION_TRIM); +} + +/** + * @brief Set counter reload value + * @rmtoll CFGR RELOAD LL_CRS_SetReloadCounter + * @param Value a number between Min_Data = 0 and Max_Data = 0xFFFF + * @note Default value can be set thanks to @ref LL_CRS_RELOADVALUE_DEFAULT + * Otherwise it can be calculated in using macro @ref __LL_CRS_CALC_CALCULATE_RELOADVALUE (_FTARGET_, _FSYNC_) + * @retval None + */ +__STATIC_INLINE void LL_CRS_SetReloadCounter(uint32_t Value) +{ + MODIFY_REG(CRS->CFGR, CRS_CFGR_RELOAD, Value); +} + +/** + * @brief Get counter reload value + * @rmtoll CFGR RELOAD LL_CRS_GetReloadCounter + * @retval a number between Min_Data = 0 and Max_Data = 0xFFFF + */ +__STATIC_INLINE uint32_t LL_CRS_GetReloadCounter(void) +{ + return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD)); +} + +/** + * @brief Set frequency error limit + * @rmtoll CFGR FELIM LL_CRS_SetFreqErrorLimit + * @param Value a number between Min_Data = 0 and Max_Data = 255 + * @note Default value can be set thanks to @ref LL_CRS_ERRORLIMIT_DEFAULT + * @retval None + */ +__STATIC_INLINE void LL_CRS_SetFreqErrorLimit(uint32_t Value) +{ + MODIFY_REG(CRS->CFGR, CRS_CFGR_FELIM, Value << CRS_POSITION_FELIM); +} + +/** + * @brief Get frequency error limit + * @rmtoll CFGR FELIM LL_CRS_GetFreqErrorLimit + * @retval A number between Min_Data = 0 and Max_Data = 255 + */ +__STATIC_INLINE uint32_t LL_CRS_GetFreqErrorLimit(void) +{ + return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_FELIM) >> CRS_POSITION_FELIM); +} + +/** + * @brief Set division factor for SYNC signal + * @rmtoll CFGR SYNCDIV LL_CRS_SetSyncDivider + * @param Divider This parameter can be one of the following values: + * @arg @ref LL_CRS_SYNC_DIV_1 + * @arg @ref LL_CRS_SYNC_DIV_2 + * @arg @ref LL_CRS_SYNC_DIV_4 + * @arg @ref LL_CRS_SYNC_DIV_8 + * @arg @ref LL_CRS_SYNC_DIV_16 + * @arg @ref LL_CRS_SYNC_DIV_32 + * @arg @ref LL_CRS_SYNC_DIV_64 + * @arg @ref LL_CRS_SYNC_DIV_128 + * @retval None + */ +__STATIC_INLINE void LL_CRS_SetSyncDivider(uint32_t Divider) +{ + MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCDIV, Divider); +} + +/** + * @brief Get division factor for SYNC signal + * @rmtoll CFGR SYNCDIV LL_CRS_GetSyncDivider + * @retval Returned value can be one of the following values: + * @arg @ref LL_CRS_SYNC_DIV_1 + * @arg @ref LL_CRS_SYNC_DIV_2 + * @arg @ref LL_CRS_SYNC_DIV_4 + * @arg @ref LL_CRS_SYNC_DIV_8 + * @arg @ref LL_CRS_SYNC_DIV_16 + * @arg @ref LL_CRS_SYNC_DIV_32 + * @arg @ref LL_CRS_SYNC_DIV_64 + * @arg @ref LL_CRS_SYNC_DIV_128 + */ +__STATIC_INLINE uint32_t LL_CRS_GetSyncDivider(void) +{ + return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCDIV)); +} + +/** + * @brief Set SYNC signal source + * @rmtoll CFGR SYNCSRC LL_CRS_SetSyncSignalSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_CRS_SYNC_SOURCE_GPIO + * @arg @ref LL_CRS_SYNC_SOURCE_LSE + * @arg @ref LL_CRS_SYNC_SOURCE_USB + * @retval None + */ +__STATIC_INLINE void LL_CRS_SetSyncSignalSource(uint32_t Source) +{ + MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCSRC, Source); +} + +/** + * @brief Get SYNC signal source + * @rmtoll CFGR SYNCSRC LL_CRS_GetSyncSignalSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_CRS_SYNC_SOURCE_GPIO + * @arg @ref LL_CRS_SYNC_SOURCE_LSE + * @arg @ref LL_CRS_SYNC_SOURCE_USB + */ +__STATIC_INLINE uint32_t LL_CRS_GetSyncSignalSource(void) +{ + return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCSRC)); +} + +/** + * @brief Set input polarity for the SYNC signal source + * @rmtoll CFGR SYNCPOL LL_CRS_SetSyncPolarity + * @param Polarity This parameter can be one of the following values: + * @arg @ref LL_CRS_SYNC_POLARITY_RISING + * @arg @ref LL_CRS_SYNC_POLARITY_FALLING + * @retval None + */ +__STATIC_INLINE void LL_CRS_SetSyncPolarity(uint32_t Polarity) +{ + MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCPOL, Polarity); +} + +/** + * @brief Get input polarity for the SYNC signal source + * @rmtoll CFGR SYNCPOL LL_CRS_GetSyncPolarity + * @retval Returned value can be one of the following values: + * @arg @ref LL_CRS_SYNC_POLARITY_RISING + * @arg @ref LL_CRS_SYNC_POLARITY_FALLING + */ +__STATIC_INLINE uint32_t LL_CRS_GetSyncPolarity(void) +{ + return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCPOL)); +} + +/** + * @brief Configure CRS for the synchronization + * @rmtoll CR TRIM LL_CRS_ConfigSynchronization\n + * CFGR RELOAD LL_CRS_ConfigSynchronization\n + * CFGR FELIM LL_CRS_ConfigSynchronization\n + * CFGR SYNCDIV LL_CRS_ConfigSynchronization\n + * CFGR SYNCSRC LL_CRS_ConfigSynchronization\n + * CFGR SYNCPOL LL_CRS_ConfigSynchronization + * @param HSI48CalibrationValue a number between Min_Data = 0 and Max_Data = 63 + * @param ErrorLimitValue a number between Min_Data = 0 and Max_Data = 0xFFFF + * @param ReloadValue a number between Min_Data = 0 and Max_Data = 255 + * @param Settings This parameter can be a combination of the following values: + * @arg @ref LL_CRS_SYNC_DIV_1 or @ref LL_CRS_SYNC_DIV_2 or @ref LL_CRS_SYNC_DIV_4 or @ref LL_CRS_SYNC_DIV_8 + * or @ref LL_CRS_SYNC_DIV_16 or @ref LL_CRS_SYNC_DIV_32 or @ref LL_CRS_SYNC_DIV_64 or @ref LL_CRS_SYNC_DIV_128 + * @arg @ref LL_CRS_SYNC_SOURCE_GPIO or @ref LL_CRS_SYNC_SOURCE_LSE or @ref LL_CRS_SYNC_SOURCE_USB + * @arg @ref LL_CRS_SYNC_POLARITY_RISING or @ref LL_CRS_SYNC_POLARITY_FALLING + * @retval None + */ +__STATIC_INLINE void LL_CRS_ConfigSynchronization(uint32_t HSI48CalibrationValue, uint32_t ErrorLimitValue, uint32_t ReloadValue, uint32_t Settings) +{ + MODIFY_REG(CRS->CR, CRS_CR_TRIM, HSI48CalibrationValue); + MODIFY_REG(CRS->CFGR, + CRS_CFGR_RELOAD | CRS_CFGR_FELIM | CRS_CFGR_SYNCDIV | CRS_CFGR_SYNCSRC | CRS_CFGR_SYNCPOL, + ReloadValue | (ErrorLimitValue << CRS_POSITION_FELIM) | Settings); +} + +/** + * @} + */ + +/** @defgroup CRS_LL_EF_CRS_Management CRS_Management + * @{ + */ + +/** + * @brief Generate software SYNC event + * @rmtoll CR SWSYNC LL_CRS_GenerateEvent_SWSYNC + * @retval None + */ +__STATIC_INLINE void LL_CRS_GenerateEvent_SWSYNC(void) +{ + SET_BIT(CRS->CR, CRS_CR_SWSYNC); +} + +/** + * @brief Get the frequency error direction latched in the time of the last + * SYNC event + * @rmtoll ISR FEDIR LL_CRS_GetFreqErrorDirection + * @retval Returned value can be one of the following values: + * @arg @ref LL_CRS_FREQ_ERROR_DIR_UP + * @arg @ref LL_CRS_FREQ_ERROR_DIR_DOWN + */ +__STATIC_INLINE uint32_t LL_CRS_GetFreqErrorDirection(void) +{ + return (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FEDIR)); +} + +/** + * @brief Get the frequency error counter value latched in the time of the last SYNC event + * @rmtoll ISR FECAP LL_CRS_GetFreqErrorCapture + * @retval A number between Min_Data = 0x0000 and Max_Data = 0xFFFF + */ +__STATIC_INLINE uint32_t LL_CRS_GetFreqErrorCapture(void) +{ + return (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> CRS_POSITION_FECAP); +} + +/** + * @} + */ + +/** @defgroup CRS_LL_EF_FLAG_Management FLAG_Management + * @{ + */ + +/** + * @brief Check if SYNC event OK signal occurred or not + * @rmtoll ISR SYNCOKF LL_CRS_IsActiveFlag_SYNCOK + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCOK(void) +{ + return (READ_BIT(CRS->ISR, CRS_ISR_SYNCOKF) == (CRS_ISR_SYNCOKF)); +} + +/** + * @brief Check if SYNC warning signal occurred or not + * @rmtoll ISR SYNCWARNF LL_CRS_IsActiveFlag_SYNCWARN + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCWARN(void) +{ + return (READ_BIT(CRS->ISR, CRS_ISR_SYNCWARNF) == (CRS_ISR_SYNCWARNF)); +} + +/** + * @brief Check if Synchronization or trimming error signal occurred or not + * @rmtoll ISR ERRF LL_CRS_IsActiveFlag_ERR + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_ERR(void) +{ + return (READ_BIT(CRS->ISR, CRS_ISR_ERRF) == (CRS_ISR_ERRF)); +} + +/** + * @brief Check if Expected SYNC signal occurred or not + * @rmtoll ISR ESYNCF LL_CRS_IsActiveFlag_ESYNC + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_ESYNC(void) +{ + return (READ_BIT(CRS->ISR, CRS_ISR_ESYNCF) == (CRS_ISR_ESYNCF)); +} + +/** + * @brief Check if SYNC error signal occurred or not + * @rmtoll ISR SYNCERR LL_CRS_IsActiveFlag_SYNCERR + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCERR(void) +{ + return (READ_BIT(CRS->ISR, CRS_ISR_SYNCERR) == (CRS_ISR_SYNCERR)); +} + +/** + * @brief Check if SYNC missed error signal occurred or not + * @rmtoll ISR SYNCMISS LL_CRS_IsActiveFlag_SYNCMISS + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCMISS(void) +{ + return (READ_BIT(CRS->ISR, CRS_ISR_SYNCMISS) == (CRS_ISR_SYNCMISS)); +} + +/** + * @brief Check if Trimming overflow or underflow occurred or not + * @rmtoll ISR TRIMOVF LL_CRS_IsActiveFlag_TRIMOVF + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_TRIMOVF(void) +{ + return (READ_BIT(CRS->ISR, CRS_ISR_TRIMOVF) == (CRS_ISR_TRIMOVF)); +} + +/** + * @brief Clear the SYNC event OK flag + * @rmtoll ICR SYNCOKC LL_CRS_ClearFlag_SYNCOK + * @retval None + */ +__STATIC_INLINE void LL_CRS_ClearFlag_SYNCOK(void) +{ + WRITE_REG(CRS->ICR, CRS_ICR_SYNCOKC); +} + +/** + * @brief Clear the SYNC warning flag + * @rmtoll ICR SYNCWARNC LL_CRS_ClearFlag_SYNCWARN + * @retval None + */ +__STATIC_INLINE void LL_CRS_ClearFlag_SYNCWARN(void) +{ + WRITE_REG(CRS->ICR, CRS_ICR_SYNCWARNC); +} + +/** + * @brief Clear TRIMOVF, SYNCMISS and SYNCERR bits and consequently also + * the ERR flag + * @rmtoll ICR ERRC LL_CRS_ClearFlag_ERR + * @retval None + */ +__STATIC_INLINE void LL_CRS_ClearFlag_ERR(void) +{ + WRITE_REG(CRS->ICR, CRS_ICR_ERRC); +} + +/** + * @brief Clear Expected SYNC flag + * @rmtoll ICR ESYNCC LL_CRS_ClearFlag_ESYNC + * @retval None + */ +__STATIC_INLINE void LL_CRS_ClearFlag_ESYNC(void) +{ + WRITE_REG(CRS->ICR, CRS_ICR_ESYNCC); +} + +/** + * @} + */ + +/** @defgroup CRS_LL_EF_IT_Management IT_Management + * @{ + */ + +/** + * @brief Enable SYNC event OK interrupt + * @rmtoll CR SYNCOKIE LL_CRS_EnableIT_SYNCOK + * @retval None + */ +__STATIC_INLINE void LL_CRS_EnableIT_SYNCOK(void) +{ + SET_BIT(CRS->CR, CRS_CR_SYNCOKIE); +} + +/** + * @brief Disable SYNC event OK interrupt + * @rmtoll CR SYNCOKIE LL_CRS_DisableIT_SYNCOK + * @retval None + */ +__STATIC_INLINE void LL_CRS_DisableIT_SYNCOK(void) +{ + CLEAR_BIT(CRS->CR, CRS_CR_SYNCOKIE); +} + +/** + * @brief Check if SYNC event OK interrupt is enabled or not + * @rmtoll CR SYNCOKIE LL_CRS_IsEnabledIT_SYNCOK + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_SYNCOK(void) +{ + return (READ_BIT(CRS->CR, CRS_CR_SYNCOKIE) == (CRS_CR_SYNCOKIE)); +} + +/** + * @brief Enable SYNC warning interrupt + * @rmtoll CR SYNCWARNIE LL_CRS_EnableIT_SYNCWARN + * @retval None + */ +__STATIC_INLINE void LL_CRS_EnableIT_SYNCWARN(void) +{ + SET_BIT(CRS->CR, CRS_CR_SYNCWARNIE); +} + +/** + * @brief Disable SYNC warning interrupt + * @rmtoll CR SYNCWARNIE LL_CRS_DisableIT_SYNCWARN + * @retval None + */ +__STATIC_INLINE void LL_CRS_DisableIT_SYNCWARN(void) +{ + CLEAR_BIT(CRS->CR, CRS_CR_SYNCWARNIE); +} + +/** + * @brief Check if SYNC warning interrupt is enabled or not + * @rmtoll CR SYNCWARNIE LL_CRS_IsEnabledIT_SYNCWARN + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_SYNCWARN(void) +{ + return (READ_BIT(CRS->CR, CRS_CR_SYNCWARNIE) == (CRS_CR_SYNCWARNIE)); +} + +/** + * @brief Enable Synchronization or trimming error interrupt + * @rmtoll CR ERRIE LL_CRS_EnableIT_ERR + * @retval None + */ +__STATIC_INLINE void LL_CRS_EnableIT_ERR(void) +{ + SET_BIT(CRS->CR, CRS_CR_ERRIE); +} + +/** + * @brief Disable Synchronization or trimming error interrupt + * @rmtoll CR ERRIE LL_CRS_DisableIT_ERR + * @retval None + */ +__STATIC_INLINE void LL_CRS_DisableIT_ERR(void) +{ + CLEAR_BIT(CRS->CR, CRS_CR_ERRIE); +} + +/** + * @brief Check if Synchronization or trimming error interrupt is enabled or not + * @rmtoll CR ERRIE LL_CRS_IsEnabledIT_ERR + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_ERR(void) +{ + return (READ_BIT(CRS->CR, CRS_CR_ERRIE) == (CRS_CR_ERRIE)); +} + +/** + * @brief Enable Expected SYNC interrupt + * @rmtoll CR ESYNCIE LL_CRS_EnableIT_ESYNC + * @retval None + */ +__STATIC_INLINE void LL_CRS_EnableIT_ESYNC(void) +{ + SET_BIT(CRS->CR, CRS_CR_ESYNCIE); +} + +/** + * @brief Disable Expected SYNC interrupt + * @rmtoll CR ESYNCIE LL_CRS_DisableIT_ESYNC + * @retval None + */ +__STATIC_INLINE void LL_CRS_DisableIT_ESYNC(void) +{ + CLEAR_BIT(CRS->CR, CRS_CR_ESYNCIE); +} + +/** + * @brief Check if Expected SYNC interrupt is enabled or not + * @rmtoll CR ESYNCIE LL_CRS_IsEnabledIT_ESYNC + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_ESYNC(void) +{ + return (READ_BIT(CRS->CR, CRS_CR_ESYNCIE) == (CRS_CR_ESYNCIE)); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup CRS_LL_EF_Init Initialization and de-initialization functions + * @{ + */ + +ErrorStatus LL_CRS_DeInit(void); + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined(CRS) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32L0xx_LL_CRS_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/fw/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h b/fw/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h new file mode 100644 index 0000000..5459bc0 --- /dev/null +++ b/fw/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h @@ -0,0 +1,2129 @@ +/** + ****************************************************************************** + * @file stm32l0xx_ll_dma.h + * @author MCD Application Team + * @brief Header file of DMA LL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32L0xx_LL_DMA_H +#define STM32L0xx_LL_DMA_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l0xx.h" + +/** @addtogroup STM32L0xx_LL_Driver + * @{ + */ + +#if defined (DMA1) + +/** @defgroup DMA_LL DMA + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/** @defgroup DMA_LL_Private_Variables DMA Private Variables + * @{ + */ +/* Array used to get the DMA channel register offset versus channel index LL_DMA_CHANNEL_x */ +static const uint8_t CHANNEL_OFFSET_TAB[] = +{ + (uint8_t)(DMA1_Channel1_BASE - DMA1_BASE), + (uint8_t)(DMA1_Channel2_BASE - DMA1_BASE), + (uint8_t)(DMA1_Channel3_BASE - DMA1_BASE), + (uint8_t)(DMA1_Channel4_BASE - DMA1_BASE), + (uint8_t)(DMA1_Channel5_BASE - DMA1_BASE), +#if defined(DMA1_Channel6) + (uint8_t)(DMA1_Channel6_BASE - DMA1_BASE), +#endif /*DMA1_Channel6*/ +#if defined(DMA1_Channel7) + (uint8_t)(DMA1_Channel7_BASE - DMA1_BASE) +#endif /*DMA1_Channel7*/ +}; +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup DMA_LL_Private_Constants DMA Private Constants + * @{ + */ +/* Define used to get CSELR register offset */ +#define DMA_CSELR_OFFSET (uint32_t)(DMA1_CSELR_BASE - DMA1_BASE) + +/* Defines used for the bit position in the register and perform offsets */ +#define DMA_POSITION_CSELR_CXS ((Channel-1U)*4U) +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup DMA_LL_Private_Macros DMA Private Macros + * @{ + */ +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup DMA_LL_ES_INIT DMA Exported Init structure + * @{ + */ +typedef struct +{ + uint32_t PeriphOrM2MSrcAddress; /*!< Specifies the peripheral base address for DMA transfer + or as Source base address in case of memory to memory transfer direction. + + This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */ + + uint32_t MemoryOrM2MDstAddress; /*!< Specifies the memory base address for DMA transfer + or as Destination base address in case of memory to memory transfer direction. + + This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */ + + uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, + from memory to memory or from peripheral to memory. + This parameter can be a value of @ref DMA_LL_EC_DIRECTION + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataTransferDirection(). */ + + uint32_t Mode; /*!< Specifies the normal or circular operation mode. + This parameter can be a value of @ref DMA_LL_EC_MODE + @note: The circular buffer mode cannot be used if the memory to memory + data transfer direction is configured on the selected Channel + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetMode(). */ + + uint32_t PeriphOrM2MSrcIncMode; /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction + is incremented or not. + This parameter can be a value of @ref DMA_LL_EC_PERIPH + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphIncMode(). */ + + uint32_t MemoryOrM2MDstIncMode; /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction + is incremented or not. + This parameter can be a value of @ref DMA_LL_EC_MEMORY + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryIncMode(). */ + + uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word) + in case of memory to memory transfer direction. + This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphSize(). */ + + uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word) + in case of memory to memory transfer direction. + This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemorySize(). */ + + uint32_t NbData; /*!< Specifies the number of data to transfer, in data unit. + The data unit is equal to the source buffer configuration set in PeripheralSize + or MemorySize parameters depending in the transfer direction. + This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */ + + uint32_t PeriphRequest; /*!< Specifies the peripheral request. + This parameter can be a value of @ref DMA_LL_EC_REQUEST + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphRequest(). */ + + uint32_t Priority; /*!< Specifies the channel priority level. + This parameter can be a value of @ref DMA_LL_EC_PRIORITY + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetChannelPriorityLevel(). */ + +} LL_DMA_InitTypeDef; +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup DMA_LL_Exported_Constants DMA Exported Constants + * @{ + */ +/** @defgroup DMA_LL_EC_CLEAR_FLAG Clear Flags Defines + * @brief Flags defines which can be used with LL_DMA_WriteReg function + * @{ + */ +#define LL_DMA_IFCR_CGIF1 DMA_IFCR_CGIF1 /*!< Channel 1 global flag */ +#define LL_DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1 /*!< Channel 1 transfer complete flag */ +#define LL_DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1 /*!< Channel 1 half transfer flag */ +#define LL_DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1 /*!< Channel 1 transfer error flag */ +#define LL_DMA_IFCR_CGIF2 DMA_IFCR_CGIF2 /*!< Channel 2 global flag */ +#define LL_DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2 /*!< Channel 2 transfer complete flag */ +#define LL_DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2 /*!< Channel 2 half transfer flag */ +#define LL_DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2 /*!< Channel 2 transfer error flag */ +#define LL_DMA_IFCR_CGIF3 DMA_IFCR_CGIF3 /*!< Channel 3 global flag */ +#define LL_DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3 /*!< Channel 3 transfer complete flag */ +#define LL_DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3 /*!< Channel 3 half transfer flag */ +#define LL_DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3 /*!< Channel 3 transfer error flag */ +#define LL_DMA_IFCR_CGIF4 DMA_IFCR_CGIF4 /*!< Channel 4 global flag */ +#define LL_DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4 /*!< Channel 4 transfer complete flag */ +#define LL_DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4 /*!< Channel 4 half transfer flag */ +#define LL_DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4 /*!< Channel 4 transfer error flag */ +#define LL_DMA_IFCR_CGIF5 DMA_IFCR_CGIF5 /*!< Channel 5 global flag */ +#define LL_DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5 /*!< Channel 5 transfer complete flag */ +#define LL_DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5 /*!< Channel 5 half transfer flag */ +#define LL_DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5 /*!< Channel 5 transfer error flag */ +#if defined(DMA1_Channel6) +#define LL_DMA_IFCR_CGIF6 DMA_IFCR_CGIF6 /*!< Channel 6 global flag */ +#define LL_DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6 /*!< Channel 6 transfer complete flag */ +#define LL_DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6 /*!< Channel 6 half transfer flag */ +#define LL_DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6 /*!< Channel 6 transfer error flag */ +#endif +#if defined(DMA1_Channel7) +#define LL_DMA_IFCR_CGIF7 DMA_IFCR_CGIF7 /*!< Channel 7 global flag */ +#define LL_DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7 /*!< Channel 7 transfer complete flag */ +#define LL_DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7 /*!< Channel 7 half transfer flag */ +#define LL_DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7 /*!< Channel 7 transfer error flag */ +#endif +/** + * @} + */ + +/** @defgroup DMA_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_DMA_ReadReg function + * @{ + */ +#define LL_DMA_ISR_GIF1 DMA_ISR_GIF1 /*!< Channel 1 global flag */ +#define LL_DMA_ISR_TCIF1 DMA_ISR_TCIF1 /*!< Channel 1 transfer complete flag */ +#define LL_DMA_ISR_HTIF1 DMA_ISR_HTIF1 /*!< Channel 1 half transfer flag */ +#define LL_DMA_ISR_TEIF1 DMA_ISR_TEIF1 /*!< Channel 1 transfer error flag */ +#define LL_DMA_ISR_GIF2 DMA_ISR_GIF2 /*!< Channel 2 global flag */ +#define LL_DMA_ISR_TCIF2 DMA_ISR_TCIF2 /*!< Channel 2 transfer complete flag */ +#define LL_DMA_ISR_HTIF2 DMA_ISR_HTIF2 /*!< Channel 2 half transfer flag */ +#define LL_DMA_ISR_TEIF2 DMA_ISR_TEIF2 /*!< Channel 2 transfer error flag */ +#define LL_DMA_ISR_GIF3 DMA_ISR_GIF3 /*!< Channel 3 global flag */ +#define LL_DMA_ISR_TCIF3 DMA_ISR_TCIF3 /*!< Channel 3 transfer complete flag */ +#define LL_DMA_ISR_HTIF3 DMA_ISR_HTIF3 /*!< Channel 3 half transfer flag */ +#define LL_DMA_ISR_TEIF3 DMA_ISR_TEIF3 /*!< Channel 3 transfer error flag */ +#define LL_DMA_ISR_GIF4 DMA_ISR_GIF4 /*!< Channel 4 global flag */ +#define LL_DMA_ISR_TCIF4 DMA_ISR_TCIF4 /*!< Channel 4 transfer complete flag */ +#define LL_DMA_ISR_HTIF4 DMA_ISR_HTIF4 /*!< Channel 4 half transfer flag */ +#define LL_DMA_ISR_TEIF4 DMA_ISR_TEIF4 /*!< Channel 4 transfer error flag */ +#define LL_DMA_ISR_GIF5 DMA_ISR_GIF5 /*!< Channel 5 global flag */ +#define LL_DMA_ISR_TCIF5 DMA_ISR_TCIF5 /*!< Channel 5 transfer complete flag */ +#define LL_DMA_ISR_HTIF5 DMA_ISR_HTIF5 /*!< Channel 5 half transfer flag */ +#define LL_DMA_ISR_TEIF5 DMA_ISR_TEIF5 /*!< Channel 5 transfer error flag */ +#if defined(DMA1_Channel6) +#define LL_DMA_ISR_GIF6 DMA_ISR_GIF6 /*!< Channel 6 global flag */ +#define LL_DMA_ISR_TCIF6 DMA_ISR_TCIF6 /*!< Channel 6 transfer complete flag */ +#define LL_DMA_ISR_HTIF6 DMA_ISR_HTIF6 /*!< Channel 6 half transfer flag */ +#define LL_DMA_ISR_TEIF6 DMA_ISR_TEIF6 /*!< Channel 6 transfer error flag */ +#endif +#if defined(DMA1_Channel7) +#define LL_DMA_ISR_GIF7 DMA_ISR_GIF7 /*!< Channel 7 global flag */ +#define LL_DMA_ISR_TCIF7 DMA_ISR_TCIF7 /*!< Channel 7 transfer complete flag */ +#define LL_DMA_ISR_HTIF7 DMA_ISR_HTIF7 /*!< Channel 7 half transfer flag */ +#define LL_DMA_ISR_TEIF7 DMA_ISR_TEIF7 /*!< Channel 7 transfer error flag */ +#endif +/** + * @} + */ + +/** @defgroup DMA_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_DMA_ReadReg and LL_DMA_WriteReg functions + * @{ + */ +#define LL_DMA_CCR_TCIE DMA_CCR_TCIE /*!< Transfer complete interrupt */ +#define LL_DMA_CCR_HTIE DMA_CCR_HTIE /*!< Half Transfer interrupt */ +#define LL_DMA_CCR_TEIE DMA_CCR_TEIE /*!< Transfer error interrupt */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_CHANNEL CHANNEL + * @{ + */ +#define LL_DMA_CHANNEL_1 0x00000001U /*!< DMA Channel 1 */ +#define LL_DMA_CHANNEL_2 0x00000002U /*!< DMA Channel 2 */ +#define LL_DMA_CHANNEL_3 0x00000003U /*!< DMA Channel 3 */ +#define LL_DMA_CHANNEL_4 0x00000004U /*!< DMA Channel 4 */ +#define LL_DMA_CHANNEL_5 0x00000005U /*!< DMA Channel 5 */ +#if defined(DMA1_Channel6) +#define LL_DMA_CHANNEL_6 0x00000006U /*!< DMA Channel 6 */ +#endif +#if defined(DMA1_Channel7) +#define LL_DMA_CHANNEL_7 0x00000007U /*!< DMA Channel 7 */ +#endif +#if defined(USE_FULL_LL_DRIVER) +#define LL_DMA_CHANNEL_ALL 0xFFFF0000U /*!< DMA Channel all (used only for function @ref LL_DMA_DeInit(). */ +#endif /*USE_FULL_LL_DRIVER*/ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_DIRECTION Transfer Direction + * @{ + */ +#define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */ +#define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CCR_DIR /*!< Memory to peripheral direction */ +#define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM /*!< Memory to memory direction */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_MODE Transfer mode + * @{ + */ +#define LL_DMA_MODE_NORMAL 0x00000000U /*!< Normal Mode */ +#define LL_DMA_MODE_CIRCULAR DMA_CCR_CIRC /*!< Circular Mode */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_PERIPH Peripheral increment mode + * @{ + */ +#define LL_DMA_PERIPH_INCREMENT DMA_CCR_PINC /*!< Peripheral increment mode Enable */ +#define LL_DMA_PERIPH_NOINCREMENT 0x00000000U /*!< Peripheral increment mode Disable */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_MEMORY Memory increment mode + * @{ + */ +#define LL_DMA_MEMORY_INCREMENT DMA_CCR_MINC /*!< Memory increment mode Enable */ +#define LL_DMA_MEMORY_NOINCREMENT 0x00000000U /*!< Memory increment mode Disable */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_PDATAALIGN Peripheral data alignment + * @{ + */ +#define LL_DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment : Byte */ +#define LL_DMA_PDATAALIGN_HALFWORD DMA_CCR_PSIZE_0 /*!< Peripheral data alignment : HalfWord */ +#define LL_DMA_PDATAALIGN_WORD DMA_CCR_PSIZE_1 /*!< Peripheral data alignment : Word */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_MDATAALIGN Memory data alignment + * @{ + */ +#define LL_DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment : Byte */ +#define LL_DMA_MDATAALIGN_HALFWORD DMA_CCR_MSIZE_0 /*!< Memory data alignment : HalfWord */ +#define LL_DMA_MDATAALIGN_WORD DMA_CCR_MSIZE_1 /*!< Memory data alignment : Word */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_PRIORITY Transfer Priority level + * @{ + */ +#define LL_DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */ +#define LL_DMA_PRIORITY_MEDIUM DMA_CCR_PL_0 /*!< Priority level : Medium */ +#define LL_DMA_PRIORITY_HIGH DMA_CCR_PL_1 /*!< Priority level : High */ +#define LL_DMA_PRIORITY_VERYHIGH DMA_CCR_PL /*!< Priority level : Very_High */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_REQUEST Transfer peripheral request + * @{ + */ +#define LL_DMA_REQUEST_0 0x00000000U /*!< DMA peripheral request 0 */ +#define LL_DMA_REQUEST_1 0x00000001U /*!< DMA peripheral request 1 */ +#define LL_DMA_REQUEST_2 0x00000002U /*!< DMA peripheral request 2 */ +#define LL_DMA_REQUEST_3 0x00000003U /*!< DMA peripheral request 3 */ +#define LL_DMA_REQUEST_4 0x00000004U /*!< DMA peripheral request 4 */ +#define LL_DMA_REQUEST_5 0x00000005U /*!< DMA peripheral request 5 */ +#define LL_DMA_REQUEST_6 0x00000006U /*!< DMA peripheral request 6 */ +#define LL_DMA_REQUEST_7 0x00000007U /*!< DMA peripheral request 7 */ +#define LL_DMA_REQUEST_8 0x00000008U /*!< DMA peripheral request 8 */ +#define LL_DMA_REQUEST_9 0x00000009U /*!< DMA peripheral request 9 */ +#define LL_DMA_REQUEST_10 0x0000000AU /*!< DMA peripheral request 10 */ +#define LL_DMA_REQUEST_11 0x0000000BU /*!< DMA peripheral request 11 */ +#define LL_DMA_REQUEST_12 0x0000000CU /*!< DMA peripheral request 12 */ +#define LL_DMA_REQUEST_13 0x0000000DU /*!< DMA peripheral request 13 */ +#define LL_DMA_REQUEST_14 0x0000000EU /*!< DMA peripheral request 14 */ +#define LL_DMA_REQUEST_15 0x0000000FU /*!< DMA peripheral request 15 */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup DMA_LL_Exported_Macros DMA Exported Macros + * @{ + */ + +/** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros + * @{ + */ +/** + * @brief Write a value in DMA register + * @param __INSTANCE__ DMA Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in DMA register + * @param __INSTANCE__ DMA Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxChannely + * @{ + */ +/** + * @brief Convert DMAx_Channely into DMAx + * @param __CHANNEL_INSTANCE__ DMAx_Channely + * @retval DMAx + */ +#define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) (DMA1) + +/** + * @brief Convert DMAx_Channely into LL_DMA_CHANNEL_y + * @param __CHANNEL_INSTANCE__ DMAx_Channely + * @retval LL_DMA_CHANNEL_y + */ +#if defined (DMA1_Channel6) && defined (DMA1_Channel7) +#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \ +(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \ + LL_DMA_CHANNEL_7) +#elif defined (DMA1_Channel6) +#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \ +(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \ + LL_DMA_CHANNEL_6) +#else +#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \ +(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \ + LL_DMA_CHANNEL_5) +#endif /* DMA1_Channel6 && DMA1_Channel7 */ + +/** + * @brief Convert DMA Instance DMAx and LL_DMA_CHANNEL_y into DMAx_Channely + * @param __DMA_INSTANCE__ DMAx + * @param __CHANNEL__ LL_DMA_CHANNEL_y + * @retval DMAx_Channely + */ +#if defined (DMA1_Channel6) && defined (DMA1_Channel7) +#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \ +((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \ + DMA1_Channel7) +#elif defined (DMA1_Channel6) +#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \ +((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \ + DMA1_Channel6) +#else +#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \ +((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \ + DMA1_Channel5) +#endif /* DMA1_Channel6 && DMA1_Channel7 */ + +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup DMA_LL_Exported_Functions DMA Exported Functions + * @{ + */ + +/** @defgroup DMA_LL_EF_Configuration Configuration + * @{ + */ +/** + * @brief Enable DMA channel. + * @rmtoll CCR EN LL_DMA_EnableChannel + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_EnableChannel(DMA_TypeDef *DMAx, uint32_t Channel) +{ + SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN); +} + +/** + * @brief Disable DMA channel. + * @rmtoll CCR EN LL_DMA_DisableChannel + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_DisableChannel(DMA_TypeDef *DMAx, uint32_t Channel) +{ + CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN); +} + +/** + * @brief Check if DMA channel is enabled or disabled. + * @rmtoll CCR EN LL_DMA_IsEnabledChannel + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return ((READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + DMA_CCR_EN) == (DMA_CCR_EN)) ? 1UL : 0UL); +} + +/** + * @brief Configure all parameters link to DMA transfer. + * @rmtoll CCR DIR LL_DMA_ConfigTransfer\n + * CCR MEM2MEM LL_DMA_ConfigTransfer\n + * CCR CIRC LL_DMA_ConfigTransfer\n + * CCR PINC LL_DMA_ConfigTransfer\n + * CCR MINC LL_DMA_ConfigTransfer\n + * CCR PSIZE LL_DMA_ConfigTransfer\n + * CCR MSIZE LL_DMA_ConfigTransfer\n + * CCR PL LL_DMA_ConfigTransfer + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param Configuration This parameter must be a combination of all the following values: + * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY + * @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR + * @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT + * @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT + * @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDATAALIGN_WORD + * @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDATAALIGN_WORD + * @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or @ref LL_DMA_PRIORITY_VERYHIGH + * @retval None + */ +__STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration) +{ + MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + DMA_CCR_DIR | DMA_CCR_MEM2MEM | DMA_CCR_CIRC | DMA_CCR_PINC | DMA_CCR_MINC | DMA_CCR_PSIZE | DMA_CCR_MSIZE | DMA_CCR_PL, + Configuration); +} + +/** + * @brief Set Data transfer direction (read from peripheral or from memory). + * @rmtoll CCR DIR LL_DMA_SetDataTransferDirection\n + * CCR MEM2MEM LL_DMA_SetDataTransferDirection + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param Direction This parameter can be one of the following values: + * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Direction) +{ + MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + DMA_CCR_DIR | DMA_CCR_MEM2MEM, Direction); +} + +/** + * @brief Get Data transfer direction (read from peripheral or from memory). + * @rmtoll CCR DIR LL_DMA_GetDataTransferDirection\n + * CCR MEM2MEM LL_DMA_GetDataTransferDirection + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY + */ +__STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + DMA_CCR_DIR | DMA_CCR_MEM2MEM)); +} + +/** + * @brief Set DMA mode circular or normal. + * @note The circular buffer mode cannot be used if the memory-to-memory + * data transfer is configured on the selected Channel. + * @rmtoll CCR CIRC LL_DMA_SetMode + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param Mode This parameter can be one of the following values: + * @arg @ref LL_DMA_MODE_NORMAL + * @arg @ref LL_DMA_MODE_CIRCULAR + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Mode) +{ + MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_CIRC, + Mode); +} + +/** + * @brief Get DMA mode circular or normal. + * @rmtoll CCR CIRC LL_DMA_GetMode + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_MODE_NORMAL + * @arg @ref LL_DMA_MODE_CIRCULAR + */ +__STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + DMA_CCR_CIRC)); +} + +/** + * @brief Set Peripheral increment mode. + * @rmtoll CCR PINC LL_DMA_SetPeriphIncMode + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param PeriphOrM2MSrcIncMode This parameter can be one of the following values: + * @arg @ref LL_DMA_PERIPH_INCREMENT + * @arg @ref LL_DMA_PERIPH_NOINCREMENT + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode) +{ + MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PINC, + PeriphOrM2MSrcIncMode); +} + +/** + * @brief Get Peripheral increment mode. + * @rmtoll CCR PINC LL_DMA_GetPeriphIncMode + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_PERIPH_INCREMENT + * @arg @ref LL_DMA_PERIPH_NOINCREMENT + */ +__STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + DMA_CCR_PINC)); +} + +/** + * @brief Set Memory increment mode. + * @rmtoll CCR MINC LL_DMA_SetMemoryIncMode + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param MemoryOrM2MDstIncMode This parameter can be one of the following values: + * @arg @ref LL_DMA_MEMORY_INCREMENT + * @arg @ref LL_DMA_MEMORY_NOINCREMENT + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode) +{ + MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MINC, + MemoryOrM2MDstIncMode); +} + +/** + * @brief Get Memory increment mode. + * @rmtoll CCR MINC LL_DMA_GetMemoryIncMode + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_MEMORY_INCREMENT + * @arg @ref LL_DMA_MEMORY_NOINCREMENT + */ +__STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + DMA_CCR_MINC)); +} + +/** + * @brief Set Peripheral size. + * @rmtoll CCR PSIZE LL_DMA_SetPeriphSize + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param PeriphOrM2MSrcDataSize This parameter can be one of the following values: + * @arg @ref LL_DMA_PDATAALIGN_BYTE + * @arg @ref LL_DMA_PDATAALIGN_HALFWORD + * @arg @ref LL_DMA_PDATAALIGN_WORD + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize) +{ + MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PSIZE, + PeriphOrM2MSrcDataSize); +} + +/** + * @brief Get Peripheral size. + * @rmtoll CCR PSIZE LL_DMA_GetPeriphSize + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_PDATAALIGN_BYTE + * @arg @ref LL_DMA_PDATAALIGN_HALFWORD + * @arg @ref LL_DMA_PDATAALIGN_WORD + */ +__STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + DMA_CCR_PSIZE)); +} + +/** + * @brief Set Memory size. + * @rmtoll CCR MSIZE LL_DMA_SetMemorySize + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param MemoryOrM2MDstDataSize This parameter can be one of the following values: + * @arg @ref LL_DMA_MDATAALIGN_BYTE + * @arg @ref LL_DMA_MDATAALIGN_HALFWORD + * @arg @ref LL_DMA_MDATAALIGN_WORD + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize) +{ + MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MSIZE, + MemoryOrM2MDstDataSize); +} + +/** + * @brief Get Memory size. + * @rmtoll CCR MSIZE LL_DMA_GetMemorySize + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_MDATAALIGN_BYTE + * @arg @ref LL_DMA_MDATAALIGN_HALFWORD + * @arg @ref LL_DMA_MDATAALIGN_WORD + */ +__STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + DMA_CCR_MSIZE)); +} + +/** + * @brief Set Channel priority level. + * @rmtoll CCR PL LL_DMA_SetChannelPriorityLevel + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param Priority This parameter can be one of the following values: + * @arg @ref LL_DMA_PRIORITY_LOW + * @arg @ref LL_DMA_PRIORITY_MEDIUM + * @arg @ref LL_DMA_PRIORITY_HIGH + * @arg @ref LL_DMA_PRIORITY_VERYHIGH + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Priority) +{ + MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PL, + Priority); +} + +/** + * @brief Get Channel priority level. + * @rmtoll CCR PL LL_DMA_GetChannelPriorityLevel + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_PRIORITY_LOW + * @arg @ref LL_DMA_PRIORITY_MEDIUM + * @arg @ref LL_DMA_PRIORITY_HIGH + * @arg @ref LL_DMA_PRIORITY_VERYHIGH + */ +__STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + DMA_CCR_PL)); +} + +/** + * @brief Set Number of data to transfer. + * @note This action has no effect if + * channel is enabled. + * @rmtoll CNDTR NDT LL_DMA_SetDataLength + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param NbData Between Min_Data = 0 and Max_Data = 0x0000FFFF + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t NbData) +{ + MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR, + DMA_CNDTR_NDT, NbData); +} + +/** + * @brief Get Number of data to transfer. + * @note Once the channel is enabled, the return value indicate the + * remaining bytes to be transmitted. + * @rmtoll CNDTR NDT LL_DMA_GetDataLength + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR, + DMA_CNDTR_NDT)); +} + +/** + * @brief Configure the Source and Destination addresses. + * @note This API must not be called when the DMA channel is enabled. + * @note Each IP using DMA provides an API to get directly the register adress (LL_PPP_DMA_GetRegAddr). + * @rmtoll CPAR PA LL_DMA_ConfigAddresses\n + * CMAR MA LL_DMA_ConfigAddresses + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param SrcAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + * @param DstAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + * @param Direction This parameter can be one of the following values: + * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY + * @retval None + */ +__STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress, + uint32_t DstAddress, uint32_t Direction) +{ + /* Direction Memory to Periph */ + if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) + { + WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, SrcAddress); + WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, DstAddress); + } + /* Direction Periph to Memory and Memory to Memory */ + else + { + WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, SrcAddress); + WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, DstAddress); + } +} + +/** + * @brief Set the Memory address. + * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. + * @note This API must not be called when the DMA channel is enabled. + * @rmtoll CMAR MA LL_DMA_SetMemoryAddress + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress) +{ + WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, MemoryAddress); +} + +/** + * @brief Set the Peripheral address. + * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. + * @note This API must not be called when the DMA channel is enabled. + * @rmtoll CPAR PA LL_DMA_SetPeriphAddress + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param PeriphAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphAddress) +{ + WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, PeriphAddress); +} + +/** + * @brief Get Memory address. + * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. + * @rmtoll CMAR MA LL_DMA_GetMemoryAddress + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR)); +} + +/** + * @brief Get Peripheral address. + * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. + * @rmtoll CPAR PA LL_DMA_GetPeriphAddress + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR)); +} + +/** + * @brief Set the Memory to Memory Source address. + * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. + * @note This API must not be called when the DMA channel is enabled. + * @rmtoll CPAR PA LL_DMA_SetM2MSrcAddress + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress) +{ + WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, MemoryAddress); +} + +/** + * @brief Set the Memory to Memory Destination address. + * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. + * @note This API must not be called when the DMA channel is enabled. + * @rmtoll CMAR MA LL_DMA_SetM2MDstAddress + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress) +{ + WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, MemoryAddress); +} + +/** + * @brief Get the Memory to Memory Source address. + * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. + * @rmtoll CPAR PA LL_DMA_GetM2MSrcAddress + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR)); +} + +/** + * @brief Get the Memory to Memory Destination address. + * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. + * @rmtoll CMAR MA LL_DMA_GetM2MDstAddress + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR)); +} + +/** + * @brief Set DMA request for DMA instance on Channel x. + * @note Please refer to Reference Manual to get the available mapping of Request value link to Channel Selection. + * @rmtoll CSELR C1S LL_DMA_SetPeriphRequest\n + * CSELR C2S LL_DMA_SetPeriphRequest\n + * CSELR C3S LL_DMA_SetPeriphRequest\n + * CSELR C4S LL_DMA_SetPeriphRequest\n + * CSELR C5S LL_DMA_SetPeriphRequest\n + * CSELR C6S LL_DMA_SetPeriphRequest\n + * CSELR C7S LL_DMA_SetPeriphRequest + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @param PeriphRequest This parameter can be one of the following values: + * @arg @ref LL_DMA_REQUEST_0 + * @arg @ref LL_DMA_REQUEST_1 + * @arg @ref LL_DMA_REQUEST_2 + * @arg @ref LL_DMA_REQUEST_3 + * @arg @ref LL_DMA_REQUEST_4 + * @arg @ref LL_DMA_REQUEST_5 + * @arg @ref LL_DMA_REQUEST_6 + * @arg @ref LL_DMA_REQUEST_7 + * @arg @ref LL_DMA_REQUEST_8 + * @arg @ref LL_DMA_REQUEST_9 + * @arg @ref LL_DMA_REQUEST_10 + * @arg @ref LL_DMA_REQUEST_11 + * @arg @ref LL_DMA_REQUEST_12 + * @arg @ref LL_DMA_REQUEST_13 + * @arg @ref LL_DMA_REQUEST_14 + * @arg @ref LL_DMA_REQUEST_15 + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Request) +{ + MODIFY_REG(((DMA_Request_TypeDef *)((uint32_t)((uint32_t)DMAx + DMA_CSELR_OFFSET)))->CSELR, + DMA_CSELR_C1S << ((Channel - 1U) * 4U), Request << DMA_POSITION_CSELR_CXS); +} + +/** + * @brief Get DMA request for DMA instance on Channel x. + * @rmtoll CSELR C1S LL_DMA_GetPeriphRequest\n + * CSELR C2S LL_DMA_GetPeriphRequest\n + * CSELR C3S LL_DMA_GetPeriphRequest\n + * CSELR C4S LL_DMA_GetPeriphRequest\n + * CSELR C5S LL_DMA_GetPeriphRequest\n + * CSELR C6S LL_DMA_GetPeriphRequest\n + * CSELR C7S LL_DMA_GetPeriphRequest + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_REQUEST_0 + * @arg @ref LL_DMA_REQUEST_1 + * @arg @ref LL_DMA_REQUEST_2 + * @arg @ref LL_DMA_REQUEST_3 + * @arg @ref LL_DMA_REQUEST_4 + * @arg @ref LL_DMA_REQUEST_5 + * @arg @ref LL_DMA_REQUEST_6 + * @arg @ref LL_DMA_REQUEST_7 + * @arg @ref LL_DMA_REQUEST_8 + * @arg @ref LL_DMA_REQUEST_9 + * @arg @ref LL_DMA_REQUEST_10 + * @arg @ref LL_DMA_REQUEST_11 + * @arg @ref LL_DMA_REQUEST_12 + * @arg @ref LL_DMA_REQUEST_13 + * @arg @ref LL_DMA_REQUEST_14 + * @arg @ref LL_DMA_REQUEST_15 + */ +__STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return (READ_BIT(((DMA_Request_TypeDef *)((uint32_t)((uint32_t)DMAx + DMA_CSELR_OFFSET)))->CSELR, + DMA_CSELR_C1S << ((Channel - 1U) * 4U)) >> DMA_POSITION_CSELR_CXS); +} + +/** + * @} + */ + +/** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management + * @{ + */ + +/** + * @brief Get Channel 1 global interrupt flag. + * @rmtoll ISR GIF1 LL_DMA_IsActiveFlag_GI1 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI1(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF1) == (DMA_ISR_GIF1)) ? 1UL : 0UL); +} + +/** + * @brief Get Channel 2 global interrupt flag. + * @rmtoll ISR GIF2 LL_DMA_IsActiveFlag_GI2 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI2(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF2) == (DMA_ISR_GIF2)) ? 1UL : 0UL); +} + +/** + * @brief Get Channel 3 global interrupt flag. + * @rmtoll ISR GIF3 LL_DMA_IsActiveFlag_GI3 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI3(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF3) == (DMA_ISR_GIF3)) ? 1UL : 0UL); +} + +/** + * @brief Get Channel 4 global interrupt flag. + * @rmtoll ISR GIF4 LL_DMA_IsActiveFlag_GI4 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI4(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF4) == (DMA_ISR_GIF4)) ? 1UL : 0UL); +} + +/** + * @brief Get Channel 5 global interrupt flag. + * @rmtoll ISR GIF5 LL_DMA_IsActiveFlag_GI5 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI5(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF5) == (DMA_ISR_GIF5)) ? 1UL : 0UL); +} + +#if defined(DMA1_Channel6) +/** + * @brief Get Channel 6 global interrupt flag. + * @rmtoll ISR GIF6 LL_DMA_IsActiveFlag_GI6 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI6(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF6) == (DMA_ISR_GIF6)) ? 1UL : 0UL); +} +#endif + +#if defined(DMA1_Channel7) +/** + * @brief Get Channel 7 global interrupt flag. + * @rmtoll ISR GIF7 LL_DMA_IsActiveFlag_GI7 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI7(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF7) == (DMA_ISR_GIF7)) ? 1UL : 0UL); +} +#endif + +/** + * @brief Get Channel 1 transfer complete flag. + * @rmtoll ISR TCIF1 LL_DMA_IsActiveFlag_TC1 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF1) == (DMA_ISR_TCIF1)) ? 1UL : 0UL); +} + +/** + * @brief Get Channel 2 transfer complete flag. + * @rmtoll ISR TCIF2 LL_DMA_IsActiveFlag_TC2 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF2) == (DMA_ISR_TCIF2)) ? 1UL : 0UL); +} + +/** + * @brief Get Channel 3 transfer complete flag. + * @rmtoll ISR TCIF3 LL_DMA_IsActiveFlag_TC3 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF3) == (DMA_ISR_TCIF3)) ? 1UL : 0UL); +} + +/** + * @brief Get Channel 4 transfer complete flag. + * @rmtoll ISR TCIF4 LL_DMA_IsActiveFlag_TC4 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF4) == (DMA_ISR_TCIF4)) ? 1UL : 0UL); +} + +/** + * @brief Get Channel 5 transfer complete flag. + * @rmtoll ISR TCIF5 LL_DMA_IsActiveFlag_TC5 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF5) == (DMA_ISR_TCIF5)) ? 1UL : 0UL); +} + +#if defined(DMA1_Channel6) +/** + * @brief Get Channel 6 transfer complete flag. + * @rmtoll ISR TCIF6 LL_DMA_IsActiveFlag_TC6 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF6) == (DMA_ISR_TCIF6)) ? 1UL : 0UL); +} +#endif + +#if defined(DMA1_Channel7) +/** + * @brief Get Channel 7 transfer complete flag. + * @rmtoll ISR TCIF7 LL_DMA_IsActiveFlag_TC7 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF7) == (DMA_ISR_TCIF7)) ? 1UL : 0UL); +} +#endif + +/** + * @brief Get Channel 1 half transfer flag. + * @rmtoll ISR HTIF1 LL_DMA_IsActiveFlag_HT1 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF1) == (DMA_ISR_HTIF1)) ? 1UL : 0UL); +} + +/** + * @brief Get Channel 2 half transfer flag. + * @rmtoll ISR HTIF2 LL_DMA_IsActiveFlag_HT2 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF2) == (DMA_ISR_HTIF2)) ? 1UL : 0UL); +} + +/** + * @brief Get Channel 3 half transfer flag. + * @rmtoll ISR HTIF3 LL_DMA_IsActiveFlag_HT3 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF3) == (DMA_ISR_HTIF3)) ? 1UL : 0UL); +} + +/** + * @brief Get Channel 4 half transfer flag. + * @rmtoll ISR HTIF4 LL_DMA_IsActiveFlag_HT4 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF4) == (DMA_ISR_HTIF4)) ? 1UL : 0UL); +} + +/** + * @brief Get Channel 5 half transfer flag. + * @rmtoll ISR HTIF5 LL_DMA_IsActiveFlag_HT5 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF5) == (DMA_ISR_HTIF5)) ? 1UL : 0UL); +} + +#if defined(DMA1_Channel6) +/** + * @brief Get Channel 6 half transfer flag. + * @rmtoll ISR HTIF6 LL_DMA_IsActiveFlag_HT6 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF6) == (DMA_ISR_HTIF6)) ? 1UL : 0UL); +} +#endif + +#if defined(DMA1_Channel7) +/** + * @brief Get Channel 7 half transfer flag. + * @rmtoll ISR HTIF7 LL_DMA_IsActiveFlag_HT7 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF7) == (DMA_ISR_HTIF7)) ? 1UL : 0UL); +} +#endif + +/** + * @brief Get Channel 1 transfer error flag. + * @rmtoll ISR TEIF1 LL_DMA_IsActiveFlag_TE1 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF1) == (DMA_ISR_TEIF1)) ? 1UL : 0UL); +} + +/** + * @brief Get Channel 2 transfer error flag. + * @rmtoll ISR TEIF2 LL_DMA_IsActiveFlag_TE2 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF2) == (DMA_ISR_TEIF2)) ? 1UL : 0UL); +} + +/** + * @brief Get Channel 3 transfer error flag. + * @rmtoll ISR TEIF3 LL_DMA_IsActiveFlag_TE3 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF3) == (DMA_ISR_TEIF3)) ? 1UL : 0UL); +} + +/** + * @brief Get Channel 4 transfer error flag. + * @rmtoll ISR TEIF4 LL_DMA_IsActiveFlag_TE4 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF4) == (DMA_ISR_TEIF4)) ? 1UL : 0UL); +} + +/** + * @brief Get Channel 5 transfer error flag. + * @rmtoll ISR TEIF5 LL_DMA_IsActiveFlag_TE5 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF5) == (DMA_ISR_TEIF5)) ? 1UL : 0UL); +} + +#if defined(DMA1_Channel6) +/** + * @brief Get Channel 6 transfer error flag. + * @rmtoll ISR TEIF6 LL_DMA_IsActiveFlag_TE6 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF6) == (DMA_ISR_TEIF6)) ? 1UL : 0UL); +} +#endif + +#if defined(DMA1_Channel7) +/** + * @brief Get Channel 7 transfer error flag. + * @rmtoll ISR TEIF7 LL_DMA_IsActiveFlag_TE7 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx) +{ + return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF7) == (DMA_ISR_TEIF7)) ? 1UL : 0UL); +} +#endif + +/** + * @brief Clear Channel 1 global interrupt flag. + * @rmtoll IFCR CGIF1 LL_DMA_ClearFlag_GI1 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_GI1(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF1); +} + +/** + * @brief Clear Channel 2 global interrupt flag. + * @rmtoll IFCR CGIF2 LL_DMA_ClearFlag_GI2 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_GI2(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF2); +} + +/** + * @brief Clear Channel 3 global interrupt flag. + * @rmtoll IFCR CGIF3 LL_DMA_ClearFlag_GI3 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_GI3(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF3); +} + +/** + * @brief Clear Channel 4 global interrupt flag. + * @rmtoll IFCR CGIF4 LL_DMA_ClearFlag_GI4 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_GI4(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF4); +} + +/** + * @brief Clear Channel 5 global interrupt flag. + * @rmtoll IFCR CGIF5 LL_DMA_ClearFlag_GI5 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_GI5(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF5); +} + +#if defined(DMA1_Channel6) +/** + * @brief Clear Channel 6 global interrupt flag. + * @rmtoll IFCR CGIF6 LL_DMA_ClearFlag_GI6 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_GI6(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF6); +} +#endif + +#if defined(DMA1_Channel7) +/** + * @brief Clear Channel 7 global interrupt flag. + * @rmtoll IFCR CGIF7 LL_DMA_ClearFlag_GI7 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_GI7(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF7); +} +#endif + +/** + * @brief Clear Channel 1 transfer complete flag. + * @rmtoll IFCR CTCIF1 LL_DMA_ClearFlag_TC1 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF1); +} + +/** + * @brief Clear Channel 2 transfer complete flag. + * @rmtoll IFCR CTCIF2 LL_DMA_ClearFlag_TC2 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF2); +} + +/** + * @brief Clear Channel 3 transfer complete flag. + * @rmtoll IFCR CTCIF3 LL_DMA_ClearFlag_TC3 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF3); +} + +/** + * @brief Clear Channel 4 transfer complete flag. + * @rmtoll IFCR CTCIF4 LL_DMA_ClearFlag_TC4 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF4); +} + +/** + * @brief Clear Channel 5 transfer complete flag. + * @rmtoll IFCR CTCIF5 LL_DMA_ClearFlag_TC5 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF5); +} + +#if defined(DMA1_Channel6) +/** + * @brief Clear Channel 6 transfer complete flag. + * @rmtoll IFCR CTCIF6 LL_DMA_ClearFlag_TC6 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF6); +} +#endif + +#if defined(DMA1_Channel7) +/** + * @brief Clear Channel 7 transfer complete flag. + * @rmtoll IFCR CTCIF7 LL_DMA_ClearFlag_TC7 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF7); +} +#endif + +/** + * @brief Clear Channel 1 half transfer flag. + * @rmtoll IFCR CHTIF1 LL_DMA_ClearFlag_HT1 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF1); +} + +/** + * @brief Clear Channel 2 half transfer flag. + * @rmtoll IFCR CHTIF2 LL_DMA_ClearFlag_HT2 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF2); +} + +/** + * @brief Clear Channel 3 half transfer flag. + * @rmtoll IFCR CHTIF3 LL_DMA_ClearFlag_HT3 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF3); +} + +/** + * @brief Clear Channel 4 half transfer flag. + * @rmtoll IFCR CHTIF4 LL_DMA_ClearFlag_HT4 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF4); +} + +/** + * @brief Clear Channel 5 half transfer flag. + * @rmtoll IFCR CHTIF5 LL_DMA_ClearFlag_HT5 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF5); +} + +#if defined(DMA1_Channel6) +/** + * @brief Clear Channel 6 half transfer flag. + * @rmtoll IFCR CHTIF6 LL_DMA_ClearFlag_HT6 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF6); +} +#endif + +#if defined(DMA1_Channel7) +/** + * @brief Clear Channel 7 half transfer flag. + * @rmtoll IFCR CHTIF7 LL_DMA_ClearFlag_HT7 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF7); +} +#endif + +/** + * @brief Clear Channel 1 transfer error flag. + * @rmtoll IFCR CTEIF1 LL_DMA_ClearFlag_TE1 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF1); +} + +/** + * @brief Clear Channel 2 transfer error flag. + * @rmtoll IFCR CTEIF2 LL_DMA_ClearFlag_TE2 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF2); +} + +/** + * @brief Clear Channel 3 transfer error flag. + * @rmtoll IFCR CTEIF3 LL_DMA_ClearFlag_TE3 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF3); +} + +/** + * @brief Clear Channel 4 transfer error flag. + * @rmtoll IFCR CTEIF4 LL_DMA_ClearFlag_TE4 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF4); +} + +/** + * @brief Clear Channel 5 transfer error flag. + * @rmtoll IFCR CTEIF5 LL_DMA_ClearFlag_TE5 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF5); +} + +#if defined(DMA1_Channel6) +/** + * @brief Clear Channel 6 transfer error flag. + * @rmtoll IFCR CTEIF6 LL_DMA_ClearFlag_TE6 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF6); +} +#endif + +#if defined(DMA1_Channel7) +/** + * @brief Clear Channel 7 transfer error flag. + * @rmtoll IFCR CTEIF7 LL_DMA_ClearFlag_TE7 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF7); +} +#endif + +/** + * @} + */ + +/** @defgroup DMA_LL_EF_IT_Management IT_Management + * @{ + */ +/** + * @brief Enable Transfer complete interrupt. + * @rmtoll CCR TCIE LL_DMA_EnableIT_TC + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) +{ + SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE); +} + +/** + * @brief Enable Half transfer interrupt. + * @rmtoll CCR HTIE LL_DMA_EnableIT_HT + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) +{ + SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE); +} + +/** + * @brief Enable Transfer error interrupt. + * @rmtoll CCR TEIE LL_DMA_EnableIT_TE + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) +{ + SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE); +} + +/** + * @brief Disable Transfer complete interrupt. + * @rmtoll CCR TCIE LL_DMA_DisableIT_TC + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) +{ + CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE); +} + +/** + * @brief Disable Half transfer interrupt. + * @rmtoll CCR HTIE LL_DMA_DisableIT_HT + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) +{ + CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE); +} + +/** + * @brief Disable Transfer error interrupt. + * @rmtoll CCR TEIE LL_DMA_DisableIT_TE + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) +{ + CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE); +} + +/** + * @brief Check if Transfer complete Interrupt is enabled. + * @rmtoll CCR TCIE LL_DMA_IsEnabledIT_TC + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return ((READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + DMA_CCR_TCIE) == (DMA_CCR_TCIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if Half transfer Interrupt is enabled. + * @rmtoll CCR HTIE LL_DMA_IsEnabledIT_HT + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return ((READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + DMA_CCR_HTIE) == (DMA_CCR_HTIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if Transfer error Interrupt is enabled. + * @rmtoll CCR TEIE LL_DMA_IsEnabledIT_TE + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return ((READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + DMA_CCR_TEIE) == (DMA_CCR_TEIE)) ? 1UL : 0UL); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions + * @{ + */ +ErrorStatus LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct); +ErrorStatus LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel); +void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct); + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* DMA1 */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32L0xx_LL_DMA_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/fw/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h b/fw/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h new file mode 100644 index 0000000..b7905ef --- /dev/null +++ b/fw/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h @@ -0,0 +1,1016 @@ +/** + ****************************************************************************** + * @file stm32l0xx_ll_exti.h + * @author MCD Application Team + * @brief Header file of EXTI LL module. + ****************************************************************************** + * @attention + * + *

© Copyright(c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32L0xx_LL_EXTI_H +#define __STM32L0xx_LL_EXTI_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l0xx.h" + +/** @addtogroup STM32L0xx_LL_Driver + * @{ + */ + +#if defined (EXTI) + +/** @defgroup EXTI_LL EXTI + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private Macros ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup EXTI_LL_Private_Macros EXTI Private Macros + * @{ + */ +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup EXTI_LL_ES_INIT EXTI Exported Init structure + * @{ + */ +typedef struct +{ + + uint32_t Line_0_31; /*!< Specifies the EXTI lines to be enabled or disabled for Lines in range 0 to 31 + This parameter can be any combination of @ref EXTI_LL_EC_LINE */ + + FunctionalState LineCommand; /*!< Specifies the new state of the selected EXTI lines. + This parameter can be set either to ENABLE or DISABLE */ + + uint8_t Mode; /*!< Specifies the mode for the EXTI lines. + This parameter can be a value of @ref EXTI_LL_EC_MODE. */ + + uint8_t Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines. + This parameter can be a value of @ref EXTI_LL_EC_TRIGGER. */ +} LL_EXTI_InitTypeDef; + +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup EXTI_LL_Exported_Constants EXTI Exported Constants + * @{ + */ + +/** @defgroup EXTI_LL_EC_LINE LINE + * @{ + */ +#define LL_EXTI_LINE_0 EXTI_IMR_IM0 /*!< Extended line 0 */ +#define LL_EXTI_LINE_1 EXTI_IMR_IM1 /*!< Extended line 1 */ +#define LL_EXTI_LINE_2 EXTI_IMR_IM2 /*!< Extended line 2 */ +#define LL_EXTI_LINE_3 EXTI_IMR_IM3 /*!< Extended line 3 */ +#define LL_EXTI_LINE_4 EXTI_IMR_IM4 /*!< Extended line 4 */ +#define LL_EXTI_LINE_5 EXTI_IMR_IM5 /*!< Extended line 5 */ +#define LL_EXTI_LINE_6 EXTI_IMR_IM6 /*!< Extended line 6 */ +#define LL_EXTI_LINE_7 EXTI_IMR_IM7 /*!< Extended line 7 */ +#define LL_EXTI_LINE_8 EXTI_IMR_IM8 /*!< Extended line 8 */ +#define LL_EXTI_LINE_9 EXTI_IMR_IM9 /*!< Extended line 9 */ +#define LL_EXTI_LINE_10 EXTI_IMR_IM10 /*!< Extended line 10 */ +#define LL_EXTI_LINE_11 EXTI_IMR_IM11 /*!< Extended line 11 */ +#define LL_EXTI_LINE_12 EXTI_IMR_IM12 /*!< Extended line 12 */ +#define LL_EXTI_LINE_13 EXTI_IMR_IM13 /*!< Extended line 13 */ +#define LL_EXTI_LINE_14 EXTI_IMR_IM14 /*!< Extended line 14 */ +#define LL_EXTI_LINE_15 EXTI_IMR_IM15 /*!< Extended line 15 */ +#if defined(EXTI_IMR_IM16) +#define LL_EXTI_LINE_16 EXTI_IMR_IM16 /*!< Extended line 16 */ +#endif +#define LL_EXTI_LINE_17 EXTI_IMR_IM17 /*!< Extended line 17 */ +#if defined(EXTI_IMR_IM18) +#define LL_EXTI_LINE_18 EXTI_IMR_IM18 /*!< Extended line 18 */ +#endif +#define LL_EXTI_LINE_19 EXTI_IMR_IM19 /*!< Extended line 19 */ +#if defined(EXTI_IMR_IM20) +#define LL_EXTI_LINE_20 EXTI_IMR_IM20 /*!< Extended line 20 */ +#endif +#if defined(EXTI_IMR_IM21) +#define LL_EXTI_LINE_21 EXTI_IMR_IM21 /*!< Extended line 21 */ +#endif +#if defined(EXTI_IMR_IM22) +#define LL_EXTI_LINE_22 EXTI_IMR_IM22 /*!< Extended line 22 */ +#endif +#define LL_EXTI_LINE_23 EXTI_IMR_IM23 /*!< Extended line 23 */ +#if defined(EXTI_IMR_IM24) +#define LL_EXTI_LINE_24 EXTI_IMR_IM24 /*!< Extended line 24 */ +#endif +#if defined(EXTI_IMR_IM25) +#define LL_EXTI_LINE_25 EXTI_IMR_IM25 /*!< Extended line 25 */ +#endif +#if defined(EXTI_IMR_IM26) +#define LL_EXTI_LINE_26 EXTI_IMR_IM26 /*!< Extended line 26 */ +#endif +#if defined(EXTI_IMR_IM27) +#define LL_EXTI_LINE_27 EXTI_IMR_IM27 /*!< Extended line 27 */ +#endif +#if defined(EXTI_IMR_IM28) +#define LL_EXTI_LINE_28 EXTI_IMR_IM28 /*!< Extended line 28 */ +#endif +#if defined(EXTI_IMR_IM29) +#define LL_EXTI_LINE_29 EXTI_IMR_IM29 /*!< Extended line 29 */ +#endif +#if defined(EXTI_IMR_IM30) +#define LL_EXTI_LINE_30 EXTI_IMR_IM30 /*!< Extended line 30 */ +#endif +#if defined(EXTI_IMR_IM31) +#define LL_EXTI_LINE_31 EXTI_IMR_IM31 /*!< Extended line 31 */ +#endif +#define LL_EXTI_LINE_ALL_0_31 EXTI_IMR_IM /*!< All Extended line not reserved*/ + + +#define LL_EXTI_LINE_ALL (0xFFFFFFFFU) /*!< All Extended line */ + +#if defined(USE_FULL_LL_DRIVER) +#define LL_EXTI_LINE_NONE (0x00000000U) /*!< None Extended line */ +#endif /*USE_FULL_LL_DRIVER*/ + +/** + * @} + */ +#if defined(USE_FULL_LL_DRIVER) + +/** @defgroup EXTI_LL_EC_MODE Mode + * @{ + */ +#define LL_EXTI_MODE_IT (0x00U) /*!< Interrupt Mode */ +#define LL_EXTI_MODE_EVENT (0x01U) /*!< Event Mode */ +#define LL_EXTI_MODE_IT_EVENT (0x02U) /*!< Interrupt & Event Mode */ +/** + * @} + */ + +/** @defgroup EXTI_LL_EC_TRIGGER Edge Trigger + * @{ + */ +#define LL_EXTI_TRIGGER_NONE (0x00U) /*!< No Trigger Mode */ +#define LL_EXTI_TRIGGER_RISING (0x01U) /*!< Trigger Rising Mode */ +#define LL_EXTI_TRIGGER_FALLING (0x02U) /*!< Trigger Falling Mode */ +#define LL_EXTI_TRIGGER_RISING_FALLING (0x03U) /*!< Trigger Rising & Falling Mode */ + +/** + * @} + */ + + +#endif /*USE_FULL_LL_DRIVER*/ + + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup EXTI_LL_Exported_Macros EXTI Exported Macros + * @{ + */ + +/** @defgroup EXTI_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in EXTI register + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_EXTI_WriteReg(__REG__, __VALUE__) WRITE_REG(EXTI->__REG__, (__VALUE__)) + +/** + * @brief Read a value in EXTI register + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_EXTI_ReadReg(__REG__) READ_REG(EXTI->__REG__) +/** + * @} + */ + + +/** + * @} + */ + + + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup EXTI_LL_Exported_Functions EXTI Exported Functions + * @{ + */ +/** @defgroup EXTI_LL_EF_IT_Management IT_Management + * @{ + */ + +/** + * @brief Enable ExtiLine Interrupt request for Lines in range 0 to 31 + * @note The reset value for the direct or internal lines (see RM) + * is set to 1 in order to enable the interrupt by default. + * Bits are set automatically at Power on. + * @rmtoll IMR IMx LL_EXTI_EnableIT_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 + * @arg @ref LL_EXTI_LINE_25 + * @arg @ref LL_EXTI_LINE_26 + * @arg @ref LL_EXTI_LINE_27 + * @arg @ref LL_EXTI_LINE_28 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableIT_0_31(uint32_t ExtiLine) +{ + SET_BIT(EXTI->IMR, ExtiLine); +} + +/** + * @brief Disable ExtiLine Interrupt request for Lines in range 0 to 31 + * @note The reset value for the direct or internal lines (see RM) + * is set to 1 in order to enable the interrupt by default. + * Bits are set automatically at Power on. + * @rmtoll IMR IMx LL_EXTI_DisableIT_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 + * @arg @ref LL_EXTI_LINE_25 + * @arg @ref LL_EXTI_LINE_26 + * @arg @ref LL_EXTI_LINE_27 + * @arg @ref LL_EXTI_LINE_28 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableIT_0_31(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->IMR, ExtiLine); +} + + +/** + * @brief Indicate if ExtiLine Interrupt request is enabled for Lines in range 0 to 31 + * @note The reset value for the direct or internal lines (see RM) + * is set to 1 in order to enable the interrupt by default. + * Bits are set automatically at Power on. + * @rmtoll IMR IMx LL_EXTI_IsEnabledIT_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 + * @arg @ref LL_EXTI_LINE_25 + * @arg @ref LL_EXTI_LINE_26 + * @arg @ref LL_EXTI_LINE_27 + * @arg @ref LL_EXTI_LINE_28 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_0_31(uint32_t ExtiLine) +{ + return (READ_BIT(EXTI->IMR, ExtiLine) == (ExtiLine)); +} + + +/** + * @} + */ + +/** @defgroup EXTI_LL_EF_Event_Management Event_Management + * @{ + */ + +/** + * @brief Enable ExtiLine Event request for Lines in range 0 to 31 + * @rmtoll EMR EMx LL_EXTI_EnableEvent_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 + * @arg @ref LL_EXTI_LINE_25 + * @arg @ref LL_EXTI_LINE_26 + * @arg @ref LL_EXTI_LINE_27 + * @arg @ref LL_EXTI_LINE_28 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableEvent_0_31(uint32_t ExtiLine) +{ + SET_BIT(EXTI->EMR, ExtiLine); + +} + + +/** + * @brief Disable ExtiLine Event request for Lines in range 0 to 31 + * @rmtoll EMR EMx LL_EXTI_DisableEvent_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 + * @arg @ref LL_EXTI_LINE_25 + * @arg @ref LL_EXTI_LINE_26 + * @arg @ref LL_EXTI_LINE_27 + * @arg @ref LL_EXTI_LINE_28 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableEvent_0_31(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->EMR, ExtiLine); +} + + +/** + * @brief Indicate if ExtiLine Event request is enabled for Lines in range 0 to 31 + * @rmtoll EMR EMx LL_EXTI_IsEnabledEvent_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24 + * @arg @ref LL_EXTI_LINE_25 + * @arg @ref LL_EXTI_LINE_26 + * @arg @ref LL_EXTI_LINE_27 + * @arg @ref LL_EXTI_LINE_28 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_0_31(uint32_t ExtiLine) +{ + return (READ_BIT(EXTI->EMR, ExtiLine) == (ExtiLine)); + +} + + +/** + * @} + */ + +/** @defgroup EXTI_LL_EF_Rising_Trigger_Management Rising_Trigger_Management + * @{ + */ + +/** + * @brief Enable ExtiLine Rising Edge Trigger for Lines in range 0 to 31 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a rising edge on a configurable interrupt + * line occurs during a write operation in the EXTI_RTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for + * the same interrupt line. In this case, both generate a trigger + * condition. + * @rmtoll RTSR RTx LL_EXTI_EnableRisingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableRisingTrig_0_31(uint32_t ExtiLine) +{ + SET_BIT(EXTI->RTSR, ExtiLine); + +} + + +/** + * @brief Disable ExtiLine Rising Edge Trigger for Lines in range 0 to 31 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a rising edge on a configurable interrupt + * line occurs during a write operation in the EXTI_RTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for + * the same interrupt line. In this case, both generate a trigger + * condition. + * @rmtoll RTSR RTx LL_EXTI_DisableRisingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableRisingTrig_0_31(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->RTSR, ExtiLine); + +} + + +/** + * @brief Check if rising edge trigger is enabled for Lines in range 0 to 31 + * @rmtoll RTSR RTx LL_EXTI_IsEnabledRisingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_0_31(uint32_t ExtiLine) +{ + return (READ_BIT(EXTI->RTSR, ExtiLine) == (ExtiLine)); +} + + +/** + * @} + */ + +/** @defgroup EXTI_LL_EF_Falling_Trigger_Management Falling_Trigger_Management + * @{ + */ + +/** + * @brief Enable ExtiLine Falling Edge Trigger for Lines in range 0 to 31 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a falling edge on a configurable interrupt + * line occurs during a write operation in the EXTI_FTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for + * the same interrupt line. In this case, both generate a trigger + * condition. + * @rmtoll FTSR FTx LL_EXTI_EnableFallingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableFallingTrig_0_31(uint32_t ExtiLine) +{ + SET_BIT(EXTI->FTSR, ExtiLine); +} + + +/** + * @brief Disable ExtiLine Falling Edge Trigger for Lines in range 0 to 31 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a Falling edge on a configurable interrupt + * line occurs during a write operation in the EXTI_FTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for the same interrupt line. + * In this case, both generate a trigger condition. + * @rmtoll FTSR FTx LL_EXTI_DisableFallingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableFallingTrig_0_31(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->FTSR, ExtiLine); +} + + +/** + * @brief Check if falling edge trigger is enabled for Lines in range 0 to 31 + * @rmtoll FTSR FTx LL_EXTI_IsEnabledFallingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_0_31(uint32_t ExtiLine) +{ + return (READ_BIT(EXTI->FTSR, ExtiLine) == (ExtiLine)); +} + + +/** + * @} + */ + +/** @defgroup EXTI_LL_EF_Software_Interrupt_Management Software_Interrupt_Management + * @{ + */ + +/** + * @brief Generate a software Interrupt Event for Lines in range 0 to 31 + * @note If the interrupt is enabled on this line in the EXTI_IMR, writing a 1 to + * this bit when it is at '0' sets the corresponding pending bit in EXTI_PR + * resulting in an interrupt request generation. + * This bit is cleared by clearing the corresponding bit in the EXTI_PR + * register (by writing a 1 into the bit) + * @rmtoll SWIER SWIx LL_EXTI_GenerateSWI_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_GenerateSWI_0_31(uint32_t ExtiLine) +{ + SET_BIT(EXTI->SWIER, ExtiLine); +} + + +/** + * @} + */ + +/** @defgroup EXTI_LL_EF_Flag_Management Flag_Management + * @{ + */ + +/** + * @brief Check if the ExtLine Flag is set or not for Lines in range 0 to 31 + * @note This bit is set when the selected edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll PR PIFx LL_EXTI_IsActiveFlag_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsActiveFlag_0_31(uint32_t ExtiLine) +{ + return (READ_BIT(EXTI->PR, ExtiLine) == (ExtiLine)); +} + + +/** + * @brief Read ExtLine Combination Flag for Lines in range 0 to 31 + * @note This bit is set when the selected edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll PR PIFx LL_EXTI_ReadFlag_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval @note This bit is set when the selected edge event arrives on the interrupt + */ +__STATIC_INLINE uint32_t LL_EXTI_ReadFlag_0_31(uint32_t ExtiLine) +{ + return (uint32_t)(READ_BIT(EXTI->PR, ExtiLine)); +} + + +/** + * @brief Clear ExtLine Flags for Lines in range 0 to 31 + * @note This bit is set when the selected edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll PR PIFx LL_EXTI_ClearFlag_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_29 + * @arg @ref LL_EXTI_LINE_30 + * @arg @ref LL_EXTI_LINE_31 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_ClearFlag_0_31(uint32_t ExtiLine) +{ + WRITE_REG(EXTI->PR, ExtiLine); +} + + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup EXTI_LL_EF_Init Initialization and de-initialization functions + * @{ + */ + +uint32_t LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct); +uint32_t LL_EXTI_DeInit(void); +void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct); + + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* EXTI */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32L0xx_LL_EXTI_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/fw/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h b/fw/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h new file mode 100644 index 0000000..d3fb40f --- /dev/null +++ b/fw/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h @@ -0,0 +1,945 @@ +/** + ****************************************************************************** + * @file stm32l0xx_ll_gpio.h + * @author MCD Application Team + * @brief Header file of GPIO LL module. + ****************************************************************************** + * @attention + * + *

© Copyright(c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32L0xx_LL_GPIO_H +#define __STM32L0xx_LL_GPIO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l0xx.h" + +/** @addtogroup STM32L0xx_LL_Driver + * @{ + */ + +#if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOH) + +/** @defgroup GPIO_LL GPIO + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup GPIO_LL_Private_Macros GPIO Private Macros + * @{ + */ + +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup GPIO_LL_ES_INIT GPIO Exported Init structures + * @{ + */ + +/** + * @brief LL GPIO Init Structure definition + */ +typedef struct +{ + uint32_t Pin; /*!< Specifies the GPIO pins to be configured. + This parameter can be any value of @ref GPIO_LL_EC_PIN */ + + uint32_t Mode; /*!< Specifies the operating mode for the selected pins. + This parameter can be a value of @ref GPIO_LL_EC_MODE. + + GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinMode().*/ + + uint32_t Speed; /*!< Specifies the speed for the selected pins. + This parameter can be a value of @ref GPIO_LL_EC_SPEED. + + GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinSpeed().*/ + + uint32_t OutputType; /*!< Specifies the operating output type for the selected pins. + This parameter can be a value of @ref GPIO_LL_EC_OUTPUT. + + GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinOutputType().*/ + + uint32_t Pull; /*!< Specifies the operating Pull-up/Pull down for the selected pins. + This parameter can be a value of @ref GPIO_LL_EC_PULL. + + GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinPull().*/ + + uint32_t Alternate; /*!< Specifies the Peripheral to be connected to the selected pins. + This parameter can be a value of @ref GPIO_LL_EC_AF. + + GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetAFPin_0_7() and LL_GPIO_SetAFPin_8_15().*/ +} LL_GPIO_InitTypeDef; + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup GPIO_LL_Exported_Constants GPIO Exported Constants + * @{ + */ + +/** @defgroup GPIO_LL_EC_PIN PIN + * @{ + */ +#define LL_GPIO_PIN_0 GPIO_BSRR_BS_0 /*!< Select pin 0 */ +#define LL_GPIO_PIN_1 GPIO_BSRR_BS_1 /*!< Select pin 1 */ +#define LL_GPIO_PIN_2 GPIO_BSRR_BS_2 /*!< Select pin 2 */ +#define LL_GPIO_PIN_3 GPIO_BSRR_BS_3 /*!< Select pin 3 */ +#define LL_GPIO_PIN_4 GPIO_BSRR_BS_4 /*!< Select pin 4 */ +#define LL_GPIO_PIN_5 GPIO_BSRR_BS_5 /*!< Select pin 5 */ +#define LL_GPIO_PIN_6 GPIO_BSRR_BS_6 /*!< Select pin 6 */ +#define LL_GPIO_PIN_7 GPIO_BSRR_BS_7 /*!< Select pin 7 */ +#define LL_GPIO_PIN_8 GPIO_BSRR_BS_8 /*!< Select pin 8 */ +#define LL_GPIO_PIN_9 GPIO_BSRR_BS_9 /*!< Select pin 9 */ +#define LL_GPIO_PIN_10 GPIO_BSRR_BS_10 /*!< Select pin 10 */ +#define LL_GPIO_PIN_11 GPIO_BSRR_BS_11 /*!< Select pin 11 */ +#define LL_GPIO_PIN_12 GPIO_BSRR_BS_12 /*!< Select pin 12 */ +#define LL_GPIO_PIN_13 GPIO_BSRR_BS_13 /*!< Select pin 13 */ +#define LL_GPIO_PIN_14 GPIO_BSRR_BS_14 /*!< Select pin 14 */ +#define LL_GPIO_PIN_15 GPIO_BSRR_BS_15 /*!< Select pin 15 */ +#define LL_GPIO_PIN_ALL (GPIO_BSRR_BS_0 | GPIO_BSRR_BS_1 | GPIO_BSRR_BS_2 | \ + GPIO_BSRR_BS_3 | GPIO_BSRR_BS_4 | GPIO_BSRR_BS_5 | \ + GPIO_BSRR_BS_6 | GPIO_BSRR_BS_7 | GPIO_BSRR_BS_8 | \ + GPIO_BSRR_BS_9 | GPIO_BSRR_BS_10 | GPIO_BSRR_BS_11 | \ + GPIO_BSRR_BS_12 | GPIO_BSRR_BS_13 | GPIO_BSRR_BS_14 | \ + GPIO_BSRR_BS_15) /*!< Select all pins */ +/** + * @} + */ + +/** @defgroup GPIO_LL_EC_MODE Mode + * @{ + */ +#define LL_GPIO_MODE_INPUT (0x00000000U) /*!< Select input mode */ +#define LL_GPIO_MODE_OUTPUT GPIO_MODER_MODE0_0 /*!< Select output mode */ +#define LL_GPIO_MODE_ALTERNATE GPIO_MODER_MODE0_1 /*!< Select alternate function mode */ +#define LL_GPIO_MODE_ANALOG GPIO_MODER_MODE0 /*!< Select analog mode */ +/** + * @} + */ + +/** @defgroup GPIO_LL_EC_OUTPUT Output Type + * @{ + */ +#define LL_GPIO_OUTPUT_PUSHPULL (0x00000000U) /*!< Select push-pull as output type */ +#define LL_GPIO_OUTPUT_OPENDRAIN GPIO_OTYPER_OT_0 /*!< Select open-drain as output type */ +/** + * @} + */ + +/** @defgroup GPIO_LL_EC_SPEED Output Speed + * @{ + */ +#define LL_GPIO_SPEED_FREQ_LOW (0x00000000U) /*!< Select I/O low output speed */ +#define LL_GPIO_SPEED_FREQ_MEDIUM GPIO_OSPEEDER_OSPEED0_0 /*!< Select I/O medium output speed */ +#define LL_GPIO_SPEED_FREQ_HIGH GPIO_OSPEEDER_OSPEED0_1 /*!< Select I/O fast output speed */ +#define LL_GPIO_SPEED_FREQ_VERY_HIGH GPIO_OSPEEDER_OSPEED0 /*!< Select I/O high output speed */ +/** + * @} + */ +#define LL_GPIO_SPEED_LOW LL_GPIO_SPEED_FREQ_LOW +#define LL_GPIO_SPEED_MEDIUM LL_GPIO_SPEED_FREQ_MEDIUM +#define LL_GPIO_SPEED_FAST LL_GPIO_SPEED_FREQ_HIGH +#define LL_GPIO_SPEED_HIGH LL_GPIO_SPEED_FREQ_VERY_HIGH + +/** @defgroup GPIO_LL_EC_PULL Pull Up Pull Down + * @{ + */ +#define LL_GPIO_PULL_NO (0x00000000U) /*!< Select I/O no pull */ +#define LL_GPIO_PULL_UP GPIO_PUPDR_PUPD0_0 /*!< Select I/O pull up */ +#define LL_GPIO_PULL_DOWN GPIO_PUPDR_PUPD0_1 /*!< Select I/O pull down */ +/** + * @} + */ + +/** @defgroup GPIO_LL_EC_AF Alternate Function + * @{ + */ +#define LL_GPIO_AF_0 (0x0000000U) /*!< Select alternate function 0 */ +#define LL_GPIO_AF_1 (0x0000001U) /*!< Select alternate function 1 */ +#define LL_GPIO_AF_2 (0x0000002U) /*!< Select alternate function 2 */ +#define LL_GPIO_AF_3 (0x0000003U) /*!< Select alternate function 3 */ +#define LL_GPIO_AF_4 (0x0000004U) /*!< Select alternate function 4 */ +#define LL_GPIO_AF_5 (0x0000005U) /*!< Select alternate function 5 */ +#define LL_GPIO_AF_6 (0x0000006U) /*!< Select alternate function 6 */ +#define LL_GPIO_AF_7 (0x0000007U) /*!< Select alternate function 7 */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup GPIO_LL_Exported_Macros GPIO Exported Macros + * @{ + */ + +/** @defgroup GPIO_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in GPIO register + * @param __INSTANCE__ GPIO Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_GPIO_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in GPIO register + * @param __INSTANCE__ GPIO Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_GPIO_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup GPIO_LL_Exported_Functions GPIO Exported Functions + * @{ + */ + +/** @defgroup GPIO_LL_EF_Port_Configuration Port Configuration + * @{ + */ + +/** + * @brief Configure gpio mode for a dedicated pin on dedicated port. + * @note I/O mode can be Input mode, General purpose output, Alternate function mode or Analog. + * @note Warning: only one pin can be passed as parameter. + * @rmtoll MODER MODEy LL_GPIO_SetPinMode + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @param Mode This parameter can be one of the following values: + * @arg @ref LL_GPIO_MODE_INPUT + * @arg @ref LL_GPIO_MODE_OUTPUT + * @arg @ref LL_GPIO_MODE_ALTERNATE + * @arg @ref LL_GPIO_MODE_ANALOG + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Mode) +{ + MODIFY_REG(GPIOx->MODER, ((Pin * Pin) * GPIO_MODER_MODE0), ((Pin * Pin) * Mode)); +} + +/** + * @brief Return gpio mode for a dedicated pin on dedicated port. + * @note I/O mode can be Input mode, General purpose output, Alternate function mode or Analog. + * @note Warning: only one pin can be passed as parameter. + * @rmtoll MODER MODEy LL_GPIO_GetPinMode + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPIO_MODE_INPUT + * @arg @ref LL_GPIO_MODE_OUTPUT + * @arg @ref LL_GPIO_MODE_ALTERNATE + * @arg @ref LL_GPIO_MODE_ANALOG + */ +__STATIC_INLINE uint32_t LL_GPIO_GetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->MODER, ((Pin * Pin) * GPIO_MODER_MODE0)) / (Pin * Pin)); +} + +/** + * @brief Configure gpio output type for several pins on dedicated port. + * @note Output type as to be set when gpio pin is in output or + * alternate modes. Possible type are Push-pull or Open-drain. + * @rmtoll OTYPER OTy LL_GPIO_SetPinOutputType + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @param OutputType This parameter can be one of the following values: + * @arg @ref LL_GPIO_OUTPUT_PUSHPULL + * @arg @ref LL_GPIO_OUTPUT_OPENDRAIN + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t PinMask, uint32_t OutputType) +{ + MODIFY_REG(GPIOx->OTYPER, PinMask, (PinMask * OutputType)); +} + +/** + * @brief Return gpio output type for several pins on dedicated port. + * @note Output type as to be set when gpio pin is in output or + * alternate modes. Possible type are Push-pull or Open-drain. + * @note Warning: only one pin can be passed as parameter. + * @rmtoll OTYPER OTy LL_GPIO_GetPinOutputType + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPIO_OUTPUT_PUSHPULL + * @arg @ref LL_GPIO_OUTPUT_OPENDRAIN + */ +__STATIC_INLINE uint32_t LL_GPIO_GetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->OTYPER, Pin) / Pin); +} + +/** + * @brief Configure gpio speed for a dedicated pin on dedicated port. + * @note I/O speed can be Low, Medium, Fast or High speed. + * @note Warning: only one pin can be passed as parameter. + * @note Refer to datasheet for frequency specifications and the power + * supply and load conditions for each speed. + * @rmtoll OSPEEDR OSPEEDy LL_GPIO_SetPinSpeed + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @param Speed This parameter can be one of the following values: + * @arg @ref LL_GPIO_SPEED_FREQ_LOW + * @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM + * @arg @ref LL_GPIO_SPEED_FREQ_HIGH + * @arg @ref LL_GPIO_SPEED_FREQ_VERY_HIGH + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Speed) +{ + MODIFY_REG(GPIOx->OSPEEDR, ((Pin * Pin) * GPIO_OSPEEDER_OSPEED0), ((Pin * Pin) * Speed)); +} + +/** + * @brief Return gpio speed for a dedicated pin on dedicated port. + * @note I/O speed can be Low, Medium, Fast or High speed. + * @note Warning: only one pin can be passed as parameter. + * @note Refer to datasheet for frequency specifications and the power + * supply and load conditions for each speed. + * @rmtoll OSPEEDR OSPEEDy LL_GPIO_GetPinSpeed + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPIO_SPEED_FREQ_LOW + * @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM + * @arg @ref LL_GPIO_SPEED_FREQ_HIGH + * @arg @ref LL_GPIO_SPEED_FREQ_VERY_HIGH + */ +__STATIC_INLINE uint32_t LL_GPIO_GetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->OSPEEDR, ((Pin * Pin) * GPIO_OSPEEDER_OSPEED0)) / (Pin * Pin)); +} + +/** + * @brief Configure gpio pull-up or pull-down for a dedicated pin on a dedicated port. + * @note Warning: only one pin can be passed as parameter. + * @rmtoll PUPDR PUPDy LL_GPIO_SetPinPull + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @param Pull This parameter can be one of the following values: + * @arg @ref LL_GPIO_PULL_NO + * @arg @ref LL_GPIO_PULL_UP + * @arg @ref LL_GPIO_PULL_DOWN + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Pull) +{ + MODIFY_REG(GPIOx->PUPDR, ((Pin * Pin) * GPIO_PUPDR_PUPD0), ((Pin * Pin) * Pull)); +} + +/** + * @brief Return gpio pull-up or pull-down for a dedicated pin on a dedicated port + * @note Warning: only one pin can be passed as parameter. + * @rmtoll PUPDR PUPDy LL_GPIO_GetPinPull + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPIO_PULL_NO + * @arg @ref LL_GPIO_PULL_UP + * @arg @ref LL_GPIO_PULL_DOWN + */ +__STATIC_INLINE uint32_t LL_GPIO_GetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->PUPDR, ((Pin * Pin) * GPIO_PUPDR_PUPD0)) / (Pin * Pin)); +} + +/** + * @brief Configure gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port. + * @note Possible values are from AF0 to AF7 depending on target. + * @note Warning: only one pin can be passed as parameter. + * @rmtoll AFRL AFSELy LL_GPIO_SetAFPin_0_7 + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @param Alternate This parameter can be one of the following values: + * @arg @ref LL_GPIO_AF_0 + * @arg @ref LL_GPIO_AF_1 + * @arg @ref LL_GPIO_AF_2 + * @arg @ref LL_GPIO_AF_3 + * @arg @ref LL_GPIO_AF_4 + * @arg @ref LL_GPIO_AF_5 + * @arg @ref LL_GPIO_AF_6 + * @arg @ref LL_GPIO_AF_7 + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate) +{ + MODIFY_REG(GPIOx->AFR[0], ((((Pin * Pin) * Pin) * Pin) * GPIO_AFRL_AFSEL0), + ((((Pin * Pin) * Pin) * Pin) * Alternate)); +} + +/** + * @brief Return gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port. + * @rmtoll AFRL AFSELy LL_GPIO_GetAFPin_0_7 + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPIO_AF_0 + * @arg @ref LL_GPIO_AF_1 + * @arg @ref LL_GPIO_AF_2 + * @arg @ref LL_GPIO_AF_3 + * @arg @ref LL_GPIO_AF_4 + * @arg @ref LL_GPIO_AF_5 + * @arg @ref LL_GPIO_AF_6 + * @arg @ref LL_GPIO_AF_7 + */ +__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->AFR[0], + ((((Pin * Pin) * Pin) * Pin) * GPIO_AFRL_AFSEL0)) / (((Pin * Pin) * Pin) * Pin)); +} + +/** + * @brief Configure gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port. + * @note Possible values are from AF0 to AF7 depending on target. + * @note Warning: only one pin can be passed as parameter. + * @rmtoll AFRH AFSELy LL_GPIO_SetAFPin_8_15 + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @param Alternate This parameter can be one of the following values: + * @arg @ref LL_GPIO_AF_0 + * @arg @ref LL_GPIO_AF_1 + * @arg @ref LL_GPIO_AF_2 + * @arg @ref LL_GPIO_AF_3 + * @arg @ref LL_GPIO_AF_4 + * @arg @ref LL_GPIO_AF_5 + * @arg @ref LL_GPIO_AF_6 + * @arg @ref LL_GPIO_AF_7 + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate) +{ + MODIFY_REG(GPIOx->AFR[1], (((((Pin >> 8U) * (Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U)) * GPIO_AFRH_AFSEL8), + (((((Pin >> 8U) * (Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U)) * Alternate)); +} + +/** + * @brief Return gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port. + * @note Possible values are from AF0 to AF7 depending on target. + * @rmtoll AFRH AFSELy LL_GPIO_GetAFPin_8_15 + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPIO_AF_0 + * @arg @ref LL_GPIO_AF_1 + * @arg @ref LL_GPIO_AF_2 + * @arg @ref LL_GPIO_AF_3 + * @arg @ref LL_GPIO_AF_4 + * @arg @ref LL_GPIO_AF_5 + * @arg @ref LL_GPIO_AF_6 + * @arg @ref LL_GPIO_AF_7 + */ +__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->AFR[1], + (((((Pin >> 8U) * (Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U)) * GPIO_AFRH_AFSEL8)) / ((((Pin >> 8U) * + (Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U))); +} + + +/** + * @brief Lock configuration of several pins for a dedicated port. + * @note When the lock sequence has been applied on a port bit, the + * value of this port bit can no longer be modified until the + * next reset. + * @note Each lock bit freezes a specific configuration register + * (control and alternate function registers). + * @rmtoll LCKR LCKK LL_GPIO_LockPin + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval None + */ +__STATIC_INLINE void LL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + __IO uint32_t temp; + WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask); + WRITE_REG(GPIOx->LCKR, PinMask); + WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask); + /* Read LCKK register. This read is mandatory to complete key lock sequence */ + temp = READ_REG(GPIOx->LCKR); + (void) temp; +} + +/** + * @brief Return 1 if all pins passed as parameter, of a dedicated port, are locked. else Return 0. + * @rmtoll LCKR LCKy LL_GPIO_IsPinLocked + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_GPIO_IsPinLocked(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + return (READ_BIT(GPIOx->LCKR, PinMask) == (PinMask)); +} + +/** + * @brief Return 1 if one of the pin of a dedicated port is locked. else return 0. + * @rmtoll LCKR LCKK LL_GPIO_IsAnyPinLocked + * @param GPIOx GPIO Port + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_GPIO_IsAnyPinLocked(GPIO_TypeDef *GPIOx) +{ + return (READ_BIT(GPIOx->LCKR, GPIO_LCKR_LCKK) == (GPIO_LCKR_LCKK)); +} + +/** + * @} + */ + +/** @defgroup GPIO_LL_EF_Data_Access Data Access + * @{ + */ + +/** + * @brief Return full input data register value for a dedicated port. + * @rmtoll IDR IDy LL_GPIO_ReadInputPort + * @param GPIOx GPIO Port + * @retval Input data register value of port + */ +__STATIC_INLINE uint32_t LL_GPIO_ReadInputPort(GPIO_TypeDef *GPIOx) +{ + return (uint32_t)(READ_REG(GPIOx->IDR)); +} + +/** + * @brief Return if input data level for several pins of dedicated port is high or low. + * @rmtoll IDR IDy LL_GPIO_IsInputPinSet + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_GPIO_IsInputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + return (READ_BIT(GPIOx->IDR, PinMask) == (PinMask)); +} + +/** + * @brief Write output data register for the port. + * @rmtoll ODR ODy LL_GPIO_WriteOutputPort + * @param GPIOx GPIO Port + * @param PortValue Level value for each pin of the port + * @retval None + */ +__STATIC_INLINE void LL_GPIO_WriteOutputPort(GPIO_TypeDef *GPIOx, uint32_t PortValue) +{ + WRITE_REG(GPIOx->ODR, PortValue); +} + +/** + * @brief Return full output data register value for a dedicated port. + * @rmtoll ODR ODy LL_GPIO_ReadOutputPort + * @param GPIOx GPIO Port + * @retval Output data register value of port + */ +__STATIC_INLINE uint32_t LL_GPIO_ReadOutputPort(GPIO_TypeDef *GPIOx) +{ + return (uint32_t)(READ_REG(GPIOx->ODR)); +} + +/** + * @brief Return if input data level for several pins of dedicated port is high or low. + * @rmtoll ODR ODy LL_GPIO_IsOutputPinSet + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_GPIO_IsOutputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + return (READ_BIT(GPIOx->ODR, PinMask) == (PinMask)); +} + +/** + * @brief Set several pins to high level on dedicated gpio port. + * @rmtoll BSRR BSy LL_GPIO_SetOutputPin + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + WRITE_REG(GPIOx->BSRR, PinMask); +} + +/** + * @brief Set several pins to low level on dedicated gpio port. + * @rmtoll BRR BRy LL_GPIO_ResetOutputPin + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval None + */ +__STATIC_INLINE void LL_GPIO_ResetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + WRITE_REG(GPIOx->BRR, PinMask); +} + +/** + * @brief Toggle data value for several pin of dedicated port. + * @rmtoll ODR ODy LL_GPIO_TogglePin + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval None + */ +__STATIC_INLINE void LL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + uint32_t odr = READ_REG(GPIOx->ODR); + WRITE_REG(GPIOx->BSRR, ((odr & PinMask) << 16u) | (~odr & PinMask)); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup GPIO_LL_EF_Init Initialization and de-initialization functions + * @{ + */ + +ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx); +ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct); +void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct); + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOH) */ +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32L0xx_LL_GPIO_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/fw/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h b/fw/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h new file mode 100644 index 0000000..a0b07be --- /dev/null +++ b/fw/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h @@ -0,0 +1,2230 @@ +/** + ****************************************************************************** + * @file stm32l0xx_ll_i2c.h + * @author MCD Application Team + * @brief Header file of I2C LL module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32L0xx_LL_I2C_H +#define STM32L0xx_LL_I2C_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l0xx.h" + +/** @addtogroup STM32L0xx_LL_Driver + * @{ + */ + +#if defined (I2C1) || defined (I2C2) || defined (I2C3) + +/** @defgroup I2C_LL I2C + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup I2C_LL_Private_Constants I2C Private Constants + * @{ + */ +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup I2C_LL_Private_Macros I2C Private Macros + * @{ + */ +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup I2C_LL_ES_INIT I2C Exported Init structure + * @{ + */ +typedef struct +{ + uint32_t PeripheralMode; /*!< Specifies the peripheral mode. + This parameter can be a value of @ref I2C_LL_EC_PERIPHERAL_MODE. + + This feature can be modified afterwards using unitary function @ref LL_I2C_SetMode(). */ + + uint32_t Timing; /*!< Specifies the SDA setup, hold time and the SCL high, low period values. + This parameter must be set by referring to the STM32CubeMX Tool and + the helper macro @ref __LL_I2C_CONVERT_TIMINGS(). + + This feature can be modified afterwards using unitary function @ref LL_I2C_SetTiming(). */ + + uint32_t AnalogFilter; /*!< Enables or disables analog noise filter. + This parameter can be a value of @ref I2C_LL_EC_ANALOGFILTER_SELECTION. + + This feature can be modified afterwards using unitary functions @ref LL_I2C_EnableAnalogFilter() or LL_I2C_DisableAnalogFilter(). */ + + uint32_t DigitalFilter; /*!< Configures the digital noise filter. + This parameter can be a number between Min_Data = 0x00 and Max_Data = 0x0F. + + This feature can be modified afterwards using unitary function @ref LL_I2C_SetDigitalFilter(). */ + + uint32_t OwnAddress1; /*!< Specifies the device own address 1. + This parameter must be a value between Min_Data = 0x00 and Max_Data = 0x3FF. + + This feature can be modified afterwards using unitary function @ref LL_I2C_SetOwnAddress1(). */ + + uint32_t TypeAcknowledge; /*!< Specifies the ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte. + This parameter can be a value of @ref I2C_LL_EC_I2C_ACKNOWLEDGE. + + This feature can be modified afterwards using unitary function @ref LL_I2C_AcknowledgeNextData(). */ + + uint32_t OwnAddrSize; /*!< Specifies the device own address 1 size (7-bit or 10-bit). + This parameter can be a value of @ref I2C_LL_EC_OWNADDRESS1. + + This feature can be modified afterwards using unitary function @ref LL_I2C_SetOwnAddress1(). */ +} LL_I2C_InitTypeDef; +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup I2C_LL_Exported_Constants I2C Exported Constants + * @{ + */ + +/** @defgroup I2C_LL_EC_CLEAR_FLAG Clear Flags Defines + * @brief Flags defines which can be used with LL_I2C_WriteReg function + * @{ + */ +#define LL_I2C_ICR_ADDRCF I2C_ICR_ADDRCF /*!< Address Matched flag */ +#define LL_I2C_ICR_NACKCF I2C_ICR_NACKCF /*!< Not Acknowledge flag */ +#define LL_I2C_ICR_STOPCF I2C_ICR_STOPCF /*!< Stop detection flag */ +#define LL_I2C_ICR_BERRCF I2C_ICR_BERRCF /*!< Bus error flag */ +#define LL_I2C_ICR_ARLOCF I2C_ICR_ARLOCF /*!< Arbitration Lost flag */ +#define LL_I2C_ICR_OVRCF I2C_ICR_OVRCF /*!< Overrun/Underrun flag */ +#define LL_I2C_ICR_PECCF I2C_ICR_PECCF /*!< PEC error flag */ +#define LL_I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF /*!< Timeout detection flag */ +#define LL_I2C_ICR_ALERTCF I2C_ICR_ALERTCF /*!< Alert flag */ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_I2C_ReadReg function + * @{ + */ +#define LL_I2C_ISR_TXE I2C_ISR_TXE /*!< Transmit data register empty */ +#define LL_I2C_ISR_TXIS I2C_ISR_TXIS /*!< Transmit interrupt status */ +#define LL_I2C_ISR_RXNE I2C_ISR_RXNE /*!< Receive data register not empty */ +#define LL_I2C_ISR_ADDR I2C_ISR_ADDR /*!< Address matched (slave mode) */ +#define LL_I2C_ISR_NACKF I2C_ISR_NACKF /*!< Not Acknowledge received flag */ +#define LL_I2C_ISR_STOPF I2C_ISR_STOPF /*!< Stop detection flag */ +#define LL_I2C_ISR_TC I2C_ISR_TC /*!< Transfer Complete (master mode) */ +#define LL_I2C_ISR_TCR I2C_ISR_TCR /*!< Transfer Complete Reload */ +#define LL_I2C_ISR_BERR I2C_ISR_BERR /*!< Bus error */ +#define LL_I2C_ISR_ARLO I2C_ISR_ARLO /*!< Arbitration lost */ +#define LL_I2C_ISR_OVR I2C_ISR_OVR /*!< Overrun/Underrun (slave mode) */ +#define LL_I2C_ISR_PECERR I2C_ISR_PECERR /*!< PEC Error in reception (SMBus mode) */ +#define LL_I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT /*!< Timeout detection flag (SMBus mode) */ +#define LL_I2C_ISR_ALERT I2C_ISR_ALERT /*!< SMBus alert (SMBus mode) */ +#define LL_I2C_ISR_BUSY I2C_ISR_BUSY /*!< Bus busy */ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_I2C_ReadReg and LL_I2C_WriteReg functions + * @{ + */ +#define LL_I2C_CR1_TXIE I2C_CR1_TXIE /*!< TX Interrupt enable */ +#define LL_I2C_CR1_RXIE I2C_CR1_RXIE /*!< RX Interrupt enable */ +#define LL_I2C_CR1_ADDRIE I2C_CR1_ADDRIE /*!< Address match Interrupt enable (slave only) */ +#define LL_I2C_CR1_NACKIE I2C_CR1_NACKIE /*!< Not acknowledge received Interrupt enable */ +#define LL_I2C_CR1_STOPIE I2C_CR1_STOPIE /*!< STOP detection Interrupt enable */ +#define LL_I2C_CR1_TCIE I2C_CR1_TCIE /*!< Transfer Complete interrupt enable */ +#define LL_I2C_CR1_ERRIE I2C_CR1_ERRIE /*!< Error interrupts enable */ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_PERIPHERAL_MODE Peripheral Mode + * @{ + */ +#define LL_I2C_MODE_I2C 0x00000000U /*!< I2C Master or Slave mode */ +#define LL_I2C_MODE_SMBUS_HOST I2C_CR1_SMBHEN /*!< SMBus Host address acknowledge */ +#define LL_I2C_MODE_SMBUS_DEVICE 0x00000000U /*!< SMBus Device default mode (Default address not acknowledge) */ +#define LL_I2C_MODE_SMBUS_DEVICE_ARP I2C_CR1_SMBDEN /*!< SMBus Device Default address acknowledge */ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_ANALOGFILTER_SELECTION Analog Filter Selection + * @{ + */ +#define LL_I2C_ANALOGFILTER_ENABLE 0x00000000U /*!< Analog filter is enabled. */ +#define LL_I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF /*!< Analog filter is disabled. */ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_ADDRESSING_MODE Master Addressing Mode + * @{ + */ +#define LL_I2C_ADDRESSING_MODE_7BIT 0x00000000U /*!< Master operates in 7-bit addressing mode. */ +#define LL_I2C_ADDRESSING_MODE_10BIT I2C_CR2_ADD10 /*!< Master operates in 10-bit addressing mode.*/ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_OWNADDRESS1 Own Address 1 Length + * @{ + */ +#define LL_I2C_OWNADDRESS1_7BIT 0x00000000U /*!< Own address 1 is a 7-bit address. */ +#define LL_I2C_OWNADDRESS1_10BIT I2C_OAR1_OA1MODE /*!< Own address 1 is a 10-bit address.*/ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_OWNADDRESS2 Own Address 2 Masks + * @{ + */ +#define LL_I2C_OWNADDRESS2_NOMASK I2C_OAR2_OA2NOMASK /*!< Own Address2 No mask. */ +#define LL_I2C_OWNADDRESS2_MASK01 I2C_OAR2_OA2MASK01 /*!< Only Address2 bits[7:2] are compared. */ +#define LL_I2C_OWNADDRESS2_MASK02 I2C_OAR2_OA2MASK02 /*!< Only Address2 bits[7:3] are compared. */ +#define LL_I2C_OWNADDRESS2_MASK03 I2C_OAR2_OA2MASK03 /*!< Only Address2 bits[7:4] are compared. */ +#define LL_I2C_OWNADDRESS2_MASK04 I2C_OAR2_OA2MASK04 /*!< Only Address2 bits[7:5] are compared. */ +#define LL_I2C_OWNADDRESS2_MASK05 I2C_OAR2_OA2MASK05 /*!< Only Address2 bits[7:6] are compared. */ +#define LL_I2C_OWNADDRESS2_MASK06 I2C_OAR2_OA2MASK06 /*!< Only Address2 bits[7] are compared. */ +#define LL_I2C_OWNADDRESS2_MASK07 I2C_OAR2_OA2MASK07 /*!< No comparison is done. All Address2 are acknowledged.*/ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_I2C_ACKNOWLEDGE Acknowledge Generation + * @{ + */ +#define LL_I2C_ACK 0x00000000U /*!< ACK is sent after current received byte. */ +#define LL_I2C_NACK I2C_CR2_NACK /*!< NACK is sent after current received byte.*/ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_ADDRSLAVE Slave Address Length + * @{ + */ +#define LL_I2C_ADDRSLAVE_7BIT 0x00000000U /*!< Slave Address in 7-bit. */ +#define LL_I2C_ADDRSLAVE_10BIT I2C_CR2_ADD10 /*!< Slave Address in 10-bit.*/ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_REQUEST Transfer Request Direction + * @{ + */ +#define LL_I2C_REQUEST_WRITE 0x00000000U /*!< Master request a write transfer. */ +#define LL_I2C_REQUEST_READ I2C_CR2_RD_WRN /*!< Master request a read transfer. */ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_MODE Transfer End Mode + * @{ + */ +#define LL_I2C_MODE_RELOAD I2C_CR2_RELOAD /*!< Enable I2C Reload mode. */ +#define LL_I2C_MODE_AUTOEND I2C_CR2_AUTOEND /*!< Enable I2C Automatic end mode with no HW PEC comparison. */ +#define LL_I2C_MODE_SOFTEND 0x00000000U /*!< Enable I2C Software end mode with no HW PEC comparison. */ +#define LL_I2C_MODE_SMBUS_RELOAD LL_I2C_MODE_RELOAD /*!< Enable SMBUS Automatic end mode with HW PEC comparison. */ +#define LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC LL_I2C_MODE_AUTOEND /*!< Enable SMBUS Automatic end mode with HW PEC comparison. */ +#define LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC LL_I2C_MODE_SOFTEND /*!< Enable SMBUS Software end mode with HW PEC comparison. */ +#define LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC (uint32_t)(LL_I2C_MODE_AUTOEND | I2C_CR2_PECBYTE) /*!< Enable SMBUS Automatic end mode with HW PEC comparison. */ +#define LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC (uint32_t)(LL_I2C_MODE_SOFTEND | I2C_CR2_PECBYTE) /*!< Enable SMBUS Software end mode with HW PEC comparison. */ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_GENERATE Start And Stop Generation + * @{ + */ +#define LL_I2C_GENERATE_NOSTARTSTOP 0x00000000U /*!< Don't Generate Stop and Start condition. */ +#define LL_I2C_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP) /*!< Generate Stop condition (Size should be set to 0). */ +#define LL_I2C_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN) /*!< Generate Start for read request. */ +#define LL_I2C_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START) /*!< Generate Start for write request. */ +#define LL_I2C_GENERATE_RESTART_7BIT_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN) /*!< Generate Restart for read request, slave 7Bit address. */ +#define LL_I2C_GENERATE_RESTART_7BIT_WRITE (uint32_t)(0x80000000U | I2C_CR2_START) /*!< Generate Restart for write request, slave 7Bit address. */ +#define LL_I2C_GENERATE_RESTART_10BIT_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN | I2C_CR2_HEAD10R) /*!< Generate Restart for read request, slave 10Bit address. */ +#define LL_I2C_GENERATE_RESTART_10BIT_WRITE (uint32_t)(0x80000000U | I2C_CR2_START) /*!< Generate Restart for write request, slave 10Bit address.*/ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_DIRECTION Read Write Direction + * @{ + */ +#define LL_I2C_DIRECTION_WRITE 0x00000000U /*!< Write transfer request by master, slave enters receiver mode. */ +#define LL_I2C_DIRECTION_READ I2C_ISR_DIR /*!< Read transfer request by master, slave enters transmitter mode.*/ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_DMA_REG_DATA DMA Register Data + * @{ + */ +#define LL_I2C_DMA_REG_DATA_TRANSMIT 0x00000000U /*!< Get address of data register used for transmission */ +#define LL_I2C_DMA_REG_DATA_RECEIVE 0x00000001U /*!< Get address of data register used for reception */ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_SMBUS_TIMEOUTA_MODE SMBus TimeoutA Mode SCL SDA Timeout + * @{ + */ +#define LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW 0x00000000U /*!< TimeoutA is used to detect SCL low level timeout. */ +#define LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH I2C_TIMEOUTR_TIDLE /*!< TimeoutA is used to detect both SCL and SDA high level timeout.*/ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_SMBUS_TIMEOUT_SELECTION SMBus Timeout Selection + * @{ + */ +#define LL_I2C_SMBUS_TIMEOUTA I2C_TIMEOUTR_TIMOUTEN /*!< TimeoutA enable bit */ +#define LL_I2C_SMBUS_TIMEOUTB I2C_TIMEOUTR_TEXTEN /*!< TimeoutB (extended clock) enable bit */ +#define LL_I2C_SMBUS_ALL_TIMEOUT (uint32_t)(I2C_TIMEOUTR_TIMOUTEN | I2C_TIMEOUTR_TEXTEN) /*!< TimeoutA and TimeoutB (extended clock) enable bits */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup I2C_LL_Exported_Macros I2C Exported Macros + * @{ + */ + +/** @defgroup I2C_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in I2C register + * @param __INSTANCE__ I2C Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_I2C_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in I2C register + * @param __INSTANCE__ I2C Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_I2C_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** @defgroup I2C_LL_EM_CONVERT_TIMINGS Convert SDA SCL timings + * @{ + */ +/** + * @brief Configure the SDA setup, hold time and the SCL high, low period. + * @param __PRESCALER__ This parameter must be a value between Min_Data=0 and Max_Data=0xF. + * @param __DATA_SETUP_TIME__ This parameter must be a value between Min_Data=0 and Max_Data=0xF. (tscldel = (SCLDEL+1)xtpresc) + * @param __DATA_HOLD_TIME__ This parameter must be a value between Min_Data=0 and Max_Data=0xF. (tsdadel = SDADELxtpresc) + * @param __CLOCK_HIGH_PERIOD__ This parameter must be a value between Min_Data=0 and Max_Data=0xFF. (tsclh = (SCLH+1)xtpresc) + * @param __CLOCK_LOW_PERIOD__ This parameter must be a value between Min_Data=0 and Max_Data=0xFF. (tscll = (SCLL+1)xtpresc) + * @retval Value between Min_Data=0 and Max_Data=0xFFFFFFFF + */ +#define __LL_I2C_CONVERT_TIMINGS(__PRESCALER__, __DATA_SETUP_TIME__, __DATA_HOLD_TIME__, __CLOCK_HIGH_PERIOD__, __CLOCK_LOW_PERIOD__) \ + ((((uint32_t)(__PRESCALER__) << I2C_TIMINGR_PRESC_Pos) & I2C_TIMINGR_PRESC) | \ + (((uint32_t)(__DATA_SETUP_TIME__) << I2C_TIMINGR_SCLDEL_Pos) & I2C_TIMINGR_SCLDEL) | \ + (((uint32_t)(__DATA_HOLD_TIME__) << I2C_TIMINGR_SDADEL_Pos) & I2C_TIMINGR_SDADEL) | \ + (((uint32_t)(__CLOCK_HIGH_PERIOD__) << I2C_TIMINGR_SCLH_Pos) & I2C_TIMINGR_SCLH) | \ + (((uint32_t)(__CLOCK_LOW_PERIOD__) << I2C_TIMINGR_SCLL_Pos) & I2C_TIMINGR_SCLL)) +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup I2C_LL_Exported_Functions I2C Exported Functions + * @{ + */ + +/** @defgroup I2C_LL_EF_Configuration Configuration + * @{ + */ + +/** + * @brief Enable I2C peripheral (PE = 1). + * @rmtoll CR1 PE LL_I2C_Enable + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_Enable(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_PE); +} + +/** + * @brief Disable I2C peripheral (PE = 0). + * @note When PE = 0, the I2C SCL and SDA lines are released. + * Internal state machines and status bits are put back to their reset value. + * When cleared, PE must be kept low for at least 3 APB clock cycles. + * @rmtoll CR1 PE LL_I2C_Disable + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_Disable(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_PE); +} + +/** + * @brief Check if the I2C peripheral is enabled or disabled. + * @rmtoll CR1 PE LL_I2C_IsEnabled + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabled(I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR1, I2C_CR1_PE) == (I2C_CR1_PE)) ? 1UL : 0UL); +} + +/** + * @brief Configure Noise Filters (Analog and Digital). + * @note If the analog filter is also enabled, the digital filter is added to analog filter. + * The filters can only be programmed when the I2C is disabled (PE = 0). + * @rmtoll CR1 ANFOFF LL_I2C_ConfigFilters\n + * CR1 DNF LL_I2C_ConfigFilters + * @param I2Cx I2C Instance. + * @param AnalogFilter This parameter can be one of the following values: + * @arg @ref LL_I2C_ANALOGFILTER_ENABLE + * @arg @ref LL_I2C_ANALOGFILTER_DISABLE + * @param DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled) and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk). + * This parameter is used to configure the digital noise filter on SDA and SCL input. + * The digital filter will filter spikes with a length of up to DNF[3:0]*ti2cclk. + * @retval None + */ +__STATIC_INLINE void LL_I2C_ConfigFilters(I2C_TypeDef *I2Cx, uint32_t AnalogFilter, uint32_t DigitalFilter) +{ + MODIFY_REG(I2Cx->CR1, I2C_CR1_ANFOFF | I2C_CR1_DNF, AnalogFilter | (DigitalFilter << I2C_CR1_DNF_Pos)); +} + +/** + * @brief Configure Digital Noise Filter. + * @note If the analog filter is also enabled, the digital filter is added to analog filter. + * This filter can only be programmed when the I2C is disabled (PE = 0). + * @rmtoll CR1 DNF LL_I2C_SetDigitalFilter + * @param I2Cx I2C Instance. + * @param DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled) and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk). + * This parameter is used to configure the digital noise filter on SDA and SCL input. + * The digital filter will filter spikes with a length of up to DNF[3:0]*ti2cclk. + * @retval None + */ +__STATIC_INLINE void LL_I2C_SetDigitalFilter(I2C_TypeDef *I2Cx, uint32_t DigitalFilter) +{ + MODIFY_REG(I2Cx->CR1, I2C_CR1_DNF, DigitalFilter << I2C_CR1_DNF_Pos); +} + +/** + * @brief Get the current Digital Noise Filter configuration. + * @rmtoll CR1 DNF LL_I2C_GetDigitalFilter + * @param I2Cx I2C Instance. + * @retval Value between Min_Data=0x0 and Max_Data=0xF + */ +__STATIC_INLINE uint32_t LL_I2C_GetDigitalFilter(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_DNF) >> I2C_CR1_DNF_Pos); +} + +/** + * @brief Enable Analog Noise Filter. + * @note This filter can only be programmed when the I2C is disabled (PE = 0). + * @rmtoll CR1 ANFOFF LL_I2C_EnableAnalogFilter + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableAnalogFilter(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_ANFOFF); +} + +/** + * @brief Disable Analog Noise Filter. + * @note This filter can only be programmed when the I2C is disabled (PE = 0). + * @rmtoll CR1 ANFOFF LL_I2C_DisableAnalogFilter + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableAnalogFilter(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_ANFOFF); +} + +/** + * @brief Check if Analog Noise Filter is enabled or disabled. + * @rmtoll CR1 ANFOFF LL_I2C_IsEnabledAnalogFilter + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledAnalogFilter(I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR1, I2C_CR1_ANFOFF) != (I2C_CR1_ANFOFF)) ? 1UL : 0UL); +} + +/** + * @brief Enable DMA transmission requests. + * @rmtoll CR1 TXDMAEN LL_I2C_EnableDMAReq_TX + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableDMAReq_TX(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN); +} + +/** + * @brief Disable DMA transmission requests. + * @rmtoll CR1 TXDMAEN LL_I2C_DisableDMAReq_TX + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableDMAReq_TX(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN); +} + +/** + * @brief Check if DMA transmission requests are enabled or disabled. + * @rmtoll CR1 TXDMAEN LL_I2C_IsEnabledDMAReq_TX + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_TX(I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN) == (I2C_CR1_TXDMAEN)) ? 1UL : 0UL); +} + +/** + * @brief Enable DMA reception requests. + * @rmtoll CR1 RXDMAEN LL_I2C_EnableDMAReq_RX + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableDMAReq_RX(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN); +} + +/** + * @brief Disable DMA reception requests. + * @rmtoll CR1 RXDMAEN LL_I2C_DisableDMAReq_RX + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableDMAReq_RX(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN); +} + +/** + * @brief Check if DMA reception requests are enabled or disabled. + * @rmtoll CR1 RXDMAEN LL_I2C_IsEnabledDMAReq_RX + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX(I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN) == (I2C_CR1_RXDMAEN)) ? 1UL : 0UL); +} + +/** + * @brief Get the data register address used for DMA transfer + * @rmtoll TXDR TXDATA LL_I2C_DMA_GetRegAddr\n + * RXDR RXDATA LL_I2C_DMA_GetRegAddr + * @param I2Cx I2C Instance + * @param Direction This parameter can be one of the following values: + * @arg @ref LL_I2C_DMA_REG_DATA_TRANSMIT + * @arg @ref LL_I2C_DMA_REG_DATA_RECEIVE + * @retval Address of data register + */ +__STATIC_INLINE uint32_t LL_I2C_DMA_GetRegAddr(I2C_TypeDef *I2Cx, uint32_t Direction) +{ + uint32_t data_reg_addr; + + if (Direction == LL_I2C_DMA_REG_DATA_TRANSMIT) + { + /* return address of TXDR register */ + data_reg_addr = (uint32_t) &(I2Cx->TXDR); + } + else + { + /* return address of RXDR register */ + data_reg_addr = (uint32_t) &(I2Cx->RXDR); + } + + return data_reg_addr; +} + +/** + * @brief Enable Clock stretching. + * @note This bit can only be programmed when the I2C is disabled (PE = 0). + * @rmtoll CR1 NOSTRETCH LL_I2C_EnableClockStretching + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableClockStretching(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH); +} + +/** + * @brief Disable Clock stretching. + * @note This bit can only be programmed when the I2C is disabled (PE = 0). + * @rmtoll CR1 NOSTRETCH LL_I2C_DisableClockStretching + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableClockStretching(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH); +} + +/** + * @brief Check if Clock stretching is enabled or disabled. + * @rmtoll CR1 NOSTRETCH LL_I2C_IsEnabledClockStretching + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledClockStretching(I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH) != (I2C_CR1_NOSTRETCH)) ? 1UL : 0UL); +} + +/** + * @brief Enable hardware byte control in slave mode. + * @rmtoll CR1 SBC LL_I2C_EnableSlaveByteControl + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableSlaveByteControl(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_SBC); +} + +/** + * @brief Disable hardware byte control in slave mode. + * @rmtoll CR1 SBC LL_I2C_DisableSlaveByteControl + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableSlaveByteControl(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_SBC); +} + +/** + * @brief Check if hardware byte control in slave mode is enabled or disabled. + * @rmtoll CR1 SBC LL_I2C_IsEnabledSlaveByteControl + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledSlaveByteControl(I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR1, I2C_CR1_SBC) == (I2C_CR1_SBC)) ? 1UL : 0UL); +} + +/** + * @brief Enable Wakeup from STOP. + * @note Macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not + * WakeUpFromStop feature is supported by the I2Cx Instance. + * @note This bit can only be programmed when Digital Filter is disabled. + * @rmtoll CR1 WUPEN LL_I2C_EnableWakeUpFromStop + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableWakeUpFromStop(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_WUPEN); +} + +/** + * @brief Disable Wakeup from STOP. + * @note Macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not + * WakeUpFromStop feature is supported by the I2Cx Instance. + * @rmtoll CR1 WUPEN LL_I2C_DisableWakeUpFromStop + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableWakeUpFromStop(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_WUPEN); +} + +/** + * @brief Check if Wakeup from STOP is enabled or disabled. + * @note Macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not + * WakeUpFromStop feature is supported by the I2Cx Instance. + * @rmtoll CR1 WUPEN LL_I2C_IsEnabledWakeUpFromStop + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledWakeUpFromStop(I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR1, I2C_CR1_WUPEN) == (I2C_CR1_WUPEN)) ? 1UL : 0UL); +} + +/** + * @brief Enable General Call. + * @note When enabled the Address 0x00 is ACKed. + * @rmtoll CR1 GCEN LL_I2C_EnableGeneralCall + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableGeneralCall(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_GCEN); +} + +/** + * @brief Disable General Call. + * @note When disabled the Address 0x00 is NACKed. + * @rmtoll CR1 GCEN LL_I2C_DisableGeneralCall + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableGeneralCall(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_GCEN); +} + +/** + * @brief Check if General Call is enabled or disabled. + * @rmtoll CR1 GCEN LL_I2C_IsEnabledGeneralCall + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledGeneralCall(I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR1, I2C_CR1_GCEN) == (I2C_CR1_GCEN)) ? 1UL : 0UL); +} + +/** + * @brief Configure the Master to operate in 7-bit or 10-bit addressing mode. + * @note Changing this bit is not allowed, when the START bit is set. + * @rmtoll CR2 ADD10 LL_I2C_SetMasterAddressingMode + * @param I2Cx I2C Instance. + * @param AddressingMode This parameter can be one of the following values: + * @arg @ref LL_I2C_ADDRESSING_MODE_7BIT + * @arg @ref LL_I2C_ADDRESSING_MODE_10BIT + * @retval None + */ +__STATIC_INLINE void LL_I2C_SetMasterAddressingMode(I2C_TypeDef *I2Cx, uint32_t AddressingMode) +{ + MODIFY_REG(I2Cx->CR2, I2C_CR2_ADD10, AddressingMode); +} + +/** + * @brief Get the Master addressing mode. + * @rmtoll CR2 ADD10 LL_I2C_GetMasterAddressingMode + * @param I2Cx I2C Instance. + * @retval Returned value can be one of the following values: + * @arg @ref LL_I2C_ADDRESSING_MODE_7BIT + * @arg @ref LL_I2C_ADDRESSING_MODE_10BIT + */ +__STATIC_INLINE uint32_t LL_I2C_GetMasterAddressingMode(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_ADD10)); +} + +/** + * @brief Set the Own Address1. + * @rmtoll OAR1 OA1 LL_I2C_SetOwnAddress1\n + * OAR1 OA1MODE LL_I2C_SetOwnAddress1 + * @param I2Cx I2C Instance. + * @param OwnAddress1 This parameter must be a value between Min_Data=0 and Max_Data=0x3FF. + * @param OwnAddrSize This parameter can be one of the following values: + * @arg @ref LL_I2C_OWNADDRESS1_7BIT + * @arg @ref LL_I2C_OWNADDRESS1_10BIT + * @retval None + */ +__STATIC_INLINE void LL_I2C_SetOwnAddress1(I2C_TypeDef *I2Cx, uint32_t OwnAddress1, uint32_t OwnAddrSize) +{ + MODIFY_REG(I2Cx->OAR1, I2C_OAR1_OA1 | I2C_OAR1_OA1MODE, OwnAddress1 | OwnAddrSize); +} + +/** + * @brief Enable acknowledge on Own Address1 match address. + * @rmtoll OAR1 OA1EN LL_I2C_EnableOwnAddress1 + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableOwnAddress1(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN); +} + +/** + * @brief Disable acknowledge on Own Address1 match address. + * @rmtoll OAR1 OA1EN LL_I2C_DisableOwnAddress1 + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableOwnAddress1(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN); +} + +/** + * @brief Check if Own Address1 acknowledge is enabled or disabled. + * @rmtoll OAR1 OA1EN LL_I2C_IsEnabledOwnAddress1 + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress1(I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN) == (I2C_OAR1_OA1EN)) ? 1UL : 0UL); +} + +/** + * @brief Set the 7bits Own Address2. + * @note This action has no effect if own address2 is enabled. + * @rmtoll OAR2 OA2 LL_I2C_SetOwnAddress2\n + * OAR2 OA2MSK LL_I2C_SetOwnAddress2 + * @param I2Cx I2C Instance. + * @param OwnAddress2 Value between Min_Data=0 and Max_Data=0x7F. + * @param OwnAddrMask This parameter can be one of the following values: + * @arg @ref LL_I2C_OWNADDRESS2_NOMASK + * @arg @ref LL_I2C_OWNADDRESS2_MASK01 + * @arg @ref LL_I2C_OWNADDRESS2_MASK02 + * @arg @ref LL_I2C_OWNADDRESS2_MASK03 + * @arg @ref LL_I2C_OWNADDRESS2_MASK04 + * @arg @ref LL_I2C_OWNADDRESS2_MASK05 + * @arg @ref LL_I2C_OWNADDRESS2_MASK06 + * @arg @ref LL_I2C_OWNADDRESS2_MASK07 + * @retval None + */ +__STATIC_INLINE void LL_I2C_SetOwnAddress2(I2C_TypeDef *I2Cx, uint32_t OwnAddress2, uint32_t OwnAddrMask) +{ + MODIFY_REG(I2Cx->OAR2, I2C_OAR2_OA2 | I2C_OAR2_OA2MSK, OwnAddress2 | OwnAddrMask); +} + +/** + * @brief Enable acknowledge on Own Address2 match address. + * @rmtoll OAR2 OA2EN LL_I2C_EnableOwnAddress2 + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableOwnAddress2(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN); +} + +/** + * @brief Disable acknowledge on Own Address2 match address. + * @rmtoll OAR2 OA2EN LL_I2C_DisableOwnAddress2 + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableOwnAddress2(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN); +} + +/** + * @brief Check if Own Address1 acknowledge is enabled or disabled. + * @rmtoll OAR2 OA2EN LL_I2C_IsEnabledOwnAddress2 + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress2(I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN) == (I2C_OAR2_OA2EN)) ? 1UL : 0UL); +} + +/** + * @brief Configure the SDA setup, hold time and the SCL high, low period. + * @note This bit can only be programmed when the I2C is disabled (PE = 0). + * @rmtoll TIMINGR TIMINGR LL_I2C_SetTiming + * @param I2Cx I2C Instance. + * @param Timing This parameter must be a value between Min_Data=0 and Max_Data=0xFFFFFFFF. + * @note This parameter is computed with the STM32CubeMX Tool. + * @retval None + */ +__STATIC_INLINE void LL_I2C_SetTiming(I2C_TypeDef *I2Cx, uint32_t Timing) +{ + WRITE_REG(I2Cx->TIMINGR, Timing); +} + +/** + * @brief Get the Timing Prescaler setting. + * @rmtoll TIMINGR PRESC LL_I2C_GetTimingPrescaler + * @param I2Cx I2C Instance. + * @retval Value between Min_Data=0x0 and Max_Data=0xF + */ +__STATIC_INLINE uint32_t LL_I2C_GetTimingPrescaler(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_PRESC) >> I2C_TIMINGR_PRESC_Pos); +} + +/** + * @brief Get the SCL low period setting. + * @rmtoll TIMINGR SCLL LL_I2C_GetClockLowPeriod + * @param I2Cx I2C Instance. + * @retval Value between Min_Data=0x00 and Max_Data=0xFF + */ +__STATIC_INLINE uint32_t LL_I2C_GetClockLowPeriod(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLL) >> I2C_TIMINGR_SCLL_Pos); +} + +/** + * @brief Get the SCL high period setting. + * @rmtoll TIMINGR SCLH LL_I2C_GetClockHighPeriod + * @param I2Cx I2C Instance. + * @retval Value between Min_Data=0x00 and Max_Data=0xFF + */ +__STATIC_INLINE uint32_t LL_I2C_GetClockHighPeriod(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLH) >> I2C_TIMINGR_SCLH_Pos); +} + +/** + * @brief Get the SDA hold time. + * @rmtoll TIMINGR SDADEL LL_I2C_GetDataHoldTime + * @param I2Cx I2C Instance. + * @retval Value between Min_Data=0x0 and Max_Data=0xF + */ +__STATIC_INLINE uint32_t LL_I2C_GetDataHoldTime(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SDADEL) >> I2C_TIMINGR_SDADEL_Pos); +} + +/** + * @brief Get the SDA setup time. + * @rmtoll TIMINGR SCLDEL LL_I2C_GetDataSetupTime + * @param I2Cx I2C Instance. + * @retval Value between Min_Data=0x0 and Max_Data=0xF + */ +__STATIC_INLINE uint32_t LL_I2C_GetDataSetupTime(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLDEL) >> I2C_TIMINGR_SCLDEL_Pos); +} + +/** + * @brief Configure peripheral mode. + * @note Macro IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll CR1 SMBHEN LL_I2C_SetMode\n + * CR1 SMBDEN LL_I2C_SetMode + * @param I2Cx I2C Instance. + * @param PeripheralMode This parameter can be one of the following values: + * @arg @ref LL_I2C_MODE_I2C + * @arg @ref LL_I2C_MODE_SMBUS_HOST + * @arg @ref LL_I2C_MODE_SMBUS_DEVICE + * @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP + * @retval None + */ +__STATIC_INLINE void LL_I2C_SetMode(I2C_TypeDef *I2Cx, uint32_t PeripheralMode) +{ + MODIFY_REG(I2Cx->CR1, I2C_CR1_SMBHEN | I2C_CR1_SMBDEN, PeripheralMode); +} + +/** + * @brief Get peripheral mode. + * @note Macro IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll CR1 SMBHEN LL_I2C_GetMode\n + * CR1 SMBDEN LL_I2C_GetMode + * @param I2Cx I2C Instance. + * @retval Returned value can be one of the following values: + * @arg @ref LL_I2C_MODE_I2C + * @arg @ref LL_I2C_MODE_SMBUS_HOST + * @arg @ref LL_I2C_MODE_SMBUS_DEVICE + * @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP + */ +__STATIC_INLINE uint32_t LL_I2C_GetMode(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_SMBHEN | I2C_CR1_SMBDEN)); +} + +/** + * @brief Enable SMBus alert (Host or Device mode) + * @note Macro IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @note SMBus Device mode: + * - SMBus Alert pin is drived low and + * Alert Response Address Header acknowledge is enabled. + * SMBus Host mode: + * - SMBus Alert pin management is supported. + * @rmtoll CR1 ALERTEN LL_I2C_EnableSMBusAlert + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableSMBusAlert(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_ALERTEN); +} + +/** + * @brief Disable SMBus alert (Host or Device mode) + * @note Macro IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @note SMBus Device mode: + * - SMBus Alert pin is not drived (can be used as a standard GPIO) and + * Alert Response Address Header acknowledge is disabled. + * SMBus Host mode: + * - SMBus Alert pin management is not supported. + * @rmtoll CR1 ALERTEN LL_I2C_DisableSMBusAlert + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableSMBusAlert(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_ALERTEN); +} + +/** + * @brief Check if SMBus alert (Host or Device mode) is enabled or disabled. + * @note Macro IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll CR1 ALERTEN LL_I2C_IsEnabledSMBusAlert + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusAlert(I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR1, I2C_CR1_ALERTEN) == (I2C_CR1_ALERTEN)) ? 1UL : 0UL); +} + +/** + * @brief Enable SMBus Packet Error Calculation (PEC). + * @note Macro IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll CR1 PECEN LL_I2C_EnableSMBusPEC + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableSMBusPEC(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_PECEN); +} + +/** + * @brief Disable SMBus Packet Error Calculation (PEC). + * @note Macro IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll CR1 PECEN LL_I2C_DisableSMBusPEC + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableSMBusPEC(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_PECEN); +} + +/** + * @brief Check if SMBus Packet Error Calculation (PEC) is enabled or disabled. + * @note Macro IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll CR1 PECEN LL_I2C_IsEnabledSMBusPEC + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPEC(I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR1, I2C_CR1_PECEN) == (I2C_CR1_PECEN)) ? 1UL : 0UL); +} + +/** + * @brief Configure the SMBus Clock Timeout. + * @note Macro IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @note This configuration can only be programmed when associated Timeout is disabled (TimeoutA and/orTimeoutB). + * @rmtoll TIMEOUTR TIMEOUTA LL_I2C_ConfigSMBusTimeout\n + * TIMEOUTR TIDLE LL_I2C_ConfigSMBusTimeout\n + * TIMEOUTR TIMEOUTB LL_I2C_ConfigSMBusTimeout + * @param I2Cx I2C Instance. + * @param TimeoutA This parameter must be a value between Min_Data=0 and Max_Data=0xFFF. + * @param TimeoutAMode This parameter can be one of the following values: + * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW + * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH + * @param TimeoutB + * @retval None + */ +__STATIC_INLINE void LL_I2C_ConfigSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t TimeoutA, uint32_t TimeoutAMode, + uint32_t TimeoutB) +{ + MODIFY_REG(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTA | I2C_TIMEOUTR_TIDLE | I2C_TIMEOUTR_TIMEOUTB, + TimeoutA | TimeoutAMode | (TimeoutB << I2C_TIMEOUTR_TIMEOUTB_Pos)); +} + +/** + * @brief Configure the SMBus Clock TimeoutA (SCL low timeout or SCL and SDA high timeout depends on TimeoutA mode). + * @note Macro IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @note These bits can only be programmed when TimeoutA is disabled. + * @rmtoll TIMEOUTR TIMEOUTA LL_I2C_SetSMBusTimeoutA + * @param I2Cx I2C Instance. + * @param TimeoutA This parameter must be a value between Min_Data=0 and Max_Data=0xFFF. + * @retval None + */ +__STATIC_INLINE void LL_I2C_SetSMBusTimeoutA(I2C_TypeDef *I2Cx, uint32_t TimeoutA) +{ + WRITE_REG(I2Cx->TIMEOUTR, TimeoutA); +} + +/** + * @brief Get the SMBus Clock TimeoutA setting. + * @note Macro IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll TIMEOUTR TIMEOUTA LL_I2C_GetSMBusTimeoutA + * @param I2Cx I2C Instance. + * @retval Value between Min_Data=0 and Max_Data=0xFFF + */ +__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutA(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTA)); +} + +/** + * @brief Set the SMBus Clock TimeoutA mode. + * @note Macro IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @note This bit can only be programmed when TimeoutA is disabled. + * @rmtoll TIMEOUTR TIDLE LL_I2C_SetSMBusTimeoutAMode + * @param I2Cx I2C Instance. + * @param TimeoutAMode This parameter can be one of the following values: + * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW + * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH + * @retval None + */ +__STATIC_INLINE void LL_I2C_SetSMBusTimeoutAMode(I2C_TypeDef *I2Cx, uint32_t TimeoutAMode) +{ + WRITE_REG(I2Cx->TIMEOUTR, TimeoutAMode); +} + +/** + * @brief Get the SMBus Clock TimeoutA mode. + * @note Macro IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll TIMEOUTR TIDLE LL_I2C_GetSMBusTimeoutAMode + * @param I2Cx I2C Instance. + * @retval Returned value can be one of the following values: + * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW + * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH + */ +__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutAMode(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIDLE)); +} + +/** + * @brief Configure the SMBus Extended Cumulative Clock TimeoutB (Master or Slave mode). + * @note Macro IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @note These bits can only be programmed when TimeoutB is disabled. + * @rmtoll TIMEOUTR TIMEOUTB LL_I2C_SetSMBusTimeoutB + * @param I2Cx I2C Instance. + * @param TimeoutB This parameter must be a value between Min_Data=0 and Max_Data=0xFFF. + * @retval None + */ +__STATIC_INLINE void LL_I2C_SetSMBusTimeoutB(I2C_TypeDef *I2Cx, uint32_t TimeoutB) +{ + WRITE_REG(I2Cx->TIMEOUTR, TimeoutB << I2C_TIMEOUTR_TIMEOUTB_Pos); +} + +/** + * @brief Get the SMBus Extended Cumulative Clock TimeoutB setting. + * @note Macro IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll TIMEOUTR TIMEOUTB LL_I2C_GetSMBusTimeoutB + * @param I2Cx I2C Instance. + * @retval Value between Min_Data=0 and Max_Data=0xFFF + */ +__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutB(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTB) >> I2C_TIMEOUTR_TIMEOUTB_Pos); +} + +/** + * @brief Enable the SMBus Clock Timeout. + * @note Macro IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll TIMEOUTR TIMOUTEN LL_I2C_EnableSMBusTimeout\n + * TIMEOUTR TEXTEN LL_I2C_EnableSMBusTimeout + * @param I2Cx I2C Instance. + * @param ClockTimeout This parameter can be one of the following values: + * @arg @ref LL_I2C_SMBUS_TIMEOUTA + * @arg @ref LL_I2C_SMBUS_TIMEOUTB + * @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout) +{ + SET_BIT(I2Cx->TIMEOUTR, ClockTimeout); +} + +/** + * @brief Disable the SMBus Clock Timeout. + * @note Macro IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll TIMEOUTR TIMOUTEN LL_I2C_DisableSMBusTimeout\n + * TIMEOUTR TEXTEN LL_I2C_DisableSMBusTimeout + * @param I2Cx I2C Instance. + * @param ClockTimeout This parameter can be one of the following values: + * @arg @ref LL_I2C_SMBUS_TIMEOUTA + * @arg @ref LL_I2C_SMBUS_TIMEOUTB + * @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout) +{ + CLEAR_BIT(I2Cx->TIMEOUTR, ClockTimeout); +} + +/** + * @brief Check if the SMBus Clock Timeout is enabled or disabled. + * @note Macro IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll TIMEOUTR TIMOUTEN LL_I2C_IsEnabledSMBusTimeout\n + * TIMEOUTR TEXTEN LL_I2C_IsEnabledSMBusTimeout + * @param I2Cx I2C Instance. + * @param ClockTimeout This parameter can be one of the following values: + * @arg @ref LL_I2C_SMBUS_TIMEOUTA + * @arg @ref LL_I2C_SMBUS_TIMEOUTB + * @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout) +{ + return ((READ_BIT(I2Cx->TIMEOUTR, (I2C_TIMEOUTR_TIMOUTEN | I2C_TIMEOUTR_TEXTEN)) == (ClockTimeout)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup I2C_LL_EF_IT_Management IT_Management + * @{ + */ + +/** + * @brief Enable TXIS interrupt. + * @rmtoll CR1 TXIE LL_I2C_EnableIT_TX + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableIT_TX(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_TXIE); +} + +/** + * @brief Disable TXIS interrupt. + * @rmtoll CR1 TXIE LL_I2C_DisableIT_TX + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableIT_TX(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_TXIE); +} + +/** + * @brief Check if the TXIS Interrupt is enabled or disabled. + * @rmtoll CR1 TXIE LL_I2C_IsEnabledIT_TX + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TX(I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR1, I2C_CR1_TXIE) == (I2C_CR1_TXIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable RXNE interrupt. + * @rmtoll CR1 RXIE LL_I2C_EnableIT_RX + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableIT_RX(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_RXIE); +} + +/** + * @brief Disable RXNE interrupt. + * @rmtoll CR1 RXIE LL_I2C_DisableIT_RX + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableIT_RX(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_RXIE); +} + +/** + * @brief Check if the RXNE Interrupt is enabled or disabled. + * @rmtoll CR1 RXIE LL_I2C_IsEnabledIT_RX + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_RX(I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR1, I2C_CR1_RXIE) == (I2C_CR1_RXIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable Address match interrupt (slave mode only). + * @rmtoll CR1 ADDRIE LL_I2C_EnableIT_ADDR + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableIT_ADDR(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_ADDRIE); +} + +/** + * @brief Disable Address match interrupt (slave mode only). + * @rmtoll CR1 ADDRIE LL_I2C_DisableIT_ADDR + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableIT_ADDR(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_ADDRIE); +} + +/** + * @brief Check if Address match interrupt is enabled or disabled. + * @rmtoll CR1 ADDRIE LL_I2C_IsEnabledIT_ADDR + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ADDR(I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR1, I2C_CR1_ADDRIE) == (I2C_CR1_ADDRIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable Not acknowledge received interrupt. + * @rmtoll CR1 NACKIE LL_I2C_EnableIT_NACK + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableIT_NACK(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_NACKIE); +} + +/** + * @brief Disable Not acknowledge received interrupt. + * @rmtoll CR1 NACKIE LL_I2C_DisableIT_NACK + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableIT_NACK(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_NACKIE); +} + +/** + * @brief Check if Not acknowledge received interrupt is enabled or disabled. + * @rmtoll CR1 NACKIE LL_I2C_IsEnabledIT_NACK + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_NACK(I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR1, I2C_CR1_NACKIE) == (I2C_CR1_NACKIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable STOP detection interrupt. + * @rmtoll CR1 STOPIE LL_I2C_EnableIT_STOP + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableIT_STOP(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_STOPIE); +} + +/** + * @brief Disable STOP detection interrupt. + * @rmtoll CR1 STOPIE LL_I2C_DisableIT_STOP + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableIT_STOP(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_STOPIE); +} + +/** + * @brief Check if STOP detection interrupt is enabled or disabled. + * @rmtoll CR1 STOPIE LL_I2C_IsEnabledIT_STOP + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_STOP(I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR1, I2C_CR1_STOPIE) == (I2C_CR1_STOPIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable Transfer Complete interrupt. + * @note Any of these events will generate interrupt : + * Transfer Complete (TC) + * Transfer Complete Reload (TCR) + * @rmtoll CR1 TCIE LL_I2C_EnableIT_TC + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableIT_TC(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_TCIE); +} + +/** + * @brief Disable Transfer Complete interrupt. + * @note Any of these events will generate interrupt : + * Transfer Complete (TC) + * Transfer Complete Reload (TCR) + * @rmtoll CR1 TCIE LL_I2C_DisableIT_TC + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableIT_TC(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_TCIE); +} + +/** + * @brief Check if Transfer Complete interrupt is enabled or disabled. + * @rmtoll CR1 TCIE LL_I2C_IsEnabledIT_TC + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TC(I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR1, I2C_CR1_TCIE) == (I2C_CR1_TCIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable Error interrupts. + * @note Macro IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @note Any of these errors will generate interrupt : + * Arbitration Loss (ARLO) + * Bus Error detection (BERR) + * Overrun/Underrun (OVR) + * SMBus Timeout detection (TIMEOUT) + * SMBus PEC error detection (PECERR) + * SMBus Alert pin event detection (ALERT) + * @rmtoll CR1 ERRIE LL_I2C_EnableIT_ERR + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableIT_ERR(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_ERRIE); +} + +/** + * @brief Disable Error interrupts. + * @note Macro IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @note Any of these errors will generate interrupt : + * Arbitration Loss (ARLO) + * Bus Error detection (BERR) + * Overrun/Underrun (OVR) + * SMBus Timeout detection (TIMEOUT) + * SMBus PEC error detection (PECERR) + * SMBus Alert pin event detection (ALERT) + * @rmtoll CR1 ERRIE LL_I2C_DisableIT_ERR + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableIT_ERR(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_ERRIE); +} + +/** + * @brief Check if Error interrupts are enabled or disabled. + * @rmtoll CR1 ERRIE LL_I2C_IsEnabledIT_ERR + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ERR(I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR1, I2C_CR1_ERRIE) == (I2C_CR1_ERRIE)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup I2C_LL_EF_FLAG_management FLAG_management + * @{ + */ + +/** + * @brief Indicate the status of Transmit data register empty flag. + * @note RESET: When next data is written in Transmit data register. + * SET: When Transmit data register is empty. + * @rmtoll ISR TXE LL_I2C_IsActiveFlag_TXE + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXE(I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->ISR, I2C_ISR_TXE) == (I2C_ISR_TXE)) ? 1UL : 0UL); +} + +/** + * @brief Indicate the status of Transmit interrupt flag. + * @note RESET: When next data is written in Transmit data register. + * SET: When Transmit data register is empty. + * @rmtoll ISR TXIS LL_I2C_IsActiveFlag_TXIS + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXIS(I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->ISR, I2C_ISR_TXIS) == (I2C_ISR_TXIS)) ? 1UL : 0UL); +} + +/** + * @brief Indicate the status of Receive data register not empty flag. + * @note RESET: When Receive data register is read. + * SET: When the received data is copied in Receive data register. + * @rmtoll ISR RXNE LL_I2C_IsActiveFlag_RXNE + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_RXNE(I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->ISR, I2C_ISR_RXNE) == (I2C_ISR_RXNE)) ? 1UL : 0UL); +} + +/** + * @brief Indicate the status of Address matched flag (slave mode). + * @note RESET: Clear default value. + * SET: When the received slave address matched with one of the enabled slave address. + * @rmtoll ISR ADDR LL_I2C_IsActiveFlag_ADDR + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR(I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->ISR, I2C_ISR_ADDR) == (I2C_ISR_ADDR)) ? 1UL : 0UL); +} + +/** + * @brief Indicate the status of Not Acknowledge received flag. + * @note RESET: Clear default value. + * SET: When a NACK is received after a byte transmission. + * @rmtoll ISR NACKF LL_I2C_IsActiveFlag_NACK + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_NACK(I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->ISR, I2C_ISR_NACKF) == (I2C_ISR_NACKF)) ? 1UL : 0UL); +} + +/** + * @brief Indicate the status of Stop detection flag. + * @note RESET: Clear default value. + * SET: When a Stop condition is detected. + * @rmtoll ISR STOPF LL_I2C_IsActiveFlag_STOP + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_STOP(I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->ISR, I2C_ISR_STOPF) == (I2C_ISR_STOPF)) ? 1UL : 0UL); +} + +/** + * @brief Indicate the status of Transfer complete flag (master mode). + * @note RESET: Clear default value. + * SET: When RELOAD=0, AUTOEND=0 and NBYTES date have been transferred. + * @rmtoll ISR TC LL_I2C_IsActiveFlag_TC + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TC(I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->ISR, I2C_ISR_TC) == (I2C_ISR_TC)) ? 1UL : 0UL); +} + +/** + * @brief Indicate the status of Transfer complete flag (master mode). + * @note RESET: Clear default value. + * SET: When RELOAD=1 and NBYTES date have been transferred. + * @rmtoll ISR TCR LL_I2C_IsActiveFlag_TCR + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TCR(I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->ISR, I2C_ISR_TCR) == (I2C_ISR_TCR)) ? 1UL : 0UL); +} + +/** + * @brief Indicate the status of Bus error flag. + * @note RESET: Clear default value. + * SET: When a misplaced Start or Stop condition is detected. + * @rmtoll ISR BERR LL_I2C_IsActiveFlag_BERR + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BERR(I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->ISR, I2C_ISR_BERR) == (I2C_ISR_BERR)) ? 1UL : 0UL); +} + +/** + * @brief Indicate the status of Arbitration lost flag. + * @note RESET: Clear default value. + * SET: When arbitration lost. + * @rmtoll ISR ARLO LL_I2C_IsActiveFlag_ARLO + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ARLO(I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->ISR, I2C_ISR_ARLO) == (I2C_ISR_ARLO)) ? 1UL : 0UL); +} + +/** + * @brief Indicate the status of Overrun/Underrun flag (slave mode). + * @note RESET: Clear default value. + * SET: When an overrun/underrun error occurs (Clock Stretching Disabled). + * @rmtoll ISR OVR LL_I2C_IsActiveFlag_OVR + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR(I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->ISR, I2C_ISR_OVR) == (I2C_ISR_OVR)) ? 1UL : 0UL); +} + +/** + * @brief Indicate the status of SMBus PEC error flag in reception. + * @note Macro IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @note RESET: Clear default value. + * SET: When the received PEC does not match with the PEC register content. + * @rmtoll ISR PECERR LL_I2C_IsActiveSMBusFlag_PECERR + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR(I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->ISR, I2C_ISR_PECERR) == (I2C_ISR_PECERR)) ? 1UL : 0UL); +} + +/** + * @brief Indicate the status of SMBus Timeout detection flag. + * @note Macro IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @note RESET: Clear default value. + * SET: When a timeout or extended clock timeout occurs. + * @rmtoll ISR TIMEOUT LL_I2C_IsActiveSMBusFlag_TIMEOUT + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->ISR, I2C_ISR_TIMEOUT) == (I2C_ISR_TIMEOUT)) ? 1UL : 0UL); +} + +/** + * @brief Indicate the status of SMBus alert flag. + * @note Macro IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @note RESET: Clear default value. + * SET: When SMBus host configuration, SMBus alert enabled and + * a falling edge event occurs on SMBA pin. + * @rmtoll ISR ALERT LL_I2C_IsActiveSMBusFlag_ALERT + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_ALERT(I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->ISR, I2C_ISR_ALERT) == (I2C_ISR_ALERT)) ? 1UL : 0UL); +} + +/** + * @brief Indicate the status of Bus Busy flag. + * @note RESET: Clear default value. + * SET: When a Start condition is detected. + * @rmtoll ISR BUSY LL_I2C_IsActiveFlag_BUSY + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BUSY(I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->ISR, I2C_ISR_BUSY) == (I2C_ISR_BUSY)) ? 1UL : 0UL); +} + +/** + * @brief Clear Address Matched flag. + * @rmtoll ICR ADDRCF LL_I2C_ClearFlag_ADDR + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_ClearFlag_ADDR(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ICR, I2C_ICR_ADDRCF); +} + +/** + * @brief Clear Not Acknowledge flag. + * @rmtoll ICR NACKCF LL_I2C_ClearFlag_NACK + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_ClearFlag_NACK(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ICR, I2C_ICR_NACKCF); +} + +/** + * @brief Clear Stop detection flag. + * @rmtoll ICR STOPCF LL_I2C_ClearFlag_STOP + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_ClearFlag_STOP(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ICR, I2C_ICR_STOPCF); +} + +/** + * @brief Clear Transmit data register empty flag (TXE). + * @note This bit can be clear by software in order to flush the transmit data register (TXDR). + * @rmtoll ISR TXE LL_I2C_ClearFlag_TXE + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_ClearFlag_TXE(I2C_TypeDef *I2Cx) +{ + WRITE_REG(I2Cx->ISR, I2C_ISR_TXE); +} + +/** + * @brief Clear Bus error flag. + * @rmtoll ICR BERRCF LL_I2C_ClearFlag_BERR + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_ClearFlag_BERR(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ICR, I2C_ICR_BERRCF); +} + +/** + * @brief Clear Arbitration lost flag. + * @rmtoll ICR ARLOCF LL_I2C_ClearFlag_ARLO + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_ClearFlag_ARLO(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ICR, I2C_ICR_ARLOCF); +} + +/** + * @brief Clear Overrun/Underrun flag. + * @rmtoll ICR OVRCF LL_I2C_ClearFlag_OVR + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_ClearFlag_OVR(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ICR, I2C_ICR_OVRCF); +} + +/** + * @brief Clear SMBus PEC error flag. + * @note Macro IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll ICR PECCF LL_I2C_ClearSMBusFlag_PECERR + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_ClearSMBusFlag_PECERR(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ICR, I2C_ICR_PECCF); +} + +/** + * @brief Clear SMBus Timeout detection flag. + * @note Macro IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll ICR TIMOUTCF LL_I2C_ClearSMBusFlag_TIMEOUT + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_ClearSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ICR, I2C_ICR_TIMOUTCF); +} + +/** + * @brief Clear SMBus Alert flag. + * @note Macro IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll ICR ALERTCF LL_I2C_ClearSMBusFlag_ALERT + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_ClearSMBusFlag_ALERT(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ICR, I2C_ICR_ALERTCF); +} + +/** + * @} + */ + +/** @defgroup I2C_LL_EF_Data_Management Data_Management + * @{ + */ + +/** + * @brief Enable automatic STOP condition generation (master mode). + * @note Automatic end mode : a STOP condition is automatically sent when NBYTES data are transferred. + * This bit has no effect in slave mode or when RELOAD bit is set. + * @rmtoll CR2 AUTOEND LL_I2C_EnableAutoEndMode + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableAutoEndMode(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR2, I2C_CR2_AUTOEND); +} + +/** + * @brief Disable automatic STOP condition generation (master mode). + * @note Software end mode : TC flag is set when NBYTES data are transferre, stretching SCL low. + * @rmtoll CR2 AUTOEND LL_I2C_DisableAutoEndMode + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableAutoEndMode(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR2, I2C_CR2_AUTOEND); +} + +/** + * @brief Check if automatic STOP condition is enabled or disabled. + * @rmtoll CR2 AUTOEND LL_I2C_IsEnabledAutoEndMode + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledAutoEndMode(I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR2, I2C_CR2_AUTOEND) == (I2C_CR2_AUTOEND)) ? 1UL : 0UL); +} + +/** + * @brief Enable reload mode (master mode). + * @note The transfer is not completed after the NBYTES data transfer, NBYTES will be reloaded when TCR flag is set. + * @rmtoll CR2 RELOAD LL_I2C_EnableReloadMode + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableReloadMode(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR2, I2C_CR2_RELOAD); +} + +/** + * @brief Disable reload mode (master mode). + * @note The transfer is completed after the NBYTES data transfer(STOP or RESTART will follow). + * @rmtoll CR2 RELOAD LL_I2C_DisableReloadMode + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableReloadMode(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR2, I2C_CR2_RELOAD); +} + +/** + * @brief Check if reload mode is enabled or disabled. + * @rmtoll CR2 RELOAD LL_I2C_IsEnabledReloadMode + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledReloadMode(I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR2, I2C_CR2_RELOAD) == (I2C_CR2_RELOAD)) ? 1UL : 0UL); +} + +/** + * @brief Configure the number of bytes for transfer. + * @note Changing these bits when START bit is set is not allowed. + * @rmtoll CR2 NBYTES LL_I2C_SetTransferSize + * @param I2Cx I2C Instance. + * @param TransferSize This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF. + * @retval None + */ +__STATIC_INLINE void LL_I2C_SetTransferSize(I2C_TypeDef *I2Cx, uint32_t TransferSize) +{ + MODIFY_REG(I2Cx->CR2, I2C_CR2_NBYTES, TransferSize << I2C_CR2_NBYTES_Pos); +} + +/** + * @brief Get the number of bytes configured for transfer. + * @rmtoll CR2 NBYTES LL_I2C_GetTransferSize + * @param I2Cx I2C Instance. + * @retval Value between Min_Data=0x0 and Max_Data=0xFF + */ +__STATIC_INLINE uint32_t LL_I2C_GetTransferSize(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_NBYTES) >> I2C_CR2_NBYTES_Pos); +} + +/** + * @brief Prepare the generation of a ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte. + * @note Usage in Slave mode only. + * @rmtoll CR2 NACK LL_I2C_AcknowledgeNextData + * @param I2Cx I2C Instance. + * @param TypeAcknowledge This parameter can be one of the following values: + * @arg @ref LL_I2C_ACK + * @arg @ref LL_I2C_NACK + * @retval None + */ +__STATIC_INLINE void LL_I2C_AcknowledgeNextData(I2C_TypeDef *I2Cx, uint32_t TypeAcknowledge) +{ + MODIFY_REG(I2Cx->CR2, I2C_CR2_NACK, TypeAcknowledge); +} + +/** + * @brief Generate a START or RESTART condition + * @note The START bit can be set even if bus is BUSY or I2C is in slave mode. + * This action has no effect when RELOAD is set. + * @rmtoll CR2 START LL_I2C_GenerateStartCondition + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_GenerateStartCondition(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR2, I2C_CR2_START); +} + +/** + * @brief Generate a STOP condition after the current byte transfer (master mode). + * @rmtoll CR2 STOP LL_I2C_GenerateStopCondition + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_GenerateStopCondition(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR2, I2C_CR2_STOP); +} + +/** + * @brief Enable automatic RESTART Read request condition for 10bit address header (master mode). + * @note The master sends the complete 10bit slave address read sequence : + * Start + 2 bytes 10bit address in Write direction + Restart + first 7 bits of 10bit address in Read direction. + * @rmtoll CR2 HEAD10R LL_I2C_EnableAuto10BitRead + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableAuto10BitRead(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR2, I2C_CR2_HEAD10R); +} + +/** + * @brief Disable automatic RESTART Read request condition for 10bit address header (master mode). + * @note The master only sends the first 7 bits of 10bit address in Read direction. + * @rmtoll CR2 HEAD10R LL_I2C_DisableAuto10BitRead + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableAuto10BitRead(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR2, I2C_CR2_HEAD10R); +} + +/** + * @brief Check if automatic RESTART Read request condition for 10bit address header is enabled or disabled. + * @rmtoll CR2 HEAD10R LL_I2C_IsEnabledAuto10BitRead + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledAuto10BitRead(I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR2, I2C_CR2_HEAD10R) != (I2C_CR2_HEAD10R)) ? 1UL : 0UL); +} + +/** + * @brief Configure the transfer direction (master mode). + * @note Changing these bits when START bit is set is not allowed. + * @rmtoll CR2 RD_WRN LL_I2C_SetTransferRequest + * @param I2Cx I2C Instance. + * @param TransferRequest This parameter can be one of the following values: + * @arg @ref LL_I2C_REQUEST_WRITE + * @arg @ref LL_I2C_REQUEST_READ + * @retval None + */ +__STATIC_INLINE void LL_I2C_SetTransferRequest(I2C_TypeDef *I2Cx, uint32_t TransferRequest) +{ + MODIFY_REG(I2Cx->CR2, I2C_CR2_RD_WRN, TransferRequest); +} + +/** + * @brief Get the transfer direction requested (master mode). + * @rmtoll CR2 RD_WRN LL_I2C_GetTransferRequest + * @param I2Cx I2C Instance. + * @retval Returned value can be one of the following values: + * @arg @ref LL_I2C_REQUEST_WRITE + * @arg @ref LL_I2C_REQUEST_READ + */ +__STATIC_INLINE uint32_t LL_I2C_GetTransferRequest(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_RD_WRN)); +} + +/** + * @brief Configure the slave address for transfer (master mode). + * @note Changing these bits when START bit is set is not allowed. + * @rmtoll CR2 SADD LL_I2C_SetSlaveAddr + * @param I2Cx I2C Instance. + * @param SlaveAddr This parameter must be a value between Min_Data=0x00 and Max_Data=0x3F. + * @retval None + */ +__STATIC_INLINE void LL_I2C_SetSlaveAddr(I2C_TypeDef *I2Cx, uint32_t SlaveAddr) +{ + MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD, SlaveAddr); +} + +/** + * @brief Get the slave address programmed for transfer. + * @rmtoll CR2 SADD LL_I2C_GetSlaveAddr + * @param I2Cx I2C Instance. + * @retval Value between Min_Data=0x0 and Max_Data=0x3F + */ +__STATIC_INLINE uint32_t LL_I2C_GetSlaveAddr(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_SADD)); +} + +/** + * @brief Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set). + * @rmtoll CR2 SADD LL_I2C_HandleTransfer\n + * CR2 ADD10 LL_I2C_HandleTransfer\n + * CR2 RD_WRN LL_I2C_HandleTransfer\n + * CR2 START LL_I2C_HandleTransfer\n + * CR2 STOP LL_I2C_HandleTransfer\n + * CR2 RELOAD LL_I2C_HandleTransfer\n + * CR2 NBYTES LL_I2C_HandleTransfer\n + * CR2 AUTOEND LL_I2C_HandleTransfer\n + * CR2 HEAD10R LL_I2C_HandleTransfer + * @param I2Cx I2C Instance. + * @param SlaveAddr Specifies the slave address to be programmed. + * @param SlaveAddrSize This parameter can be one of the following values: + * @arg @ref LL_I2C_ADDRSLAVE_7BIT + * @arg @ref LL_I2C_ADDRSLAVE_10BIT + * @param TransferSize Specifies the number of bytes to be programmed. + * This parameter must be a value between Min_Data=0 and Max_Data=255. + * @param EndMode This parameter can be one of the following values: + * @arg @ref LL_I2C_MODE_RELOAD + * @arg @ref LL_I2C_MODE_AUTOEND + * @arg @ref LL_I2C_MODE_SOFTEND + * @arg @ref LL_I2C_MODE_SMBUS_RELOAD + * @arg @ref LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC + * @arg @ref LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC + * @arg @ref LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC + * @arg @ref LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC + * @param Request This parameter can be one of the following values: + * @arg @ref LL_I2C_GENERATE_NOSTARTSTOP + * @arg @ref LL_I2C_GENERATE_STOP + * @arg @ref LL_I2C_GENERATE_START_READ + * @arg @ref LL_I2C_GENERATE_START_WRITE + * @arg @ref LL_I2C_GENERATE_RESTART_7BIT_READ + * @arg @ref LL_I2C_GENERATE_RESTART_7BIT_WRITE + * @arg @ref LL_I2C_GENERATE_RESTART_10BIT_READ + * @arg @ref LL_I2C_GENERATE_RESTART_10BIT_WRITE + * @retval None + */ +__STATIC_INLINE void LL_I2C_HandleTransfer(I2C_TypeDef *I2Cx, uint32_t SlaveAddr, uint32_t SlaveAddrSize, + uint32_t TransferSize, uint32_t EndMode, uint32_t Request) +{ + MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD | I2C_CR2_ADD10 | + (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | + I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_RELOAD | + I2C_CR2_NBYTES | I2C_CR2_AUTOEND | I2C_CR2_HEAD10R, + SlaveAddr | SlaveAddrSize | (TransferSize << I2C_CR2_NBYTES_Pos) | EndMode | Request); +} + +/** + * @brief Indicate the value of transfer direction (slave mode). + * @note RESET: Write transfer, Slave enters in receiver mode. + * SET: Read transfer, Slave enters in transmitter mode. + * @rmtoll ISR DIR LL_I2C_GetTransferDirection + * @param I2Cx I2C Instance. + * @retval Returned value can be one of the following values: + * @arg @ref LL_I2C_DIRECTION_WRITE + * @arg @ref LL_I2C_DIRECTION_READ + */ +__STATIC_INLINE uint32_t LL_I2C_GetTransferDirection(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_DIR)); +} + +/** + * @brief Return the slave matched address. + * @rmtoll ISR ADDCODE LL_I2C_GetAddressMatchCode + * @param I2Cx I2C Instance. + * @retval Value between Min_Data=0x00 and Max_Data=0x3F + */ +__STATIC_INLINE uint32_t LL_I2C_GetAddressMatchCode(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_ADDCODE) >> I2C_ISR_ADDCODE_Pos << 1); +} + +/** + * @brief Enable internal comparison of the SMBus Packet Error byte (transmission or reception mode). + * @note Macro IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @note This feature is cleared by hardware when the PEC byte is transferred, or when a STOP condition or an Address Matched is received. + * This bit has no effect when RELOAD bit is set. + * This bit has no effect in device mode when SBC bit is not set. + * @rmtoll CR2 PECBYTE LL_I2C_EnableSMBusPECCompare + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableSMBusPECCompare(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR2, I2C_CR2_PECBYTE); +} + +/** + * @brief Check if the SMBus Packet Error byte internal comparison is requested or not. + * @note Macro IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll CR2 PECBYTE LL_I2C_IsEnabledSMBusPECCompare + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPECCompare(I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR2, I2C_CR2_PECBYTE) == (I2C_CR2_PECBYTE)) ? 1UL : 0UL); +} + +/** + * @brief Get the SMBus Packet Error byte calculated. + * @note Macro IS_SMBUS_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll PECR PEC LL_I2C_GetSMBusPEC + * @param I2Cx I2C Instance. + * @retval Value between Min_Data=0x00 and Max_Data=0xFF + */ +__STATIC_INLINE uint32_t LL_I2C_GetSMBusPEC(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->PECR, I2C_PECR_PEC)); +} + +/** + * @brief Read Receive Data register. + * @rmtoll RXDR RXDATA LL_I2C_ReceiveData8 + * @param I2Cx I2C Instance. + * @retval Value between Min_Data=0x00 and Max_Data=0xFF + */ +__STATIC_INLINE uint8_t LL_I2C_ReceiveData8(I2C_TypeDef *I2Cx) +{ + return (uint8_t)(READ_BIT(I2Cx->RXDR, I2C_RXDR_RXDATA)); +} + +/** + * @brief Write in Transmit Data Register . + * @rmtoll TXDR TXDATA LL_I2C_TransmitData8 + * @param I2Cx I2C Instance. + * @param Data Value between Min_Data=0x00 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void LL_I2C_TransmitData8(I2C_TypeDef *I2Cx, uint8_t Data) +{ + WRITE_REG(I2Cx->TXDR, Data); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup I2C_LL_EF_Init Initialization and de-initialization functions + * @{ + */ + +ErrorStatus LL_I2C_Init(I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct); +ErrorStatus LL_I2C_DeInit(I2C_TypeDef *I2Cx); +void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct); + + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* I2C1 || I2C2 || I2C3 */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32L0xx_LL_I2C_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/fw/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h b/fw/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h new file mode 100644 index 0000000..7e5f6f0 --- /dev/null +++ b/fw/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h @@ -0,0 +1,2198 @@ +/** + ****************************************************************************** + * @file stm32l0xx_ll_lpuart.h + * @author MCD Application Team + * @brief Header file of LPUART LL module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32L0xx_LL_LPUART_H +#define STM32L0xx_LL_LPUART_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l0xx.h" + +/** @addtogroup STM32L0xx_LL_Driver + * @{ + */ + +#if defined (LPUART1) + +/** @defgroup LPUART_LL LPUART + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup LPUART_LL_Private_Constants LPUART Private Constants + * @{ + */ +/* Defines used in Baud Rate related macros and corresponding register setting computation */ +#define LPUART_LPUARTDIV_FREQ_MUL 256U +#define LPUART_BRR_MASK 0x000FFFFFU +#define LPUART_BRR_MIN_VALUE 0x00000300U +/** + * @} + */ + + +/* Private macros ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup LPUART_LL_Private_Macros LPUART Private Macros + * @{ + */ +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup LPUART_LL_ES_INIT LPUART Exported Init structures + * @{ + */ + +/** + * @brief LL LPUART Init Structure definition + */ +typedef struct +{ + uint32_t BaudRate; /*!< This field defines expected LPUART communication baud rate. + + This feature can be modified afterwards using unitary + function @ref LL_LPUART_SetBaudRate().*/ + + uint32_t DataWidth; /*!< Specifies the number of data bits transmitted or received in a frame. + This parameter can be a value of @ref LPUART_LL_EC_DATAWIDTH. + + This feature can be modified afterwards using unitary + function @ref LL_LPUART_SetDataWidth().*/ + + uint32_t StopBits; /*!< Specifies the number of stop bits transmitted. + This parameter can be a value of @ref LPUART_LL_EC_STOPBITS. + + This feature can be modified afterwards using unitary + function @ref LL_LPUART_SetStopBitsLength().*/ + + uint32_t Parity; /*!< Specifies the parity mode. + This parameter can be a value of @ref LPUART_LL_EC_PARITY. + + This feature can be modified afterwards using unitary + function @ref LL_LPUART_SetParity().*/ + + uint32_t TransferDirection; /*!< Specifies whether the Receive and/or Transmit mode is enabled or disabled. + This parameter can be a value of @ref LPUART_LL_EC_DIRECTION. + + This feature can be modified afterwards using unitary + function @ref LL_LPUART_SetTransferDirection().*/ + + uint32_t HardwareFlowControl; /*!< Specifies whether the hardware flow control mode is enabled or disabled. + This parameter can be a value of @ref LPUART_LL_EC_HWCONTROL. + + This feature can be modified afterwards using unitary + function @ref LL_LPUART_SetHWFlowCtrl().*/ + +} LL_LPUART_InitTypeDef; + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup LPUART_LL_Exported_Constants LPUART Exported Constants + * @{ + */ + +/** @defgroup LPUART_LL_EC_CLEAR_FLAG Clear Flags Defines + * @brief Flags defines which can be used with LL_LPUART_WriteReg function + * @{ + */ +#define LL_LPUART_ICR_PECF USART_ICR_PECF /*!< Parity error flag */ +#define LL_LPUART_ICR_FECF USART_ICR_FECF /*!< Framing error flag */ +#define LL_LPUART_ICR_NCF USART_ICR_NCF /*!< Noise error detected flag */ +#define LL_LPUART_ICR_ORECF USART_ICR_ORECF /*!< Overrun error flag */ +#define LL_LPUART_ICR_IDLECF USART_ICR_IDLECF /*!< Idle line detected flag */ +#define LL_LPUART_ICR_TCCF USART_ICR_TCCF /*!< Transmission complete flag */ +#define LL_LPUART_ICR_CTSCF USART_ICR_CTSCF /*!< CTS flag */ +#define LL_LPUART_ICR_CMCF USART_ICR_CMCF /*!< Character match flag */ +#define LL_LPUART_ICR_WUCF USART_ICR_WUCF /*!< Wakeup from Stop mode flag */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_LPUART_ReadReg function + * @{ + */ +#define LL_LPUART_ISR_PE USART_ISR_PE /*!< Parity error flag */ +#define LL_LPUART_ISR_FE USART_ISR_FE /*!< Framing error flag */ +#define LL_LPUART_ISR_NE USART_ISR_NE /*!< Noise detected flag */ +#define LL_LPUART_ISR_ORE USART_ISR_ORE /*!< Overrun error flag */ +#define LL_LPUART_ISR_IDLE USART_ISR_IDLE /*!< Idle line detected flag */ +#define LL_LPUART_ISR_RXNE USART_ISR_RXNE /*!< Read data register not empty flag */ +#define LL_LPUART_ISR_TC USART_ISR_TC /*!< Transmission complete flag */ +#define LL_LPUART_ISR_TXE USART_ISR_TXE /*!< Transmit data register empty flag */ +#define LL_LPUART_ISR_CTSIF USART_ISR_CTSIF /*!< CTS interrupt flag */ +#define LL_LPUART_ISR_CTS USART_ISR_CTS /*!< CTS flag */ +#define LL_LPUART_ISR_BUSY USART_ISR_BUSY /*!< Busy flag */ +#define LL_LPUART_ISR_CMF USART_ISR_CMF /*!< Character match flag */ +#define LL_LPUART_ISR_SBKF USART_ISR_SBKF /*!< Send break flag */ +#define LL_LPUART_ISR_RWU USART_ISR_RWU /*!< Receiver wakeup from Mute mode flag */ +#define LL_LPUART_ISR_WUF USART_ISR_WUF /*!< Wakeup from Stop mode flag */ +#define LL_LPUART_ISR_TEACK USART_ISR_TEACK /*!< Transmit enable acknowledge flag */ +#define LL_LPUART_ISR_REACK USART_ISR_REACK /*!< Receive enable acknowledge flag */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_LPUART_ReadReg and LL_LPUART_WriteReg functions + * @{ + */ +#define LL_LPUART_CR1_IDLEIE USART_CR1_IDLEIE /*!< IDLE interrupt enable */ +#define LL_LPUART_CR1_RXNEIE USART_CR1_RXNEIE /*!< Read data register not empty interrupt enable */ +#define LL_LPUART_CR1_TCIE USART_CR1_TCIE /*!< Transmission complete interrupt enable */ +#define LL_LPUART_CR1_TXEIE USART_CR1_TXEIE /*!< Transmit data register empty interrupt enable */ +#define LL_LPUART_CR1_PEIE USART_CR1_PEIE /*!< Parity error */ +#define LL_LPUART_CR1_CMIE USART_CR1_CMIE /*!< Character match interrupt enable */ +#define LL_LPUART_CR3_EIE USART_CR3_EIE /*!< Error interrupt enable */ +#define LL_LPUART_CR3_CTSIE USART_CR3_CTSIE /*!< CTS interrupt enable */ +#define LL_LPUART_CR3_WUFIE USART_CR3_WUFIE /*!< Wakeup from Stop mode interrupt enable */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_DIRECTION Direction + * @{ + */ +#define LL_LPUART_DIRECTION_NONE 0x00000000U /*!< Transmitter and Receiver are disabled */ +#define LL_LPUART_DIRECTION_RX USART_CR1_RE /*!< Transmitter is disabled and Receiver is enabled */ +#define LL_LPUART_DIRECTION_TX USART_CR1_TE /*!< Transmitter is enabled and Receiver is disabled */ +#define LL_LPUART_DIRECTION_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< Transmitter and Receiver are enabled */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_PARITY Parity Control + * @{ + */ +#define LL_LPUART_PARITY_NONE 0x00000000U /*!< Parity control disabled */ +#define LL_LPUART_PARITY_EVEN USART_CR1_PCE /*!< Parity control enabled and Even Parity is selected */ +#define LL_LPUART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< Parity control enabled and Odd Parity is selected */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_WAKEUP Wakeup + * @{ + */ +#define LL_LPUART_WAKEUP_IDLELINE 0x00000000U /*!< LPUART wake up from Mute mode on Idle Line */ +#define LL_LPUART_WAKEUP_ADDRESSMARK USART_CR1_WAKE /*!< LPUART wake up from Mute mode on Address Mark */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_DATAWIDTH Datawidth + * @{ + */ +#define LL_LPUART_DATAWIDTH_7B USART_CR1_M1 /*!< 7 bits word length : Start bit, 7 data bits, n stop bits */ +#define LL_LPUART_DATAWIDTH_8B 0x00000000U /*!< 8 bits word length : Start bit, 8 data bits, n stop bits */ +#define LL_LPUART_DATAWIDTH_9B USART_CR1_M0 /*!< 9 bits word length : Start bit, 9 data bits, n stop bits */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_STOPBITS Stop Bits + * @{ + */ +#define LL_LPUART_STOPBITS_1 0x00000000U /*!< 1 stop bit */ +#define LL_LPUART_STOPBITS_2 USART_CR2_STOP_1 /*!< 2 stop bits */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_TXRX TX RX Pins Swap + * @{ + */ +#define LL_LPUART_TXRX_STANDARD 0x00000000U /*!< TX/RX pins are used as defined in standard pinout */ +#define LL_LPUART_TXRX_SWAPPED (USART_CR2_SWAP) /*!< TX and RX pins functions are swapped. */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_RXPIN_LEVEL RX Pin Active Level Inversion + * @{ + */ +#define LL_LPUART_RXPIN_LEVEL_STANDARD 0x00000000U /*!< RX pin signal works using the standard logic levels */ +#define LL_LPUART_RXPIN_LEVEL_INVERTED (USART_CR2_RXINV) /*!< RX pin signal values are inverted. */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_TXPIN_LEVEL TX Pin Active Level Inversion + * @{ + */ +#define LL_LPUART_TXPIN_LEVEL_STANDARD 0x00000000U /*!< TX pin signal works using the standard logic levels */ +#define LL_LPUART_TXPIN_LEVEL_INVERTED (USART_CR2_TXINV) /*!< TX pin signal values are inverted. */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_BINARY_LOGIC Binary Data Inversion + * @{ + */ +#define LL_LPUART_BINARY_LOGIC_POSITIVE 0x00000000U /*!< Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L) */ +#define LL_LPUART_BINARY_LOGIC_NEGATIVE USART_CR2_DATAINV /*!< Logical data from the data register are send/received in negative/inverse logic. (1=L, 0=H). The parity bit is also inverted. */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_BITORDER Bit Order + * @{ + */ +#define LL_LPUART_BITORDER_LSBFIRST 0x00000000U /*!< data is transmitted/received with data bit 0 first, following the start bit */ +#define LL_LPUART_BITORDER_MSBFIRST USART_CR2_MSBFIRST /*!< data is transmitted/received with the MSB first, following the start bit */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_ADDRESS_DETECT Address Length Detection + * @{ + */ +#define LL_LPUART_ADDRESS_DETECT_4B 0x00000000U /*!< 4-bit address detection method selected */ +#define LL_LPUART_ADDRESS_DETECT_7B USART_CR2_ADDM7 /*!< 7-bit address detection (in 8-bit data mode) method selected */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_HWCONTROL Hardware Control + * @{ + */ +#define LL_LPUART_HWCONTROL_NONE 0x00000000U /*!< CTS and RTS hardware flow control disabled */ +#define LL_LPUART_HWCONTROL_RTS USART_CR3_RTSE /*!< RTS output enabled, data is only requested when there is space in the receive buffer */ +#define LL_LPUART_HWCONTROL_CTS USART_CR3_CTSE /*!< CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0) */ +#define LL_LPUART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) /*!< CTS and RTS hardware flow control enabled */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_WAKEUP_ON Wakeup Activation + * @{ + */ +#define LL_LPUART_WAKEUP_ON_ADDRESS 0x00000000U /*!< Wake up active on address match */ +#define LL_LPUART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1 /*!< Wake up active on Start bit detection */ +#define LL_LPUART_WAKEUP_ON_RXNE (USART_CR3_WUS_0 | USART_CR3_WUS_1) /*!< Wake up active on RXNE */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_DE_POLARITY Driver Enable Polarity + * @{ + */ +#define LL_LPUART_DE_POLARITY_HIGH 0x00000000U /*!< DE signal is active high */ +#define LL_LPUART_DE_POLARITY_LOW USART_CR3_DEP /*!< DE signal is active low */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_DMA_REG_DATA DMA Register Data + * @{ + */ +#define LL_LPUART_DMA_REG_DATA_TRANSMIT 0x00000000U /*!< Get address of data register used for transmission */ +#define LL_LPUART_DMA_REG_DATA_RECEIVE 0x00000001U /*!< Get address of data register used for reception */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup LPUART_LL_Exported_Macros LPUART Exported Macros + * @{ + */ + +/** @defgroup LPUART_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in LPUART register + * @param __INSTANCE__ LPUART Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_LPUART_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in LPUART register + * @param __INSTANCE__ LPUART Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_LPUART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** @defgroup LPUART_LL_EM_Exported_Macros_Helper Helper Macros + * @{ + */ + +/** + * @brief Compute LPUARTDIV value according to Peripheral Clock and + * expected Baud Rate (20-bit value of LPUARTDIV is returned) + * @param __PERIPHCLK__ Peripheral Clock frequency used for LPUART Instance + * @param __BAUDRATE__ Baud Rate value to achieve + * @retval LPUARTDIV value to be used for BRR register filling + */ +#define __LL_LPUART_DIV(__PERIPHCLK__, __BAUDRATE__) (uint32_t)(((((uint64_t)(__PERIPHCLK__)*LPUART_LPUARTDIV_FREQ_MUL) + (uint32_t)((__BAUDRATE__)/2U))/(__BAUDRATE__))\ + & LPUART_BRR_MASK) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup LPUART_LL_Exported_Functions LPUART Exported Functions + * @{ + */ + +/** @defgroup LPUART_LL_EF_Configuration Configuration functions + * @{ + */ + +/** + * @brief LPUART Enable + * @rmtoll CR1 UE LL_LPUART_Enable + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_Enable(USART_TypeDef *LPUARTx) +{ + SET_BIT(LPUARTx->CR1, USART_CR1_UE); +} + +/** + * @brief LPUART Disable + * @note When LPUART is disabled, LPUART prescalers and outputs are stopped immediately, + * and current operations are discarded. The configuration of the LPUART is kept, but all the status + * flags, in the LPUARTx_ISR are set to their default values. + * @note In order to go into low-power mode without generating errors on the line, + * the TE bit must be reset before and the software must wait + * for the TC bit in the LPUART_ISR to be set before resetting the UE bit. + * The DMA requests are also reset when UE = 0 so the DMA channel must + * be disabled before resetting the UE bit. + * @rmtoll CR1 UE LL_LPUART_Disable + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_Disable(USART_TypeDef *LPUARTx) +{ + CLEAR_BIT(LPUARTx->CR1, USART_CR1_UE); +} + +/** + * @brief Indicate if LPUART is enabled + * @rmtoll CR1 UE LL_LPUART_IsEnabled + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabled(USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR1, USART_CR1_UE) == (USART_CR1_UE)) ? 1UL : 0UL); +} + + +/** + * @brief LPUART enabled in STOP Mode + * @note When this function is enabled, LPUART is able to wake up the MCU from Stop mode, provided that + * LPUART clock selection is HSI or LSE in RCC. + * @rmtoll CR1 UESM LL_LPUART_EnableInStopMode + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableInStopMode(USART_TypeDef *LPUARTx) +{ + SET_BIT(LPUARTx->CR1, USART_CR1_UESM); +} + +/** + * @brief LPUART disabled in STOP Mode + * @note When this function is disabled, LPUART is not able to wake up the MCU from Stop mode + * @rmtoll CR1 UESM LL_LPUART_DisableInStopMode + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableInStopMode(USART_TypeDef *LPUARTx) +{ + CLEAR_BIT(LPUARTx->CR1, USART_CR1_UESM); +} + +/** + * @brief Indicate if LPUART is enabled in STOP Mode + * (able to wake up MCU from Stop mode or not) + * @rmtoll CR1 UESM LL_LPUART_IsEnabledInStopMode + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledInStopMode(USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR1, USART_CR1_UESM) == (USART_CR1_UESM)) ? 1UL : 0UL); +} + +/** + * @brief LPUART Clock enabled in STOP Mode + * @note When this function is called, LPUART Clock is enabled while in STOP mode + * @rmtoll CR3 UCESM LL_LPUART_EnableClockInStopMode + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableClockInStopMode(USART_TypeDef *LPUARTx) +{ + SET_BIT(LPUARTx->CR3, USART_CR3_UCESM); +} + +/** + * @brief LPUART clock disabled in STOP Mode + * @note When this function is called, LPUART Clock is disabled while in STOP mode + * @rmtoll CR3 UCESM LL_LPUART_DisableClockInStopMode + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableClockInStopMode(USART_TypeDef *LPUARTx) +{ + CLEAR_BIT(LPUARTx->CR3, USART_CR3_UCESM); +} + +/** + * @brief Indicate if LPUART clock is enabled in STOP Mode + * @rmtoll CR3 UCESM LL_LPUART_IsClockEnabledInStopMode + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsClockEnabledInStopMode(USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR3, USART_CR3_UCESM) == (USART_CR3_UCESM)) ? 1UL : 0UL); +} + +/** + * @brief Receiver Enable (Receiver is enabled and begins searching for a start bit) + * @rmtoll CR1 RE LL_LPUART_EnableDirectionRx + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableDirectionRx(USART_TypeDef *LPUARTx) +{ + SET_BIT(LPUARTx->CR1, USART_CR1_RE); +} + +/** + * @brief Receiver Disable + * @rmtoll CR1 RE LL_LPUART_DisableDirectionRx + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableDirectionRx(USART_TypeDef *LPUARTx) +{ + CLEAR_BIT(LPUARTx->CR1, USART_CR1_RE); +} + +/** + * @brief Transmitter Enable + * @rmtoll CR1 TE LL_LPUART_EnableDirectionTx + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableDirectionTx(USART_TypeDef *LPUARTx) +{ + SET_BIT(LPUARTx->CR1, USART_CR1_TE); +} + +/** + * @brief Transmitter Disable + * @rmtoll CR1 TE LL_LPUART_DisableDirectionTx + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableDirectionTx(USART_TypeDef *LPUARTx) +{ + CLEAR_BIT(LPUARTx->CR1, USART_CR1_TE); +} + +/** + * @brief Configure simultaneously enabled/disabled states + * of Transmitter and Receiver + * @rmtoll CR1 RE LL_LPUART_SetTransferDirection\n + * CR1 TE LL_LPUART_SetTransferDirection + * @param LPUARTx LPUART Instance + * @param TransferDirection This parameter can be one of the following values: + * @arg @ref LL_LPUART_DIRECTION_NONE + * @arg @ref LL_LPUART_DIRECTION_RX + * @arg @ref LL_LPUART_DIRECTION_TX + * @arg @ref LL_LPUART_DIRECTION_TX_RX + * @retval None + */ +__STATIC_INLINE void LL_LPUART_SetTransferDirection(USART_TypeDef *LPUARTx, uint32_t TransferDirection) +{ + MODIFY_REG(LPUARTx->CR1, USART_CR1_RE | USART_CR1_TE, TransferDirection); +} + +/** + * @brief Return enabled/disabled states of Transmitter and Receiver + * @rmtoll CR1 RE LL_LPUART_GetTransferDirection\n + * CR1 TE LL_LPUART_GetTransferDirection + * @param LPUARTx LPUART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPUART_DIRECTION_NONE + * @arg @ref LL_LPUART_DIRECTION_RX + * @arg @ref LL_LPUART_DIRECTION_TX + * @arg @ref LL_LPUART_DIRECTION_TX_RX + */ +__STATIC_INLINE uint32_t LL_LPUART_GetTransferDirection(USART_TypeDef *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_RE | USART_CR1_TE)); +} + +/** + * @brief Configure Parity (enabled/disabled and parity mode if enabled) + * @note This function selects if hardware parity control (generation and detection) is enabled or disabled. + * When the parity control is enabled (Odd or Even), computed parity bit is inserted at the MSB position + * (depending on data width) and parity is checked on the received data. + * @rmtoll CR1 PS LL_LPUART_SetParity\n + * CR1 PCE LL_LPUART_SetParity + * @param LPUARTx LPUART Instance + * @param Parity This parameter can be one of the following values: + * @arg @ref LL_LPUART_PARITY_NONE + * @arg @ref LL_LPUART_PARITY_EVEN + * @arg @ref LL_LPUART_PARITY_ODD + * @retval None + */ +__STATIC_INLINE void LL_LPUART_SetParity(USART_TypeDef *LPUARTx, uint32_t Parity) +{ + MODIFY_REG(LPUARTx->CR1, USART_CR1_PS | USART_CR1_PCE, Parity); +} + +/** + * @brief Return Parity configuration (enabled/disabled and parity mode if enabled) + * @rmtoll CR1 PS LL_LPUART_GetParity\n + * CR1 PCE LL_LPUART_GetParity + * @param LPUARTx LPUART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPUART_PARITY_NONE + * @arg @ref LL_LPUART_PARITY_EVEN + * @arg @ref LL_LPUART_PARITY_ODD + */ +__STATIC_INLINE uint32_t LL_LPUART_GetParity(USART_TypeDef *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_PS | USART_CR1_PCE)); +} + +/** + * @brief Set Receiver Wake Up method from Mute mode. + * @rmtoll CR1 WAKE LL_LPUART_SetWakeUpMethod + * @param LPUARTx LPUART Instance + * @param Method This parameter can be one of the following values: + * @arg @ref LL_LPUART_WAKEUP_IDLELINE + * @arg @ref LL_LPUART_WAKEUP_ADDRESSMARK + * @retval None + */ +__STATIC_INLINE void LL_LPUART_SetWakeUpMethod(USART_TypeDef *LPUARTx, uint32_t Method) +{ + MODIFY_REG(LPUARTx->CR1, USART_CR1_WAKE, Method); +} + +/** + * @brief Return Receiver Wake Up method from Mute mode + * @rmtoll CR1 WAKE LL_LPUART_GetWakeUpMethod + * @param LPUARTx LPUART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPUART_WAKEUP_IDLELINE + * @arg @ref LL_LPUART_WAKEUP_ADDRESSMARK + */ +__STATIC_INLINE uint32_t LL_LPUART_GetWakeUpMethod(USART_TypeDef *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_WAKE)); +} + +/** + * @brief Set Word length (nb of data bits, excluding start and stop bits) + * @rmtoll CR1 M LL_LPUART_SetDataWidth + * @param LPUARTx LPUART Instance + * @param DataWidth This parameter can be one of the following values: + * @arg @ref LL_LPUART_DATAWIDTH_7B + * @arg @ref LL_LPUART_DATAWIDTH_8B + * @arg @ref LL_LPUART_DATAWIDTH_9B + * @retval None + */ +__STATIC_INLINE void LL_LPUART_SetDataWidth(USART_TypeDef *LPUARTx, uint32_t DataWidth) +{ + MODIFY_REG(LPUARTx->CR1, USART_CR1_M, DataWidth); +} + +/** + * @brief Return Word length (i.e. nb of data bits, excluding start and stop bits) + * @rmtoll CR1 M LL_LPUART_GetDataWidth + * @param LPUARTx LPUART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPUART_DATAWIDTH_7B + * @arg @ref LL_LPUART_DATAWIDTH_8B + * @arg @ref LL_LPUART_DATAWIDTH_9B + */ +__STATIC_INLINE uint32_t LL_LPUART_GetDataWidth(USART_TypeDef *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_M)); +} + +/** + * @brief Allow switch between Mute Mode and Active mode + * @rmtoll CR1 MME LL_LPUART_EnableMuteMode + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableMuteMode(USART_TypeDef *LPUARTx) +{ + SET_BIT(LPUARTx->CR1, USART_CR1_MME); +} + +/** + * @brief Prevent Mute Mode use. Set Receiver in active mode permanently. + * @rmtoll CR1 MME LL_LPUART_DisableMuteMode + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableMuteMode(USART_TypeDef *LPUARTx) +{ + CLEAR_BIT(LPUARTx->CR1, USART_CR1_MME); +} + +/** + * @brief Indicate if switch between Mute Mode and Active mode is allowed + * @rmtoll CR1 MME LL_LPUART_IsEnabledMuteMode + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledMuteMode(USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR1, USART_CR1_MME) == (USART_CR1_MME)) ? 1UL : 0UL); +} + + +/** + * @brief Set the length of the stop bits + * @rmtoll CR2 STOP LL_LPUART_SetStopBitsLength + * @param LPUARTx LPUART Instance + * @param StopBits This parameter can be one of the following values: + * @arg @ref LL_LPUART_STOPBITS_1 + * @arg @ref LL_LPUART_STOPBITS_2 + * @retval None + */ +__STATIC_INLINE void LL_LPUART_SetStopBitsLength(USART_TypeDef *LPUARTx, uint32_t StopBits) +{ + MODIFY_REG(LPUARTx->CR2, USART_CR2_STOP, StopBits); +} + +/** + * @brief Retrieve the length of the stop bits + * @rmtoll CR2 STOP LL_LPUART_GetStopBitsLength + * @param LPUARTx LPUART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPUART_STOPBITS_1 + * @arg @ref LL_LPUART_STOPBITS_2 + */ +__STATIC_INLINE uint32_t LL_LPUART_GetStopBitsLength(USART_TypeDef *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_STOP)); +} + +/** + * @brief Configure Character frame format (Datawidth, Parity control, Stop Bits) + * @note Call of this function is equivalent to following function call sequence : + * - Data Width configuration using @ref LL_LPUART_SetDataWidth() function + * - Parity Control and mode configuration using @ref LL_LPUART_SetParity() function + * - Stop bits configuration using @ref LL_LPUART_SetStopBitsLength() function + * @rmtoll CR1 PS LL_LPUART_ConfigCharacter\n + * CR1 PCE LL_LPUART_ConfigCharacter\n + * CR1 M LL_LPUART_ConfigCharacter\n + * CR2 STOP LL_LPUART_ConfigCharacter + * @param LPUARTx LPUART Instance + * @param DataWidth This parameter can be one of the following values: + * @arg @ref LL_LPUART_DATAWIDTH_7B + * @arg @ref LL_LPUART_DATAWIDTH_8B + * @arg @ref LL_LPUART_DATAWIDTH_9B + * @param Parity This parameter can be one of the following values: + * @arg @ref LL_LPUART_PARITY_NONE + * @arg @ref LL_LPUART_PARITY_EVEN + * @arg @ref LL_LPUART_PARITY_ODD + * @param StopBits This parameter can be one of the following values: + * @arg @ref LL_LPUART_STOPBITS_1 + * @arg @ref LL_LPUART_STOPBITS_2 + * @retval None + */ +__STATIC_INLINE void LL_LPUART_ConfigCharacter(USART_TypeDef *LPUARTx, uint32_t DataWidth, uint32_t Parity, + uint32_t StopBits) +{ + MODIFY_REG(LPUARTx->CR1, USART_CR1_PS | USART_CR1_PCE | USART_CR1_M, Parity | DataWidth); + MODIFY_REG(LPUARTx->CR2, USART_CR2_STOP, StopBits); +} + +/** + * @brief Configure TX/RX pins swapping setting. + * @rmtoll CR2 SWAP LL_LPUART_SetTXRXSwap + * @param LPUARTx LPUART Instance + * @param SwapConfig This parameter can be one of the following values: + * @arg @ref LL_LPUART_TXRX_STANDARD + * @arg @ref LL_LPUART_TXRX_SWAPPED + * @retval None + */ +__STATIC_INLINE void LL_LPUART_SetTXRXSwap(USART_TypeDef *LPUARTx, uint32_t SwapConfig) +{ + MODIFY_REG(LPUARTx->CR2, USART_CR2_SWAP, SwapConfig); +} + +/** + * @brief Retrieve TX/RX pins swapping configuration. + * @rmtoll CR2 SWAP LL_LPUART_GetTXRXSwap + * @param LPUARTx LPUART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPUART_TXRX_STANDARD + * @arg @ref LL_LPUART_TXRX_SWAPPED + */ +__STATIC_INLINE uint32_t LL_LPUART_GetTXRXSwap(USART_TypeDef *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_SWAP)); +} + +/** + * @brief Configure RX pin active level logic + * @rmtoll CR2 RXINV LL_LPUART_SetRXPinLevel + * @param LPUARTx LPUART Instance + * @param PinInvMethod This parameter can be one of the following values: + * @arg @ref LL_LPUART_RXPIN_LEVEL_STANDARD + * @arg @ref LL_LPUART_RXPIN_LEVEL_INVERTED + * @retval None + */ +__STATIC_INLINE void LL_LPUART_SetRXPinLevel(USART_TypeDef *LPUARTx, uint32_t PinInvMethod) +{ + MODIFY_REG(LPUARTx->CR2, USART_CR2_RXINV, PinInvMethod); +} + +/** + * @brief Retrieve RX pin active level logic configuration + * @rmtoll CR2 RXINV LL_LPUART_GetRXPinLevel + * @param LPUARTx LPUART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPUART_RXPIN_LEVEL_STANDARD + * @arg @ref LL_LPUART_RXPIN_LEVEL_INVERTED + */ +__STATIC_INLINE uint32_t LL_LPUART_GetRXPinLevel(USART_TypeDef *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_RXINV)); +} + +/** + * @brief Configure TX pin active level logic + * @rmtoll CR2 TXINV LL_LPUART_SetTXPinLevel + * @param LPUARTx LPUART Instance + * @param PinInvMethod This parameter can be one of the following values: + * @arg @ref LL_LPUART_TXPIN_LEVEL_STANDARD + * @arg @ref LL_LPUART_TXPIN_LEVEL_INVERTED + * @retval None + */ +__STATIC_INLINE void LL_LPUART_SetTXPinLevel(USART_TypeDef *LPUARTx, uint32_t PinInvMethod) +{ + MODIFY_REG(LPUARTx->CR2, USART_CR2_TXINV, PinInvMethod); +} + +/** + * @brief Retrieve TX pin active level logic configuration + * @rmtoll CR2 TXINV LL_LPUART_GetTXPinLevel + * @param LPUARTx LPUART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPUART_TXPIN_LEVEL_STANDARD + * @arg @ref LL_LPUART_TXPIN_LEVEL_INVERTED + */ +__STATIC_INLINE uint32_t LL_LPUART_GetTXPinLevel(USART_TypeDef *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_TXINV)); +} + +/** + * @brief Configure Binary data logic. + * + * @note Allow to define how Logical data from the data register are send/received : + * either in positive/direct logic (1=H, 0=L) or in negative/inverse logic (1=L, 0=H) + * @rmtoll CR2 DATAINV LL_LPUART_SetBinaryDataLogic + * @param LPUARTx LPUART Instance + * @param DataLogic This parameter can be one of the following values: + * @arg @ref LL_LPUART_BINARY_LOGIC_POSITIVE + * @arg @ref LL_LPUART_BINARY_LOGIC_NEGATIVE + * @retval None + */ +__STATIC_INLINE void LL_LPUART_SetBinaryDataLogic(USART_TypeDef *LPUARTx, uint32_t DataLogic) +{ + MODIFY_REG(LPUARTx->CR2, USART_CR2_DATAINV, DataLogic); +} + +/** + * @brief Retrieve Binary data configuration + * @rmtoll CR2 DATAINV LL_LPUART_GetBinaryDataLogic + * @param LPUARTx LPUART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPUART_BINARY_LOGIC_POSITIVE + * @arg @ref LL_LPUART_BINARY_LOGIC_NEGATIVE + */ +__STATIC_INLINE uint32_t LL_LPUART_GetBinaryDataLogic(USART_TypeDef *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_DATAINV)); +} + +/** + * @brief Configure transfer bit order (either Less or Most Significant Bit First) + * @note MSB First means data is transmitted/received with the MSB first, following the start bit. + * LSB First means data is transmitted/received with data bit 0 first, following the start bit. + * @rmtoll CR2 MSBFIRST LL_LPUART_SetTransferBitOrder + * @param LPUARTx LPUART Instance + * @param BitOrder This parameter can be one of the following values: + * @arg @ref LL_LPUART_BITORDER_LSBFIRST + * @arg @ref LL_LPUART_BITORDER_MSBFIRST + * @retval None + */ +__STATIC_INLINE void LL_LPUART_SetTransferBitOrder(USART_TypeDef *LPUARTx, uint32_t BitOrder) +{ + MODIFY_REG(LPUARTx->CR2, USART_CR2_MSBFIRST, BitOrder); +} + +/** + * @brief Return transfer bit order (either Less or Most Significant Bit First) + * @note MSB First means data is transmitted/received with the MSB first, following the start bit. + * LSB First means data is transmitted/received with data bit 0 first, following the start bit. + * @rmtoll CR2 MSBFIRST LL_LPUART_GetTransferBitOrder + * @param LPUARTx LPUART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPUART_BITORDER_LSBFIRST + * @arg @ref LL_LPUART_BITORDER_MSBFIRST + */ +__STATIC_INLINE uint32_t LL_LPUART_GetTransferBitOrder(USART_TypeDef *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_MSBFIRST)); +} + +/** + * @brief Set Address of the LPUART node. + * @note This is used in multiprocessor communication during Mute mode or Stop mode, + * for wake up with address mark detection. + * @note 4bits address node is used when 4-bit Address Detection is selected in ADDM7. + * (b7-b4 should be set to 0) + * 8bits address node is used when 7-bit Address Detection is selected in ADDM7. + * (This is used in multiprocessor communication during Mute mode or Stop mode, + * for wake up with 7-bit address mark detection. + * The MSB of the character sent by the transmitter should be equal to 1. + * It may also be used for character detection during normal reception, + * Mute mode inactive (for example, end of block detection in ModBus protocol). + * In this case, the whole received character (8-bit) is compared to the ADD[7:0] + * value and CMF flag is set on match) + * @rmtoll CR2 ADD LL_LPUART_ConfigNodeAddress\n + * CR2 ADDM7 LL_LPUART_ConfigNodeAddress + * @param LPUARTx LPUART Instance + * @param AddressLen This parameter can be one of the following values: + * @arg @ref LL_LPUART_ADDRESS_DETECT_4B + * @arg @ref LL_LPUART_ADDRESS_DETECT_7B + * @param NodeAddress 4 or 7 bit Address of the LPUART node. + * @retval None + */ +__STATIC_INLINE void LL_LPUART_ConfigNodeAddress(USART_TypeDef *LPUARTx, uint32_t AddressLen, uint32_t NodeAddress) +{ + MODIFY_REG(LPUARTx->CR2, USART_CR2_ADD | USART_CR2_ADDM7, + (uint32_t)(AddressLen | (NodeAddress << USART_CR2_ADD_Pos))); +} + +/** + * @brief Return 8 bit Address of the LPUART node as set in ADD field of CR2. + * @note If 4-bit Address Detection is selected in ADDM7, + * only 4bits (b3-b0) of returned value are relevant (b31-b4 are not relevant) + * If 7-bit Address Detection is selected in ADDM7, + * only 8bits (b7-b0) of returned value are relevant (b31-b8 are not relevant) + * @rmtoll CR2 ADD LL_LPUART_GetNodeAddress + * @param LPUARTx LPUART Instance + * @retval Address of the LPUART node (Value between Min_Data=0 and Max_Data=255) + */ +__STATIC_INLINE uint32_t LL_LPUART_GetNodeAddress(USART_TypeDef *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_ADD) >> USART_CR2_ADD_Pos); +} + +/** + * @brief Return Length of Node Address used in Address Detection mode (7-bit or 4-bit) + * @rmtoll CR2 ADDM7 LL_LPUART_GetNodeAddressLen + * @param LPUARTx LPUART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPUART_ADDRESS_DETECT_4B + * @arg @ref LL_LPUART_ADDRESS_DETECT_7B + */ +__STATIC_INLINE uint32_t LL_LPUART_GetNodeAddressLen(USART_TypeDef *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_ADDM7)); +} + +/** + * @brief Enable RTS HW Flow Control + * @rmtoll CR3 RTSE LL_LPUART_EnableRTSHWFlowCtrl + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableRTSHWFlowCtrl(USART_TypeDef *LPUARTx) +{ + SET_BIT(LPUARTx->CR3, USART_CR3_RTSE); +} + +/** + * @brief Disable RTS HW Flow Control + * @rmtoll CR3 RTSE LL_LPUART_DisableRTSHWFlowCtrl + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableRTSHWFlowCtrl(USART_TypeDef *LPUARTx) +{ + CLEAR_BIT(LPUARTx->CR3, USART_CR3_RTSE); +} + +/** + * @brief Enable CTS HW Flow Control + * @rmtoll CR3 CTSE LL_LPUART_EnableCTSHWFlowCtrl + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableCTSHWFlowCtrl(USART_TypeDef *LPUARTx) +{ + SET_BIT(LPUARTx->CR3, USART_CR3_CTSE); +} + +/** + * @brief Disable CTS HW Flow Control + * @rmtoll CR3 CTSE LL_LPUART_DisableCTSHWFlowCtrl + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableCTSHWFlowCtrl(USART_TypeDef *LPUARTx) +{ + CLEAR_BIT(LPUARTx->CR3, USART_CR3_CTSE); +} + +/** + * @brief Configure HW Flow Control mode (both CTS and RTS) + * @rmtoll CR3 RTSE LL_LPUART_SetHWFlowCtrl\n + * CR3 CTSE LL_LPUART_SetHWFlowCtrl + * @param LPUARTx LPUART Instance + * @param HardwareFlowControl This parameter can be one of the following values: + * @arg @ref LL_LPUART_HWCONTROL_NONE + * @arg @ref LL_LPUART_HWCONTROL_RTS + * @arg @ref LL_LPUART_HWCONTROL_CTS + * @arg @ref LL_LPUART_HWCONTROL_RTS_CTS + * @retval None + */ +__STATIC_INLINE void LL_LPUART_SetHWFlowCtrl(USART_TypeDef *LPUARTx, uint32_t HardwareFlowControl) +{ + MODIFY_REG(LPUARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE, HardwareFlowControl); +} + +/** + * @brief Return HW Flow Control configuration (both CTS and RTS) + * @rmtoll CR3 RTSE LL_LPUART_GetHWFlowCtrl\n + * CR3 CTSE LL_LPUART_GetHWFlowCtrl + * @param LPUARTx LPUART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPUART_HWCONTROL_NONE + * @arg @ref LL_LPUART_HWCONTROL_RTS + * @arg @ref LL_LPUART_HWCONTROL_CTS + * @arg @ref LL_LPUART_HWCONTROL_RTS_CTS + */ +__STATIC_INLINE uint32_t LL_LPUART_GetHWFlowCtrl(USART_TypeDef *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE)); +} + +/** + * @brief Enable Overrun detection + * @rmtoll CR3 OVRDIS LL_LPUART_EnableOverrunDetect + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableOverrunDetect(USART_TypeDef *LPUARTx) +{ + CLEAR_BIT(LPUARTx->CR3, USART_CR3_OVRDIS); +} + +/** + * @brief Disable Overrun detection + * @rmtoll CR3 OVRDIS LL_LPUART_DisableOverrunDetect + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableOverrunDetect(USART_TypeDef *LPUARTx) +{ + SET_BIT(LPUARTx->CR3, USART_CR3_OVRDIS); +} + +/** + * @brief Indicate if Overrun detection is enabled + * @rmtoll CR3 OVRDIS LL_LPUART_IsEnabledOverrunDetect + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledOverrunDetect(USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR3, USART_CR3_OVRDIS) != USART_CR3_OVRDIS) ? 1UL : 0UL); +} + +/** + * @brief Select event type for Wake UP Interrupt Flag (WUS[1:0] bits) + * @rmtoll CR3 WUS LL_LPUART_SetWKUPType + * @param LPUARTx LPUART Instance + * @param Type This parameter can be one of the following values: + * @arg @ref LL_LPUART_WAKEUP_ON_ADDRESS + * @arg @ref LL_LPUART_WAKEUP_ON_STARTBIT + * @arg @ref LL_LPUART_WAKEUP_ON_RXNE + * @retval None + */ +__STATIC_INLINE void LL_LPUART_SetWKUPType(USART_TypeDef *LPUARTx, uint32_t Type) +{ + MODIFY_REG(LPUARTx->CR3, USART_CR3_WUS, Type); +} + +/** + * @brief Return event type for Wake UP Interrupt Flag (WUS[1:0] bits) + * @rmtoll CR3 WUS LL_LPUART_GetWKUPType + * @param LPUARTx LPUART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPUART_WAKEUP_ON_ADDRESS + * @arg @ref LL_LPUART_WAKEUP_ON_STARTBIT + * @arg @ref LL_LPUART_WAKEUP_ON_RXNE + */ +__STATIC_INLINE uint32_t LL_LPUART_GetWKUPType(USART_TypeDef *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_WUS)); +} + +/** + * @brief Configure LPUART BRR register for achieving expected Baud Rate value. + * + * @note Compute and set LPUARTDIV value in BRR Register (full BRR content) + * according to used Peripheral Clock and expected Baud Rate values + * @note Peripheral clock and Baud Rate values provided as function parameters should be valid + * (Baud rate value != 0). + * @note Provided that LPUARTx_BRR must be > = 0x300 and LPUART_BRR is 20-bit, + * a care should be taken when generating high baud rates using high PeriphClk + * values. PeriphClk must be in the range [3 x BaudRate, 4096 x BaudRate]. + * @rmtoll BRR BRR LL_LPUART_SetBaudRate + * @param LPUARTx LPUART Instance + * @param PeriphClk Peripheral Clock + * @param BaudRate Baud Rate + * @retval None + */ +__STATIC_INLINE void LL_LPUART_SetBaudRate(USART_TypeDef *LPUARTx, uint32_t PeriphClk, uint32_t BaudRate) +{ + if (BaudRate != 0U) + { + LPUARTx->BRR = __LL_LPUART_DIV(PeriphClk, BaudRate); + } +} + +/** + * @brief Return current Baud Rate value, according to LPUARTDIV present in BRR register + * (full BRR content), and to used Peripheral Clock values + * @note In case of non-initialized or invalid value stored in BRR register, value 0 will be returned. + * @rmtoll BRR BRR LL_LPUART_GetBaudRate + * @param LPUARTx LPUART Instance + * @param PeriphClk Peripheral Clock + * @retval Baud Rate + */ +__STATIC_INLINE uint32_t LL_LPUART_GetBaudRate(USART_TypeDef *LPUARTx, uint32_t PeriphClk) +{ + uint32_t lpuartdiv; + uint32_t brrresult; + + lpuartdiv = LPUARTx->BRR & LPUART_BRR_MASK; + + if (lpuartdiv >= LPUART_BRR_MIN_VALUE) + { + brrresult = (uint32_t)(((uint64_t)(PeriphClk) * LPUART_LPUARTDIV_FREQ_MUL) / lpuartdiv); + } + else + { + brrresult = 0x0UL; + } + + return (brrresult); +} + +/** + * @} + */ + +/** @defgroup LPUART_LL_EF_Configuration_HalfDuplex Configuration functions related to Half Duplex feature + * @{ + */ + +/** + * @brief Enable Single Wire Half-Duplex mode + * @rmtoll CR3 HDSEL LL_LPUART_EnableHalfDuplex + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableHalfDuplex(USART_TypeDef *LPUARTx) +{ + SET_BIT(LPUARTx->CR3, USART_CR3_HDSEL); +} + +/** + * @brief Disable Single Wire Half-Duplex mode + * @rmtoll CR3 HDSEL LL_LPUART_DisableHalfDuplex + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableHalfDuplex(USART_TypeDef *LPUARTx) +{ + CLEAR_BIT(LPUARTx->CR3, USART_CR3_HDSEL); +} + +/** + * @brief Indicate if Single Wire Half-Duplex mode is enabled + * @rmtoll CR3 HDSEL LL_LPUART_IsEnabledHalfDuplex + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledHalfDuplex(USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup LPUART_LL_EF_Configuration_DE Configuration functions related to Driver Enable feature + * @{ + */ + +/** + * @brief Set DEDT (Driver Enable De-Assertion Time), Time value expressed on 5 bits ([4:0] bits). + * @rmtoll CR1 DEDT LL_LPUART_SetDEDeassertionTime + * @param LPUARTx LPUART Instance + * @param Time Value between Min_Data=0 and Max_Data=31 + * @retval None + */ +__STATIC_INLINE void LL_LPUART_SetDEDeassertionTime(USART_TypeDef *LPUARTx, uint32_t Time) +{ + MODIFY_REG(LPUARTx->CR1, USART_CR1_DEDT, Time << USART_CR1_DEDT_Pos); +} + +/** + * @brief Return DEDT (Driver Enable De-Assertion Time) + * @rmtoll CR1 DEDT LL_LPUART_GetDEDeassertionTime + * @param LPUARTx LPUART Instance + * @retval Time value expressed on 5 bits ([4:0] bits) : c + */ +__STATIC_INLINE uint32_t LL_LPUART_GetDEDeassertionTime(USART_TypeDef *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_DEDT) >> USART_CR1_DEDT_Pos); +} + +/** + * @brief Set DEAT (Driver Enable Assertion Time), Time value expressed on 5 bits ([4:0] bits). + * @rmtoll CR1 DEAT LL_LPUART_SetDEAssertionTime + * @param LPUARTx LPUART Instance + * @param Time Value between Min_Data=0 and Max_Data=31 + * @retval None + */ +__STATIC_INLINE void LL_LPUART_SetDEAssertionTime(USART_TypeDef *LPUARTx, uint32_t Time) +{ + MODIFY_REG(LPUARTx->CR1, USART_CR1_DEAT, Time << USART_CR1_DEAT_Pos); +} + +/** + * @brief Return DEAT (Driver Enable Assertion Time) + * @rmtoll CR1 DEAT LL_LPUART_GetDEAssertionTime + * @param LPUARTx LPUART Instance + * @retval Time value expressed on 5 bits ([4:0] bits) : Time Value between Min_Data=0 and Max_Data=31 + */ +__STATIC_INLINE uint32_t LL_LPUART_GetDEAssertionTime(USART_TypeDef *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_DEAT) >> USART_CR1_DEAT_Pos); +} + +/** + * @brief Enable Driver Enable (DE) Mode + * @rmtoll CR3 DEM LL_LPUART_EnableDEMode + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableDEMode(USART_TypeDef *LPUARTx) +{ + SET_BIT(LPUARTx->CR3, USART_CR3_DEM); +} + +/** + * @brief Disable Driver Enable (DE) Mode + * @rmtoll CR3 DEM LL_LPUART_DisableDEMode + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableDEMode(USART_TypeDef *LPUARTx) +{ + CLEAR_BIT(LPUARTx->CR3, USART_CR3_DEM); +} + +/** + * @brief Indicate if Driver Enable (DE) Mode is enabled + * @rmtoll CR3 DEM LL_LPUART_IsEnabledDEMode + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDEMode(USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR3, USART_CR3_DEM) == (USART_CR3_DEM)) ? 1UL : 0UL); +} + +/** + * @brief Select Driver Enable Polarity + * @rmtoll CR3 DEP LL_LPUART_SetDESignalPolarity + * @param LPUARTx LPUART Instance + * @param Polarity This parameter can be one of the following values: + * @arg @ref LL_LPUART_DE_POLARITY_HIGH + * @arg @ref LL_LPUART_DE_POLARITY_LOW + * @retval None + */ +__STATIC_INLINE void LL_LPUART_SetDESignalPolarity(USART_TypeDef *LPUARTx, uint32_t Polarity) +{ + MODIFY_REG(LPUARTx->CR3, USART_CR3_DEP, Polarity); +} + +/** + * @brief Return Driver Enable Polarity + * @rmtoll CR3 DEP LL_LPUART_GetDESignalPolarity + * @param LPUARTx LPUART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPUART_DE_POLARITY_HIGH + * @arg @ref LL_LPUART_DE_POLARITY_LOW + */ +__STATIC_INLINE uint32_t LL_LPUART_GetDESignalPolarity(USART_TypeDef *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_DEP)); +} + +/** + * @} + */ + +/** @defgroup LPUART_LL_EF_FLAG_Management FLAG_Management + * @{ + */ + +/** + * @brief Check if the LPUART Parity Error Flag is set or not + * @rmtoll ISR PE LL_LPUART_IsActiveFlag_PE + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_PE(USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->ISR, USART_ISR_PE) == (USART_ISR_PE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART Framing Error Flag is set or not + * @rmtoll ISR FE LL_LPUART_IsActiveFlag_FE + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_FE(USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->ISR, USART_ISR_FE) == (USART_ISR_FE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART Noise error detected Flag is set or not + * @rmtoll ISR NE LL_LPUART_IsActiveFlag_NE + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_NE(USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->ISR, USART_ISR_NE) == (USART_ISR_NE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART OverRun Error Flag is set or not + * @rmtoll ISR ORE LL_LPUART_IsActiveFlag_ORE + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_ORE(USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->ISR, USART_ISR_ORE) == (USART_ISR_ORE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART IDLE line detected Flag is set or not + * @rmtoll ISR IDLE LL_LPUART_IsActiveFlag_IDLE + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_IDLE(USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->ISR, USART_ISR_IDLE) == (USART_ISR_IDLE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART Read Data Register Not Empty Flag is set or not + * @rmtoll ISR RXNE LL_LPUART_IsActiveFlag_RXNE + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXNE(USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->ISR, USART_ISR_RXNE) == (USART_ISR_RXNE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART Transmission Complete Flag is set or not + * @rmtoll ISR TC LL_LPUART_IsActiveFlag_TC + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TC(USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->ISR, USART_ISR_TC) == (USART_ISR_TC)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART Transmit Data Register Empty Flag is set or not + * @rmtoll ISR TXE LL_LPUART_IsActiveFlag_TXE + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXE(USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->ISR, USART_ISR_TXE) == (USART_ISR_TXE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART CTS interrupt Flag is set or not + * @rmtoll ISR CTSIF LL_LPUART_IsActiveFlag_nCTS + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_nCTS(USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->ISR, USART_ISR_CTSIF) == (USART_ISR_CTSIF)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART CTS Flag is set or not + * @rmtoll ISR CTS LL_LPUART_IsActiveFlag_CTS + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_CTS(USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->ISR, USART_ISR_CTS) == (USART_ISR_CTS)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART Busy Flag is set or not + * @rmtoll ISR BUSY LL_LPUART_IsActiveFlag_BUSY + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_BUSY(USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->ISR, USART_ISR_BUSY) == (USART_ISR_BUSY)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART Character Match Flag is set or not + * @rmtoll ISR CMF LL_LPUART_IsActiveFlag_CM + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_CM(USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->ISR, USART_ISR_CMF) == (USART_ISR_CMF)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART Send Break Flag is set or not + * @rmtoll ISR SBKF LL_LPUART_IsActiveFlag_SBK + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_SBK(USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->ISR, USART_ISR_SBKF) == (USART_ISR_SBKF)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART Receive Wake Up from mute mode Flag is set or not + * @rmtoll ISR RWU LL_LPUART_IsActiveFlag_RWU + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RWU(USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->ISR, USART_ISR_RWU) == (USART_ISR_RWU)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART Wake Up from stop mode Flag is set or not + * @rmtoll ISR WUF LL_LPUART_IsActiveFlag_WKUP + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_WKUP(USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->ISR, USART_ISR_WUF) == (USART_ISR_WUF)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART Transmit Enable Acknowledge Flag is set or not + * @rmtoll ISR TEACK LL_LPUART_IsActiveFlag_TEACK + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TEACK(USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->ISR, USART_ISR_TEACK) == (USART_ISR_TEACK)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART Receive Enable Acknowledge Flag is set or not + * @rmtoll ISR REACK LL_LPUART_IsActiveFlag_REACK + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_REACK(USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->ISR, USART_ISR_REACK) == (USART_ISR_REACK)) ? 1UL : 0UL); +} + + +/** + * @brief Clear Parity Error Flag + * @rmtoll ICR PECF LL_LPUART_ClearFlag_PE + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_ClearFlag_PE(USART_TypeDef *LPUARTx) +{ + WRITE_REG(LPUARTx->ICR, USART_ICR_PECF); +} + +/** + * @brief Clear Framing Error Flag + * @rmtoll ICR FECF LL_LPUART_ClearFlag_FE + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_ClearFlag_FE(USART_TypeDef *LPUARTx) +{ + WRITE_REG(LPUARTx->ICR, USART_ICR_FECF); +} + +/** + * @brief Clear Noise detected Flag + * @rmtoll ICR NCF LL_LPUART_ClearFlag_NE + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_ClearFlag_NE(USART_TypeDef *LPUARTx) +{ + WRITE_REG(LPUARTx->ICR, USART_ICR_NCF); +} + +/** + * @brief Clear OverRun Error Flag + * @rmtoll ICR ORECF LL_LPUART_ClearFlag_ORE + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_ClearFlag_ORE(USART_TypeDef *LPUARTx) +{ + WRITE_REG(LPUARTx->ICR, USART_ICR_ORECF); +} + +/** + * @brief Clear IDLE line detected Flag + * @rmtoll ICR IDLECF LL_LPUART_ClearFlag_IDLE + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_ClearFlag_IDLE(USART_TypeDef *LPUARTx) +{ + WRITE_REG(LPUARTx->ICR, USART_ICR_IDLECF); +} + + +/** + * @brief Clear Transmission Complete Flag + * @rmtoll ICR TCCF LL_LPUART_ClearFlag_TC + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_ClearFlag_TC(USART_TypeDef *LPUARTx) +{ + WRITE_REG(LPUARTx->ICR, USART_ICR_TCCF); +} + +/** + * @brief Clear CTS Interrupt Flag + * @rmtoll ICR CTSCF LL_LPUART_ClearFlag_nCTS + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_ClearFlag_nCTS(USART_TypeDef *LPUARTx) +{ + WRITE_REG(LPUARTx->ICR, USART_ICR_CTSCF); +} + +/** + * @brief Clear Character Match Flag + * @rmtoll ICR CMCF LL_LPUART_ClearFlag_CM + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_ClearFlag_CM(USART_TypeDef *LPUARTx) +{ + WRITE_REG(LPUARTx->ICR, USART_ICR_CMCF); +} + +/** + * @brief Clear Wake Up from stop mode Flag + * @rmtoll ICR WUCF LL_LPUART_ClearFlag_WKUP + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_ClearFlag_WKUP(USART_TypeDef *LPUARTx) +{ + WRITE_REG(LPUARTx->ICR, USART_ICR_WUCF); +} + +/** + * @} + */ + +/** @defgroup LPUART_LL_EF_IT_Management IT_Management + * @{ + */ + +/** + * @brief Enable IDLE Interrupt + * @rmtoll CR1 IDLEIE LL_LPUART_EnableIT_IDLE + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableIT_IDLE(USART_TypeDef *LPUARTx) +{ + SET_BIT(LPUARTx->CR1, USART_CR1_IDLEIE); +} + + +/** + * @brief Enable RX Not Empty Interrupt + * @rmtoll CR1 RXNEIE LL_LPUART_EnableIT_RXNE + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableIT_RXNE(USART_TypeDef *LPUARTx) +{ + SET_BIT(LPUARTx->CR1, USART_CR1_RXNEIE); +} + +/** + * @brief Enable Transmission Complete Interrupt + * @rmtoll CR1 TCIE LL_LPUART_EnableIT_TC + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableIT_TC(USART_TypeDef *LPUARTx) +{ + SET_BIT(LPUARTx->CR1, USART_CR1_TCIE); +} + + +/** + * @brief Enable TX Empty Interrupt + * @rmtoll CR1 TXEIE LL_LPUART_EnableIT_TXE + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableIT_TXE(USART_TypeDef *LPUARTx) +{ + SET_BIT(LPUARTx->CR1, USART_CR1_TXEIE); +} + +/** + * @brief Enable Parity Error Interrupt + * @rmtoll CR1 PEIE LL_LPUART_EnableIT_PE + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableIT_PE(USART_TypeDef *LPUARTx) +{ + SET_BIT(LPUARTx->CR1, USART_CR1_PEIE); +} + +/** + * @brief Enable Character Match Interrupt + * @rmtoll CR1 CMIE LL_LPUART_EnableIT_CM + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableIT_CM(USART_TypeDef *LPUARTx) +{ + SET_BIT(LPUARTx->CR1, USART_CR1_CMIE); +} + + +/** + * @brief Enable Error Interrupt + * @note When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing + * error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register). + * - 0: Interrupt is inhibited + * - 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register. + * @rmtoll CR3 EIE LL_LPUART_EnableIT_ERROR + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableIT_ERROR(USART_TypeDef *LPUARTx) +{ + SET_BIT(LPUARTx->CR3, USART_CR3_EIE); +} + +/** + * @brief Enable CTS Interrupt + * @rmtoll CR3 CTSIE LL_LPUART_EnableIT_CTS + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableIT_CTS(USART_TypeDef *LPUARTx) +{ + SET_BIT(LPUARTx->CR3, USART_CR3_CTSIE); +} + +/** + * @brief Enable Wake Up from Stop Mode Interrupt + * @rmtoll CR3 WUFIE LL_LPUART_EnableIT_WKUP + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableIT_WKUP(USART_TypeDef *LPUARTx) +{ + SET_BIT(LPUARTx->CR3, USART_CR3_WUFIE); +} + + +/** + * @brief Disable IDLE Interrupt + * @rmtoll CR1 IDLEIE LL_LPUART_DisableIT_IDLE + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableIT_IDLE(USART_TypeDef *LPUARTx) +{ + CLEAR_BIT(LPUARTx->CR1, USART_CR1_IDLEIE); +} + + +/** + * @brief Disable RX Not Empty Interrupt + * @rmtoll CR1 RXNEIE LL_LPUART_DisableIT_RXNE + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableIT_RXNE(USART_TypeDef *LPUARTx) +{ + CLEAR_BIT(LPUARTx->CR1, USART_CR1_RXNEIE); +} + +/** + * @brief Disable Transmission Complete Interrupt + * @rmtoll CR1 TCIE LL_LPUART_DisableIT_TC + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableIT_TC(USART_TypeDef *LPUARTx) +{ + CLEAR_BIT(LPUARTx->CR1, USART_CR1_TCIE); +} + + +/** + * @brief Disable TX Empty Interrupt + * @rmtoll CR1 TXEIE LL_LPUART_DisableIT_TXE + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableIT_TXE(USART_TypeDef *LPUARTx) +{ + CLEAR_BIT(LPUARTx->CR1, USART_CR1_TXEIE); +} + +/** + * @brief Disable Parity Error Interrupt + * @rmtoll CR1 PEIE LL_LPUART_DisableIT_PE + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableIT_PE(USART_TypeDef *LPUARTx) +{ + CLEAR_BIT(LPUARTx->CR1, USART_CR1_PEIE); +} + +/** + * @brief Disable Character Match Interrupt + * @rmtoll CR1 CMIE LL_LPUART_DisableIT_CM + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableIT_CM(USART_TypeDef *LPUARTx) +{ + CLEAR_BIT(LPUARTx->CR1, USART_CR1_CMIE); +} + + +/** + * @brief Disable Error Interrupt + * @note When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing + * error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register). + * - 0: Interrupt is inhibited + * - 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register. + * @rmtoll CR3 EIE LL_LPUART_DisableIT_ERROR + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableIT_ERROR(USART_TypeDef *LPUARTx) +{ + CLEAR_BIT(LPUARTx->CR3, USART_CR3_EIE); +} + +/** + * @brief Disable CTS Interrupt + * @rmtoll CR3 CTSIE LL_LPUART_DisableIT_CTS + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableIT_CTS(USART_TypeDef *LPUARTx) +{ + CLEAR_BIT(LPUARTx->CR3, USART_CR3_CTSIE); +} + +/** + * @brief Disable Wake Up from Stop Mode Interrupt + * @rmtoll CR3 WUFIE LL_LPUART_DisableIT_WKUP + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableIT_WKUP(USART_TypeDef *LPUARTx) +{ + CLEAR_BIT(LPUARTx->CR3, USART_CR3_WUFIE); +} + + +/** + * @brief Check if the LPUART IDLE Interrupt source is enabled or disabled. + * @rmtoll CR1 IDLEIE LL_LPUART_IsEnabledIT_IDLE + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_IDLE(USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE)) ? 1UL : 0UL); +} + + +/** + * @brief Check if the LPUART RX Not Empty Interrupt is enabled or disabled. + * @rmtoll CR1 RXNEIE LL_LPUART_IsEnabledIT_RXNE + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXNE(USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR1, USART_CR1_RXNEIE) == (USART_CR1_RXNEIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART Transmission Complete Interrupt is enabled or disabled. + * @rmtoll CR1 TCIE LL_LPUART_IsEnabledIT_TC + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TC(USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE)) ? 1UL : 0UL); +} + + +/** + * @brief Check if the LPUART TX Empty Interrupt is enabled or disabled. + * @rmtoll CR1 TXEIE LL_LPUART_IsEnabledIT_TXE + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXE(USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR1, USART_CR1_TXEIE) == (USART_CR1_TXEIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART Parity Error Interrupt is enabled or disabled. + * @rmtoll CR1 PEIE LL_LPUART_IsEnabledIT_PE + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_PE(USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART Character Match Interrupt is enabled or disabled. + * @rmtoll CR1 CMIE LL_LPUART_IsEnabledIT_CM + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CM(USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR1, USART_CR1_CMIE) == (USART_CR1_CMIE)) ? 1UL : 0UL); +} + + +/** + * @brief Check if the LPUART Error Interrupt is enabled or disabled. + * @rmtoll CR3 EIE LL_LPUART_IsEnabledIT_ERROR + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_ERROR(USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART CTS Interrupt is enabled or disabled. + * @rmtoll CR3 CTSIE LL_LPUART_IsEnabledIT_CTS + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CTS(USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART Wake Up from Stop Mode Interrupt is enabled or disabled. + * @rmtoll CR3 WUFIE LL_LPUART_IsEnabledIT_WKUP + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_WKUP(USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR3, USART_CR3_WUFIE) == (USART_CR3_WUFIE)) ? 1UL : 0UL); +} + + +/** + * @} + */ + +/** @defgroup LPUART_LL_EF_DMA_Management DMA_Management + * @{ + */ + +/** + * @brief Enable DMA Mode for reception + * @rmtoll CR3 DMAR LL_LPUART_EnableDMAReq_RX + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableDMAReq_RX(USART_TypeDef *LPUARTx) +{ + SET_BIT(LPUARTx->CR3, USART_CR3_DMAR); +} + +/** + * @brief Disable DMA Mode for reception + * @rmtoll CR3 DMAR LL_LPUART_DisableDMAReq_RX + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableDMAReq_RX(USART_TypeDef *LPUARTx) +{ + CLEAR_BIT(LPUARTx->CR3, USART_CR3_DMAR); +} + +/** + * @brief Check if DMA Mode is enabled for reception + * @rmtoll CR3 DMAR LL_LPUART_IsEnabledDMAReq_RX + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMAReq_RX(USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR)) ? 1UL : 0UL); +} + +/** + * @brief Enable DMA Mode for transmission + * @rmtoll CR3 DMAT LL_LPUART_EnableDMAReq_TX + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableDMAReq_TX(USART_TypeDef *LPUARTx) +{ + SET_BIT(LPUARTx->CR3, USART_CR3_DMAT); +} + +/** + * @brief Disable DMA Mode for transmission + * @rmtoll CR3 DMAT LL_LPUART_DisableDMAReq_TX + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableDMAReq_TX(USART_TypeDef *LPUARTx) +{ + CLEAR_BIT(LPUARTx->CR3, USART_CR3_DMAT); +} + +/** + * @brief Check if DMA Mode is enabled for transmission + * @rmtoll CR3 DMAT LL_LPUART_IsEnabledDMAReq_TX + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMAReq_TX(USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT)) ? 1UL : 0UL); +} + +/** + * @brief Enable DMA Disabling on Reception Error + * @rmtoll CR3 DDRE LL_LPUART_EnableDMADeactOnRxErr + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableDMADeactOnRxErr(USART_TypeDef *LPUARTx) +{ + SET_BIT(LPUARTx->CR3, USART_CR3_DDRE); +} + +/** + * @brief Disable DMA Disabling on Reception Error + * @rmtoll CR3 DDRE LL_LPUART_DisableDMADeactOnRxErr + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableDMADeactOnRxErr(USART_TypeDef *LPUARTx) +{ + CLEAR_BIT(LPUARTx->CR3, USART_CR3_DDRE); +} + +/** + * @brief Indicate if DMA Disabling on Reception Error is disabled + * @rmtoll CR3 DDRE LL_LPUART_IsEnabledDMADeactOnRxErr + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMADeactOnRxErr(USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR3, USART_CR3_DDRE) == (USART_CR3_DDRE)) ? 1UL : 0UL); +} + +/** + * @brief Get the LPUART data register address used for DMA transfer + * @rmtoll RDR RDR LL_LPUART_DMA_GetRegAddr\n + * @rmtoll TDR TDR LL_LPUART_DMA_GetRegAddr + * @param LPUARTx LPUART Instance + * @param Direction This parameter can be one of the following values: + * @arg @ref LL_LPUART_DMA_REG_DATA_TRANSMIT + * @arg @ref LL_LPUART_DMA_REG_DATA_RECEIVE + * @retval Address of data register + */ +__STATIC_INLINE uint32_t LL_LPUART_DMA_GetRegAddr(USART_TypeDef *LPUARTx, uint32_t Direction) +{ + uint32_t data_reg_addr; + + if (Direction == LL_LPUART_DMA_REG_DATA_TRANSMIT) + { + /* return address of TDR register */ + data_reg_addr = (uint32_t) &(LPUARTx->TDR); + } + else + { + /* return address of RDR register */ + data_reg_addr = (uint32_t) &(LPUARTx->RDR); + } + + return data_reg_addr; +} + +/** + * @} + */ + +/** @defgroup LPUART_LL_EF_Data_Management Data_Management + * @{ + */ + +/** + * @brief Read Receiver Data register (Receive Data value, 8 bits) + * @rmtoll RDR RDR LL_LPUART_ReceiveData8 + * @param LPUARTx LPUART Instance + * @retval Time Value between Min_Data=0x00 and Max_Data=0xFF + */ +__STATIC_INLINE uint8_t LL_LPUART_ReceiveData8(USART_TypeDef *LPUARTx) +{ + return (uint8_t)(READ_BIT(LPUARTx->RDR, USART_RDR_RDR) & 0xFFU); +} + +/** + * @brief Read Receiver Data register (Receive Data value, 9 bits) + * @rmtoll RDR RDR LL_LPUART_ReceiveData9 + * @param LPUARTx LPUART Instance + * @retval Time Value between Min_Data=0x00 and Max_Data=0x1FF + */ +__STATIC_INLINE uint16_t LL_LPUART_ReceiveData9(USART_TypeDef *LPUARTx) +{ + return (uint16_t)(READ_BIT(LPUARTx->RDR, USART_RDR_RDR)); +} + +/** + * @brief Write in Transmitter Data Register (Transmit Data value, 8 bits) + * @rmtoll TDR TDR LL_LPUART_TransmitData8 + * @param LPUARTx LPUART Instance + * @param Value between Min_Data=0x00 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void LL_LPUART_TransmitData8(USART_TypeDef *LPUARTx, uint8_t Value) +{ + LPUARTx->TDR = Value; +} + +/** + * @brief Write in Transmitter Data Register (Transmit Data value, 9 bits) + * @rmtoll TDR TDR LL_LPUART_TransmitData9 + * @param LPUARTx LPUART Instance + * @param Value between Min_Data=0x00 and Max_Data=0x1FF + * @retval None + */ +__STATIC_INLINE void LL_LPUART_TransmitData9(USART_TypeDef *LPUARTx, uint16_t Value) +{ + LPUARTx->TDR = Value & 0x1FFUL; +} + +/** + * @} + */ + +/** @defgroup LPUART_LL_EF_Execution Execution + * @{ + */ + +/** + * @brief Request Break sending + * @rmtoll RQR SBKRQ LL_LPUART_RequestBreakSending + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_RequestBreakSending(USART_TypeDef *LPUARTx) +{ + SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_SBKRQ); +} + +/** + * @brief Put LPUART in mute mode and set the RWU flag + * @rmtoll RQR MMRQ LL_LPUART_RequestEnterMuteMode + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_RequestEnterMuteMode(USART_TypeDef *LPUARTx) +{ + SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_MMRQ); +} + +/** + * @brief Request a Receive Data flush + * @note Allows to discard the received data without reading them, and avoid an overrun + * condition. + * @rmtoll RQR RXFRQ LL_LPUART_RequestRxDataFlush + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_RequestRxDataFlush(USART_TypeDef *LPUARTx) +{ + SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_RXFRQ); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup LPUART_LL_EF_Init Initialization and de-initialization functions + * @{ + */ +ErrorStatus LL_LPUART_DeInit(USART_TypeDef *LPUARTx); +ErrorStatus LL_LPUART_Init(USART_TypeDef *LPUARTx, LL_LPUART_InitTypeDef *LPUART_InitStruct); +void LL_LPUART_StructInit(LL_LPUART_InitTypeDef *LPUART_InitStruct); +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* LPUART1 */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32L0xx_LL_LPUART_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/fw/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h b/fw/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h new file mode 100644 index 0000000..f21d7f6 --- /dev/null +++ b/fw/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h @@ -0,0 +1,746 @@ +/** + ****************************************************************************** + * @file stm32l0xx_ll_pwr.h + * @author MCD Application Team + * @brief Header file of PWR LL module. + ****************************************************************************** + * @attention + * + *

© Copyright(c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32L0xx_LL_PWR_H +#define __STM32L0xx_LL_PWR_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l0xx.h" + +/** @addtogroup STM32L0xx_LL_Driver + * @{ + */ + +#if defined(PWR) + +/** @defgroup PWR_LL PWR + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup PWR_LL_Exported_Constants PWR Exported Constants + * @{ + */ + +/** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines + * @brief Flags defines which can be used with LL_PWR_WriteReg function + * @{ + */ +#define LL_PWR_CR_CSBF PWR_CR_CSBF /*!< Clear standby flag */ +#define LL_PWR_CR_CWUF PWR_CR_CWUF /*!< Clear wakeup flag */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_PWR_ReadReg function + * @{ + */ +#define LL_PWR_CSR_WUF PWR_CSR_WUF /*!< Wakeup flag */ +#define LL_PWR_CSR_SBF PWR_CSR_SBF /*!< Standby flag */ +#if defined(PWR_PVD_SUPPORT) +#define LL_PWR_CSR_PVDO PWR_CSR_PVDO /*!< Power voltage detector output flag */ +#endif /* PWR_PVD_SUPPORT */ +#if defined(PWR_CSR_VREFINTRDYF) +#define LL_PWR_CSR_VREFINTRDYF PWR_CSR_VREFINTRDYF /*!< VREFINT ready flag */ +#endif /* PWR_CSR_VREFINTRDYF */ +#define LL_PWR_CSR_VOS PWR_CSR_VOSF /*!< Voltage scaling select flag */ +#define LL_PWR_CSR_REGLPF PWR_CSR_REGLPF /*!< Regulator low power flag */ +#define LL_PWR_CSR_EWUP1 PWR_CSR_EWUP1 /*!< Enable WKUP pin 1 */ +#define LL_PWR_CSR_EWUP2 PWR_CSR_EWUP2 /*!< Enable WKUP pin 2 */ +#if defined(PWR_CSR_EWUP3) +#define LL_PWR_CSR_EWUP3 PWR_CSR_EWUP3 /*!< Enable WKUP pin 3 */ +#endif /* PWR_CSR_EWUP3 */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_REGU_VOLTAGE Regulator Voltage + * @{ + */ +#define LL_PWR_REGU_VOLTAGE_SCALE1 (PWR_CR_VOS_0) /*!< 1.8V (range 1) */ +#define LL_PWR_REGU_VOLTAGE_SCALE2 (PWR_CR_VOS_1) /*!< 1.5V (range 2) */ +#define LL_PWR_REGU_VOLTAGE_SCALE3 (PWR_CR_VOS_0 | PWR_CR_VOS_1) /*!< 1.2V (range 3) */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_MODE_PWR Mode Power + * @{ + */ +#define LL_PWR_MODE_STOP 0x00000000U /*!< Enter Stop mode when the CPU enters deepsleep */ +#define LL_PWR_MODE_STANDBY (PWR_CR_PDDS) /*!< Enter Standby mode when the CPU enters deepsleep */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_REGU_MODE_LP_MODES Regulator Mode In Low Power Modes + * @{ + */ +#define LL_PWR_REGU_LPMODES_MAIN 0x00000000U /*!< Voltage regulator in main mode during deepsleep/sleep/low-power run mode */ +#define LL_PWR_REGU_LPMODES_LOW_POWER (PWR_CR_LPSDSR) /*!< Voltage regulator in low-power mode during deepsleep/sleep/low-power run mode */ +/** + * @} + */ +#if defined(PWR_CR_LPDS) +/** @defgroup PWR_LL_EC_REGU_MODE_DS_MODE Regulator Mode In Deep Sleep Mode + * @{ + */ +#define LL_PWR_REGU_DSMODE_MAIN 0x00000000U /*!< Voltage regulator in main mode during deepsleep mode when PWR_CR_LPSDSR = 0 */ +#define LL_PWR_REGU_DSMODE_LOW_POWER (PWR_CR_LPDS) /*!< Voltage regulator in low-power mode during deepsleep mode when PWR_CR_LPSDSR = 0 */ +/** + * @} + */ +#endif /* PWR_CR_LPDS */ + +#if defined(PWR_PVD_SUPPORT) +/** @defgroup PWR_LL_EC_PVDLEVEL Power Voltage Detector Level + * @{ + */ +#define LL_PWR_PVDLEVEL_0 (PWR_CR_PLS_LEV0) /*!< Voltage threshold detected by PVD 1.9 V */ +#define LL_PWR_PVDLEVEL_1 (PWR_CR_PLS_LEV1) /*!< Voltage threshold detected by PVD 2.1 V */ +#define LL_PWR_PVDLEVEL_2 (PWR_CR_PLS_LEV2) /*!< Voltage threshold detected by PVD 2.3 V */ +#define LL_PWR_PVDLEVEL_3 (PWR_CR_PLS_LEV3) /*!< Voltage threshold detected by PVD 2.5 V */ +#define LL_PWR_PVDLEVEL_4 (PWR_CR_PLS_LEV4) /*!< Voltage threshold detected by PVD 2.7 V */ +#define LL_PWR_PVDLEVEL_5 (PWR_CR_PLS_LEV5) /*!< Voltage threshold detected by PVD 2.9 V */ +#define LL_PWR_PVDLEVEL_6 (PWR_CR_PLS_LEV6) /*!< Voltage threshold detected by PVD 3.1 V */ +#define LL_PWR_PVDLEVEL_7 (PWR_CR_PLS_LEV7) /*!< External input analog voltage (Compare internally to VREFINT) */ +/** + * @} + */ +#endif /* PWR_PVD_SUPPORT */ +/** @defgroup PWR_LL_EC_WAKEUP_PIN Wakeup Pins + * @{ + */ +#define LL_PWR_WAKEUP_PIN1 (PWR_CSR_EWUP1) /*!< WKUP pin 1 : PA0 */ +#define LL_PWR_WAKEUP_PIN2 (PWR_CSR_EWUP2) /*!< WKUP pin 2 : PC13 */ +#if defined(PWR_CSR_EWUP3) +#define LL_PWR_WAKEUP_PIN3 (PWR_CSR_EWUP3) /*!< WKUP pin 3 : PE6 or PA2 according to device */ +#endif /* PWR_CSR_EWUP3 */ +/** + * @} + */ + +/** + * @} + */ + + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup PWR_LL_Exported_Macros PWR Exported Macros + * @{ + */ + +/** @defgroup PWR_LL_EM_WRITE_READ Common write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in PWR register + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__)) + +/** + * @brief Read a value in PWR register + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__) +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup PWR_LL_Exported_Functions PWR Exported Functions + * @{ + */ + +/** @defgroup PWR_LL_EF_Configuration Configuration + * @{ + */ +/** + * @brief Switch the regulator from main mode to low-power mode + * @rmtoll CR LPRUN LL_PWR_EnableLowPowerRunMode + * @note Remind to set the regulator to low power before enabling + * LowPower run mode (bit @ref LL_PWR_REGU_LPMODES_LOW_POWER). + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableLowPowerRunMode(void) +{ + SET_BIT(PWR->CR, PWR_CR_LPRUN); +} + +/** + * @brief Switch the regulator from low-power mode to main mode + * @rmtoll CR LPRUN LL_PWR_DisableLowPowerRunMode + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableLowPowerRunMode(void) +{ + CLEAR_BIT(PWR->CR, PWR_CR_LPRUN); +} + +/** + * @brief Check if the regulator is in low-power mode + * @rmtoll CR LPRUN LL_PWR_IsEnabledLowPowerRunMode + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledLowPowerRunMode(void) +{ + return (READ_BIT(PWR->CR, PWR_CR_LPRUN) == (PWR_CR_LPRUN)); +} + +/** + * @brief Set voltage regulator to low-power and switch from + * run main mode to run low-power mode. + * @rmtoll CR LPSDSR LL_PWR_EnterLowPowerRunMode\n + * CR LPRUN LL_PWR_EnterLowPowerRunMode + * @note This "high level" function is introduced to provide functional + * compatibility with other families. Notice that the two registers + * have to be written sequentially, so this function is not atomic. + * To assure atomicity you can call separately the following functions: + * - @ref LL_PWR_SetRegulModeLP(@ref LL_PWR_REGU_LPMODES_LOW_POWER); + * - @ref LL_PWR_EnableLowPowerRunMode(); + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnterLowPowerRunMode(void) +{ + SET_BIT(PWR->CR, PWR_CR_LPSDSR); /* => LL_PWR_SetRegulModeLP(LL_PWR_REGU_LPMODES_LOW_POWER) */ + SET_BIT(PWR->CR, PWR_CR_LPRUN); /* => LL_PWR_EnableLowPowerRunMode() */ +} + +/** + * @brief Set voltage regulator to main and switch from + * run main mode to low-power mode. + * @rmtoll CR LPSDSR LL_PWR_ExitLowPowerRunMode\n + * CR LPRUN LL_PWR_ExitLowPowerRunMode + * @note This "high level" function is introduced to provide functional + * compatibility with other families. Notice that the two registers + * have to be written sequentially, so this function is not atomic. + * To assure atomicity you can call separately the following functions: + * - @ref LL_PWR_DisableLowPowerRunMode(); + * - @ref LL_PWR_SetRegulModeLP(@ref LL_PWR_REGU_LPMODES_MAIN); + * @retval None + */ +__STATIC_INLINE void LL_PWR_ExitLowPowerRunMode(void) +{ + CLEAR_BIT(PWR->CR, PWR_CR_LPRUN); /* => LL_PWR_DisableLowPowerRunMode() */ + CLEAR_BIT(PWR->CR, PWR_CR_LPSDSR); /* => LL_PWR_SetRegulModeLP(LL_PWR_REGU_LPMODES_MAIN) */ +} +/** + * @brief Set the main internal regulator output voltage + * @rmtoll CR VOS LL_PWR_SetRegulVoltageScaling + * @param VoltageScaling This parameter can be one of the following values: + * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1 + * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2 + * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE3 + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetRegulVoltageScaling(uint32_t VoltageScaling) +{ + MODIFY_REG(PWR->CR, PWR_CR_VOS, VoltageScaling); +} + +/** + * @brief Get the main internal regulator output voltage + * @rmtoll CR VOS LL_PWR_GetRegulVoltageScaling + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1 + * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2 + * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE3 + */ +__STATIC_INLINE uint32_t LL_PWR_GetRegulVoltageScaling(void) +{ + return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_VOS)); +} + +/** + * @brief Enable access to the backup domain + * @rmtoll CR DBP LL_PWR_EnableBkUpAccess + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableBkUpAccess(void) +{ + SET_BIT(PWR->CR, PWR_CR_DBP); +} + +/** + * @brief Disable access to the backup domain + * @rmtoll CR DBP LL_PWR_DisableBkUpAccess + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableBkUpAccess(void) +{ + CLEAR_BIT(PWR->CR, PWR_CR_DBP); +} + +/** + * @brief Check if the backup domain is enabled + * @rmtoll CR DBP LL_PWR_IsEnabledBkUpAccess + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void) +{ + return (READ_BIT(PWR->CR, PWR_CR_DBP) == (PWR_CR_DBP)); +} + +/** + * @brief Set voltage regulator mode during low power modes + * @rmtoll CR LPSDSR LL_PWR_SetRegulModeLP + * @param RegulMode This parameter can be one of the following values: + * @arg @ref LL_PWR_REGU_LPMODES_MAIN + * @arg @ref LL_PWR_REGU_LPMODES_LOW_POWER + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetRegulModeLP(uint32_t RegulMode) +{ + MODIFY_REG(PWR->CR, PWR_CR_LPSDSR, RegulMode); +} + +/** + * @brief Get voltage regulator mode during low power modes + * @rmtoll CR LPSDSR LL_PWR_GetRegulModeLP + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_REGU_LPMODES_MAIN + * @arg @ref LL_PWR_REGU_LPMODES_LOW_POWER + */ +__STATIC_INLINE uint32_t LL_PWR_GetRegulModeLP(void) +{ + return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_LPSDSR)); +} + +#if defined(PWR_CR_LPDS) +/** + * @brief Set voltage regulator mode during deep sleep mode + * @rmtoll CR LPDS LL_PWR_SetRegulModeDS + * @param RegulMode This parameter can be one of the following values: + * @arg @ref LL_PWR_REGU_DSMODE_MAIN + * @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetRegulModeDS(uint32_t RegulMode) +{ + MODIFY_REG(PWR->CR, PWR_CR_LPDS, RegulMode); +} + +/** + * @brief Get voltage regulator mode during deep sleep mode + * @rmtoll CR LPDS LL_PWR_GetRegulModeDS + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_REGU_DSMODE_MAIN + * @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER + */ +__STATIC_INLINE uint32_t LL_PWR_GetRegulModeDS(void) +{ + return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_LPDS)); +} +#endif /* PWR_CR_LPDS */ + +/** + * @brief Set power down mode when CPU enters deepsleep + * @rmtoll CR PDDS LL_PWR_SetPowerMode + * @param PDMode This parameter can be one of the following values: + * @arg @ref LL_PWR_MODE_STOP + * @arg @ref LL_PWR_MODE_STANDBY + * @note Set the regulator to low power (bit @ref LL_PWR_REGU_LPMODES_LOW_POWER) + * before setting MODE_STOP. If the regulator remains in "main mode", + * it consumes more power without providing any additional feature. + * In MODE_STANDBY the regulator is automatically off. + * @note It is forbidden to configure both EN_VREFINT=1 and ULP=1 if the device is + * in Stop mode or in Sleep/Low-power sleep mode. If the device is not in + * low-power mode, VREFINT is always enabled whatever the state of EN_VREFINT and ULP + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t PDMode) +{ + MODIFY_REG(PWR->CR, PWR_CR_PDDS, PDMode); +} + +/** + * @brief Get power down mode when CPU enters deepsleep + * @rmtoll CR PDDS LL_PWR_GetPowerMode + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_MODE_STOP + * @arg @ref LL_PWR_MODE_STANDBY + */ +__STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void) +{ + return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_PDDS)); +} + +#if defined(PWR_PVD_SUPPORT) +/** + * @brief Configure the voltage threshold detected by the Power Voltage Detector + * @rmtoll CR PLS LL_PWR_SetPVDLevel + * @param PVDLevel This parameter can be one of the following values: + * @arg @ref LL_PWR_PVDLEVEL_0 + * @arg @ref LL_PWR_PVDLEVEL_1 + * @arg @ref LL_PWR_PVDLEVEL_2 + * @arg @ref LL_PWR_PVDLEVEL_3 + * @arg @ref LL_PWR_PVDLEVEL_4 + * @arg @ref LL_PWR_PVDLEVEL_5 + * @arg @ref LL_PWR_PVDLEVEL_6 + * @arg @ref LL_PWR_PVDLEVEL_7 + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetPVDLevel(uint32_t PVDLevel) +{ + MODIFY_REG(PWR->CR, PWR_CR_PLS, PVDLevel); +} + +/** + * @brief Get the voltage threshold detection + * @rmtoll CR PLS LL_PWR_GetPVDLevel + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_PVDLEVEL_0 + * @arg @ref LL_PWR_PVDLEVEL_1 + * @arg @ref LL_PWR_PVDLEVEL_2 + * @arg @ref LL_PWR_PVDLEVEL_3 + * @arg @ref LL_PWR_PVDLEVEL_4 + * @arg @ref LL_PWR_PVDLEVEL_5 + * @arg @ref LL_PWR_PVDLEVEL_6 + * @arg @ref LL_PWR_PVDLEVEL_7 + */ +__STATIC_INLINE uint32_t LL_PWR_GetPVDLevel(void) +{ + return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_PLS)); +} + +/** + * @brief Enable Power Voltage Detector + * @rmtoll CR PVDE LL_PWR_EnablePVD + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnablePVD(void) +{ + SET_BIT(PWR->CR, PWR_CR_PVDE); +} + +/** + * @brief Disable Power Voltage Detector + * @rmtoll CR PVDE LL_PWR_DisablePVD + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisablePVD(void) +{ + CLEAR_BIT(PWR->CR, PWR_CR_PVDE); +} + +/** + * @brief Check if Power Voltage Detector is enabled + * @rmtoll CR PVDE LL_PWR_IsEnabledPVD + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void) +{ + return (READ_BIT(PWR->CR, PWR_CR_PVDE) == (PWR_CR_PVDE)); +} +#endif /* PWR_PVD_SUPPORT */ + +/** + * @brief Enable the WakeUp PINx functionality + * @rmtoll CSR EWUP1 LL_PWR_EnableWakeUpPin\n + * @rmtoll CSR EWUP2 LL_PWR_EnableWakeUpPin\n + * @rmtoll CSR EWUP3 LL_PWR_EnableWakeUpPin + * @param WakeUpPin This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1 + * @arg @ref LL_PWR_WAKEUP_PIN2 + * @arg @ref LL_PWR_WAKEUP_PIN3 (*) + * + * (*) not available on all devices + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin) +{ + SET_BIT(PWR->CSR, WakeUpPin); +} + +/** + * @brief Disable the WakeUp PINx functionality + * @rmtoll CSR EWUP1 LL_PWR_DisableWakeUpPin\n + * @rmtoll CSR EWUP2 LL_PWR_DisableWakeUpPin\n + * @rmtoll CSR EWUP3 LL_PWR_DisableWakeUpPin + * @param WakeUpPin This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1 + * @arg @ref LL_PWR_WAKEUP_PIN2 + * @arg @ref LL_PWR_WAKEUP_PIN3 (*) + * + * (*) not available on all devices + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin) +{ + CLEAR_BIT(PWR->CSR, WakeUpPin); +} + +/** + * @brief Check if the WakeUp PINx functionality is enabled + * @rmtoll CSR EWUP1 LL_PWR_IsEnabledWakeUpPin\n + * @rmtoll CSR EWUP2 LL_PWR_IsEnabledWakeUpPin\n + * @rmtoll CSR EWUP3 LL_PWR_IsEnabledWakeUpPin + * @param WakeUpPin This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1 + * @arg @ref LL_PWR_WAKEUP_PIN2 + * @arg @ref LL_PWR_WAKEUP_PIN3 (*) + * + * (*) not available on all devices + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin) +{ + return (READ_BIT(PWR->CSR, WakeUpPin) == (WakeUpPin)); +} + +/** + * @brief Enable ultra low-power mode by enabling VREFINT switch off in low-power modes + * @rmtoll CR ULP LL_PWR_EnableUltraLowPower + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableUltraLowPower(void) +{ + SET_BIT(PWR->CR, PWR_CR_ULP); +} + +/** + * @brief Disable ultra low-power mode by disabling VREFINT switch off in low-power modes + * @rmtoll CR ULP LL_PWR_DisableUltraLowPower + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableUltraLowPower(void) +{ + CLEAR_BIT(PWR->CR, PWR_CR_ULP); +} + +/** + * @brief Check if ultra low-power mode is enabled by checking if VREFINT switch off in low-power modes is enabled + * @rmtoll CR ULP LL_PWR_IsEnabledUltraLowPower + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledUltraLowPower(void) +{ + return (READ_BIT(PWR->CR, PWR_CR_ULP) == (PWR_CR_ULP)); +} + +/** + * @brief Enable fast wakeup by ignoring VREFINT startup time when exiting from low-power mode + * @rmtoll CR FWU LL_PWR_EnableFastWakeUp + * @note Works in conjunction with ultra low power mode. + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableFastWakeUp(void) +{ + SET_BIT(PWR->CR, PWR_CR_FWU); +} + +/** + * @brief Disable fast wakeup by waiting VREFINT startup time when exiting from low-power mode + * @rmtoll CR FWU LL_PWR_DisableFastWakeUp + * @note Works in conjunction with ultra low power mode. + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableFastWakeUp(void) +{ + CLEAR_BIT(PWR->CR, PWR_CR_FWU); +} + +/** + * @brief Check if fast wakeup is enabled by checking if VREFINT startup time when exiting from low-power mode is ignored + * @rmtoll CR FWU LL_PWR_IsEnabledFastWakeUp + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledFastWakeUp(void) +{ + return (READ_BIT(PWR->CR, PWR_CR_FWU) == (PWR_CR_FWU)); +} + +/** + * @brief Enable non-volatile memory (Flash and EEPROM) keeping off feature when exiting from low-power mode + * @rmtoll CR DS_EE_KOFF LL_PWR_EnableNVMKeptOff + * @note When enabled, after entering low-power mode (Stop or Standby only), if RUN_PD of FLASH_ACR register + * is also set, the Flash memory will not be woken up when exiting from deepsleep mode. + * When enabled, the EEPROM will not be woken up when exiting from low-power mode (if the bit RUN_PD is set) + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableNVMKeptOff(void) +{ + SET_BIT(PWR->CR, PWR_CR_DSEEKOFF); +} + +/** + * @brief Disable non-volatile memory (Flash and EEPROM) keeping off feature when exiting from low-power mode + * @rmtoll CR DS_EE_KOFF LL_PWR_DisableNVMKeptOff + * @note When disabled, Flash memory is woken up when exiting from deepsleep mode even if the bit RUN_PD is set + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableNVMKeptOff(void) +{ + CLEAR_BIT(PWR->CR, PWR_CR_DSEEKOFF); +} + +/** + * @brief Check if non-volatile memory (Flash and EEPROM) keeping off feature when exiting from low-power mode is enabled + * @rmtoll CR DS_EE_KOFF LL_PWR_IsEnabledNVMKeptOff + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledNVMKeptOff(void) +{ + return (READ_BIT(PWR->CR, PWR_CR_DSEEKOFF) == (PWR_CR_DSEEKOFF)); +} + +/** + * @} + */ + +/** @defgroup PWR_LL_EF_FLAG_Management FLAG_Management + * @{ + */ + +/** + * @brief Get Wake-up Flag + * @rmtoll CSR WUF LL_PWR_IsActiveFlag_WU + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU(void) +{ + return (READ_BIT(PWR->CSR, PWR_CSR_WUF) == (PWR_CSR_WUF)); +} + +/** + * @brief Get Standby Flag + * @rmtoll CSR SBF LL_PWR_IsActiveFlag_SB + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SB(void) +{ + return (READ_BIT(PWR->CSR, PWR_CSR_SBF) == (PWR_CSR_SBF)); +} + +#if defined(PWR_PVD_SUPPORT) +/** + * @brief Indicate whether VDD voltage is below the selected PVD threshold + * @rmtoll CSR PVDO LL_PWR_IsActiveFlag_PVDO + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void) +{ + return (READ_BIT(PWR->CSR, PWR_CSR_PVDO) == (PWR_CSR_PVDO)); +} +#endif /* PWR_PVD_SUPPORT */ + +#if defined(PWR_CSR_VREFINTRDYF) +/** + * @brief Get Internal Reference VrefInt Flag + * @rmtoll CSR VREFINTRDYF LL_PWR_IsActiveFlag_VREFINTRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VREFINTRDY(void) +{ + return (READ_BIT(PWR->CSR, PWR_CSR_VREFINTRDYF) == (PWR_CSR_VREFINTRDYF)); +} +#endif /* PWR_CSR_VREFINTRDYF */ +/** + * @brief Indicate whether the regulator is ready in the selected voltage range or if its output voltage is still changing to the required voltage level + * @rmtoll CSR VOSF LL_PWR_IsActiveFlag_VOS + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VOS(void) +{ + return (READ_BIT(PWR->CSR, LL_PWR_CSR_VOS) == (LL_PWR_CSR_VOS)); +} +/** + * @brief Indicate whether the regulator is ready in main mode or is in low-power mode + * @rmtoll CSR REGLPF LL_PWR_IsActiveFlag_REGLPF + * @note Take care, return value "0" means the regulator is ready. Return value "1" means the output voltage range is still changing. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_REGLPF(void) +{ + return (READ_BIT(PWR->CSR, PWR_CSR_REGLPF) == (PWR_CSR_REGLPF)); +} +/** + * @brief Clear Standby Flag + * @rmtoll CR CSBF LL_PWR_ClearFlag_SB + * @retval None + */ +__STATIC_INLINE void LL_PWR_ClearFlag_SB(void) +{ + SET_BIT(PWR->CR, PWR_CR_CSBF); +} + +/** + * @brief Clear Wake-up Flags + * @rmtoll CR CWUF LL_PWR_ClearFlag_WU + * @retval None + */ +__STATIC_INLINE void LL_PWR_ClearFlag_WU(void) +{ + SET_BIT(PWR->CR, PWR_CR_CWUF); +} +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup PWR_LL_EF_Init De-initialization function + * @{ + */ +ErrorStatus LL_PWR_DeInit(void); +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined(PWR) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32L0xx_LL_PWR_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/fw/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h b/fw/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h new file mode 100644 index 0000000..1195380 --- /dev/null +++ b/fw/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h @@ -0,0 +1,2497 @@ +/** + ****************************************************************************** + * @file stm32l0xx_ll_rcc.h + * @author MCD Application Team + * @brief Header file of RCC LL module. + ****************************************************************************** + * @attention + * + *

© Copyright(c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32L0xx_LL_RCC_H +#define __STM32L0xx_LL_RCC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l0xx.h" + +/** @addtogroup STM32L0xx_LL_Driver + * @{ + */ + +#if defined(RCC) + +/** @defgroup RCC_LL RCC + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/** @defgroup RCC_LL_Private_Variables RCC Private Variables + * @{ + */ + +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup RCC_LL_Private_Constants RCC Private Constants + * @{ + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup RCC_LL_Private_Macros RCC Private Macros + * @{ + */ +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup RCC_LL_Exported_Types RCC Exported Types + * @{ + */ + +/** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure + * @{ + */ + +/** + * @brief RCC Clocks Frequency Structure + */ +typedef struct +{ + uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency */ + uint32_t HCLK_Frequency; /*!< HCLK clock frequency */ + uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency */ + uint32_t PCLK2_Frequency; /*!< PCLK2 clock frequency */ +} LL_RCC_ClocksTypeDef; + +/** + * @} + */ + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup RCC_LL_Exported_Constants RCC Exported Constants + * @{ + */ + +/** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation + * @brief Defines used to adapt values of different oscillators + * @note These values could be modified in the user environment according to + * HW set-up. + * @{ + */ +#if !defined (HSE_VALUE) +#define HSE_VALUE (8000000U) /*!< Value of the HSE oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSI_VALUE) +#define HSI_VALUE (16000000U) /*!< Value of the HSI oscillator in Hz */ +#endif /* HSI_VALUE */ + +#if !defined (LSE_VALUE) +#define LSE_VALUE (32768U) /*!< Value of the LSE oscillator in Hz */ +#endif /* LSE_VALUE */ + +#if !defined (LSI_VALUE) +#define LSI_VALUE (37000U) /*!< Value of the LSI oscillator in Hz */ +#endif /* LSI_VALUE */ +#if defined(RCC_HSI48_SUPPORT) + +#if !defined (HSI48_VALUE) +#define HSI48_VALUE (48000000U) /*!< Value of the HSI48 oscillator in Hz */ +#endif /* HSI48_VALUE */ +#endif /* RCC_HSI48_SUPPORT */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_CLEAR_FLAG Clear Flags Defines + * @brief Flags defines which can be used with LL_RCC_WriteReg function + * @{ + */ +#define LL_RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC /*!< LSI Ready Interrupt Clear */ +#define LL_RCC_CICR_LSERDYC RCC_CICR_LSERDYC /*!< LSE Ready Interrupt Clear */ +#define LL_RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC /*!< HSI Ready Interrupt Clear */ +#define LL_RCC_CICR_HSERDYC RCC_CICR_HSERDYC /*!< HSE Ready Interrupt Clear */ +#define LL_RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC /*!< PLL Ready Interrupt Clear */ +#define LL_RCC_CICR_MSIRDYC RCC_CICR_MSIRDYC /*!< MSI Ready Interrupt Clear */ +#if defined(RCC_HSI48_SUPPORT) +#define LL_RCC_CICR_HSI48RDYC RCC_CICR_HSI48RDYC /*!< HSI48 Ready Interrupt Clear */ +#endif /* RCC_HSI48_SUPPORT */ +#define LL_RCC_CICR_LSECSSC RCC_CICR_LSECSSC /*!< LSE Clock Security System Interrupt Clear */ +#define LL_RCC_CICR_CSSC RCC_CICR_CSSC /*!< Clock Security System Interrupt Clear */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_RCC_ReadReg function + * @{ + */ +#define LL_RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF /*!< LSI Ready Interrupt flag */ +#define LL_RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF /*!< LSE Ready Interrupt flag */ +#define LL_RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF /*!< HSI Ready Interrupt flag */ +#define LL_RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF /*!< HSE Ready Interrupt flag */ +#define LL_RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF /*!< PLL Ready Interrupt flag */ +#define LL_RCC_CIFR_MSIRDYF RCC_CIFR_MSIRDYF /*!< MSI Ready Interrupt flag */ +#if defined(RCC_HSI48_SUPPORT) +#define LL_RCC_CIFR_HSI48RDYF RCC_CIFR_HSI48RDYF /*!< HSI48 Ready Interrupt flag */ +#endif /* RCC_HSI48_SUPPORT */ +#define LL_RCC_CIFR_LSECSSF RCC_CIFR_LSECSSF /*!< LSE Clock Security System Interrupt flag */ +#define LL_RCC_CIFR_CSSF RCC_CIFR_CSSF /*!< Clock Security System Interrupt flag */ +#define LL_RCC_CSR_FWRSTF RCC_CSR_FWRSTF /*!< Firewall reset flag */ +#define LL_RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF /*!< OBL reset flag */ +#define LL_RCC_CSR_PINRSTF RCC_CSR_PINRSTF /*!< PIN reset flag */ +#define LL_RCC_CSR_PORRSTF RCC_CSR_PORRSTF /*!< POR/PDR reset flag */ +#define LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF /*!< Software Reset flag */ +#define LL_RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF /*!< Independent Watchdog reset flag */ +#define LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF /*!< Window watchdog reset flag */ +#define LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF /*!< Low-Power reset flag */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_RCC_ReadReg and LL_RCC_WriteReg functions + * @{ + */ +#define LL_RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE /*!< LSI Ready Interrupt Enable */ +#define LL_RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE /*!< LSE Ready Interrupt Enable */ +#define LL_RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE /*!< HSI Ready Interrupt Enable */ +#define LL_RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE /*!< HSE Ready Interrupt Enable */ +#define LL_RCC_CIER_PLLRDYIE RCC_CIER_PLLRDYIE /*!< PLL Ready Interrupt Enable */ +#define LL_RCC_CIER_MSIRDYIE RCC_CIER_MSIRDYIE /*!< MSI Ready Interrupt Enable */ +#if defined(RCC_HSI48_SUPPORT) +#define LL_RCC_CIER_HSI48RDYIE RCC_CIER_HSI48RDYIE /*!< HSI48 Ready Interrupt Enable */ +#endif /* RCC_HSI48_SUPPORT */ +#define LL_RCC_CIER_LSECSSIE RCC_CIER_LSECSSIE /*!< LSE CSS Interrupt Enable */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_LSEDRIVE LSE oscillator drive capability + * @{ + */ +#define LL_RCC_LSEDRIVE_LOW (0x00000000U) /*!< Xtal mode lower driving capability */ +#define LL_RCC_LSEDRIVE_MEDIUMLOW RCC_CSR_LSEDRV_0 /*!< Xtal mode medium low driving capability */ +#define LL_RCC_LSEDRIVE_MEDIUMHIGH RCC_CSR_LSEDRV_1 /*!< Xtal mode medium high driving capability */ +#define LL_RCC_LSEDRIVE_HIGH RCC_CSR_LSEDRV /*!< Xtal mode higher driving capability */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_RTC_HSE_DIV RTC HSE Prescaler + * @{ + */ +#define LL_RCC_RTC_HSE_DIV_2 0x00000000U /*!< HSE is divided by 2 for RTC clock */ +#define LL_RCC_RTC_HSE_DIV_4 RCC_CR_RTCPRE_0 /*!< HSE is divided by 4 for RTC clock */ +#define LL_RCC_RTC_HSE_DIV_8 RCC_CR_RTCPRE_1 /*!< HSE is divided by 8 for RTC clock */ +#define LL_RCC_RTC_HSE_DIV_16 RCC_CR_RTCPRE /*!< HSE is divided by 16 for RTC clock */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_MSIRANGE MSI clock ranges + * @{ + */ +#define LL_RCC_MSIRANGE_0 RCC_ICSCR_MSIRANGE_0 /*!< MSI = 65.536 KHz */ +#define LL_RCC_MSIRANGE_1 RCC_ICSCR_MSIRANGE_1 /*!< MSI = 131.072 KHz*/ +#define LL_RCC_MSIRANGE_2 RCC_ICSCR_MSIRANGE_2 /*!< MSI = 262.144 KHz */ +#define LL_RCC_MSIRANGE_3 RCC_ICSCR_MSIRANGE_3 /*!< MSI = 524.288 KHz */ +#define LL_RCC_MSIRANGE_4 RCC_ICSCR_MSIRANGE_4 /*!< MSI = 1.048 MHz */ +#define LL_RCC_MSIRANGE_5 RCC_ICSCR_MSIRANGE_5 /*!< MSI = 2.097 MHz */ +#define LL_RCC_MSIRANGE_6 RCC_ICSCR_MSIRANGE_6 /*!< MSI = 4.194 MHz */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_SYS_CLKSOURCE System clock switch + * @{ + */ +#define LL_RCC_SYS_CLKSOURCE_MSI RCC_CFGR_SW_MSI /*!< MSI selection as system clock */ +#define LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selection as system clock */ +#define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selection as system clock */ +#define LL_RCC_SYS_CLKSOURCE_PLL RCC_CFGR_SW_PLL /*!< PLL selection as system clock */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System clock switch status + * @{ + */ +#define LL_RCC_SYS_CLKSOURCE_STATUS_MSI RCC_CFGR_SWS_MSI /*!< MSI used as system clock */ +#define LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */ +#define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */ +#define LL_RCC_SYS_CLKSOURCE_STATUS_PLL RCC_CFGR_SWS_PLL /*!< PLL used as system clock */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_SYSCLK_DIV AHB prescaler + * @{ + */ +#define LL_RCC_SYSCLK_DIV_1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */ +#define LL_RCC_SYSCLK_DIV_2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */ +#define LL_RCC_SYSCLK_DIV_4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */ +#define LL_RCC_SYSCLK_DIV_8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */ +#define LL_RCC_SYSCLK_DIV_16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */ +#define LL_RCC_SYSCLK_DIV_64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */ +#define LL_RCC_SYSCLK_DIV_128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */ +#define LL_RCC_SYSCLK_DIV_256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */ +#define LL_RCC_SYSCLK_DIV_512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_APB1_DIV APB low-speed prescaler (APB1) + * @{ + */ +#define LL_RCC_APB1_DIV_1 RCC_CFGR_PPRE1_DIV1 /*!< HCLK not divided */ +#define LL_RCC_APB1_DIV_2 RCC_CFGR_PPRE1_DIV2 /*!< HCLK divided by 2 */ +#define LL_RCC_APB1_DIV_4 RCC_CFGR_PPRE1_DIV4 /*!< HCLK divided by 4 */ +#define LL_RCC_APB1_DIV_8 RCC_CFGR_PPRE1_DIV8 /*!< HCLK divided by 8 */ +#define LL_RCC_APB1_DIV_16 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_APB2_DIV APB high-speed prescaler (APB2) + * @{ + */ +#define LL_RCC_APB2_DIV_1 RCC_CFGR_PPRE2_DIV1 /*!< HCLK not divided */ +#define LL_RCC_APB2_DIV_2 RCC_CFGR_PPRE2_DIV2 /*!< HCLK divided by 2 */ +#define LL_RCC_APB2_DIV_4 RCC_CFGR_PPRE2_DIV4 /*!< HCLK divided by 4 */ +#define LL_RCC_APB2_DIV_8 RCC_CFGR_PPRE2_DIV8 /*!< HCLK divided by 8 */ +#define LL_RCC_APB2_DIV_16 RCC_CFGR_PPRE2_DIV16 /*!< HCLK divided by 16 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_STOP_WAKEUPCLOCK Wakeup from Stop and CSS backup clock selection + * @{ + */ +#define LL_RCC_STOP_WAKEUPCLOCK_MSI (0x00000000U) /*!< MSI selection after wake-up from STOP */ +#define LL_RCC_STOP_WAKEUPCLOCK_HSI RCC_CFGR_STOPWUCK /*!< HSI selection after wake-up from STOP */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_MCO1SOURCE MCO1 SOURCE selection + * @{ + */ +#define LL_RCC_MCO1SOURCE_NOCLOCK RCC_CFGR_MCOSEL_NOCLOCK /*!< MCO output disabled, no clock on MCO */ +#define LL_RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_SYSCLK /*!< SYSCLK selection as MCO source */ +#define LL_RCC_MCO1SOURCE_HSI RCC_CFGR_MCOSEL_HSI /*!< HSI selection as MCO source */ +#define LL_RCC_MCO1SOURCE_MSI RCC_CFGR_MCOSEL_MSI /*!< MSI selection as MCO source */ +#define LL_RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_HSE /*!< HSE selection as MCO source */ +#define LL_RCC_MCO1SOURCE_LSI RCC_CFGR_MCOSEL_LSI /*!< LSI selection as MCO source */ +#define LL_RCC_MCO1SOURCE_LSE RCC_CFGR_MCOSEL_LSE /*!< LSE selection as MCO source */ +#if defined(RCC_CFGR_MCOSEL_HSI48) +#define LL_RCC_MCO1SOURCE_HSI48 RCC_CFGR_MCOSEL_HSI48 /*!< HSI48 selection as MCO source */ +#endif /* RCC_CFGR_MCOSEL_HSI48 */ +#define LL_RCC_MCO1SOURCE_PLLCLK RCC_CFGR_MCOSEL_PLL /*!< PLLCLK selection as MCO source */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_MCO1_DIV MCO1 prescaler + * @{ + */ +#define LL_RCC_MCO1_DIV_1 RCC_CFGR_MCOPRE_DIV1 /*!< MCO Clock divided by 1 */ +#define LL_RCC_MCO1_DIV_2 RCC_CFGR_MCOPRE_DIV2 /*!< MCO Clock divided by 2 */ +#define LL_RCC_MCO1_DIV_4 RCC_CFGR_MCOPRE_DIV4 /*!< MCO Clock divided by 4 */ +#define LL_RCC_MCO1_DIV_8 RCC_CFGR_MCOPRE_DIV8 /*!< MCO Clock divided by 8 */ +#define LL_RCC_MCO1_DIV_16 RCC_CFGR_MCOPRE_DIV16 /*!< MCO Clock divided by 16 */ +/** + * @} + */ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency + * @{ + */ +#define LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U /*!< No clock enabled for the peripheral */ +#define LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU /*!< Frequency cannot be provided as external clock */ +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** @defgroup RCC_LL_EC_USART1_CLKSOURCE Peripheral USART clock source selection + * @{ + */ +#if defined(RCC_CCIPR_USART1SEL) +#define LL_RCC_USART1_CLKSOURCE_PCLK2 (uint32_t)((RCC_CCIPR_USART1SEL << 16U) | 0x00000000U) /*!< PCLK2 selected as USART1 clock */ +#define LL_RCC_USART1_CLKSOURCE_SYSCLK (uint32_t)((RCC_CCIPR_USART1SEL << 16U) | RCC_CCIPR_USART1SEL_0) /*!< SYSCLK selected as USART1 clock */ +#define LL_RCC_USART1_CLKSOURCE_HSI (uint32_t)((RCC_CCIPR_USART1SEL << 16U) | RCC_CCIPR_USART1SEL_1) /*!< HSI selected as USART1 clock */ +#define LL_RCC_USART1_CLKSOURCE_LSE (uint32_t)((RCC_CCIPR_USART1SEL << 16U) | RCC_CCIPR_USART1SEL) /*!< LSE selected as USART1 clock*/ +#endif /* RCC_CCIPR_USART1SEL */ +#define LL_RCC_USART2_CLKSOURCE_PCLK1 (uint32_t)((RCC_CCIPR_USART2SEL << 16U) | 0x00000000U) /*!< PCLK1 selected as USART2 clock */ +#define LL_RCC_USART2_CLKSOURCE_SYSCLK (uint32_t)((RCC_CCIPR_USART2SEL << 16U) | RCC_CCIPR_USART2SEL_0) /*!< SYSCLK selected as USART2 clock */ +#define LL_RCC_USART2_CLKSOURCE_HSI (uint32_t)((RCC_CCIPR_USART2SEL << 16U) | RCC_CCIPR_USART2SEL_1) /*!< HSI selected as USART2 clock */ +#define LL_RCC_USART2_CLKSOURCE_LSE (uint32_t)((RCC_CCIPR_USART2SEL << 16U) | RCC_CCIPR_USART2SEL) /*!< LSE selected as USART2 clock*/ +/** + * @} + */ + + + +/** @defgroup RCC_LL_EC_LPUART1_CLKSOURCE Peripheral LPUART clock source selection + * @{ + */ +#define LL_RCC_LPUART1_CLKSOURCE_PCLK1 0x00000000U /*!< PCLK1 selected as LPUART1 clock */ +#define LL_RCC_LPUART1_CLKSOURCE_SYSCLK RCC_CCIPR_LPUART1SEL_0 /*!< SYSCLK selected as LPUART1 clock */ +#define LL_RCC_LPUART1_CLKSOURCE_HSI RCC_CCIPR_LPUART1SEL_1 /*!< HSI selected as LPUART1 clock */ +#define LL_RCC_LPUART1_CLKSOURCE_LSE RCC_CCIPR_LPUART1SEL /*!< LSE selected as LPUART1 clock*/ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_I2C1_CLKSOURCE Peripheral I2C clock source selection + * @{ + */ +#define LL_RCC_I2C1_CLKSOURCE_PCLK1 (uint32_t)((RCC_CCIPR_I2C1SEL << 4U) | (0x00000000U >> 4U)) /*!< PCLK1 selected as I2C1 clock */ +#define LL_RCC_I2C1_CLKSOURCE_SYSCLK (uint32_t)((RCC_CCIPR_I2C1SEL << 4U) | (RCC_CCIPR_I2C1SEL_0 >> 4U)) /*!< SYSCLK selected as I2C1 clock */ +#define LL_RCC_I2C1_CLKSOURCE_HSI (uint32_t)((RCC_CCIPR_I2C1SEL << 4U) | (RCC_CCIPR_I2C1SEL_1 >> 4U)) /*!< HSI selected as I2C1 clock */ +#if defined(RCC_CCIPR_I2C3SEL) +#define LL_RCC_I2C3_CLKSOURCE_PCLK1 (uint32_t)((RCC_CCIPR_I2C3SEL << 4U) | (0x00000000U >> 4U)) /*!< PCLK1 selected as I2C3 clock */ +#define LL_RCC_I2C3_CLKSOURCE_SYSCLK (uint32_t)((RCC_CCIPR_I2C3SEL << 4U) | (RCC_CCIPR_I2C3SEL_0 >> 4U)) /*!< SYSCLK selected as I2C3 clock */ +#define LL_RCC_I2C3_CLKSOURCE_HSI (uint32_t)((RCC_CCIPR_I2C3SEL << 4U) | (RCC_CCIPR_I2C3SEL_1 >> 4U)) /*!< HSI selected as I2C3 clock */ +#endif /*RCC_CCIPR_I2C3SEL*/ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_LPTIM1_CLKSOURCE Peripheral LPTIM clock source selection + * @{ + */ +#define LL_RCC_LPTIM1_CLKSOURCE_PCLK1 (0x00000000U) /*!< PCLK1 selected as LPTIM1 clock */ +#define LL_RCC_LPTIM1_CLKSOURCE_LSI RCC_CCIPR_LPTIM1SEL_0 /*!< LSI selected as LPTIM1 clock */ +#define LL_RCC_LPTIM1_CLKSOURCE_HSI RCC_CCIPR_LPTIM1SEL_1 /*!< HSI selected as LPTIM1 clock */ +#define LL_RCC_LPTIM1_CLKSOURCE_LSE RCC_CCIPR_LPTIM1SEL /*!< LSE selected as LPTIM1 clock*/ +/** + * @} + */ + +#if defined(RCC_CCIPR_HSI48SEL) + +#if defined(RNG) +/** @defgroup RCC_LL_EC_RNG_CLKSOURCE Peripheral RNG clock source selection + * @{ + */ +#define LL_RCC_RNG_CLKSOURCE_PLL (0x00000000U) /*!< PLL selected as RNG clock */ +#define LL_RCC_RNG_CLKSOURCE_HSI48 RCC_CCIPR_HSI48SEL /*!< HSI48 selected as RNG clock*/ +/** + * @} + */ +#endif /* RNG */ +#if defined(USB) +/** @defgroup RCC_LL_EC_USB_CLKSOURCE Peripheral USB clock source selection + * @{ + */ +#define LL_RCC_USB_CLKSOURCE_PLL (0x00000000U) /*!< PLL selected as USB clock */ +#define LL_RCC_USB_CLKSOURCE_HSI48 RCC_CCIPR_HSI48SEL /*!< HSI48 selected as USB clock*/ +/** + * @} + */ + +#endif /* USB */ +#endif /* RCC_CCIPR_HSI48SEL */ + + +/** @defgroup RCC_LL_EC_USART1 Peripheral USART get clock source + * @{ + */ +#if defined(RCC_CCIPR_USART1SEL) +#define LL_RCC_USART1_CLKSOURCE RCC_CCIPR_USART1SEL /*!< USART1 clock source selection bits */ +#endif /* RCC_CCIPR_USART1SEL */ +#define LL_RCC_USART2_CLKSOURCE RCC_CCIPR_USART2SEL /*!< USART2 clock source selection bits */ +/** + * @} + */ + + +/** @defgroup RCC_LL_EC_LPUART1 Peripheral LPUART get clock source + * @{ + */ +#define LL_RCC_LPUART1_CLKSOURCE RCC_CCIPR_LPUART1SEL /*!< LPUART1 clock source selection bits */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_I2C1 Peripheral I2C get clock source + * @{ + */ +#define LL_RCC_I2C1_CLKSOURCE RCC_CCIPR_I2C1SEL /*!< I2C1 clock source selection bits */ +#if defined(RCC_CCIPR_I2C3SEL) +#define LL_RCC_I2C3_CLKSOURCE RCC_CCIPR_I2C3SEL /*!< I2C3 clock source selection bits */ +#endif /*RCC_CCIPR_I2C3SEL*/ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_LPTIM1 Peripheral LPTIM get clock source + * @{ + */ +#define LL_RCC_LPTIM1_CLKSOURCE RCC_CCIPR_LPTIM1SEL /*!< LPTIM1 clock source selection bits */ +/** + * @} + */ + +#if defined(RCC_CCIPR_HSI48SEL) +#if defined(RNG) +/** @defgroup RCC_LL_EC_RNG Peripheral RNG get clock source + * @{ + */ +#define LL_RCC_RNG_CLKSOURCE RCC_CCIPR_HSI48SEL /*!< HSI48 RC clock source selection bit for RNG*/ +/** + * @} + */ +#endif /* RNG */ + +#if defined(USB) +/** @defgroup RCC_LL_EC_USB Peripheral USB get clock source + * @{ + */ +#define LL_RCC_USB_CLKSOURCE RCC_CCIPR_HSI48SEL /*!< HSI48 RC clock source selection bit for USB*/ +/** + * @} + */ + +#endif /* USB */ +#endif /* RCC_CCIPR_HSI48SEL */ + +/** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection + * @{ + */ +#define LL_RCC_RTC_CLKSOURCE_NONE 0x00000000U /*!< No clock used as RTC clock */ +#define LL_RCC_RTC_CLKSOURCE_LSE RCC_CSR_RTCSEL_LSE /*!< LSE oscillator clock used as RTC clock */ +#define LL_RCC_RTC_CLKSOURCE_LSI RCC_CSR_RTCSEL_LSI /*!< LSI oscillator clock used as RTC clock */ +#define LL_RCC_RTC_CLKSOURCE_HSE RCC_CSR_RTCSEL_HSE /*!< HSE oscillator clock divided by a programmable prescaler + (selection through @ref LL_RCC_SetRTC_HSEPrescaler function ) */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_PLL_MUL PLL Multiplicator factor + * @{ + */ +#define LL_RCC_PLL_MUL_3 RCC_CFGR_PLLMUL3 /*!< PLL input clock * 3 */ +#define LL_RCC_PLL_MUL_4 RCC_CFGR_PLLMUL4 /*!< PLL input clock * 4 */ +#define LL_RCC_PLL_MUL_6 RCC_CFGR_PLLMUL6 /*!< PLL input clock * 6 */ +#define LL_RCC_PLL_MUL_8 RCC_CFGR_PLLMUL8 /*!< PLL input clock * 8 */ +#define LL_RCC_PLL_MUL_12 RCC_CFGR_PLLMUL12 /*!< PLL input clock * 12 */ +#define LL_RCC_PLL_MUL_16 RCC_CFGR_PLLMUL16 /*!< PLL input clock * 16 */ +#define LL_RCC_PLL_MUL_24 RCC_CFGR_PLLMUL24 /*!< PLL input clock * 24 */ +#define LL_RCC_PLL_MUL_32 RCC_CFGR_PLLMUL32 /*!< PLL input clock * 32 */ +#define LL_RCC_PLL_MUL_48 RCC_CFGR_PLLMUL48 /*!< PLL input clock * 48 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_PLL_DIV PLL division factor + * @{ + */ +#define LL_RCC_PLL_DIV_2 RCC_CFGR_PLLDIV2 /*!< PLL clock output = PLLVCO / 2 */ +#define LL_RCC_PLL_DIV_3 RCC_CFGR_PLLDIV3 /*!< PLL clock output = PLLVCO / 3 */ +#define LL_RCC_PLL_DIV_4 RCC_CFGR_PLLDIV4 /*!< PLL clock output = PLLVCO / 4 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_PLLSOURCE PLL SOURCE + * @{ + */ +#define LL_RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI /*!< HSI clock selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC_HSE /*!< HSE clock selected as PLL entry clock source */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup RCC_LL_Exported_Macros RCC Exported Macros + * @{ + */ + +/** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in RCC register + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__)) + +/** + * @brief Read a value in RCC register + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__) +/** + * @} + */ + +/** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies + * @{ + */ + +/** + * @brief Helper macro to calculate the PLLCLK frequency + * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE, + * @ref LL_RCC_PLL_GetMultiplicator (), + * @ref LL_RCC_PLL_GetDivider ()); + * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI) + * @param __PLLMUL__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLL_MUL_3 + * @arg @ref LL_RCC_PLL_MUL_4 + * @arg @ref LL_RCC_PLL_MUL_6 + * @arg @ref LL_RCC_PLL_MUL_8 + * @arg @ref LL_RCC_PLL_MUL_12 + * @arg @ref LL_RCC_PLL_MUL_16 + * @arg @ref LL_RCC_PLL_MUL_24 + * @arg @ref LL_RCC_PLL_MUL_32 + * @arg @ref LL_RCC_PLL_MUL_48 + * @param __PLLDIV__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLL_DIV_2 + * @arg @ref LL_RCC_PLL_DIV_3 + * @arg @ref LL_RCC_PLL_DIV_4 + * @retval PLL clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLMUL__, __PLLDIV__) ((__INPUTFREQ__) * (PLLMulTable[(__PLLMUL__) >> RCC_CFGR_PLLMUL_Pos]) / (((__PLLDIV__) >> RCC_CFGR_PLLDIV_Pos)+1UL)) + +/** + * @brief Helper macro to calculate the HCLK frequency + * @note: __AHBPRESCALER__ be retrieved by @ref LL_RCC_GetAHBPrescaler + * ex: __LL_RCC_CALC_HCLK_FREQ(LL_RCC_GetAHBPrescaler()) + * @param __SYSCLKFREQ__ SYSCLK frequency (based on MSI/HSE/HSI/PLLCLK) + * @param __AHBPRESCALER__ This parameter can be one of the following values: + * @arg @ref LL_RCC_SYSCLK_DIV_1 + * @arg @ref LL_RCC_SYSCLK_DIV_2 + * @arg @ref LL_RCC_SYSCLK_DIV_4 + * @arg @ref LL_RCC_SYSCLK_DIV_8 + * @arg @ref LL_RCC_SYSCLK_DIV_16 + * @arg @ref LL_RCC_SYSCLK_DIV_64 + * @arg @ref LL_RCC_SYSCLK_DIV_128 + * @arg @ref LL_RCC_SYSCLK_DIV_256 + * @arg @ref LL_RCC_SYSCLK_DIV_512 + * @retval HCLK clock frequency (in Hz) + */ +#define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos]) + +/** + * @brief Helper macro to calculate the PCLK1 frequency (ABP1) + * @note: __APB1PRESCALER__ be retrieved by @ref LL_RCC_GetAPB1Prescaler + * ex: __LL_RCC_CALC_PCLK1_FREQ(LL_RCC_GetAPB1Prescaler()) + * @param __HCLKFREQ__ HCLK frequency + * @param __APB1PRESCALER__ This parameter can be one of the following values: + * @arg @ref LL_RCC_APB1_DIV_1 + * @arg @ref LL_RCC_APB1_DIV_2 + * @arg @ref LL_RCC_APB1_DIV_4 + * @arg @ref LL_RCC_APB1_DIV_8 + * @arg @ref LL_RCC_APB1_DIV_16 + * @retval PCLK1 clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB1PRESCALER__) >> RCC_CFGR_PPRE1_Pos]) + +/** + * @brief Helper macro to calculate the PCLK2 frequency (ABP2) + * @note: __APB2PRESCALER__ be retrieved by @ref LL_RCC_GetAPB2Prescaler + * ex: __LL_RCC_CALC_PCLK2_FREQ(LL_RCC_GetAPB2Prescaler()) + * @param __HCLKFREQ__ HCLK frequency + * @param __APB2PRESCALER__ This parameter can be one of the following values: + * @arg @ref LL_RCC_APB2_DIV_1 + * @arg @ref LL_RCC_APB2_DIV_2 + * @arg @ref LL_RCC_APB2_DIV_4 + * @arg @ref LL_RCC_APB2_DIV_8 + * @arg @ref LL_RCC_APB2_DIV_16 + * @retval PCLK2 clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB2PRESCALER__) >> RCC_CFGR_PPRE2_Pos]) + +/** + * @brief Helper macro to calculate the MSI frequency (in Hz) + * @note: __MSIRANGE__can be retrieved by @ref LL_RCC_MSI_GetRange + * ex: __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_GetRange()) + * @param __MSIRANGE__ This parameter can be one of the following values: + * @arg @ref LL_RCC_MSIRANGE_0 + * @arg @ref LL_RCC_MSIRANGE_1 + * @arg @ref LL_RCC_MSIRANGE_2 + * @arg @ref LL_RCC_MSIRANGE_3 + * @arg @ref LL_RCC_MSIRANGE_4 + * @arg @ref LL_RCC_MSIRANGE_5 + * @arg @ref LL_RCC_MSIRANGE_6 + * @retval MSI clock frequency (in Hz) + */ +#define __LL_RCC_CALC_MSI_FREQ(__MSIRANGE__) (32768UL * ( 1UL << (((__MSIRANGE__) >> RCC_ICSCR_MSIRANGE_Pos) + 1UL) )) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup RCC_LL_Exported_Functions RCC Exported Functions + * @{ + */ + +/** @defgroup RCC_LL_EF_HSE HSE + * @{ + */ + +#if defined(RCC_HSECSS_SUPPORT) +/** + * @brief Enable the Clock Security System. + * @rmtoll CR CSSHSEON LL_RCC_HSE_EnableCSS + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_EnableCSS(void) +{ + SET_BIT(RCC->CR, RCC_CR_CSSON); +} +#endif /* RCC_HSECSS_SUPPORT */ + +/** + * @brief Enable HSE external oscillator (HSE Bypass) + * @rmtoll CR HSEBYP LL_RCC_HSE_EnableBypass + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_EnableBypass(void) +{ + SET_BIT(RCC->CR, RCC_CR_HSEBYP); +} + +/** + * @brief Disable HSE external oscillator (HSE Bypass) + * @rmtoll CR HSEBYP LL_RCC_HSE_DisableBypass + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_DisableBypass(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); +} + +/** + * @brief Enable HSE crystal oscillator (HSE ON) + * @rmtoll CR HSEON LL_RCC_HSE_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_Enable(void) +{ + SET_BIT(RCC->CR, RCC_CR_HSEON); +} + +/** + * @brief Disable HSE crystal oscillator (HSE ON) + * @rmtoll CR HSEON LL_RCC_HSE_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_Disable(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_HSEON); +} + +/** + * @brief Check if HSE oscillator Ready + * @rmtoll CR HSERDY LL_RCC_HSE_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void) +{ + return ((READ_BIT(RCC->CR, RCC_CR_HSERDY) == RCC_CR_HSERDY) ? 1UL : 0UL); +} + +/** + * @brief Configure the RTC prescaler (divider) + * @rmtoll CR RTCPRE LL_RCC_SetRTC_HSEPrescaler + * @param Div This parameter can be one of the following values: + * @arg @ref LL_RCC_RTC_HSE_DIV_2 + * @arg @ref LL_RCC_RTC_HSE_DIV_4 + * @arg @ref LL_RCC_RTC_HSE_DIV_8 + * @arg @ref LL_RCC_RTC_HSE_DIV_16 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetRTC_HSEPrescaler(uint32_t Div) +{ + MODIFY_REG(RCC->CR, RCC_CR_RTCPRE, Div); +} + +/** + * @brief Get the RTC divider (prescaler) + * @rmtoll CR RTCPRE LL_RCC_GetRTC_HSEPrescaler + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_RTC_HSE_DIV_2 + * @arg @ref LL_RCC_RTC_HSE_DIV_4 + * @arg @ref LL_RCC_RTC_HSE_DIV_8 + * @arg @ref LL_RCC_RTC_HSE_DIV_16 + */ +__STATIC_INLINE uint32_t LL_RCC_GetRTC_HSEPrescaler(void) +{ + return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_RTCPRE)); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_HSI HSI + * @{ + */ + +/** + * @brief Enable HSI oscillator + * @rmtoll CR HSION LL_RCC_HSI_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI_Enable(void) +{ + SET_BIT(RCC->CR, RCC_CR_HSION); +} + +/** + * @brief Disable HSI oscillator + * @rmtoll CR HSION LL_RCC_HSI_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI_Disable(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_HSION); +} + +/** + * @brief Check if HSI clock is ready + * @rmtoll CR HSIRDY LL_RCC_HSI_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void) +{ + return ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) == RCC_CR_HSIRDY) ? 1UL : 0UL); +} + +/** + * @brief Enable HSI even in stop mode + * @note HSI oscillator is forced ON even in Stop mode + * @rmtoll CR HSIKERON LL_RCC_HSI_EnableInStopMode + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI_EnableInStopMode(void) +{ + SET_BIT(RCC->CR, RCC_CR_HSIKERON); +} + +/** + * @brief Disable HSI in stop mode + * @rmtoll CR HSIKERON LL_RCC_HSI_DisableInStopMode + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI_DisableInStopMode(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON); +} + +/** + * @brief Enable HSI Divider (it divides by 4) + * @rmtoll CR HSIDIVEN LL_RCC_HSI_EnableDivider + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI_EnableDivider(void) +{ + SET_BIT(RCC->CR, RCC_CR_HSIDIVEN); +} + +/** + * @brief Disable HSI Divider (it divides by 4) + * @rmtoll CR HSIDIVEN LL_RCC_HSI_DisableDivider + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI_DisableDivider(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_HSIDIVEN); +} + + + +#if defined(RCC_CR_HSIOUTEN) +/** + * @brief Enable HSI Output + * @rmtoll CR HSIOUTEN LL_RCC_HSI_EnableOutput + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI_EnableOutput(void) +{ + SET_BIT(RCC->CR, RCC_CR_HSIOUTEN); +} + +/** + * @brief Disable HSI Output + * @rmtoll CR HSIOUTEN LL_RCC_HSI_DisableOutput + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI_DisableOutput(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_HSIOUTEN); +} +#endif /* RCC_CR_HSIOUTEN */ + +/** + * @brief Get HSI Calibration value + * @note When HSITRIM is written, HSICAL is updated with the sum of + * HSITRIM and the factory trim value + * @rmtoll ICSCR HSICAL LL_RCC_HSI_GetCalibration + * @retval Between Min_Data = 0x00 and Max_Data = 0xFF + */ +__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void) +{ + return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_HSICAL) >> RCC_ICSCR_HSICAL_Pos); +} + +/** + * @brief Set HSI Calibration trimming + * @note user-programmable trimming value that is added to the HSICAL + * @note Default value is 16, which, when added to the HSICAL value, + * should trim the HSI to 16 MHz +/- 1 % + * @rmtoll ICSCR HSITRIM LL_RCC_HSI_SetCalibTrimming + * @param Value between Min_Data = 0x00 and Max_Data = 0x1F + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value) +{ + MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, Value << RCC_ICSCR_HSITRIM_Pos); +} + +/** + * @brief Get HSI Calibration trimming + * @rmtoll ICSCR HSITRIM LL_RCC_HSI_GetCalibTrimming + * @retval Between Min_Data = 0x00 and Max_Data = 0x1F + */ +__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void) +{ + return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_HSITRIM) >> RCC_ICSCR_HSITRIM_Pos); +} + +/** + * @} + */ + +#if defined(RCC_HSI48_SUPPORT) +/** @defgroup RCC_LL_EF_HSI48 HSI48 + * @{ + */ + +/** + * @brief Enable HSI48 + * @rmtoll CRRCR HSI48ON LL_RCC_HSI48_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI48_Enable(void) +{ + SET_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON); +} + +/** + * @brief Disable HSI48 + * @rmtoll CRRCR HSI48ON LL_RCC_HSI48_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI48_Disable(void) +{ + CLEAR_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON); +} + +/** + * @brief Check if HSI48 oscillator Ready + * @rmtoll CRRCR HSI48RDY LL_RCC_HSI48_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_HSI48_IsReady(void) +{ + return ((READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) == RCC_CRRCR_HSI48RDY) ? 1UL : 0UL); +} + +/** + * @brief Get HSI48 Calibration value + * @rmtoll CRRCR HSI48CAL LL_RCC_HSI48_GetCalibration + * @retval Between Min_Data = 0x00 and Max_Data = 0xFF + */ +__STATIC_INLINE uint32_t LL_RCC_HSI48_GetCalibration(void) +{ + return (uint32_t)(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48CAL) >> RCC_CRRCR_HSI48CAL_Pos); +} + +#if defined(RCC_CRRCR_HSI48DIV6OUTEN) +/** + * @brief Enable HSI48 Divider (it divides by 6) + * @rmtoll CRRCR HSI48DIV6OUTEN LL_RCC_HSI48_EnableDivider + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI48_EnableDivider(void) +{ + SET_BIT(RCC->CRRCR, RCC_CRRCR_HSI48DIV6OUTEN); +} + +/** + * @brief Disable HSI48 Divider (it divides by 6) + * @rmtoll CRRCR HSI48DIV6OUTEN LL_RCC_HSI48_DisableDivider + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI48_DisableDivider(void) +{ + CLEAR_BIT(RCC->CRRCR, RCC_CRRCR_HSI48DIV6OUTEN); +} + +/** + * @brief Check if HSI48 Divider is enabled (it divides by 6) + * @rmtoll CRRCR HSI48DIV6OUTEN LL_RCC_HSI48_IsDivided + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_HSI48_IsDivided(void) +{ + return ((READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48DIV6OUTEN) == RCC_CRRCR_HSI48DIV6OUTEN) ? 1UL : 0UL); +} + +#endif /*RCC_CRRCR_HSI48DIV6OUTEN*/ + +/** + * @} + */ + +#endif /* RCC_HSI48_SUPPORT */ + +/** @defgroup RCC_LL_EF_LSE LSE + * @{ + */ + +/** + * @brief Enable Low Speed External (LSE) crystal. + * @rmtoll CSR LSEON LL_RCC_LSE_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_Enable(void) +{ + SET_BIT(RCC->CSR, RCC_CSR_LSEON); +} + +/** + * @brief Disable Low Speed External (LSE) crystal. + * @rmtoll CSR LSEON LL_RCC_LSE_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_Disable(void) +{ + CLEAR_BIT(RCC->CSR, RCC_CSR_LSEON); +} + +/** + * @brief Enable external clock source (LSE bypass). + * @rmtoll CSR LSEBYP LL_RCC_LSE_EnableBypass + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_EnableBypass(void) +{ + SET_BIT(RCC->CSR, RCC_CSR_LSEBYP); +} + +/** + * @brief Disable external clock source (LSE bypass). + * @rmtoll CSR LSEBYP LL_RCC_LSE_DisableBypass + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_DisableBypass(void) +{ + CLEAR_BIT(RCC->CSR, RCC_CSR_LSEBYP); +} + +/** + * @brief Set LSE oscillator drive capability + * @note The oscillator is in Xtal mode when it is not in bypass mode. + * @rmtoll CSR LSEDRV LL_RCC_LSE_SetDriveCapability + * @param LSEDrive This parameter can be one of the following values: + * @arg @ref LL_RCC_LSEDRIVE_LOW + * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW + * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH + * @arg @ref LL_RCC_LSEDRIVE_HIGH + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive) +{ + MODIFY_REG(RCC->CSR, RCC_CSR_LSEDRV, LSEDrive); +} + +/** + * @brief Get LSE oscillator drive capability + * @rmtoll CSR LSEDRV LL_RCC_LSE_GetDriveCapability + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_LSEDRIVE_LOW + * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW + * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH + * @arg @ref LL_RCC_LSEDRIVE_HIGH + */ +__STATIC_INLINE uint32_t LL_RCC_LSE_GetDriveCapability(void) +{ + return (uint32_t)(READ_BIT(RCC->CSR, RCC_CSR_LSEDRV)); +} + +/** + * @brief Enable Clock security system on LSE. + * @rmtoll CSR LSECSSON LL_RCC_LSE_EnableCSS + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_EnableCSS(void) +{ + SET_BIT(RCC->CSR, RCC_CSR_LSECSSON); +} + +/** + * @brief Disable Clock security system on LSE. + * @note Clock security system can be disabled only after a LSE + * failure detection. In that case it MUST be disabled by software. + * @rmtoll CSR LSECSSON LL_RCC_LSE_DisableCSS + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_DisableCSS(void) +{ + CLEAR_BIT(RCC->CSR, RCC_CSR_LSECSSON); +} + +/** + * @brief Check if LSE oscillator Ready + * @rmtoll CSR LSERDY LL_RCC_LSE_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void) +{ + return ((READ_BIT(RCC->CSR, RCC_CSR_LSERDY) == RCC_CSR_LSERDY) ? 1UL : 0UL); +} + +/** + * @brief Check if CSS on LSE failure Detection + * @rmtoll CSR LSECSSD LL_RCC_LSE_IsCSSDetected + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_LSE_IsCSSDetected(void) +{ + return ((READ_BIT(RCC->CSR, RCC_CSR_LSECSSD) == RCC_CSR_LSECSSD) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_LSI LSI + * @{ + */ + +/** + * @brief Enable LSI Oscillator + * @rmtoll CSR LSION LL_RCC_LSI_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSI_Enable(void) +{ + SET_BIT(RCC->CSR, RCC_CSR_LSION); +} + +/** + * @brief Disable LSI Oscillator + * @rmtoll CSR LSION LL_RCC_LSI_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSI_Disable(void) +{ + CLEAR_BIT(RCC->CSR, RCC_CSR_LSION); +} + +/** + * @brief Check if LSI is Ready + * @rmtoll CSR LSIRDY LL_RCC_LSI_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void) +{ + return ((READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == RCC_CSR_LSIRDY) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_MSI MSI + * @{ + */ + +/** + * @brief Enable MSI oscillator + * @rmtoll CR MSION LL_RCC_MSI_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_MSI_Enable(void) +{ + SET_BIT(RCC->CR, RCC_CR_MSION); +} + +/** + * @brief Disable MSI oscillator + * @rmtoll CR MSION LL_RCC_MSI_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_MSI_Disable(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_MSION); +} + +/** + * @brief Check if MSI oscillator Ready + * @rmtoll CR MSIRDY LL_RCC_MSI_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_MSI_IsReady(void) +{ + return ((READ_BIT(RCC->CR, RCC_CR_MSIRDY) == RCC_CR_MSIRDY) ? 1UL : 0UL); +} + +/** + * @brief Configure the Internal Multi Speed oscillator (MSI) clock range in run mode. + * @rmtoll ICSCR MSIRANGE LL_RCC_MSI_SetRange + * @param Range This parameter can be one of the following values: + * @arg @ref LL_RCC_MSIRANGE_0 + * @arg @ref LL_RCC_MSIRANGE_1 + * @arg @ref LL_RCC_MSIRANGE_2 + * @arg @ref LL_RCC_MSIRANGE_3 + * @arg @ref LL_RCC_MSIRANGE_4 + * @arg @ref LL_RCC_MSIRANGE_5 + * @arg @ref LL_RCC_MSIRANGE_6 + * @retval None + */ +__STATIC_INLINE void LL_RCC_MSI_SetRange(uint32_t Range) +{ + MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSIRANGE, Range); +} + +/** + * @brief Get the Internal Multi Speed oscillator (MSI) clock range in run mode. + * @rmtoll ICSCR MSIRANGE LL_RCC_MSI_GetRange + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_MSIRANGE_0 + * @arg @ref LL_RCC_MSIRANGE_1 + * @arg @ref LL_RCC_MSIRANGE_2 + * @arg @ref LL_RCC_MSIRANGE_3 + * @arg @ref LL_RCC_MSIRANGE_4 + * @arg @ref LL_RCC_MSIRANGE_5 + * @arg @ref LL_RCC_MSIRANGE_6 + */ +__STATIC_INLINE uint32_t LL_RCC_MSI_GetRange(void) +{ + return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_MSIRANGE)); +} + +/** + * @brief Get MSI Calibration value + * @note When MSITRIM is written, MSICAL is updated with the sum of + * MSITRIM and the factory trim value + * @rmtoll ICSCR MSICAL LL_RCC_MSI_GetCalibration + * @retval Between Min_Data = 0x00 and Max_Data = 0xFF + */ +__STATIC_INLINE uint32_t LL_RCC_MSI_GetCalibration(void) +{ + return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_MSICAL) >> RCC_ICSCR_MSICAL_Pos); +} + +/** + * @brief Set MSI Calibration trimming + * @note user-programmable trimming value that is added to the MSICAL + * @rmtoll ICSCR MSITRIM LL_RCC_MSI_SetCalibTrimming + * @param Value between Min_Data = 0x00 and Max_Data = 0xFF + * @retval None + */ +__STATIC_INLINE void LL_RCC_MSI_SetCalibTrimming(uint32_t Value) +{ + MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSITRIM, Value << RCC_ICSCR_MSITRIM_Pos); +} + +/** + * @brief Get MSI Calibration trimming + * @rmtoll ICSCR MSITRIM LL_RCC_MSI_GetCalibTrimming + * @retval Between Min_Data = 0x00 and Max_Data = 0xFF + */ +__STATIC_INLINE uint32_t LL_RCC_MSI_GetCalibTrimming(void) +{ + return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_MSITRIM) >> RCC_ICSCR_MSITRIM_Pos); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_System System + * @{ + */ + +/** + * @brief Configure the system clock source + * @rmtoll CFGR SW LL_RCC_SetSysClkSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_SYS_CLKSOURCE_MSI + * @arg @ref LL_RCC_SYS_CLKSOURCE_HSI + * @arg @ref LL_RCC_SYS_CLKSOURCE_HSE + * @arg @ref LL_RCC_SYS_CLKSOURCE_PLL + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source) +{ + MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source); +} + +/** + * @brief Get the system clock source + * @rmtoll CFGR SWS LL_RCC_GetSysClkSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_MSI + * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI + * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE + * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL + */ +__STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS)); +} + +/** + * @brief Set AHB prescaler + * @rmtoll CFGR HPRE LL_RCC_SetAHBPrescaler + * @param Prescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_SYSCLK_DIV_1 + * @arg @ref LL_RCC_SYSCLK_DIV_2 + * @arg @ref LL_RCC_SYSCLK_DIV_4 + * @arg @ref LL_RCC_SYSCLK_DIV_8 + * @arg @ref LL_RCC_SYSCLK_DIV_16 + * @arg @ref LL_RCC_SYSCLK_DIV_64 + * @arg @ref LL_RCC_SYSCLK_DIV_128 + * @arg @ref LL_RCC_SYSCLK_DIV_256 + * @arg @ref LL_RCC_SYSCLK_DIV_512 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler) +{ + MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler); +} + +/** + * @brief Set APB1 prescaler + * @rmtoll CFGR PPRE1 LL_RCC_SetAPB1Prescaler + * @param Prescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_APB1_DIV_1 + * @arg @ref LL_RCC_APB1_DIV_2 + * @arg @ref LL_RCC_APB1_DIV_4 + * @arg @ref LL_RCC_APB1_DIV_8 + * @arg @ref LL_RCC_APB1_DIV_16 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler) +{ + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, Prescaler); +} + +/** + * @brief Set APB2 prescaler + * @rmtoll CFGR PPRE2 LL_RCC_SetAPB2Prescaler + * @param Prescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_APB2_DIV_1 + * @arg @ref LL_RCC_APB2_DIV_2 + * @arg @ref LL_RCC_APB2_DIV_4 + * @arg @ref LL_RCC_APB2_DIV_8 + * @arg @ref LL_RCC_APB2_DIV_16 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler) +{ + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler); +} + +/** + * @brief Get AHB prescaler + * @rmtoll CFGR HPRE LL_RCC_GetAHBPrescaler + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_SYSCLK_DIV_1 + * @arg @ref LL_RCC_SYSCLK_DIV_2 + * @arg @ref LL_RCC_SYSCLK_DIV_4 + * @arg @ref LL_RCC_SYSCLK_DIV_8 + * @arg @ref LL_RCC_SYSCLK_DIV_16 + * @arg @ref LL_RCC_SYSCLK_DIV_64 + * @arg @ref LL_RCC_SYSCLK_DIV_128 + * @arg @ref LL_RCC_SYSCLK_DIV_256 + * @arg @ref LL_RCC_SYSCLK_DIV_512 + */ +__STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE)); +} + +/** + * @brief Get APB1 prescaler + * @rmtoll CFGR PPRE1 LL_RCC_GetAPB1Prescaler + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_APB1_DIV_1 + * @arg @ref LL_RCC_APB1_DIV_2 + * @arg @ref LL_RCC_APB1_DIV_4 + * @arg @ref LL_RCC_APB1_DIV_8 + * @arg @ref LL_RCC_APB1_DIV_16 + */ +__STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1)); +} + +/** + * @brief Get APB2 prescaler + * @rmtoll CFGR PPRE2 LL_RCC_GetAPB2Prescaler + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_APB2_DIV_1 + * @arg @ref LL_RCC_APB2_DIV_2 + * @arg @ref LL_RCC_APB2_DIV_4 + * @arg @ref LL_RCC_APB2_DIV_8 + * @arg @ref LL_RCC_APB2_DIV_16 + */ +__STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2)); +} + +/** + * @brief Set Clock After Wake-Up From Stop mode + * @rmtoll CFGR STOPWUCK LL_RCC_SetClkAfterWakeFromStop + * @param Clock This parameter can be one of the following values: + * @arg @ref LL_RCC_STOP_WAKEUPCLOCK_MSI + * @arg @ref LL_RCC_STOP_WAKEUPCLOCK_HSI + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetClkAfterWakeFromStop(uint32_t Clock) +{ + MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPWUCK, Clock); +} + +/** + * @brief Get Clock After Wake-Up From Stop mode + * @rmtoll CFGR STOPWUCK LL_RCC_GetClkAfterWakeFromStop + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_STOP_WAKEUPCLOCK_MSI + * @arg @ref LL_RCC_STOP_WAKEUPCLOCK_HSI + */ +__STATIC_INLINE uint32_t LL_RCC_GetClkAfterWakeFromStop(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_STOPWUCK)); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_MCO MCO + * @{ + */ + +/** + * @brief Configure MCOx + * @rmtoll CFGR MCOSEL LL_RCC_ConfigMCO\n + * CFGR MCOPRE LL_RCC_ConfigMCO + * @param MCOxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_MCO1SOURCE_NOCLOCK + * @arg @ref LL_RCC_MCO1SOURCE_SYSCLK + * @arg @ref LL_RCC_MCO1SOURCE_HSI + * @arg @ref LL_RCC_MCO1SOURCE_MSI + * @arg @ref LL_RCC_MCO1SOURCE_HSE + * @arg @ref LL_RCC_MCO1SOURCE_PLLCLK + * @arg @ref LL_RCC_MCO1SOURCE_LSI + * @arg @ref LL_RCC_MCO1SOURCE_LSE + * @arg @ref LL_RCC_MCO1SOURCE_HSI48 (*) + * + * (*) value not defined in all devices. + * @param MCOxPrescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_MCO1_DIV_1 + * @arg @ref LL_RCC_MCO1_DIV_2 + * @arg @ref LL_RCC_MCO1_DIV_4 + * @arg @ref LL_RCC_MCO1_DIV_8 + * @arg @ref LL_RCC_MCO1_DIV_16 + * @retval None + */ +__STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler) +{ + MODIFY_REG(RCC->CFGR, RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE, MCOxSource | MCOxPrescaler); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source + * @{ + */ + +/** + * @brief Configure USARTx clock source + * @rmtoll CCIPR USARTxSEL LL_RCC_SetUSARTClockSource + * @param USARTxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2 (*) + * @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK (*) + * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI (*) + * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE (*) + * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI + * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetUSARTClockSource(uint32_t USARTxSource) +{ + MODIFY_REG(RCC->CCIPR, (USARTxSource >> 16U), (USARTxSource & 0x0000FFFFU)); +} + +/** + * @brief Configure LPUART1x clock source + * @rmtoll CCIPR LPUART1SEL LL_RCC_SetLPUARTClockSource + * @param LPUARTxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetLPUARTClockSource(uint32_t LPUARTxSource) +{ + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART1SEL, LPUARTxSource); +} + +/** + * @brief Configure I2Cx clock source + * @rmtoll CCIPR I2CxSEL LL_RCC_SetI2CClockSource + * @param I2CxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI + * @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK1 (*) + * @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK (*) + * @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetI2CClockSource(uint32_t I2CxSource) +{ + MODIFY_REG(RCC->CCIPR, ((I2CxSource >> 4U) & 0x000FF000U), ((I2CxSource << 4U) & 0x000FF000U)); +} + +/** + * @brief Configure LPTIMx clock source + * @rmtoll CCIPR LPTIMxSEL LL_RCC_SetLPTIMClockSource + * @param LPTIMxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetLPTIMClockSource(uint32_t LPTIMxSource) +{ + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL, LPTIMxSource); +} + +#if defined(RCC_CCIPR_HSI48SEL) +#if defined(RNG) +/** + * @brief Configure RNG clock source + * @rmtoll CCIPR HSI48SEL LL_RCC_SetRNGClockSource + * @param RNGxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_RNG_CLKSOURCE_PLL + * @arg @ref LL_RCC_RNG_CLKSOURCE_HSI48 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetRNGClockSource(uint32_t RNGxSource) +{ + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_HSI48SEL, RNGxSource); +} +#endif /* RNG */ + +#if defined(USB) +/** + * @brief Configure USB clock source + * @rmtoll CCIPR HSI48SEL LL_RCC_SetUSBClockSource + * @param USBxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_RNG_CLKSOURCE_PLL + * @arg @ref LL_RCC_RNG_CLKSOURCE_HSI48 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t USBxSource) +{ + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_HSI48SEL, USBxSource); +} +#endif /* USB */ + +#endif /* RCC_CCIPR_HSI48SEL */ + +/** + * @brief Get USARTx clock source + * @rmtoll CCIPR USARTxSEL LL_RCC_GetUSARTClockSource + * @param USARTx This parameter can be one of the following values: + * @arg @ref LL_RCC_USART1_CLKSOURCE (*) + * @arg @ref LL_RCC_USART2_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2 (*) + * @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK (*) + * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI (*) + * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE (*) + * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI + * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE + * + * (*) value not defined in all devices. + */ +__STATIC_INLINE uint32_t LL_RCC_GetUSARTClockSource(uint32_t USARTx) +{ + return (uint32_t)(READ_BIT(RCC->CCIPR, USARTx) | (USARTx << 16U)); +} + + + +/** + * @brief Get LPUARTx clock source + * @rmtoll CCIPR LPUART1SEL LL_RCC_GetLPUARTClockSource + * @param LPUARTx This parameter can be one of the following values: + * @arg @ref LL_RCC_LPUART1_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI + * @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE + */ +__STATIC_INLINE uint32_t LL_RCC_GetLPUARTClockSource(uint32_t LPUARTx) +{ + return (uint32_t)(READ_BIT(RCC->CCIPR, LPUARTx)); +} + +/** + * @brief Get I2Cx clock source + * @rmtoll CCIPR I2CxSEL LL_RCC_GetI2CClockSource + * @param I2Cx This parameter can be one of the following values: + * @arg @ref LL_RCC_I2C1_CLKSOURCE + * @arg @ref LL_RCC_I2C3_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI + * @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK1 (*) + * @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK (*) + * @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI (*) + * + * (*) value not defined in all devices. + */ +__STATIC_INLINE uint32_t LL_RCC_GetI2CClockSource(uint32_t I2Cx) +{ + return (uint32_t)((READ_BIT(RCC->CCIPR, I2Cx) >> 4U) | (I2Cx << 4U)); +} + +/** + * @brief Get LPTIMx clock source + * @rmtoll CCIPR LPTIMxSEL LL_RCC_GetLPTIMClockSource + * @param LPTIMx This parameter can be one of the following values: + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE + */ +__STATIC_INLINE uint32_t LL_RCC_GetLPTIMClockSource(uint32_t LPTIMx) +{ + return (uint32_t)(READ_BIT(RCC->CCIPR, LPTIMx)); +} + +#if defined(RCC_CCIPR_HSI48SEL) +#if defined(RNG) +/** + * @brief Get RNGx clock source + * @rmtoll CCIPR CLK48SEL LL_RCC_GetRNGClockSource + * @param RNGx This parameter can be one of the following values: + * @arg @ref LL_RCC_RNG_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_RNG_CLKSOURCE_PLL + * @arg @ref LL_RCC_RNG_CLKSOURCE_HSI48 + */ +__STATIC_INLINE uint32_t LL_RCC_GetRNGClockSource(uint32_t RNGx) +{ + return (uint32_t)(READ_BIT(RCC->CCIPR, RNGx)); +} +#endif /* RNG */ + +#if defined(USB) +/** + * @brief Get USBx clock source + * @rmtoll CCIPR CLK48SEL LL_RCC_GetUSBClockSource + * @param USBx This parameter can be one of the following values: + * @arg @ref LL_RCC_USB_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_USB_CLKSOURCE_PLL + * @arg @ref LL_RCC_USB_CLKSOURCE_HSI48 + */ +__STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t USBx) +{ + return (uint32_t)(READ_BIT(RCC->CCIPR, USBx)); +} +#endif /* USB */ + +#endif /* RCC_CCIPR_HSI48SEL */ + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_RTC RTC + * @{ + */ + +/** + * @brief Set RTC Clock Source + * @note Once the RTC clock source has been selected, it cannot be changed any more unless + * the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is + * set). The RTCRST bit can be used to reset them. + * @rmtoll CSR RTCSEL LL_RCC_SetRTCClockSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE + * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE + * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI + * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source) +{ + MODIFY_REG(RCC->CSR, RCC_CSR_RTCSEL, Source); +} + +/** + * @brief Get RTC Clock Source + * @rmtoll CSR RTCSEL LL_RCC_GetRTCClockSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE + * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE + * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI + * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE + */ +__STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void) +{ + return (uint32_t)(READ_BIT(RCC->CSR, RCC_CSR_RTCSEL)); +} + +/** + * @brief Enable RTC + * @rmtoll CSR RTCEN LL_RCC_EnableRTC + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableRTC(void) +{ + SET_BIT(RCC->CSR, RCC_CSR_RTCEN); +} + +/** + * @brief Disable RTC + * @rmtoll CSR RTCEN LL_RCC_DisableRTC + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableRTC(void) +{ + CLEAR_BIT(RCC->CSR, RCC_CSR_RTCEN); +} + +/** + * @brief Check if RTC has been enabled or not + * @rmtoll CSR RTCEN LL_RCC_IsEnabledRTC + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void) +{ + return ((READ_BIT(RCC->CSR, RCC_CSR_RTCEN) == RCC_CSR_RTCEN) ? 1UL : 0UL); +} + +/** + * @brief Force the Backup domain reset + * @rmtoll CSR RTCRST LL_RCC_ForceBackupDomainReset + * @retval None + */ +__STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void) +{ + SET_BIT(RCC->CSR, RCC_CSR_RTCRST); +} + +/** + * @brief Release the Backup domain reset + * @rmtoll CSR RTCRST LL_RCC_ReleaseBackupDomainReset + * @retval None + */ +__STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void) +{ + CLEAR_BIT(RCC->CSR, RCC_CSR_RTCRST); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_PLL PLL + * @{ + */ + +/** + * @brief Enable PLL + * @rmtoll CR PLLON LL_RCC_PLL_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_Enable(void) +{ + SET_BIT(RCC->CR, RCC_CR_PLLON); +} + +/** + * @brief Disable PLL + * @note Cannot be disabled if the PLL clock is used as the system clock + * @rmtoll CR PLLON LL_RCC_PLL_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_Disable(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_PLLON); +} + +/** + * @brief Check if PLL Ready + * @rmtoll CR PLLRDY LL_RCC_PLL_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void) +{ + return ((READ_BIT(RCC->CR, RCC_CR_PLLRDY) == RCC_CR_PLLRDY) ? 1UL : 0UL); +} + +/** + * @brief Configure PLL used for SYSCLK Domain + * @rmtoll CFGR PLLSRC LL_RCC_PLL_ConfigDomain_SYS\n + * CFGR PLLMUL LL_RCC_PLL_ConfigDomain_SYS\n + * CFGR PLLDIV LL_RCC_PLL_ConfigDomain_SYS + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + * @param PLLMul This parameter can be one of the following values: + * @arg @ref LL_RCC_PLL_MUL_3 + * @arg @ref LL_RCC_PLL_MUL_4 + * @arg @ref LL_RCC_PLL_MUL_6 + * @arg @ref LL_RCC_PLL_MUL_8 + * @arg @ref LL_RCC_PLL_MUL_12 + * @arg @ref LL_RCC_PLL_MUL_16 + * @arg @ref LL_RCC_PLL_MUL_24 + * @arg @ref LL_RCC_PLL_MUL_32 + * @arg @ref LL_RCC_PLL_MUL_48 + * @param PLLDiv This parameter can be one of the following values: + * @arg @ref LL_RCC_PLL_DIV_2 + * @arg @ref LL_RCC_PLL_DIV_3 + * @arg @ref LL_RCC_PLL_DIV_4 + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLMul, uint32_t PLLDiv) +{ + MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLSRC | RCC_CFGR_PLLMUL | RCC_CFGR_PLLDIV, Source | PLLMul | PLLDiv); +} + +/** + * @brief Configure PLL clock source + * @rmtoll CFGR PLLSRC LL_RCC_PLL_SetMainSource + * @param PLLSource This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_SetMainSource(uint32_t PLLSource) +{ + MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLSRC, PLLSource); +} + +/** + * @brief Get the oscillator used as PLL clock source. + * @rmtoll CFGR PLLSRC LL_RCC_PLL_GetMainSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC)); +} + +/** + * @brief Get PLL multiplication Factor + * @rmtoll CFGR PLLMUL LL_RCC_PLL_GetMultiplicator + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLL_MUL_3 + * @arg @ref LL_RCC_PLL_MUL_4 + * @arg @ref LL_RCC_PLL_MUL_6 + * @arg @ref LL_RCC_PLL_MUL_8 + * @arg @ref LL_RCC_PLL_MUL_12 + * @arg @ref LL_RCC_PLL_MUL_16 + * @arg @ref LL_RCC_PLL_MUL_24 + * @arg @ref LL_RCC_PLL_MUL_32 + * @arg @ref LL_RCC_PLL_MUL_48 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_GetMultiplicator(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLMUL)); +} + +/** + * @brief Get Division factor for the main PLL and other PLL + * @rmtoll CFGR PLLDIV LL_RCC_PLL_GetDivider + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLL_DIV_2 + * @arg @ref LL_RCC_PLL_DIV_3 + * @arg @ref LL_RCC_PLL_DIV_4 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_GetDivider(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLDIV)); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_FLAG_Management FLAG Management + * @{ + */ + +/** + * @brief Clear LSI ready interrupt flag + * @rmtoll CICR LSIRDYC LL_RCC_ClearFlag_LSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void) +{ + SET_BIT(RCC->CICR, RCC_CICR_LSIRDYC); +} + +/** + * @brief Clear LSE ready interrupt flag + * @rmtoll CICR LSERDYC LL_RCC_ClearFlag_LSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void) +{ + SET_BIT(RCC->CICR, RCC_CICR_LSERDYC); +} + +/** + * @brief Clear MSI ready interrupt flag + * @rmtoll CICR MSIRDYC LL_RCC_ClearFlag_MSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_MSIRDY(void) +{ + SET_BIT(RCC->CICR, RCC_CICR_MSIRDYC); +} + +/** + * @brief Clear HSI ready interrupt flag + * @rmtoll CICR HSIRDYC LL_RCC_ClearFlag_HSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void) +{ + SET_BIT(RCC->CICR, RCC_CICR_HSIRDYC); +} + +/** + * @brief Clear HSE ready interrupt flag + * @rmtoll CICR HSERDYC LL_RCC_ClearFlag_HSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void) +{ + SET_BIT(RCC->CICR, RCC_CICR_HSERDYC); +} + +/** + * @brief Clear PLL ready interrupt flag + * @rmtoll CICR PLLRDYC LL_RCC_ClearFlag_PLLRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_PLLRDY(void) +{ + SET_BIT(RCC->CICR, RCC_CICR_PLLRDYC); +} + +#if defined(RCC_HSI48_SUPPORT) +/** + * @brief Clear HSI48 ready interrupt flag + * @rmtoll CICR HSI48RDYC LL_RCC_ClearFlag_HSI48RDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_HSI48RDY(void) +{ + SET_BIT(RCC->CICR, RCC_CICR_HSI48RDYC); +} +#endif /* RCC_HSI48_SUPPORT */ + +#if defined(RCC_HSECSS_SUPPORT) +/** + * @brief Clear Clock security system interrupt flag + * @rmtoll CICR CSSC LL_RCC_ClearFlag_HSECSS + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void) +{ + SET_BIT(RCC->CICR, RCC_CICR_CSSC); +} +#endif /* RCC_HSECSS_SUPPORT */ + +/** + * @brief Clear LSE Clock security system interrupt flag + * @rmtoll CICR LSECSSC LL_RCC_ClearFlag_LSECSS + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_LSECSS(void) +{ + SET_BIT(RCC->CICR, RCC_CICR_LSECSSC); +} + +/** + * @brief Check if LSI ready interrupt occurred or not + * @rmtoll CIFR LSIRDYF LL_RCC_IsActiveFlag_LSIRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void) +{ + return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSIRDYF) == RCC_CIFR_LSIRDYF) ? 1UL : 0UL); +} + +/** + * @brief Check if LSE ready interrupt occurred or not + * @rmtoll CIFR LSERDYF LL_RCC_IsActiveFlag_LSERDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void) +{ + return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSERDYF) == RCC_CIFR_LSERDYF) ? 1UL : 0UL); +} + +/** + * @brief Check if MSI ready interrupt occurred or not + * @rmtoll CIFR MSIRDYF LL_RCC_IsActiveFlag_MSIRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_MSIRDY(void) +{ + return ((READ_BIT(RCC->CIFR, RCC_CIFR_MSIRDYF) == RCC_CIFR_MSIRDYF) ? 1UL : 0UL); +} + +/** + * @brief Check if HSI ready interrupt occurred or not + * @rmtoll CIFR HSIRDYF LL_RCC_IsActiveFlag_HSIRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void) +{ + return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSIRDYF) == RCC_CIFR_HSIRDYF) ? 1UL : 0UL); +} + +/** + * @brief Check if HSE ready interrupt occurred or not + * @rmtoll CIFR HSERDYF LL_RCC_IsActiveFlag_HSERDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void) +{ + return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSERDYF) == RCC_CIFR_HSERDYF) ? 1UL : 0UL); +} + +/** + * @brief Check if PLL ready interrupt occurred or not + * @rmtoll CIFR PLLRDYF LL_RCC_IsActiveFlag_PLLRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLRDY(void) +{ + return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLLRDYF) == RCC_CIFR_PLLRDYF) ? 1UL : 0UL); +} + +#if defined(RCC_HSI48_SUPPORT) +/** + * @brief Check if HSI48 ready interrupt occurred or not + * @rmtoll CIFR HSI48RDYF LL_RCC_IsActiveFlag_HSI48RDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSI48RDY(void) +{ + return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSI48RDYF) == RCC_CIFR_HSI48RDYF) ? 1UL : 0UL); +} +#endif /* RCC_HSI48_SUPPORT */ + +#if defined(RCC_HSECSS_SUPPORT) +/** + * @brief Check if Clock security system interrupt occurred or not + * @rmtoll CIFR CSSF LL_RCC_IsActiveFlag_HSECSS + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void) +{ + return ((READ_BIT(RCC->CIFR, RCC_CIFR_CSSF) == RCC_CIFR_CSSF) ? 1UL : 0UL); +} +#endif /* RCC_HSECSS_SUPPORT */ + +/** + * @brief Check if LSE Clock security system interrupt occurred or not + * @rmtoll CIFR LSECSSF LL_RCC_IsActiveFlag_LSECSS + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSECSS(void) +{ + return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSECSSF) == RCC_CIFR_LSECSSF) ? 1UL : 0UL); +} + +/** + * @brief Check if HSI Divider is enabled (it divides by 4) + * @rmtoll CR HSIDIVF LL_RCC_IsActiveFlag_HSIDIV + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIDIV(void) +{ + return ((READ_BIT(RCC->CR, RCC_CR_HSIDIVF) == RCC_CR_HSIDIVF) ? 1UL : 0UL); +} + +#if defined(RCC_CSR_FWRSTF) +/** + * @brief Check if RCC flag FW reset is set or not. + * @rmtoll CSR FWRSTF LL_RCC_IsActiveFlag_FWRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_FWRST(void) +{ + return ((READ_BIT(RCC->CSR, RCC_CSR_FWRSTF) == RCC_CSR_FWRSTF) ? 1UL : 0UL); +} +#endif /* RCC_CSR_FWRSTF */ + +/** + * @brief Check if RCC flag Independent Watchdog reset is set or not. + * @rmtoll CSR IWDGRSTF LL_RCC_IsActiveFlag_IWDGRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void) +{ + return ((READ_BIT(RCC->CSR, RCC_CSR_IWDGRSTF) == RCC_CSR_IWDGRSTF) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC flag Low Power reset is set or not. + * @rmtoll CSR LPWRRSTF LL_RCC_IsActiveFlag_LPWRRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void) +{ + return ((READ_BIT(RCC->CSR, RCC_CSR_LPWRRSTF) == RCC_CSR_LPWRRSTF) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC flag is set or not. + * @rmtoll CSR OBLRSTF LL_RCC_IsActiveFlag_OBLRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_OBLRST(void) +{ + return ((READ_BIT(RCC->CSR, RCC_CSR_OBLRSTF) == RCC_CSR_OBLRSTF) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC flag Pin reset is set or not. + * @rmtoll CSR PINRSTF LL_RCC_IsActiveFlag_PINRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void) +{ + return ((READ_BIT(RCC->CSR, RCC_CSR_PINRSTF) == RCC_CSR_PINRSTF) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC flag POR/PDR reset is set or not. + * @rmtoll CSR PORRSTF LL_RCC_IsActiveFlag_PORRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PORRST(void) +{ + return ((READ_BIT(RCC->CSR, RCC_CSR_PORRSTF) == RCC_CSR_PORRSTF) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC flag Software reset is set or not. + * @rmtoll CSR SFTRSTF LL_RCC_IsActiveFlag_SFTRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void) +{ + return ((READ_BIT(RCC->CSR, RCC_CSR_SFTRSTF) == RCC_CSR_SFTRSTF) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC flag Window Watchdog reset is set or not. + * @rmtoll CSR WWDGRSTF LL_RCC_IsActiveFlag_WWDGRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void) +{ + return ((READ_BIT(RCC->CSR, RCC_CSR_WWDGRSTF) == RCC_CSR_WWDGRSTF) ? 1UL : 0UL); +} + +/** + * @brief Set RMVF bit to clear the reset flags. + * @rmtoll CSR RMVF LL_RCC_ClearResetFlags + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearResetFlags(void) +{ + SET_BIT(RCC->CSR, RCC_CSR_RMVF); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_IT_Management IT Management + * @{ + */ + +/** + * @brief Enable LSI ready interrupt + * @rmtoll CIER LSIRDYIE LL_RCC_EnableIT_LSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void) +{ + SET_BIT(RCC->CIER, RCC_CIER_LSIRDYIE); +} + +/** + * @brief Enable LSE ready interrupt + * @rmtoll CIER LSERDYIE LL_RCC_EnableIT_LSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void) +{ + SET_BIT(RCC->CIER, RCC_CIER_LSERDYIE); +} + +/** + * @brief Enable MSI ready interrupt + * @rmtoll CIER MSIRDYIE LL_RCC_EnableIT_MSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_MSIRDY(void) +{ + SET_BIT(RCC->CIER, RCC_CIER_MSIRDYIE); +} + +/** + * @brief Enable HSI ready interrupt + * @rmtoll CIER HSIRDYIE LL_RCC_EnableIT_HSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void) +{ + SET_BIT(RCC->CIER, RCC_CIER_HSIRDYIE); +} + +/** + * @brief Enable HSE ready interrupt + * @rmtoll CIER HSERDYIE LL_RCC_EnableIT_HSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void) +{ + SET_BIT(RCC->CIER, RCC_CIER_HSERDYIE); +} + +/** + * @brief Enable PLL ready interrupt + * @rmtoll CIER PLLRDYIE LL_RCC_EnableIT_PLLRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_PLLRDY(void) +{ + SET_BIT(RCC->CIER, RCC_CIER_PLLRDYIE); +} + +#if defined(RCC_HSI48_SUPPORT) +/** + * @brief Enable HSI48 ready interrupt + * @rmtoll CIER HSI48RDYIE LL_RCC_EnableIT_HSI48RDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_HSI48RDY(void) +{ + SET_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE); +} +#endif /* RCC_HSI48_SUPPORT */ + +/** + * @brief Enable LSE clock security system interrupt + * @rmtoll CIER LSECSSIE LL_RCC_EnableIT_LSECSS + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_LSECSS(void) +{ + SET_BIT(RCC->CIER, RCC_CIER_LSECSSIE); +} + +/** + * @brief Disable LSI ready interrupt + * @rmtoll CIER LSIRDYIE LL_RCC_DisableIT_LSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void) +{ + CLEAR_BIT(RCC->CIER, RCC_CIER_LSIRDYIE); +} + +/** + * @brief Disable LSE ready interrupt + * @rmtoll CIER LSERDYIE LL_RCC_DisableIT_LSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void) +{ + CLEAR_BIT(RCC->CIER, RCC_CIER_LSERDYIE); +} + +/** + * @brief Disable MSI ready interrupt + * @rmtoll CIER MSIRDYIE LL_RCC_DisableIT_MSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_MSIRDY(void) +{ + CLEAR_BIT(RCC->CIER, RCC_CIER_MSIRDYIE); +} + +/** + * @brief Disable HSI ready interrupt + * @rmtoll CIER HSIRDYIE LL_RCC_DisableIT_HSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void) +{ + CLEAR_BIT(RCC->CIER, RCC_CIER_HSIRDYIE); +} + +/** + * @brief Disable HSE ready interrupt + * @rmtoll CIER HSERDYIE LL_RCC_DisableIT_HSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void) +{ + CLEAR_BIT(RCC->CIER, RCC_CIER_HSERDYIE); +} + +/** + * @brief Disable PLL ready interrupt + * @rmtoll CIER PLLRDYIE LL_RCC_DisableIT_PLLRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_PLLRDY(void) +{ + CLEAR_BIT(RCC->CIER, RCC_CIER_PLLRDYIE); +} + +#if defined(RCC_HSI48_SUPPORT) +/** + * @brief Disable HSI48 ready interrupt + * @rmtoll CIER HSI48RDYIE LL_RCC_DisableIT_HSI48RDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_HSI48RDY(void) +{ + CLEAR_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE); +} +#endif /* RCC_HSI48_SUPPORT */ + +/** + * @brief Disable LSE clock security system interrupt + * @rmtoll CIER LSECSSIE LL_RCC_DisableIT_LSECSS + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_LSECSS(void) +{ + CLEAR_BIT(RCC->CIER, RCC_CIER_LSECSSIE); +} + +/** + * @brief Checks if LSI ready interrupt source is enabled or disabled. + * @rmtoll CIER LSIRDYIE LL_RCC_IsEnabledIT_LSIRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY(void) +{ + return ((READ_BIT(RCC->CIER, RCC_CIER_LSIRDYIE) == RCC_CIER_LSIRDYIE) ? 1UL : 0UL); +} + +/** + * @brief Checks if LSE ready interrupt source is enabled or disabled. + * @rmtoll CIER LSERDYIE LL_RCC_IsEnabledIT_LSERDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void) +{ + return ((READ_BIT(RCC->CIER, RCC_CIER_LSERDYIE) == RCC_CIER_LSERDYIE) ? 1UL : 0UL); +} + +/** + * @brief Checks if MSI ready interrupt source is enabled or disabled. + * @rmtoll CIER MSIRDYIE LL_RCC_IsEnabledIT_MSIRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_MSIRDY(void) +{ + return ((READ_BIT(RCC->CIER, RCC_CIER_MSIRDYIE) == RCC_CIER_MSIRDYIE) ? 1UL : 0UL); +} + +/** + * @brief Checks if HSI ready interrupt source is enabled or disabled. + * @rmtoll CIER HSIRDYIE LL_RCC_IsEnabledIT_HSIRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void) +{ + return ((READ_BIT(RCC->CIER, RCC_CIER_HSIRDYIE) == RCC_CIER_HSIRDYIE) ? 1UL : 0UL); +} + +/** + * @brief Checks if HSE ready interrupt source is enabled or disabled. + * @rmtoll CIER HSERDYIE LL_RCC_IsEnabledIT_HSERDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void) +{ + return ((READ_BIT(RCC->CIER, RCC_CIER_HSERDYIE) == RCC_CIER_HSERDYIE) ? 1UL : 0UL); +} + +/** + * @brief Checks if PLL ready interrupt source is enabled or disabled. + * @rmtoll CIER PLLRDYIE LL_RCC_IsEnabledIT_PLLRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLRDY(void) +{ + return ((READ_BIT(RCC->CIER, RCC_CIER_PLLRDYIE) == RCC_CIER_PLLRDYIE) ? 1UL : 0UL); +} + +#if defined(RCC_HSI48_SUPPORT) +/** + * @brief Checks if HSI48 ready interrupt source is enabled or disabled. + * @rmtoll CIER HSI48RDYIE LL_RCC_IsEnabledIT_HSI48RDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSI48RDY(void) +{ + return ((READ_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE) == RCC_CIER_HSI48RDYIE) ? 1UL : 0UL); +} +#endif /* RCC_HSI48_SUPPORT */ + +/** + * @brief Checks if LSECSS interrupt source is enabled or disabled. + * @rmtoll CIER LSECSSIE LL_RCC_IsEnabledIT_LSECSS + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSECSS(void) +{ + return ((READ_BIT(RCC->CIER, RCC_CIER_LSECSSIE) == RCC_CIER_LSECSSIE) ? 1UL : 0UL); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup RCC_LL_EF_Init De-initialization function + * @{ + */ +ErrorStatus LL_RCC_DeInit(void); +/** + * @} + */ + +/** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions + * @{ + */ +void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks); +uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource); +uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource); +uint32_t LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource); +uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource); +#if defined(USB_OTG_FS) || defined(USB) +uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource); +#endif /* USB_OTG_FS || USB */ +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* RCC */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32L0xx_LL_RCC_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/fw/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h b/fw/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h new file mode 100644 index 0000000..3a969ba --- /dev/null +++ b/fw/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h @@ -0,0 +1,1089 @@ +/** + ****************************************************************************** + * @file stm32l0xx_ll_system.h + * @author MCD Application Team + * @brief Header file of SYSTEM LL module. + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The LL SYSTEM driver contains a set of generic APIs that can be + used by user: + (+) Some of the FLASH features need to be handled in the SYSTEM file. + (+) Access to DBGCMU registers + (+) Access to SYSCFG registers + + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32L0xx_LL_SYSTEM_H +#define __STM32L0xx_LL_SYSTEM_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l0xx.h" + +/** @addtogroup STM32L0xx_LL_Driver + * @{ + */ + +#if defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) + +/** @defgroup SYSTEM_LL SYSTEM + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants + * @{ + */ + +/** + * @brief Power-down in Run mode Flash key + */ +#define FLASH_PDKEY1 (0x04152637U) /*!< Flash power down key1 */ +#define FLASH_PDKEY2 (0xFAFBFCFDU) /*!< Flash power down key2: used with FLASH_PDKEY1 + to unlock the RUN_PD bit in FLASH_ACR */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants + * @{ + */ + +/** @defgroup SYSTEM_LL_EC_REMAP SYSCFG Memory Remap +* @{ +*/ +#define LL_SYSCFG_REMAP_FLASH 0x00000000U /*!< Main Flash memory mapped at 0x00000000 */ +#define LL_SYSCFG_REMAP_SYSTEMFLASH SYSCFG_CFGR1_MEM_MODE_0 /*!< System Flash memory mapped at 0x00000000 */ +#define LL_SYSCFG_REMAP_SRAM (SYSCFG_CFGR1_MEM_MODE_1 | SYSCFG_CFGR1_MEM_MODE_0) /*!< SRAM mapped at 0x00000000 */ + +/** + * @} + */ + +#if defined(SYSCFG_CFGR1_UFB) +/** @defgroup SYSTEM_LL_EC_BANKMODE SYSCFG Bank Mode + * @{ + */ +#define LL_SYSCFG_BANKMODE_BANK1 0x00000000U /*!< Flash Bank1 mapped at 0x08000000 (and aliased at 0x00000000), + Flash Bank2 mapped at 0x08018000 (and aliased at 0x00018000), + Data EEPROM Bank1 mapped at 0x08080000 (and aliased at 0x00080000), + Data EEPROM Bank2 mapped at 0x08080C00 (and aliased at 0x00080C00) */ +#define LL_SYSCFG_BANKMODE_BANK2 SYSCFG_CFGR1_UFB /*!< Flash Bank2 mapped at 0x08000000 (and aliased at 0x00000000), + Flash Bank1 mapped at 0x08018000 (and aliased at 0x00018000), + Data EEPROM Bank2 mapped at 0x08080000 (and aliased at 0x00080000), + Data EEPROM Bank1 mapped at 0x08080C00 (and aliased at 0x00080C00) */ +/** + * @} + */ + +#endif /* SYSCFG_CFGR1_UFB */ + +/** @defgroup SYSTEM_LL_EC_BOOTMODE SYSCFG Boot Mode +* @{ +*/ +#define LL_SYSCFG_BOOTMODE_FLASH 0x00000000U /*!< Main Flash memory boot mode */ +#define LL_SYSCFG_BOOTMODE_SYSTEMFLASH SYSCFG_CFGR1_BOOT_MODE_0 /*!< System Flash memory boot mode */ +#define LL_SYSCFG_BOOTMODE_SRAM (SYSCFG_CFGR1_BOOT_MODE_1 | SYSCFG_CFGR1_BOOT_MODE_0) /*!< SRAM boot mode */ + +/** + * @} + */ + +#if defined(SYSCFG_CFGR2_CAPA) +/** @defgroup SYSTEM_LL_EC_CFGR2 SYSCFG VLCD Rail Connection + * @{ + */ + +#define LL_SYSCFG_CAPA_VLCD2_PB2 SYSCFG_CFGR2_CAPA_0 /*!< Connect PB2 pin to LCD_VLCD2 rails supply voltage */ +#define LL_SYSCFG_CAPA_VLCD1_PB12 SYSCFG_CFGR2_CAPA_1 /*!< Connect PB12 pin to LCD_VLCD1 rails supply voltage */ +#define LL_SYSCFG_CAPA_VLCD3_PB0 SYSCFG_CFGR2_CAPA_2 /*!< Connect PB0 pin to LCD_VLCD3 rails supply voltage */ +#if defined (SYSCFG_CFGR2_CAPA_3) +#define LL_SYSCFG_CAPA_VLCD1_PE11 SYSCFG_CFGR2_CAPA_3 /*!< Connect PE11 pin to LCD_VLCD1 rails supply voltage */ +#endif /* SYSCFG_CFGR2_CAPA_3 */ +#if defined (SYSCFG_CFGR2_CAPA_4) +#define LL_SYSCFG_CAPA_VLCD3_PE12 SYSCFG_CFGR2_CAPA_4 /*!< Connect PE12 pin to LCD_VLCD3 rails supply voltage */ +#endif /* SYSCFG_CFGR2_CAPA_4 */ +/** + * @} + */ +#endif /* SYSCFG_CFGR2_CAPA */ + +/** @defgroup SYSTEM_LL_EC_I2C_FASTMODEPLUS SYSCFG I2C FASTMODEPLUS + * @{ + */ +#define LL_SYSCFG_I2C_FASTMODEPLUS_PB6 SYSCFG_CFGR2_I2C_PB6_FMP /*!< Enable Fast Mode Plus on PB6 */ +#define LL_SYSCFG_I2C_FASTMODEPLUS_PB7 SYSCFG_CFGR2_I2C_PB7_FMP /*!< Enable Fast Mode Plus on PB7 */ +#define LL_SYSCFG_I2C_FASTMODEPLUS_PB8 SYSCFG_CFGR2_I2C_PB8_FMP /*!< Enable Fast Mode Plus on PB8 */ +#define LL_SYSCFG_I2C_FASTMODEPLUS_PB9 SYSCFG_CFGR2_I2C_PB9_FMP /*!< Enable Fast Mode Plus on PB9 */ +#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 SYSCFG_CFGR2_I2C1_FMP /*!< Enable Fast Mode Plus on I2C1 pins */ +#if defined(SYSCFG_CFGR2_I2C2_FMP) +#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 SYSCFG_CFGR2_I2C2_FMP /*!< Enable Fast Mode Plus on I2C2 pins */ +#endif /* SYSCFG_CFGR2_I2C2_FMP */ +#if defined(SYSCFG_CFGR2_I2C3_FMP) +#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 SYSCFG_CFGR2_I2C3_FMP /*!< Enable Fast Mode Plus on I2C3 pins */ +#endif /* SYSCFG_CFGR2_I2C3_FMP */ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_VREFINT_CONTROL SYSCFG VREFINT Control + * @{ + */ +#define LL_SYSCFG_VREFINT_CONNECT_NONE 0x00000000U /*!< No pad connected to VREFINT_ADC */ +#define LL_SYSCFG_VREFINT_CONNECT_IO1 SYSCFG_CFGR3_VREF_OUT_0 /*!< PB0 connected to VREFINT_ADC */ +#define LL_SYSCFG_VREFINT_CONNECT_IO2 SYSCFG_CFGR3_VREF_OUT_1 /*!< PB1 connected to VREFINT_ADC */ +#define LL_SYSCFG_VREFINT_CONNECT_IO1_IO2 (SYSCFG_CFGR3_VREF_OUT_0 | SYSCFG_CFGR3_VREF_OUT_1) /*!< PB0 and PB1 connected to VREFINT_ADC */ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_EXTI_PORT SYSCFG EXTI Port + * @{ + */ +#define LL_SYSCFG_EXTI_PORTA 0U /*!< EXTI PORT A */ +#define LL_SYSCFG_EXTI_PORTB 1U /*!< EXTI PORT B */ +#define LL_SYSCFG_EXTI_PORTC 2U /*!< EXTI PORT C */ +#if defined(GPIOD_BASE) +#define LL_SYSCFG_EXTI_PORTD 3U /*!< EXTI PORT D */ +#endif /*GPIOD_BASE*/ +#if defined(GPIOE_BASE) +#define LL_SYSCFG_EXTI_PORTE 4U /*!< EXTI PORT E */ +#endif /*GPIOE_BASE*/ +#if defined(GPIOH_BASE) +#define LL_SYSCFG_EXTI_PORTH 5U /*!< EXTI PORT H */ +#endif /*GPIOH_BASE*/ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_EXTI_LINE SYSCFG EXTI Line + * @{ + */ +#define LL_SYSCFG_EXTI_LINE0 (uint32_t)(0U << 16U | 0U) /*!< EXTI_POSITION_0 | EXTICR[0] */ +#define LL_SYSCFG_EXTI_LINE1 (uint32_t)(4U << 16U | 0U) /*!< EXTI_POSITION_4 | EXTICR[0] */ +#define LL_SYSCFG_EXTI_LINE2 (uint32_t)(8U << 16U | 0U) /*!< EXTI_POSITION_8 | EXTICR[0] */ +#define LL_SYSCFG_EXTI_LINE3 (uint32_t)(12U << 16U | 0U) /*!< EXTI_POSITION_12 | EXTICR[0] */ +#define LL_SYSCFG_EXTI_LINE4 (uint32_t)(0U << 16U | 1U) /*!< EXTI_POSITION_0 | EXTICR[1] */ +#define LL_SYSCFG_EXTI_LINE5 (uint32_t)(4U << 16U | 1U) /*!< EXTI_POSITION_4 | EXTICR[1] */ +#define LL_SYSCFG_EXTI_LINE6 (uint32_t)(8U << 16U | 1U) /*!< EXTI_POSITION_8 | EXTICR[1] */ +#define LL_SYSCFG_EXTI_LINE7 (uint32_t)(12U << 16U | 1U) /*!< EXTI_POSITION_12 | EXTICR[1] */ +#define LL_SYSCFG_EXTI_LINE8 (uint32_t)(0U << 16U | 2U) /*!< EXTI_POSITION_0 | EXTICR[2] */ +#define LL_SYSCFG_EXTI_LINE9 (uint32_t)(4U << 16U | 2U) /*!< EXTI_POSITION_4 | EXTICR[2] */ +#define LL_SYSCFG_EXTI_LINE10 (uint32_t)(8U << 16U | 2U) /*!< EXTI_POSITION_8 | EXTICR[2] */ +#define LL_SYSCFG_EXTI_LINE11 (uint32_t)(12U << 16U | 2U) /*!< EXTI_POSITION_12 | EXTICR[2] */ +#define LL_SYSCFG_EXTI_LINE12 (uint32_t)(0U << 16U | 3U) /*!< EXTI_POSITION_0 | EXTICR[3] */ +#define LL_SYSCFG_EXTI_LINE13 (uint32_t)(4U << 16U | 3U) /*!< EXTI_POSITION_4 | EXTICR[3] */ +#define LL_SYSCFG_EXTI_LINE14 (uint32_t)(8U << 16U | 3U) /*!< EXTI_POSITION_8 | EXTICR[3] */ +#define LL_SYSCFG_EXTI_LINE15 (uint32_t)(12U << 16U | 3U) /*!< EXTI_POSITION_12 | EXTICR[3] */ +/** + * @} + */ + + + +/** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP + * @{ + */ +#define LL_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP /*!< TIM2 counter stopped when core is halted */ +#if defined(TIM3) +#define LL_DBGMCU_APB1_GRP1_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP /*!< TIM3 counter stopped when core is halted */ +#endif /*TIM3*/ +#if defined(TIM6) +#define LL_DBGMCU_APB1_GRP1_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP /*!< TIM6 counter stopped when core is halted */ +#endif /*TIM6*/ +#if defined(TIM7) +#define LL_DBGMCU_APB1_GRP1_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP /*!< TIM7 counter stopped when core is halted */ +#endif /*TIM7*/ +#define LL_DBGMCU_APB1_GRP1_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP /*!< RTC Calendar frozen when core is halted */ +#define LL_DBGMCU_APB1_GRP1_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP /*!< Debug Window Watchdog stopped when Core is halted */ +#define LL_DBGMCU_APB1_GRP1_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP /*!< Debug Independent Watchdog stopped when Core is halted */ +#define LL_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_APB1_FZ_DBG_I2C1_STOP /*!< I2C1 SMBUS timeout mode stopped when Core is halted */ +#if defined(I2C2) +#define LL_DBGMCU_APB1_GRP1_I2C2_STOP DBGMCU_APB1_FZ_DBG_I2C2_STOP /*!< I2C2 SMBUS timeout mode stopped when Core is halted */ +#endif /*I2C2*/ +#if defined(I2C3) +#define LL_DBGMCU_APB1_GRP1_I2C3_STOP DBGMCU_APB1_FZ_DBG_I2C3_STOP /*!< I2C3 SMBUS timeout mode stopped when Core is halted */ +#endif /*I2C3*/ +#define LL_DBGMCU_APB1_GRP1_LPTIM1_STOP DBGMCU_APB1_FZ_DBG_LPTIMER_STOP /*!< LPTIM1 counter stopped when core is halted */ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_APB2_GRP1_STOP_IP DBGMCU APB2 GRP1 STOP IP + * @{ + */ +#if defined(TIM22) +#define LL_DBGMCU_APB2_GRP1_TIM22_STOP DBGMCU_APB2_FZ_DBG_TIM22_STOP /*!< TIM22 counter stopped when core is halted */ +#endif /*TIM22*/ +#define LL_DBGMCU_APB2_GRP1_TIM21_STOP DBGMCU_APB2_FZ_DBG_TIM21_STOP /*!< TIM21 counter stopped when core is halted */ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY + * @{ + */ +#define LL_FLASH_LATENCY_0 (0x00000000U) /*!< FLASH Zero Latency cycle */ +#define LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY /*!< FLASH One Latency cycle */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions + * @{ + */ + +/** @defgroup SYSTEM_LL_EF_SYSCFG SYSCFG + * @{ + */ + +/** + * @brief Set memory mapping at address 0x00000000 + * @rmtoll SYSCFG_CFGR1 MEM_MODE LL_SYSCFG_SetRemapMemory + * @param Memory This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_REMAP_FLASH + * @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH + * @arg @ref LL_SYSCFG_REMAP_SRAM + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetRemapMemory(uint32_t Memory) +{ + MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE, Memory); +} + +/** + * @brief Get memory mapping at address 0x00000000 + * @rmtoll SYSCFG_CFGR1 MEM_MODE LL_SYSCFG_GetRemapMemory + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSCFG_REMAP_FLASH + * @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH + * @arg @ref LL_SYSCFG_REMAP_SRAM + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetRemapMemory(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE)); +} + +#if defined(SYSCFG_CFGR1_UFB) +/** + * @brief Select Flash bank mode (Bank flashed at 0x08000000) + * @rmtoll SYSCFG_CFGR1 UFB LL_SYSCFG_SetFlashBankMode + * @param Bank This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_BANKMODE_BANK1 + * @arg @ref LL_SYSCFG_BANKMODE_BANK2 + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetFlashBankMode(uint32_t Bank) +{ + MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_UFB, Bank); +} + +/** + * @brief Get Flash bank mode (Bank flashed at 0x08000000) + * @rmtoll SYSCFG_CFGR1 UFB LL_SYSCFG_GetFlashBankMode + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSCFG_BANKMODE_BANK1 + * @arg @ref LL_SYSCFG_BANKMODE_BANK2 + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetFlashBankMode(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_UFB)); +} +#endif /* SYSCFG_CFGR1_UFB */ + +/** + * @brief Get Boot mode selected by the boot pins status bits + * @note It indicates the boot mode selected by the boot pins. Bit 9 + * corresponds to the complement of nBOOT1 bit in the FLASH_OPTR register. + * Its value is defined in the option bytes. Bit 8 corresponds to the + * value sampled on the BOOT0 pin. + * @rmtoll SYSCFG_CFGR1 BOOT_MODE LL_SYSCFG_GetBootMode + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSCFG_BOOTMODE_FLASH + * @arg @ref LL_SYSCFG_BOOTMODE_SYSTEMFLASH + * @arg @ref LL_SYSCFG_BOOTMODE_SRAM + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetBootMode(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOT_MODE)); +} + +/** + * @brief Firewall protection enabled + * @rmtoll SYSCFG_CFGR2 FWDIS LL_SYSCFG_EnableFirewall + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_EnableFirewall(void) +{ + CLEAR_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_FWDISEN); +} + +/** + * @brief Check if Firewall protection is enabled or not + * @rmtoll SYSCFG_CFGR2 FWDIS LL_SYSCFG_IsEnabledFirewall + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledFirewall(void) +{ + return !(READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_FWDISEN) == SYSCFG_CFGR2_FWDISEN); +} + +#if defined(SYSCFG_CFGR2_CAPA) +/** + * @brief Set VLCD rail connection to optional external capacitor + * @note One to three external capacitors can be connected to pads to do + * VLCD biasing. + * - LCD_VLCD1 rail can be connected to PB12 or PE11(*), + * - LCD_VLCD2 rail can be connected to PB2, + * - LCD_VLCD3 rail can be connected to PB0 or PE12(*) + * @rmtoll SYSCFG_CFGR2 CAPA LL_SYSCFG_SetVLCDRailConnection + * @param IoPinConnect This parameter can be a combination of the following values: + * @arg @ref LL_SYSCFG_CAPA_VLCD1_PB12 + * @arg @ref LL_SYSCFG_CAPA_VLCD1_PE11(*) + * @arg @ref LL_SYSCFG_CAPA_VLCD2_PB2 + * @arg @ref LL_SYSCFG_CAPA_VLCD3_PB0 + * @arg @ref LL_SYSCFG_CAPA_VLCD3_PE12(*) + * + * (*) value not defined in all devices + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetVLCDRailConnection(uint32_t IoPinConnect) +{ + MODIFY_REG(SYSCFG->CFGR2, SYSCFG_CFGR2_CAPA, IoPinConnect); +} + + +/** + * @brief Get VLCD rail connection configuration + * @note One to three external capacitors can be connected to pads to do + * VLCD biasing. + * - LCD_VLCD1 rail can be connected to PB12 or PE11(*), + * - LCD_VLCD2 rail can be connected to PB2, + * - LCD_VLCD3 rail can be connected to PB0 or PE12(*) + * @rmtoll SYSCFG_CFGR2 CAPA LL_SYSCFG_GetVLCDRailConnection + * @retval Returned value can be a combination of the following values: + * @arg @ref LL_SYSCFG_CAPA_VLCD1_PB12 + * @arg @ref LL_SYSCFG_CAPA_VLCD1_PE11(*) + * @arg @ref LL_SYSCFG_CAPA_VLCD2_PB2 + * @arg @ref LL_SYSCFG_CAPA_VLCD3_PB0 + * @arg @ref LL_SYSCFG_CAPA_VLCD3_PE12(*) + * + * (*) value not defined in all devices + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetVLCDRailConnection(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_CAPA)); +} +#endif + +/** + * @brief Enable the I2C fast mode plus driving capability. + * @rmtoll SYSCFG_CFGR2 I2C_PBx_FMP LL_SYSCFG_EnableFastModePlus\n + * SYSCFG_CFGR2 I2Cx_FMP LL_SYSCFG_EnableFastModePlus + * @param ConfigFastModePlus This parameter can be a combination of the following values: + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6 + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7 + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8 + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9 + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*) + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 (*) + * + * (*) value not defined in all devices + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus) +{ + SET_BIT(SYSCFG->CFGR2, ConfigFastModePlus); +} + +/** + * @brief Disable the I2C fast mode plus driving capability. + * @rmtoll SYSCFG_CFGR2 I2C_PBx_FMP LL_SYSCFG_DisableFastModePlus\n + * SYSCFG_CFGR2 I2Cx_FMP LL_SYSCFG_DisableFastModePlus + * @param ConfigFastModePlus This parameter can be a combination of the following values: + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6 + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7 + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8 + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9 + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*) + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 (*) + * + * (*) value not defined in all devices + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus) +{ + CLEAR_BIT(SYSCFG->CFGR2, ConfigFastModePlus); +} + +/** + * @brief Select which pad is connected to VREFINT_ADC + * @rmtoll SYSCFG_CFGR3 SEL_VREF_OUT LL_SYSCFG_VREFINT_SetConnection + * @param IoPinConnect This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_VREFINT_CONNECT_NONE + * @arg @ref LL_SYSCFG_VREFINT_CONNECT_IO1 + * @arg @ref LL_SYSCFG_VREFINT_CONNECT_IO2 + * @arg @ref LL_SYSCFG_VREFINT_CONNECT_IO1_IO2 + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_VREFINT_SetConnection(uint32_t IoPinConnect) +{ + MODIFY_REG(SYSCFG->CFGR3, SYSCFG_CFGR3_VREF_OUT, IoPinConnect); +} + +/** + * @brief Get pad connection to VREFINT_ADC + * @rmtoll SYSCFG_CFGR3 SEL_VREF_OUT LL_SYSCFG_VREFINT_GetConnection + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSCFG_VREFINT_CONNECT_NONE + * @arg @ref LL_SYSCFG_VREFINT_CONNECT_IO1 + * @arg @ref LL_SYSCFG_VREFINT_CONNECT_IO2 + * @arg @ref LL_SYSCFG_VREFINT_CONNECT_IO1_IO2 + */ +__STATIC_INLINE uint32_t LL_SYSCFG_VREFINT_GetConnection(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->CFGR3, SYSCFG_CFGR3_VREF_OUT)); +} + +/** + * @brief Buffer used to generate VREFINT reference for ADC enable + * @note The VrefInit buffer to ADC through internal path is also + * enabled using function LL_ADC_SetCommonPathInternalCh() + * with parameter LL_ADC_PATH_INTERNAL_VREFINT + * @rmtoll SYSCFG_CFGR3 ENBUF_VREFINT_ADC LL_SYSCFG_VREFINT_EnableADC + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_VREFINT_EnableADC(void) +{ + SET_BIT(SYSCFG->CFGR3, SYSCFG_CFGR3_ENBUF_VREFINT_ADC); +} + +/** + * @brief Buffer used to generate VREFINT reference for ADC disable + * @rmtoll SYSCFG_CFGR3 ENBUF_VREFINT_ADC LL_SYSCFG_VREFINT_DisableADC + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_VREFINT_DisableADC(void) +{ + CLEAR_BIT(SYSCFG->CFGR3, SYSCFG_CFGR3_ENBUF_VREFINT_ADC); +} + +/** + * @brief Buffer used to generate temperature sensor reference for ADC enable + * @rmtoll SYSCFG_CFGR3 ENBUF_SENSOR_ADC LL_SYSCFG_TEMPSENSOR_Enable + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_TEMPSENSOR_Enable(void) +{ + SET_BIT(SYSCFG->CFGR3, SYSCFG_CFGR3_ENBUF_SENSOR_ADC); +} + +/** + * @brief Buffer used to generate temperature sensor reference for ADC disable + * @rmtoll SYSCFG_CFGR3 ENBUF_SENSOR_ADC LL_SYSCFG_TEMPSENSOR_Disable + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_TEMPSENSOR_Disable(void) +{ + CLEAR_BIT(SYSCFG->CFGR3, SYSCFG_CFGR3_ENBUF_SENSOR_ADC); +} + +/** + * @brief Buffer used to generate VREFINT reference for comparator enable + * @rmtoll SYSCFG_CFGR3 ENBUF_VREFINT_COMP LL_SYSCFG_VREFINT_EnableCOMP + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_VREFINT_EnableCOMP(void) +{ + SET_BIT(SYSCFG->CFGR3, SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP); +} + +/** + * @brief Buffer used to generate VREFINT reference for comparator disable + * @rmtoll SYSCFG_CFGR3 ENBUF_VREFINT_COMP LL_SYSCFG_VREFINT_DisableCOMP + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_VREFINT_DisableCOMP(void) +{ + CLEAR_BIT(SYSCFG->CFGR3, SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP); +} + +#if defined (RCC_HSI48_SUPPORT) +/** + * @brief Buffer used to generate VREFINT reference for HSI48 oscillator enable + * @rmtoll SYSCFG_CFGR3 ENREF_HSI48 LL_SYSCFG_VREFINT_EnableHSI48 + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_VREFINT_EnableHSI48(void) +{ + SET_BIT(SYSCFG->CFGR3, SYSCFG_CFGR3_ENREF_HSI48); +} + +/** + * @brief Buffer used to generate VREFINT reference for HSI48 oscillator disable + * @rmtoll SYSCFG_CFGR3 ENREF_HSI48 LL_SYSCFG_VREFINT_DisableHSI48 + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_VREFINT_DisableHSI48(void) +{ + CLEAR_BIT(SYSCFG->CFGR3, SYSCFG_CFGR3_ENREF_HSI48); +} +#endif + +/** + * @brief Check if VREFINT is ready or not + * @note When set, it indicates that VREFINT is available for BOR, PVD and LCD + * @rmtoll SYSCFG_CFGR3 VREFINT_RDYF LL_SYSCFG_VREFINT_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_VREFINT_IsReady(void) +{ + return (READ_BIT(SYSCFG->CFGR3, SYSCFG_CFGR3_VREFINT_RDYF) == SYSCFG_CFGR3_VREFINT_RDYF); +} + +/** + * @brief Lock the whole content of SYSCFG_CFGR3 register + * @note After SYSCFG_CFGR3 register lock, only read access available. + * Only system hardware reset unlocks SYSCFG_CFGR3 register. + * @rmtoll SYSCFG_CFGR3 REF_LOCK LL_SYSCFG_VREFINT_Lock + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_VREFINT_Lock(void) +{ + SET_BIT(SYSCFG->CFGR3, SYSCFG_CFGR3_REF_LOCK); +} + +/** + * @brief Check if SYSCFG_CFGR3 register is locked (only read access) or not + * @note When set, it indicates that SYSCFG_CFGR3 register is locked, only read access available + * @rmtoll SYSCFG_CFGR3 REF_LOCK LL_SYSCFG_VREFINT_IsLocked + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_VREFINT_IsLocked(void) +{ + return (READ_BIT(SYSCFG->CFGR3, SYSCFG_CFGR3_REF_LOCK) == SYSCFG_CFGR3_REF_LOCK); +} + +/** + * @brief Configure source input for the EXTI external interrupt. + * @rmtoll SYSCFG_EXTICR1 EXTI0 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR1 EXTI1 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR1 EXTI2 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR1 EXTI3 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR2 EXTI4 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR2 EXTI5 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR2 EXTI6 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR2 EXTI7 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR3 EXTI8 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR3 EXTI9 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR3 EXTI10 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR3 EXTI11 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR4 EXTI12 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR4 EXTI13 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR4 EXTI14 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR4 EXTI15 LL_SYSCFG_SetEXTISource + * @param Port This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_EXTI_PORTA + * @arg @ref LL_SYSCFG_EXTI_PORTB + * @arg @ref LL_SYSCFG_EXTI_PORTC + * @arg @ref LL_SYSCFG_EXTI_PORTD (*) + * @arg @ref LL_SYSCFG_EXTI_PORTE (*) + * @arg @ref LL_SYSCFG_EXTI_PORTH (*) + * + * (*) value not defined in all devices + * @param Line This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_EXTI_LINE0 + * @arg @ref LL_SYSCFG_EXTI_LINE1 + * @arg @ref LL_SYSCFG_EXTI_LINE2 + * @arg @ref LL_SYSCFG_EXTI_LINE3 + * @arg @ref LL_SYSCFG_EXTI_LINE4 + * @arg @ref LL_SYSCFG_EXTI_LINE5 + * @arg @ref LL_SYSCFG_EXTI_LINE6 + * @arg @ref LL_SYSCFG_EXTI_LINE7 + * @arg @ref LL_SYSCFG_EXTI_LINE8 + * @arg @ref LL_SYSCFG_EXTI_LINE9 + * @arg @ref LL_SYSCFG_EXTI_LINE10 + * @arg @ref LL_SYSCFG_EXTI_LINE11 + * @arg @ref LL_SYSCFG_EXTI_LINE12 + * @arg @ref LL_SYSCFG_EXTI_LINE13 + * @arg @ref LL_SYSCFG_EXTI_LINE14 + * @arg @ref LL_SYSCFG_EXTI_LINE15 + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetEXTISource(uint32_t Port, uint32_t Line) +{ + MODIFY_REG(SYSCFG->EXTICR[Line & 0xFFU], SYSCFG_EXTICR1_EXTI0 << (Line >> 16U), Port << (Line >> 16U)); +} + +/** + * @brief Get the configured defined for specific EXTI Line + * @rmtoll SYSCFG_EXTICR1 EXTI0 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR1 EXTI1 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR1 EXTI2 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR1 EXTI3 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR2 EXTI4 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR2 EXTI5 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR2 EXTI6 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR2 EXTI7 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR3 EXTI8 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR3 EXTI9 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR3 EXTI10 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR3 EXTI11 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR4 EXTI12 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR4 EXTI13 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR4 EXTI14 LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR4 EXTI15 LL_SYSCFG_SetEXTISource + * @param Line This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_EXTI_LINE0 + * @arg @ref LL_SYSCFG_EXTI_LINE1 + * @arg @ref LL_SYSCFG_EXTI_LINE2 + * @arg @ref LL_SYSCFG_EXTI_LINE3 + * @arg @ref LL_SYSCFG_EXTI_LINE4 + * @arg @ref LL_SYSCFG_EXTI_LINE5 + * @arg @ref LL_SYSCFG_EXTI_LINE6 + * @arg @ref LL_SYSCFG_EXTI_LINE7 + * @arg @ref LL_SYSCFG_EXTI_LINE8 + * @arg @ref LL_SYSCFG_EXTI_LINE9 + * @arg @ref LL_SYSCFG_EXTI_LINE10 + * @arg @ref LL_SYSCFG_EXTI_LINE11 + * @arg @ref LL_SYSCFG_EXTI_LINE12 + * @arg @ref LL_SYSCFG_EXTI_LINE13 + * @arg @ref LL_SYSCFG_EXTI_LINE14 + * @arg @ref LL_SYSCFG_EXTI_LINE15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSCFG_EXTI_PORTA + * @arg @ref LL_SYSCFG_EXTI_PORTB + * @arg @ref LL_SYSCFG_EXTI_PORTC + * @arg @ref LL_SYSCFG_EXTI_PORTD (*) + * @arg @ref LL_SYSCFG_EXTI_PORTE (*) + * @arg @ref LL_SYSCFG_EXTI_PORTH (*) + * + * (*) value not defined in all devices + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetEXTISource(uint32_t Line) +{ + return (uint32_t)(READ_BIT(SYSCFG->EXTICR[Line & 0xFFU], (SYSCFG_EXTICR1_EXTI0 << (Line >> 16U))) >> (Line >> 16U)); +} + + +/** + * @} + */ + + +/** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU + * @{ + */ + +/** + * @brief Return the device identifier + * @rmtoll DBGMCU_IDCODE DEV_ID LL_DBGMCU_GetDeviceID + * @retval Values between Min_Data=0x00 and Max_Data=0x7FF (ex: L053 -> 0x417, L073 -> 0x447) + */ +__STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void) +{ + return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID)); +} + +/** + * @brief Return the device revision identifier + * @note This field indicates the revision of the device. + * @rmtoll DBGMCU_IDCODE REV_ID LL_DBGMCU_GetRevisionID + * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF + */ +__STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void) +{ + return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos); +} + +/** + * @brief Enable the Debug Module during SLEEP mode + * @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_EnableDBGSleepMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_EnableDBGSleepMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); +} + +/** + * @brief Disable the Debug Module during SLEEP mode + * @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_DisableDBGSleepMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_DisableDBGSleepMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); +} + +/** + * @brief Enable the Debug Module during STOP mode + * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_EnableDBGStopMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); +} + +/** + * @brief Disable the Debug Module during STOP mode + * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_DisableDBGStopMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); +} + +/** + * @brief Enable the Debug Module during STANDBY mode + * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_EnableDBGStandbyMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); +} + +/** + * @brief Disable the Debug Module during STANDBY mode + * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_DisableDBGStandbyMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); +} + +/** + * @brief Freeze APB1 peripherals (group1 peripherals) + * @rmtoll APB1FZ DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * APB1FZ DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * APB1FZ DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * APB1FZ DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * APB1FZ DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * APB1FZ DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * APB1FZ DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * APB1FZ DBG_I2C1_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * APB1FZ DBG_I2C2_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * APB1FZ DBG_I2C3_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * APB1FZ DBG_LPTIMER_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP (*) + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP (*) + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP (*) + * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP (*) + * @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP (*) + * @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM1_STOP + * + * (*) value not defined in all devices + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs) +{ + SET_BIT(DBGMCU->APB1FZ, Periphs); +} + +/** + * @brief Unfreeze APB1 peripherals (group1 peripherals) + * @rmtoll APB1FZ DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * APB1FZ DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * APB1FZ DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * APB1FZ DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * APB1FZ DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * APB1FZ DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * APB1FZ DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * APB1FZ DBG_I2C1_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * APB1FZ DBG_I2C2_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * APB1FZ DBG_I2C3_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * APB1FZ DBG_LPTIMER_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP (*) + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP (*) + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP (*) + * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP (*) + * @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP (*) + * @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM1_STOP + * + * (*) value not defined in all devices + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs) +{ + CLEAR_BIT(DBGMCU->APB1FZ, Periphs); +} + +/** + * @brief Freeze APB2 peripherals + * @rmtoll APB2FZ DBG_TIM22_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n + * APB2FZ DBG_TIM21_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM22_STOP (*) + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM21_STOP + * + * (*) value not defined in all devices + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs) +{ + SET_BIT(DBGMCU->APB2FZ, Periphs); +} + +/** + * @brief Unfreeze APB2 peripherals + * @rmtoll APB2FZ DBG_TIM22_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n + * APB2FZ DBG_TIM21_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM22_STOP (*) + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM21_STOP + * + * (*) value not defined in all devices + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs) +{ + CLEAR_BIT(DBGMCU->APB2FZ, Periphs); +} + +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EF_FLASH FLASH + * @{ + */ + +/** + * @brief Set FLASH Latency + * @rmtoll FLASH_ACR LATENCY LL_FLASH_SetLatency + * @param Latency This parameter can be one of the following values: + * @arg @ref LL_FLASH_LATENCY_0 + * @arg @ref LL_FLASH_LATENCY_1 + * @retval None + */ +__STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency) +{ + MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency); +} + +/** + * @brief Get FLASH Latency + * @rmtoll FLASH_ACR LATENCY LL_FLASH_GetLatency + * @retval Returned value can be one of the following values: + * @arg @ref LL_FLASH_LATENCY_0 + * @arg @ref LL_FLASH_LATENCY_1 + */ +__STATIC_INLINE uint32_t LL_FLASH_GetLatency(void) +{ + return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY)); +} + +/** + * @brief Enable Prefetch + * @rmtoll FLASH_ACR PRFTEN LL_FLASH_EnablePrefetch + * @retval None + */ +__STATIC_INLINE void LL_FLASH_EnablePrefetch(void) +{ + SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN); +} + +/** + * @brief Disable Prefetch + * @rmtoll FLASH_ACR PRFTEN LL_FLASH_DisablePrefetch + * @retval None + */ +__STATIC_INLINE void LL_FLASH_DisablePrefetch(void) +{ + CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTEN); +} + +/** + * @brief Check if Prefetch buffer is enabled + * @rmtoll FLASH_ACR PRFTEN LL_FLASH_IsPrefetchEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_FLASH_IsPrefetchEnabled(void) +{ + return (READ_BIT(FLASH->ACR, FLASH_ACR_PRFTEN) == (FLASH_ACR_PRFTEN)); +} + + +/** + * @brief Enable Flash Power-down mode during run mode or Low-power run mode + * @note Flash memory can be put in power-down mode only when the code is executed + * from RAM + * @note Flash must not be accessed when power down is enabled + * @note Flash must not be put in power-down while a program or an erase operation + * is on-going + * @rmtoll FLASH_ACR RUN_PD LL_FLASH_EnableRunPowerDown\n + * FLASH_PDKEYR PDKEY1 LL_FLASH_EnableRunPowerDown\n + * FLASH_PDKEYR PDKEY2 LL_FLASH_EnableRunPowerDown + * @retval None + */ +__STATIC_INLINE void LL_FLASH_EnableRunPowerDown(void) +{ + /* Following values must be written consecutively to unlock the RUN_PD bit in + FLASH_ACR */ + WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1); + WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY2); + SET_BIT(FLASH->ACR, FLASH_ACR_RUN_PD); +} + +/** + * @brief Disable Flash Power-down mode during run mode or Low-power run mode + * @rmtoll FLASH_ACR RUN_PD LL_FLASH_DisableRunPowerDown\n + * FLASH_PDKEYR PDKEY1 LL_FLASH_DisableRunPowerDown\n + * FLASH_PDKEYR PDKEY2 LL_FLASH_DisableRunPowerDown + * @retval None + */ +__STATIC_INLINE void LL_FLASH_DisableRunPowerDown(void) +{ + /* Following values must be written consecutively to unlock the RUN_PD bit in + FLASH_ACR */ + WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1); + WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY2); + CLEAR_BIT(FLASH->ACR, FLASH_ACR_RUN_PD); +} + +/** + * @brief Enable Flash Power-down mode during Sleep or Low-power sleep mode + * @note Flash must not be put in power-down while a program or an erase operation + * is on-going + * @rmtoll FLASH_ACR SLEEP_PD LL_FLASH_EnableSleepPowerDown + * @retval None + */ +__STATIC_INLINE void LL_FLASH_EnableSleepPowerDown(void) +{ + SET_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD); +} + +/** + * @brief Disable Flash Power-down mode during Sleep or Low-power sleep mode + * @rmtoll FLASH_ACR SLEEP_PD LL_FLASH_DisableSleepPowerDown + * @retval None + */ +__STATIC_INLINE void LL_FLASH_DisableSleepPowerDown(void) +{ + CLEAR_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD); +} + +/** + * @brief Enable buffers used as a cache during read access + * @rmtoll FLASH_ACR DISAB_BUF LL_FLASH_EnableBuffers + * @retval None + */ +__STATIC_INLINE void LL_FLASH_EnableBuffers(void) +{ + CLEAR_BIT(FLASH->ACR, FLASH_ACR_DISAB_BUF); +} + +/** + * @brief Disable buffers used as a cache during read access + * @note When disabled, every read will access the NVM even for + * an address already read (for example, the previous address). + * @rmtoll FLASH_ACR DISAB_BUF LL_FLASH_DisableBuffers + * @retval None + */ +__STATIC_INLINE void LL_FLASH_DisableBuffers(void) +{ + SET_BIT(FLASH->ACR, FLASH_ACR_DISAB_BUF); +} + +/** + * @brief Enable pre-read + * @note When enabled, the memory interface stores the last address + * read as data and tries to read the next one when no other + * read or write or prefetch operation is ongoing. + * It is automatically disabled every time the buffers are disabled. + * @rmtoll FLASH_ACR PRE_READ LL_FLASH_EnablePreRead + * @retval None + */ +__STATIC_INLINE void LL_FLASH_EnablePreRead(void) +{ + SET_BIT(FLASH->ACR, FLASH_ACR_PRE_READ); +} + +/** + * @brief Disable pre-read + * @rmtoll FLASH_ACR PRE_READ LL_FLASH_DisablePreRead + * @retval None + */ +__STATIC_INLINE void LL_FLASH_DisablePreRead(void) +{ + CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRE_READ); +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32L0xx_LL_SYSTEM_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/fw/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h b/fw/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h new file mode 100644 index 0000000..129bd8b --- /dev/null +++ b/fw/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h @@ -0,0 +1,269 @@ +/** + ****************************************************************************** + * @file stm32l0xx_ll_utils.h + * @author MCD Application Team + * @brief Header file of UTILS LL module. + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The LL UTILS driver contains a set of generic APIs that can be + used by user: + (+) Device electronic signature + (+) Timing functions + (+) PLL configuration functions + + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright(c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32L0xx_LL_UTILS_H +#define __STM32L0xx_LL_UTILS_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l0xx.h" + +/** @addtogroup STM32L0xx_LL_Driver + * @{ + */ + +/** @defgroup UTILS_LL UTILS + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup UTILS_LL_Private_Constants UTILS Private Constants + * @{ + */ + +/* Max delay can be used in LL_mDelay */ +#define LL_MAX_DELAY 0xFFFFFFFFU + +/** + * @brief Unique device ID register base address + */ +#define UID_BASE_ADDRESS UID_BASE + +/** + * @brief Flash size data register base address + */ +#define FLASHSIZE_BASE_ADDRESS FLASHSIZE_BASE + + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup UTILS_LL_Private_Macros UTILS Private Macros + * @{ + */ +/** + * @} + */ +/* Exported types ------------------------------------------------------------*/ +/** @defgroup UTILS_LL_ES_INIT UTILS Exported structures + * @{ + */ +/** + * @brief UTILS PLL structure definition + */ +typedef struct +{ + uint32_t PLLMul; /*!< Multiplication factor for PLL VCO input clock. + This parameter can be a value of @ref RCC_LL_EC_PLL_MUL + + This feature can be modified afterwards using unitary function + @ref LL_RCC_PLL_ConfigDomain_SYS(). */ + + uint32_t PLLDiv; /*!< Division factor for PLL VCO output clock. + This parameter can be a value of @ref RCC_LL_EC_PLL_DIV + + This feature can be modified afterwards using unitary function + @ref LL_RCC_PLL_ConfigDomain_SYS(). */ +} LL_UTILS_PLLInitTypeDef; + +/** + * @brief UTILS System, AHB and APB buses clock configuration structure definition + */ +typedef struct +{ + uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK). + This parameter can be a value of @ref RCC_LL_EC_SYSCLK_DIV + + This feature can be modified afterwards using unitary function + @ref LL_RCC_SetAHBPrescaler(). */ + + uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). + This parameter can be a value of @ref RCC_LL_EC_APB1_DIV + + This feature can be modified afterwards using unitary function + @ref LL_RCC_SetAPB1Prescaler(). */ + + uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK). + This parameter can be a value of @ref RCC_LL_EC_APB2_DIV + + This feature can be modified afterwards using unitary function + @ref LL_RCC_SetAPB2Prescaler(). */ + +} LL_UTILS_ClkInitTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup UTILS_LL_Exported_Constants UTILS Exported Constants + * @{ + */ + +/** @defgroup UTILS_EC_HSE_BYPASS HSE Bypass activation + * @{ + */ +#define LL_UTILS_HSEBYPASS_OFF 0x00000000U /*!< HSE Bypass is not enabled */ +#define LL_UTILS_HSEBYPASS_ON 0x00000001U /*!< HSE Bypass is enabled */ +/** + * @} + */ + + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup UTILS_LL_Exported_Functions UTILS Exported Functions + * @{ + */ + +/** @defgroup UTILS_EF_DEVICE_ELECTRONIC_SIGNATURE DEVICE ELECTRONIC SIGNATURE + * @{ + */ + +/** + * @brief Get Word0 of the unique device identifier (UID based on 96 bits) + * @retval UID[31:0] + */ +__STATIC_INLINE uint32_t LL_GetUID_Word0(void) +{ + return (uint32_t)(READ_REG(*((uint32_t *)UID_BASE_ADDRESS))); +} + +/** + * @brief Get Word1 of the unique device identifier (UID based on 96 bits) + * @retval UID[63:32] + */ +__STATIC_INLINE uint32_t LL_GetUID_Word1(void) +{ + return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 0x04U)))); +} + +/** + * @brief Get Word2 of the unique device identifier (UID based on 96 bits) + * @retval UID[95:64] + */ +__STATIC_INLINE uint32_t LL_GetUID_Word2(void) +{ + return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 0x14U)))); +} + +/** + * @brief Get Flash memory size + * @note This bitfield indicates the size of the device Flash memory expressed in + * Kbytes. As an example, 0x040 corresponds to 64 Kbytes. + * @retval FLASH_SIZE[15:0]: Flash memory size + */ +__STATIC_INLINE uint32_t LL_GetFlashSize(void) +{ + return (uint32_t)(READ_REG(*((uint32_t *)FLASHSIZE_BASE_ADDRESS)) & 0xFFFF); +} + + +/** + * @} + */ + +/** @defgroup UTILS_LL_EF_DELAY DELAY + * @{ + */ + +/** + * @brief This function configures the Cortex-M SysTick source of the time base. + * @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro) + * @note When a RTOS is used, it is recommended to avoid changing the SysTick + * configuration by calling this function, for a delay use rather osDelay RTOS service. + * @param Ticks Number of ticks + * @retval None + */ +__STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks) +{ + /* Configure the SysTick to have interrupt in 1ms time base */ + SysTick->LOAD = (uint32_t)((HCLKFrequency / Ticks) - 1UL); /* set reload register */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable the Systick Timer */ +} + +void LL_Init1msTick(uint32_t HCLKFrequency); +void LL_mDelay(uint32_t Delay); + +/** + * @} + */ + +/** @defgroup UTILS_EF_SYSTEM SYSTEM + * @{ + */ + +void LL_SetSystemCoreClock(uint32_t HCLKFrequency); +ErrorStatus LL_SetFlashLatency(uint32_t HCLKFrequency); +ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, + LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct); +ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass, + LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32L0xx_LL_UTILS_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/fw/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c b/fw/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c deleted file mode 100644 index 349c833..0000000 --- a/fw/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.c +++ /dev/null @@ -1,4145 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l0xx_hal_uart.c - * @author MCD Application Team - * @brief UART HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART). - * + Initialization and de-initialization functions - * + IO operation functions - * + Peripheral Control functions - * - * - @verbatim - =============================================================================== - ##### How to use this driver ##### - =============================================================================== - [..] - The UART HAL driver can be used as follows: - - (#) Declare a UART_HandleTypeDef handle structure (eg. UART_HandleTypeDef huart). - (#) Initialize the UART low level resources by implementing the HAL_UART_MspInit() API: - (++) Enable the USARTx interface clock. - (++) UART pins configuration: - (+++) Enable the clock for the UART GPIOs. - (+++) Configure these UART pins as alternate function pull-up. - (++) NVIC configuration if you need to use interrupt process (HAL_UART_Transmit_IT() - and HAL_UART_Receive_IT() APIs): - (+++) Configure the USARTx interrupt priority. - (+++) Enable the NVIC USART IRQ handle. - (++) UART interrupts handling: - -@@- The specific UART interrupts (Transmission complete interrupt, - RXNE interrupt, RX/TX FIFOs related interrupts and Error Interrupts) - are managed using the macros __HAL_UART_ENABLE_IT() and __HAL_UART_DISABLE_IT() - inside the transmit and receive processes. - (++) DMA Configuration if you need to use DMA process (HAL_UART_Transmit_DMA() - and HAL_UART_Receive_DMA() APIs): - (+++) Declare a DMA handle structure for the Tx/Rx channel. - (+++) Enable the DMAx interface clock. - (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters. - (+++) Configure the DMA Tx/Rx channel. - (+++) Associate the initialized DMA handle to the UART DMA Tx/Rx handle. - (+++) Configure the priority and enable the NVIC for the transfer complete - interrupt on the DMA Tx/Rx channel. - - (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Hardware - flow control and Mode (Receiver/Transmitter) in the huart handle Init structure. - - (#) If required, program UART advanced features (TX/RX pins swap, auto Baud rate detection,...) - in the huart handle AdvancedInit structure. - - (#) For the UART asynchronous mode, initialize the UART registers by calling - the HAL_UART_Init() API. - - (#) For the UART Half duplex mode, initialize the UART registers by calling - the HAL_HalfDuplex_Init() API. - - (#) For the UART LIN (Local Interconnection Network) mode, initialize the UART registers - by calling the HAL_LIN_Init() API. - - (#) For the UART Multiprocessor mode, initialize the UART registers - by calling the HAL_MultiProcessor_Init() API. - - (#) For the UART RS485 Driver Enabled mode, initialize the UART registers - by calling the HAL_RS485Ex_Init() API. - - [..] - (@) These API's (HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(), - also configure the low level Hardware GPIO, CLOCK, CORTEX...etc) by - calling the customized HAL_UART_MspInit() API. - - ##### Callback registration ##### - ================================== - - [..] - The compilation define USE_HAL_UART_REGISTER_CALLBACKS when set to 1 - allows the user to configure dynamically the driver callbacks. - - [..] - Use Function @ref HAL_UART_RegisterCallback() to register a user callback. - Function @ref HAL_UART_RegisterCallback() allows to register following callbacks: - (+) TxHalfCpltCallback : Tx Half Complete Callback. - (+) TxCpltCallback : Tx Complete Callback. - (+) RxHalfCpltCallback : Rx Half Complete Callback. - (+) RxCpltCallback : Rx Complete Callback. - (+) ErrorCallback : Error Callback. - (+) AbortCpltCallback : Abort Complete Callback. - (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback. - (+) AbortReceiveCpltCallback : Abort Receive Complete Callback. - (+) WakeupCallback : Wakeup Callback. - (+) MspInitCallback : UART MspInit. - (+) MspDeInitCallback : UART MspDeInit. - This function takes as parameters the HAL peripheral handle, the Callback ID - and a pointer to the user callback function. - - [..] - Use function @ref HAL_UART_UnRegisterCallback() to reset a callback to the default - weak (surcharged) function. - @ref HAL_UART_UnRegisterCallback() takes as parameters the HAL peripheral handle, - and the Callback ID. - This function allows to reset following callbacks: - (+) TxHalfCpltCallback : Tx Half Complete Callback. - (+) TxCpltCallback : Tx Complete Callback. - (+) RxHalfCpltCallback : Rx Half Complete Callback. - (+) RxCpltCallback : Rx Complete Callback. - (+) ErrorCallback : Error Callback. - (+) AbortCpltCallback : Abort Complete Callback. - (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback. - (+) AbortReceiveCpltCallback : Abort Receive Complete Callback. - (+) WakeupCallback : Wakeup Callback. - (+) MspInitCallback : UART MspInit. - (+) MspDeInitCallback : UART MspDeInit. - - [..] - For specific callback RxEventCallback, use dedicated registration/reset functions: - respectively @ref HAL_UART_RegisterRxEventCallback() , @ref HAL_UART_UnRegisterRxEventCallback(). - - [..] - By default, after the @ref HAL_UART_Init() and when the state is HAL_UART_STATE_RESET - all callbacks are set to the corresponding weak (surcharged) functions: - examples @ref HAL_UART_TxCpltCallback(), @ref HAL_UART_RxHalfCpltCallback(). - Exception done for MspInit and MspDeInit functions that are respectively - reset to the legacy weak (surcharged) functions in the @ref HAL_UART_Init() - and @ref HAL_UART_DeInit() only when these callbacks are null (not registered beforehand). - If not, MspInit or MspDeInit are not null, the @ref HAL_UART_Init() and @ref HAL_UART_DeInit() - keep and use the user MspInit/MspDeInit callbacks (registered beforehand). - - [..] - Callbacks can be registered/unregistered in HAL_UART_STATE_READY state only. - Exception done MspInit/MspDeInit that can be registered/unregistered - in HAL_UART_STATE_READY or HAL_UART_STATE_RESET state, thus registered (user) - MspInit/DeInit callbacks can be used during the Init/DeInit. - In that case first register the MspInit/MspDeInit user callbacks - using @ref HAL_UART_RegisterCallback() before calling @ref HAL_UART_DeInit() - or @ref HAL_UART_Init() function. - - [..] - When The compilation define USE_HAL_UART_REGISTER_CALLBACKS is set to 0 or - not defined, the callback registration feature is not available - and weak (surcharged) callbacks are used. - - - @endverbatim - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l0xx_hal.h" - -/** @addtogroup STM32L0xx_HAL_Driver - * @{ - */ - -/** @defgroup UART UART - * @brief HAL UART module driver - * @{ - */ - -#ifdef HAL_UART_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/** @defgroup UART_Private_Constants UART Private Constants - * @{ - */ -#define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \ - USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8 )) /*!< UART or USART CR1 fields of parameters set by UART_SetConfig API */ - -#define USART_CR3_FIELDS ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE | USART_CR3_ONEBIT)) /*!< UART or USART CR3 fields of parameters set by UART_SetConfig API */ - -#define LPUART_BRR_MIN 0x00000300U /* LPUART BRR minimum authorized value */ -#define LPUART_BRR_MAX 0x000FFFFFU /* LPUART BRR maximum authorized value */ - -#define UART_BRR_MIN 0x10U /* UART BRR minimum authorized value */ -#define UART_BRR_MAX 0x0000FFFFU /* UART BRR maximum authorized value */ - -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/** @addtogroup UART_Private_Functions - * @{ - */ -static void UART_EndTxTransfer(UART_HandleTypeDef *huart); -static void UART_EndRxTransfer(UART_HandleTypeDef *huart); -static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma); -static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma); -static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma); -static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma); -static void UART_DMAError(DMA_HandleTypeDef *hdma); -static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma); -static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma); -static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma); -static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma); -static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma); -static void UART_TxISR_8BIT(UART_HandleTypeDef *huart); -static void UART_TxISR_16BIT(UART_HandleTypeDef *huart); -static void UART_EndTransmit_IT(UART_HandleTypeDef *huart); -static void UART_RxISR_8BIT(UART_HandleTypeDef *huart); -static void UART_RxISR_16BIT(UART_HandleTypeDef *huart); -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ - -/** @defgroup UART_Exported_Functions UART Exported Functions - * @{ - */ - -/** @defgroup UART_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * -@verbatim -=============================================================================== - ##### Initialization and Configuration functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to initialize the USARTx or the UARTy - in asynchronous mode. - (+) For the asynchronous mode the parameters below can be configured: - (++) Baud Rate - (++) Word Length - (++) Stop Bit - (++) Parity: If the parity is enabled, then the MSB bit of the data written - in the data register is transmitted but is changed by the parity bit. - (++) Hardware flow control - (++) Receiver/transmitter modes - (++) Over Sampling Method - (++) One-Bit Sampling Method - (+) For the asynchronous mode, the following advanced features can be configured as well: - (++) TX and/or RX pin level inversion - (++) data logical level inversion - (++) RX and TX pins swap - (++) RX overrun detection disabling - (++) DMA disabling on RX error - (++) MSB first on communication line - (++) auto Baud rate detection - [..] - The HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init()and HAL_MultiProcessor_Init()API - follow respectively the UART asynchronous, UART Half duplex, UART LIN mode - and UART multiprocessor mode configuration procedures (details for the procedures - are available in reference manual). - -@endverbatim - - Depending on the frame length defined by the M1 and M0 bits (7-bit, - 8-bit or 9-bit), the possible UART formats are listed in the - following table. - - Table 1. UART frame format. - +-----------------------------------------------------------------------+ - | M1 bit | M0 bit | PCE bit | UART frame | - |---------|---------|-----------|---------------------------------------| - | 0 | 0 | 0 | | SB | 8 bit data | STB | | - |---------|---------|-----------|---------------------------------------| - | 0 | 0 | 1 | | SB | 7 bit data | PB | STB | | - |---------|---------|-----------|---------------------------------------| - | 0 | 1 | 0 | | SB | 9 bit data | STB | | - |---------|---------|-----------|---------------------------------------| - | 0 | 1 | 1 | | SB | 8 bit data | PB | STB | | - |---------|---------|-----------|---------------------------------------| - | 1 | 0 | 0 | | SB | 7 bit data | STB | | - |---------|---------|-----------|---------------------------------------| - | 1 | 0 | 1 | | SB | 6 bit data | PB | STB | | - +-----------------------------------------------------------------------+ - - * @{ - */ - -/** - * @brief Initialize the UART mode according to the specified - * parameters in the UART_InitTypeDef and initialize the associated handle. - * @param huart UART handle. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) -{ - /* Check the UART handle allocation */ - if (huart == NULL) - { - return HAL_ERROR; - } - - if (huart->Init.HwFlowCtl != UART_HWCONTROL_NONE) - { - /* Check the parameters */ - assert_param(IS_UART_HWFLOW_INSTANCE(huart->Instance)); - } - else - { - /* Check the parameters */ - assert_param((IS_UART_INSTANCE(huart->Instance)) || (IS_LPUART_INSTANCE(huart->Instance))); - } - - if (huart->gState == HAL_UART_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - huart->Lock = HAL_UNLOCKED; - -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - UART_InitCallbacksToDefault(huart); - - if (huart->MspInitCallback == NULL) - { - huart->MspInitCallback = HAL_UART_MspInit; - } - - /* Init the low level hardware */ - huart->MspInitCallback(huart); -#else - /* Init the low level hardware : GPIO, CLOCK */ - HAL_UART_MspInit(huart); -#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ - } - - huart->gState = HAL_UART_STATE_BUSY; - - __HAL_UART_DISABLE(huart); - - /* Set the UART Communication parameters */ - if (UART_SetConfig(huart) == HAL_ERROR) - { - return HAL_ERROR; - } - - if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) - { - UART_AdvFeatureConfig(huart); - } - - /* In asynchronous mode, the following bits must be kept cleared: - - LINEN and CLKEN bits in the USART_CR2 register, - - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/ - CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); - CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); - - __HAL_UART_ENABLE(huart); - - /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ - return (UART_CheckIdleState(huart)); -} - -/** - * @brief Initialize the half-duplex mode according to the specified - * parameters in the UART_InitTypeDef and creates the associated handle. - * @param huart UART handle. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart) -{ - /* Check the UART handle allocation */ - if (huart == NULL) - { - return HAL_ERROR; - } - - /* Check UART instance */ - assert_param(IS_UART_HALFDUPLEX_INSTANCE(huart->Instance)); - - if (huart->gState == HAL_UART_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - huart->Lock = HAL_UNLOCKED; - -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - UART_InitCallbacksToDefault(huart); - - if (huart->MspInitCallback == NULL) - { - huart->MspInitCallback = HAL_UART_MspInit; - } - - /* Init the low level hardware */ - huart->MspInitCallback(huart); -#else - /* Init the low level hardware : GPIO, CLOCK */ - HAL_UART_MspInit(huart); -#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ - } - - huart->gState = HAL_UART_STATE_BUSY; - - __HAL_UART_DISABLE(huart); - - /* Set the UART Communication parameters */ - if (UART_SetConfig(huart) == HAL_ERROR) - { - return HAL_ERROR; - } - - if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) - { - UART_AdvFeatureConfig(huart); - } - - /* In half-duplex mode, the following bits must be kept cleared: - - LINEN and CLKEN bits in the USART_CR2 register, - - SCEN and IREN bits in the USART_CR3 register.*/ - CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); - CLEAR_BIT(huart->Instance->CR3, (USART_CR3_IREN | USART_CR3_SCEN)); - - /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */ - SET_BIT(huart->Instance->CR3, USART_CR3_HDSEL); - - __HAL_UART_ENABLE(huart); - - /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ - return (UART_CheckIdleState(huart)); -} - - -/** - * @brief Initialize the LIN mode according to the specified - * parameters in the UART_InitTypeDef and creates the associated handle. - * @param huart UART handle. - * @param BreakDetectLength Specifies the LIN break detection length. - * This parameter can be one of the following values: - * @arg @ref UART_LINBREAKDETECTLENGTH_10B 10-bit break detection - * @arg @ref UART_LINBREAKDETECTLENGTH_11B 11-bit break detection - * @retval HAL status - */ -HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength) -{ - /* Check the UART handle allocation */ - if (huart == NULL) - { - return HAL_ERROR; - } - - /* Check the LIN UART instance */ - assert_param(IS_UART_LIN_INSTANCE(huart->Instance)); - /* Check the Break detection length parameter */ - assert_param(IS_UART_LIN_BREAK_DETECT_LENGTH(BreakDetectLength)); - - /* LIN mode limited to 16-bit oversampling only */ - if (huart->Init.OverSampling == UART_OVERSAMPLING_8) - { - return HAL_ERROR; - } - /* LIN mode limited to 8-bit data length */ - if (huart->Init.WordLength != UART_WORDLENGTH_8B) - { - return HAL_ERROR; - } - - if (huart->gState == HAL_UART_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - huart->Lock = HAL_UNLOCKED; - -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - UART_InitCallbacksToDefault(huart); - - if (huart->MspInitCallback == NULL) - { - huart->MspInitCallback = HAL_UART_MspInit; - } - - /* Init the low level hardware */ - huart->MspInitCallback(huart); -#else - /* Init the low level hardware : GPIO, CLOCK */ - HAL_UART_MspInit(huart); -#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ - } - - huart->gState = HAL_UART_STATE_BUSY; - - __HAL_UART_DISABLE(huart); - - /* Set the UART Communication parameters */ - if (UART_SetConfig(huart) == HAL_ERROR) - { - return HAL_ERROR; - } - - if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) - { - UART_AdvFeatureConfig(huart); - } - - /* In LIN mode, the following bits must be kept cleared: - - LINEN and CLKEN bits in the USART_CR2 register, - - SCEN and IREN bits in the USART_CR3 register.*/ - CLEAR_BIT(huart->Instance->CR2, USART_CR2_CLKEN); - CLEAR_BIT(huart->Instance->CR3, (USART_CR3_HDSEL | USART_CR3_IREN | USART_CR3_SCEN)); - - /* Enable the LIN mode by setting the LINEN bit in the CR2 register */ - SET_BIT(huart->Instance->CR2, USART_CR2_LINEN); - - /* Set the USART LIN Break detection length. */ - MODIFY_REG(huart->Instance->CR2, USART_CR2_LBDL, BreakDetectLength); - - __HAL_UART_ENABLE(huart); - - /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ - return (UART_CheckIdleState(huart)); -} - - -/** - * @brief Initialize the multiprocessor mode according to the specified - * parameters in the UART_InitTypeDef and initialize the associated handle. - * @param huart UART handle. - * @param Address UART node address (4-, 6-, 7- or 8-bit long). - * @param WakeUpMethod Specifies the UART wakeup method. - * This parameter can be one of the following values: - * @arg @ref UART_WAKEUPMETHOD_IDLELINE WakeUp by an idle line detection - * @arg @ref UART_WAKEUPMETHOD_ADDRESSMARK WakeUp by an address mark - * @note If the user resorts to idle line detection wake up, the Address parameter - * is useless and ignored by the initialization function. - * @note If the user resorts to address mark wake up, the address length detection - * is configured by default to 4 bits only. For the UART to be able to - * manage 6-, 7- or 8-bit long addresses detection, the API - * HAL_MultiProcessorEx_AddressLength_Set() must be called after - * HAL_MultiProcessor_Init(). - * @retval HAL status - */ -HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod) -{ - /* Check the UART handle allocation */ - if (huart == NULL) - { - return HAL_ERROR; - } - - /* Check the wake up method parameter */ - assert_param(IS_UART_WAKEUPMETHOD(WakeUpMethod)); - - if (huart->gState == HAL_UART_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - huart->Lock = HAL_UNLOCKED; - -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - UART_InitCallbacksToDefault(huart); - - if (huart->MspInitCallback == NULL) - { - huart->MspInitCallback = HAL_UART_MspInit; - } - - /* Init the low level hardware */ - huart->MspInitCallback(huart); -#else - /* Init the low level hardware : GPIO, CLOCK */ - HAL_UART_MspInit(huart); -#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ - } - - huart->gState = HAL_UART_STATE_BUSY; - - __HAL_UART_DISABLE(huart); - - /* Set the UART Communication parameters */ - if (UART_SetConfig(huart) == HAL_ERROR) - { - return HAL_ERROR; - } - - if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) - { - UART_AdvFeatureConfig(huart); - } - - /* In multiprocessor mode, the following bits must be kept cleared: - - LINEN and CLKEN bits in the USART_CR2 register, - - SCEN, HDSEL and IREN bits in the USART_CR3 register. */ - CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); - CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); - - if (WakeUpMethod == UART_WAKEUPMETHOD_ADDRESSMARK) - { - /* If address mark wake up method is chosen, set the USART address node */ - MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, ((uint32_t)Address << UART_CR2_ADDRESS_LSB_POS)); - } - - /* Set the wake up method by setting the WAKE bit in the CR1 register */ - MODIFY_REG(huart->Instance->CR1, USART_CR1_WAKE, WakeUpMethod); - - __HAL_UART_ENABLE(huart); - - /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ - return (UART_CheckIdleState(huart)); -} - - -/** - * @brief DeInitialize the UART peripheral. - * @param huart UART handle. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart) -{ - /* Check the UART handle allocation */ - if (huart == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param((IS_UART_INSTANCE(huart->Instance)) || (IS_LPUART_INSTANCE(huart->Instance))); - - huart->gState = HAL_UART_STATE_BUSY; - - __HAL_UART_DISABLE(huart); - - huart->Instance->CR1 = 0x0U; - huart->Instance->CR2 = 0x0U; - huart->Instance->CR3 = 0x0U; - -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - if (huart->MspDeInitCallback == NULL) - { - huart->MspDeInitCallback = HAL_UART_MspDeInit; - } - /* DeInit the low level hardware */ - huart->MspDeInitCallback(huart); -#else - /* DeInit the low level hardware */ - HAL_UART_MspDeInit(huart); -#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ - - huart->ErrorCode = HAL_UART_ERROR_NONE; - huart->gState = HAL_UART_STATE_RESET; - huart->RxState = HAL_UART_STATE_RESET; - huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; - - __HAL_UNLOCK(huart); - - return HAL_OK; -} - -/** - * @brief Initialize the UART MSP. - * @param huart UART handle. - * @retval None - */ -__weak void HAL_UART_MspInit(UART_HandleTypeDef *huart) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(huart); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_UART_MspInit can be implemented in the user file - */ -} - -/** - * @brief DeInitialize the UART MSP. - * @param huart UART handle. - * @retval None - */ -__weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(huart); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_UART_MspDeInit can be implemented in the user file - */ -} - -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) -/** - * @brief Register a User UART Callback - * To be used instead of the weak predefined callback - * @param huart uart handle - * @param CallbackID ID of the callback to be registered - * This parameter can be one of the following values: - * @arg @ref HAL_UART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID - * @arg @ref HAL_UART_TX_COMPLETE_CB_ID Tx Complete Callback ID - * @arg @ref HAL_UART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID - * @arg @ref HAL_UART_RX_COMPLETE_CB_ID Rx Complete Callback ID - * @arg @ref HAL_UART_ERROR_CB_ID Error Callback ID - * @arg @ref HAL_UART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID - * @arg @ref HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID - * @arg @ref HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID - * @arg @ref HAL_UART_WAKEUP_CB_ID Wakeup Callback ID - * @arg @ref HAL_UART_MSPINIT_CB_ID MspInit Callback ID - * @arg @ref HAL_UART_MSPDEINIT_CB_ID MspDeInit Callback ID - * @param pCallback pointer to the Callback function - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID, - pUART_CallbackTypeDef pCallback) -{ - HAL_StatusTypeDef status = HAL_OK; - - if (pCallback == NULL) - { - huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; - - return HAL_ERROR; - } - - __HAL_LOCK(huart); - - if (huart->gState == HAL_UART_STATE_READY) - { - switch (CallbackID) - { - case HAL_UART_TX_HALFCOMPLETE_CB_ID : - huart->TxHalfCpltCallback = pCallback; - break; - - case HAL_UART_TX_COMPLETE_CB_ID : - huart->TxCpltCallback = pCallback; - break; - - case HAL_UART_RX_HALFCOMPLETE_CB_ID : - huart->RxHalfCpltCallback = pCallback; - break; - - case HAL_UART_RX_COMPLETE_CB_ID : - huart->RxCpltCallback = pCallback; - break; - - case HAL_UART_ERROR_CB_ID : - huart->ErrorCallback = pCallback; - break; - - case HAL_UART_ABORT_COMPLETE_CB_ID : - huart->AbortCpltCallback = pCallback; - break; - - case HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID : - huart->AbortTransmitCpltCallback = pCallback; - break; - - case HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID : - huart->AbortReceiveCpltCallback = pCallback; - break; - - case HAL_UART_WAKEUP_CB_ID : - huart->WakeupCallback = pCallback; - break; - - - case HAL_UART_MSPINIT_CB_ID : - huart->MspInitCallback = pCallback; - break; - - case HAL_UART_MSPDEINIT_CB_ID : - huart->MspDeInitCallback = pCallback; - break; - - default : - huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; - - status = HAL_ERROR; - break; - } - } - else if (huart->gState == HAL_UART_STATE_RESET) - { - switch (CallbackID) - { - case HAL_UART_MSPINIT_CB_ID : - huart->MspInitCallback = pCallback; - break; - - case HAL_UART_MSPDEINIT_CB_ID : - huart->MspDeInitCallback = pCallback; - break; - - default : - huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; - - status = HAL_ERROR; - break; - } - } - else - { - huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; - - status = HAL_ERROR; - } - - __HAL_UNLOCK(huart); - - return status; -} - -/** - * @brief Unregister an UART Callback - * UART callaback is redirected to the weak predefined callback - * @param huart uart handle - * @param CallbackID ID of the callback to be unregistered - * This parameter can be one of the following values: - * @arg @ref HAL_UART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID - * @arg @ref HAL_UART_TX_COMPLETE_CB_ID Tx Complete Callback ID - * @arg @ref HAL_UART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID - * @arg @ref HAL_UART_RX_COMPLETE_CB_ID Rx Complete Callback ID - * @arg @ref HAL_UART_ERROR_CB_ID Error Callback ID - * @arg @ref HAL_UART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID - * @arg @ref HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID - * @arg @ref HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID - * @arg @ref HAL_UART_WAKEUP_CB_ID Wakeup Callback ID - * @arg @ref HAL_UART_MSPINIT_CB_ID MspInit Callback ID - * @arg @ref HAL_UART_MSPDEINIT_CB_ID MspDeInit Callback ID - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID) -{ - HAL_StatusTypeDef status = HAL_OK; - - __HAL_LOCK(huart); - - if (HAL_UART_STATE_READY == huart->gState) - { - switch (CallbackID) - { - case HAL_UART_TX_HALFCOMPLETE_CB_ID : - huart->TxHalfCpltCallback = HAL_UART_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ - break; - - case HAL_UART_TX_COMPLETE_CB_ID : - huart->TxCpltCallback = HAL_UART_TxCpltCallback; /* Legacy weak TxCpltCallback */ - break; - - case HAL_UART_RX_HALFCOMPLETE_CB_ID : - huart->RxHalfCpltCallback = HAL_UART_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ - break; - - case HAL_UART_RX_COMPLETE_CB_ID : - huart->RxCpltCallback = HAL_UART_RxCpltCallback; /* Legacy weak RxCpltCallback */ - break; - - case HAL_UART_ERROR_CB_ID : - huart->ErrorCallback = HAL_UART_ErrorCallback; /* Legacy weak ErrorCallback */ - break; - - case HAL_UART_ABORT_COMPLETE_CB_ID : - huart->AbortCpltCallback = HAL_UART_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ - break; - - case HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID : - huart->AbortTransmitCpltCallback = HAL_UART_AbortTransmitCpltCallback; /* Legacy weak - AbortTransmitCpltCallback */ - break; - - case HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID : - huart->AbortReceiveCpltCallback = HAL_UART_AbortReceiveCpltCallback; /* Legacy weak - AbortReceiveCpltCallback */ - break; - - case HAL_UART_WAKEUP_CB_ID : - huart->WakeupCallback = HAL_UARTEx_WakeupCallback; /* Legacy weak WakeupCallback */ - break; - - case HAL_UART_MSPINIT_CB_ID : - huart->MspInitCallback = HAL_UART_MspInit; /* Legacy weak MspInitCallback */ - break; - - case HAL_UART_MSPDEINIT_CB_ID : - huart->MspDeInitCallback = HAL_UART_MspDeInit; /* Legacy weak MspDeInitCallback */ - break; - - default : - huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; - - status = HAL_ERROR; - break; - } - } - else if (HAL_UART_STATE_RESET == huart->gState) - { - switch (CallbackID) - { - case HAL_UART_MSPINIT_CB_ID : - huart->MspInitCallback = HAL_UART_MspInit; - break; - - case HAL_UART_MSPDEINIT_CB_ID : - huart->MspDeInitCallback = HAL_UART_MspDeInit; - break; - - default : - huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; - - status = HAL_ERROR; - break; - } - } - else - { - huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; - - status = HAL_ERROR; - } - - __HAL_UNLOCK(huart); - - return status; -} - -/** - * @brief Register a User UART Rx Event Callback - * To be used instead of the weak predefined callback - * @param huart Uart handle - * @param pCallback Pointer to the Rx Event Callback function - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UART_RegisterRxEventCallback(UART_HandleTypeDef *huart, pUART_RxEventCallbackTypeDef pCallback) -{ - HAL_StatusTypeDef status = HAL_OK; - - if (pCallback == NULL) - { - huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; - - return HAL_ERROR; - } - - /* Process locked */ - __HAL_LOCK(huart); - - if (huart->gState == HAL_UART_STATE_READY) - { - huart->RxEventCallback = pCallback; - } - else - { - huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; - - status = HAL_ERROR; - } - - /* Release Lock */ - __HAL_UNLOCK(huart); - - return status; -} - -/** - * @brief UnRegister the UART Rx Event Callback - * UART Rx Event Callback is redirected to the weak HAL_UARTEx_RxEventCallback() predefined callback - * @param huart Uart handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Process locked */ - __HAL_LOCK(huart); - - if (huart->gState == HAL_UART_STATE_READY) - { - huart->RxEventCallback = HAL_UARTEx_RxEventCallback; /* Legacy weak UART Rx Event Callback */ - } - else - { - huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; - - status = HAL_ERROR; - } - - /* Release Lock */ - __HAL_UNLOCK(huart); - return status; -} - -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ - -/** - * @} - */ - -/** @defgroup UART_Exported_Functions_Group2 IO operation functions - * @brief UART Transmit/Receive functions - * -@verbatim - =============================================================================== - ##### IO operation functions ##### - =============================================================================== - This subsection provides a set of functions allowing to manage the UART asynchronous - and Half duplex data transfers. - - (#) There are two mode of transfer: - (+) Blocking mode: The communication is performed in polling mode. - The HAL status of all data processing is returned by the same function - after finishing transfer. - (+) Non-Blocking mode: The communication is performed using Interrupts - or DMA, These API's return the HAL status. - The end of the data processing will be indicated through the - dedicated UART IRQ when using Interrupt mode or the DMA IRQ when - using DMA mode. - The HAL_UART_TxCpltCallback(), HAL_UART_RxCpltCallback() user callbacks - will be executed respectively at the end of the transmit or Receive process - The HAL_UART_ErrorCallback()user callback will be executed when a communication error is detected - - (#) Blocking mode API's are : - (+) HAL_UART_Transmit() - (+) HAL_UART_Receive() - - (#) Non-Blocking mode API's with Interrupt are : - (+) HAL_UART_Transmit_IT() - (+) HAL_UART_Receive_IT() - (+) HAL_UART_IRQHandler() - - (#) Non-Blocking mode API's with DMA are : - (+) HAL_UART_Transmit_DMA() - (+) HAL_UART_Receive_DMA() - (+) HAL_UART_DMAPause() - (+) HAL_UART_DMAResume() - (+) HAL_UART_DMAStop() - - (#) A set of Transfer Complete Callbacks are provided in Non_Blocking mode: - (+) HAL_UART_TxHalfCpltCallback() - (+) HAL_UART_TxCpltCallback() - (+) HAL_UART_RxHalfCpltCallback() - (+) HAL_UART_RxCpltCallback() - (+) HAL_UART_ErrorCallback() - - (#) Non-Blocking mode transfers could be aborted using Abort API's : - (+) HAL_UART_Abort() - (+) HAL_UART_AbortTransmit() - (+) HAL_UART_AbortReceive() - (+) HAL_UART_Abort_IT() - (+) HAL_UART_AbortTransmit_IT() - (+) HAL_UART_AbortReceive_IT() - - (#) For Abort services based on interrupts (HAL_UART_Abortxxx_IT), a set of Abort Complete Callbacks are provided: - (+) HAL_UART_AbortCpltCallback() - (+) HAL_UART_AbortTransmitCpltCallback() - (+) HAL_UART_AbortReceiveCpltCallback() - - (#) A Rx Event Reception Callback (Rx event notification) is available for Non_Blocking modes of enhanced reception services: - (+) HAL_UARTEx_RxEventCallback() - - (#) In Non-Blocking mode transfers, possible errors are split into 2 categories. - Errors are handled as follows : - (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is - to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error - in Interrupt mode reception . - Received character is then retrieved and stored in Rx buffer, Error code is set to allow user - to identify error type, and HAL_UART_ErrorCallback() user callback is executed. - Transfer is kept ongoing on UART side. - If user wants to abort it, Abort services should be called by user. - (+) Error is considered as Blocking : Transfer could not be completed properly and is aborted. - This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode. - Error code is set to allow user to identify error type, and HAL_UART_ErrorCallback() - user callback is executed. - - -@- In the Half duplex communication, it is forbidden to run the transmit - and receive process in parallel, the UART state HAL_UART_STATE_BUSY_TX_RX can't be useful. - -@endverbatim - * @{ - */ - -/** - * @brief Send an amount of data in blocking mode. - * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), - * the sent data is handled as a set of u16. In this case, Size must indicate the number - * of u16 provided through pData. - * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), - * address of user data buffer containing data to be sent, should be aligned on a half word frontier (16 bits) - * (as sent data will be handled using u16 pointer cast). Depending on compilation chain, - * use of specific alignment compilation directives or pragmas might be required - * to ensure proper alignment for pData. - * @param huart UART handle. - * @param pData Pointer to data buffer (u8 or u16 data elements). - * @param Size Amount of data elements (u8 or u16) to be sent. - * @param Timeout Timeout duration. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout) -{ - uint8_t *pdata8bits; - uint16_t *pdata16bits; - uint32_t tickstart; - - /* Check that a Tx process is not already ongoing */ - if (huart->gState == HAL_UART_STATE_READY) - { - if ((pData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - - /* In case of 9bits/No Parity transfer, pData buffer provided as input parameter - should be aligned on a u16 frontier, as data to be filled into TDR will be - handled through a u16 cast. */ - if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) - { - if ((((uint32_t)pData) & 1U) != 0U) - { - return HAL_ERROR; - } - } - - __HAL_LOCK(huart); - - huart->ErrorCode = HAL_UART_ERROR_NONE; - huart->gState = HAL_UART_STATE_BUSY_TX; - - /* Init tickstart for timeout management */ - tickstart = HAL_GetTick(); - - huart->TxXferSize = Size; - huart->TxXferCount = Size; - - /* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */ - if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) - { - pdata8bits = NULL; - pdata16bits = (uint16_t *) pData; - } - else - { - pdata8bits = pData; - pdata16bits = NULL; - } - - __HAL_UNLOCK(huart); - - while (huart->TxXferCount > 0U) - { - if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - if (pdata8bits == NULL) - { - huart->Instance->TDR = (uint16_t)(*pdata16bits & 0x01FFU); - pdata16bits++; - } - else - { - huart->Instance->TDR = (uint8_t)(*pdata8bits & 0xFFU); - pdata8bits++; - } - huart->TxXferCount--; - } - - if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - - /* At end of Tx process, restore huart->gState to Ready */ - huart->gState = HAL_UART_STATE_READY; - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Receive an amount of data in blocking mode. - * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), - * the received data is handled as a set of u16. In this case, Size must indicate the number - * of u16 available through pData. - * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), - * address of user data buffer for storing data to be received, should be aligned on a half word frontier (16 bits) - * (as received data will be handled using u16 pointer cast). Depending on compilation chain, - * use of specific alignment compilation directives or pragmas might be required - * to ensure proper alignment for pData. - * @param huart UART handle. - * @param pData Pointer to data buffer (u8 or u16 data elements). - * @param Size Amount of data elements (u8 or u16) to be received. - * @param Timeout Timeout duration. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout) -{ - uint8_t *pdata8bits; - uint16_t *pdata16bits; - uint16_t uhMask; - uint32_t tickstart; - - /* Check that a Rx process is not already ongoing */ - if (huart->RxState == HAL_UART_STATE_READY) - { - if ((pData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - - /* In case of 9bits/No Parity transfer, pData buffer provided as input parameter - should be aligned on a u16 frontier, as data to be received from RDR will be - handled through a u16 cast. */ - if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) - { - if ((((uint32_t)pData) & 1U) != 0U) - { - return HAL_ERROR; - } - } - - __HAL_LOCK(huart); - - huart->ErrorCode = HAL_UART_ERROR_NONE; - huart->RxState = HAL_UART_STATE_BUSY_RX; - huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; - - /* Init tickstart for timeout management */ - tickstart = HAL_GetTick(); - - huart->RxXferSize = Size; - huart->RxXferCount = Size; - - /* Computation of UART mask to apply to RDR register */ - UART_MASK_COMPUTATION(huart); - uhMask = huart->Mask; - - /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */ - if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) - { - pdata8bits = NULL; - pdata16bits = (uint16_t *) pData; - } - else - { - pdata8bits = pData; - pdata16bits = NULL; - } - - __HAL_UNLOCK(huart); - - /* as long as data have to be received */ - while (huart->RxXferCount > 0U) - { - if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - if (pdata8bits == NULL) - { - *pdata16bits = (uint16_t)(huart->Instance->RDR & uhMask); - pdata16bits++; - } - else - { - *pdata8bits = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask); - pdata8bits++; - } - huart->RxXferCount--; - } - - /* At end of Rx process, restore huart->RxState to Ready */ - huart->RxState = HAL_UART_STATE_READY; - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Send an amount of data in interrupt mode. - * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), - * the sent data is handled as a set of u16. In this case, Size must indicate the number - * of u16 provided through pData. - * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), - * address of user data buffer containing data to be sent, should be aligned on a half word frontier (16 bits) - * (as sent data will be handled using u16 pointer cast). Depending on compilation chain, - * use of specific alignment compilation directives or pragmas might be required - * to ensure proper alignment for pData. - * @param huart UART handle. - * @param pData Pointer to data buffer (u8 or u16 data elements). - * @param Size Amount of data elements (u8 or u16) to be sent. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) -{ - /* Check that a Tx process is not already ongoing */ - if (huart->gState == HAL_UART_STATE_READY) - { - if ((pData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - - /* In case of 9bits/No Parity transfer, pData buffer provided as input parameter - should be aligned on a u16 frontier, as data to be filled into TDR will be - handled through a u16 cast. */ - if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) - { - if ((((uint32_t)pData) & 1U) != 0U) - { - return HAL_ERROR; - } - } - - __HAL_LOCK(huart); - - huart->pTxBuffPtr = pData; - huart->TxXferSize = Size; - huart->TxXferCount = Size; - huart->TxISR = NULL; - - huart->ErrorCode = HAL_UART_ERROR_NONE; - huart->gState = HAL_UART_STATE_BUSY_TX; - - /* Set the Tx ISR function pointer according to the data word length */ - if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) - { - huart->TxISR = UART_TxISR_16BIT; - } - else - { - huart->TxISR = UART_TxISR_8BIT; - } - - __HAL_UNLOCK(huart); - - /* Enable the Transmit Data Register Empty interrupt */ - SET_BIT(huart->Instance->CR1, USART_CR1_TXEIE); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Receive an amount of data in interrupt mode. - * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), - * the received data is handled as a set of u16. In this case, Size must indicate the number - * of u16 available through pData. - * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), - * address of user data buffer for storing data to be received, should be aligned on a half word frontier (16 bits) - * (as received data will be handled using u16 pointer cast). Depending on compilation chain, - * use of specific alignment compilation directives or pragmas might be required - * to ensure proper alignment for pData. - * @param huart UART handle. - * @param pData Pointer to data buffer (u8 or u16 data elements). - * @param Size Amount of data elements (u8 or u16) to be received. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) -{ - /* Check that a Rx process is not already ongoing */ - if (huart->RxState == HAL_UART_STATE_READY) - { - if ((pData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - - /* In case of 9bits/No Parity transfer, pData buffer provided as input parameter - should be aligned on a u16 frontier, as data to be received from RDR will be - handled through a u16 cast. */ - if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) - { - if ((((uint32_t)pData) & 1U) != 0U) - { - return HAL_ERROR; - } - } - - __HAL_LOCK(huart); - - /* Set Reception type to Standard reception */ - huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; - - if (!(IS_LPUART_INSTANCE(huart->Instance))) - { - /* Check that USART RTOEN bit is set */ - if(READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) - { - /* Enable the UART Receiver Timeout Interrupt */ - SET_BIT(huart->Instance->CR1, USART_CR1_RTOIE); - } - } - - return(UART_Start_Receive_IT(huart, pData, Size)); - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Send an amount of data in DMA mode. - * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), - * the sent data is handled as a set of u16. In this case, Size must indicate the number - * of u16 provided through pData. - * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), - * address of user data buffer containing data to be sent, should be aligned on a half word frontier (16 bits) - * (as sent data will be handled by DMA from halfword frontier). Depending on compilation chain, - * use of specific alignment compilation directives or pragmas might be required - * to ensure proper alignment for pData. - * @param huart UART handle. - * @param pData Pointer to data buffer (u8 or u16 data elements). - * @param Size Amount of data elements (u8 or u16) to be sent. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) -{ - /* Check that a Tx process is not already ongoing */ - if (huart->gState == HAL_UART_STATE_READY) - { - if ((pData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - - /* In case of 9bits/No Parity transfer, pData buffer provided as input parameter - should be aligned on a u16 frontier, as data copy into TDR will be - handled by DMA from a u16 frontier. */ - if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) - { - if ((((uint32_t)pData) & 1U) != 0U) - { - return HAL_ERROR; - } - } - - __HAL_LOCK(huart); - - huart->pTxBuffPtr = pData; - huart->TxXferSize = Size; - huart->TxXferCount = Size; - - huart->ErrorCode = HAL_UART_ERROR_NONE; - huart->gState = HAL_UART_STATE_BUSY_TX; - - if (huart->hdmatx != NULL) - { - /* Set the UART DMA transfer complete callback */ - huart->hdmatx->XferCpltCallback = UART_DMATransmitCplt; - - /* Set the UART DMA Half transfer complete callback */ - huart->hdmatx->XferHalfCpltCallback = UART_DMATxHalfCplt; - - /* Set the DMA error callback */ - huart->hdmatx->XferErrorCallback = UART_DMAError; - - /* Set the DMA abort callback */ - huart->hdmatx->XferAbortCallback = NULL; - - /* Enable the UART transmit DMA channel */ - if (HAL_DMA_Start_IT(huart->hdmatx, (uint32_t)huart->pTxBuffPtr, (uint32_t)&huart->Instance->TDR, Size) != HAL_OK) - { - /* Set error code to DMA */ - huart->ErrorCode = HAL_UART_ERROR_DMA; - - __HAL_UNLOCK(huart); - - /* Restore huart->gState to ready */ - huart->gState = HAL_UART_STATE_READY; - - return HAL_ERROR; - } - } - /* Clear the TC flag in the ICR register */ - __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_TCF); - - __HAL_UNLOCK(huart); - - /* Enable the DMA transfer for transmit request by setting the DMAT bit - in the UART CR3 register */ - SET_BIT(huart->Instance->CR3, USART_CR3_DMAT); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Receive an amount of data in DMA mode. - * @note When the UART parity is enabled (PCE = 1), the received data contain - * the parity bit (MSB position). - * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), - * the received data is handled as a set of u16. In this case, Size must indicate the number - * of u16 available through pData. - * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), - * address of user data buffer for storing data to be received, should be aligned on a half word frontier - * (16 bits) (as received data will be handled by DMA from halfword frontier). Depending on compilation chain, - * use of specific alignment compilation directives or pragmas might be required - * to ensure proper alignment for pData. - * @param huart UART handle. - * @param pData Pointer to data buffer (u8 or u16 data elements). - * @param Size Amount of data elements (u8 or u16) to be received. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) -{ - /* Check that a Rx process is not already ongoing */ - if (huart->RxState == HAL_UART_STATE_READY) - { - if ((pData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - - /* In case of 9bits/No Parity transfer, pData buffer provided as input parameter - should be aligned on a u16 frontier, as data copy from RDR will be - handled by DMA from a u16 frontier. */ - if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) - { - if ((((uint32_t)pData) & 1U) != 0U) - { - return HAL_ERROR; - } - } - - __HAL_LOCK(huart); - - /* Set Reception type to Standard reception */ - huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; - - if (!(IS_LPUART_INSTANCE(huart->Instance))) - { - /* Check that USART RTOEN bit is set */ - if(READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) - { - /* Enable the UART Receiver Timeout Interrupt */ - SET_BIT(huart->Instance->CR1, USART_CR1_RTOIE); - } - } - - return(UART_Start_Receive_DMA(huart, pData, Size)); - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Pause the DMA Transfer. - * @param huart UART handle. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart) -{ - const HAL_UART_StateTypeDef gstate = huart->gState; - const HAL_UART_StateTypeDef rxstate = huart->RxState; - - __HAL_LOCK(huart); - - if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) && - (gstate == HAL_UART_STATE_BUSY_TX)) - { - /* Disable the UART DMA Tx request */ - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); - } - if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) && - (rxstate == HAL_UART_STATE_BUSY_RX)) - { - /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ - CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); - CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); - - /* Disable the UART DMA Rx request */ - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); - } - - __HAL_UNLOCK(huart); - - return HAL_OK; -} - -/** - * @brief Resume the DMA Transfer. - * @param huart UART handle. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart) -{ - __HAL_LOCK(huart); - - if (huart->gState == HAL_UART_STATE_BUSY_TX) - { - /* Enable the UART DMA Tx request */ - SET_BIT(huart->Instance->CR3, USART_CR3_DMAT); - } - if (huart->RxState == HAL_UART_STATE_BUSY_RX) - { - /* Clear the Overrun flag before resuming the Rx transfer */ - __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF); - - /* Re-enable PE and ERR (Frame error, noise error, overrun error) interrupts */ - SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); - SET_BIT(huart->Instance->CR3, USART_CR3_EIE); - - /* Enable the UART DMA Rx request */ - SET_BIT(huart->Instance->CR3, USART_CR3_DMAR); - } - - __HAL_UNLOCK(huart); - - return HAL_OK; -} - -/** - * @brief Stop the DMA Transfer. - * @param huart UART handle. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart) -{ - /* The Lock is not implemented on this API to allow the user application - to call the HAL UART API under callbacks HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback() / - HAL_UART_TxHalfCpltCallback / HAL_UART_RxHalfCpltCallback: - indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete - interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of - the stream and the corresponding call back is executed. */ - - const HAL_UART_StateTypeDef gstate = huart->gState; - const HAL_UART_StateTypeDef rxstate = huart->RxState; - - /* Stop UART DMA Tx request if ongoing */ - if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) && - (gstate == HAL_UART_STATE_BUSY_TX)) - { - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); - - /* Abort the UART DMA Tx channel */ - if (huart->hdmatx != NULL) - { - if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK) - { - if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT) - { - /* Set error code to DMA */ - huart->ErrorCode = HAL_UART_ERROR_DMA; - - return HAL_TIMEOUT; - } - } - } - - UART_EndTxTransfer(huart); - } - - /* Stop UART DMA Rx request if ongoing */ - if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) && - (rxstate == HAL_UART_STATE_BUSY_RX)) - { - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); - - /* Abort the UART DMA Rx channel */ - if (huart->hdmarx != NULL) - { - if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK) - { - if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT) - { - /* Set error code to DMA */ - huart->ErrorCode = HAL_UART_ERROR_DMA; - - return HAL_TIMEOUT; - } - } - } - - UART_EndRxTransfer(huart); - } - - return HAL_OK; -} - -/** - * @brief Abort ongoing transfers (blocking mode). - * @param huart UART handle. - * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. - * This procedure performs following operations : - * - Disable UART Interrupts (Tx and Rx) - * - Disable the DMA transfer in the peripheral register (if enabled) - * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) - * - Set handle State to READY - * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart) -{ - /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE)); - CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); - - /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */ - if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) - { - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); - } - - /* Disable the UART DMA Tx request if enabled */ - if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) - { - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); - - /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */ - if (huart->hdmatx != NULL) - { - /* Set the UART DMA Abort callback to Null. - No call back execution at end of DMA abort procedure */ - huart->hdmatx->XferAbortCallback = NULL; - - if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK) - { - if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT) - { - /* Set error code to DMA */ - huart->ErrorCode = HAL_UART_ERROR_DMA; - - return HAL_TIMEOUT; - } - } - } - } - - /* Disable the UART DMA Rx request if enabled */ - if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) - { - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); - - /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */ - if (huart->hdmarx != NULL) - { - /* Set the UART DMA Abort callback to Null. - No call back execution at end of DMA abort procedure */ - huart->hdmarx->XferAbortCallback = NULL; - - if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK) - { - if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT) - { - /* Set error code to DMA */ - huart->ErrorCode = HAL_UART_ERROR_DMA; - - return HAL_TIMEOUT; - } - } - } - } - - /* Reset Tx and Rx transfer counters */ - huart->TxXferCount = 0U; - huart->RxXferCount = 0U; - - /* Clear the Error flags in the ICR register */ - __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); - - - /* Discard the received data */ - __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); - - /* Restore huart->gState and huart->RxState to Ready */ - huart->gState = HAL_UART_STATE_READY; - huart->RxState = HAL_UART_STATE_READY; - huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; - - huart->ErrorCode = HAL_UART_ERROR_NONE; - - return HAL_OK; -} - -/** - * @brief Abort ongoing Transmit transfer (blocking mode). - * @param huart UART handle. - * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode. - * This procedure performs following operations : - * - Disable UART Interrupts (Tx) - * - Disable the DMA transfer in the peripheral register (if enabled) - * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) - * - Set handle State to READY - * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart) -{ - /* Disable TXEIE and TCIE interrupts */ - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); - - /* Disable the UART DMA Tx request if enabled */ - if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) - { - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); - - /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */ - if (huart->hdmatx != NULL) - { - /* Set the UART DMA Abort callback to Null. - No call back execution at end of DMA abort procedure */ - huart->hdmatx->XferAbortCallback = NULL; - - if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK) - { - if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT) - { - /* Set error code to DMA */ - huart->ErrorCode = HAL_UART_ERROR_DMA; - - return HAL_TIMEOUT; - } - } - } - } - - /* Reset Tx transfer counter */ - huart->TxXferCount = 0U; - - - /* Restore huart->gState to Ready */ - huart->gState = HAL_UART_STATE_READY; - - return HAL_OK; -} - -/** - * @brief Abort ongoing Receive transfer (blocking mode). - * @param huart UART handle. - * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode. - * This procedure performs following operations : - * - Disable UART Interrupts (Rx) - * - Disable the DMA transfer in the peripheral register (if enabled) - * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) - * - Set handle State to READY - * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart) -{ - /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); - CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); - - /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */ - if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) - { - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); - } - - /* Disable the UART DMA Rx request if enabled */ - if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) - { - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); - - /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */ - if (huart->hdmarx != NULL) - { - /* Set the UART DMA Abort callback to Null. - No call back execution at end of DMA abort procedure */ - huart->hdmarx->XferAbortCallback = NULL; - - if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK) - { - if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT) - { - /* Set error code to DMA */ - huart->ErrorCode = HAL_UART_ERROR_DMA; - - return HAL_TIMEOUT; - } - } - } - } - - /* Reset Rx transfer counter */ - huart->RxXferCount = 0U; - - /* Clear the Error flags in the ICR register */ - __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); - - /* Discard the received data */ - __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); - - /* Restore huart->RxState to Ready */ - huart->RxState = HAL_UART_STATE_READY; - huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; - - return HAL_OK; -} - -/** - * @brief Abort ongoing transfers (Interrupt mode). - * @param huart UART handle. - * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. - * This procedure performs following operations : - * - Disable UART Interrupts (Tx and Rx) - * - Disable the DMA transfer in the peripheral register (if enabled) - * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) - * - Set handle State to READY - * - At abort completion, call user abort complete callback - * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be - * considered as completed only when user abort complete callback is executed (not when exiting function). - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart) -{ - uint32_t abortcplt = 1U; - - /* Disable interrupts */ - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE)); - CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); - - /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */ - if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) - { - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); - } - - /* If DMA Tx and/or DMA Rx Handles are associated to UART Handle, DMA Abort complete callbacks should be initialised - before any call to DMA Abort functions */ - /* DMA Tx Handle is valid */ - if (huart->hdmatx != NULL) - { - /* Set DMA Abort Complete callback if UART DMA Tx request if enabled. - Otherwise, set it to NULL */ - if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) - { - huart->hdmatx->XferAbortCallback = UART_DMATxAbortCallback; - } - else - { - huart->hdmatx->XferAbortCallback = NULL; - } - } - /* DMA Rx Handle is valid */ - if (huart->hdmarx != NULL) - { - /* Set DMA Abort Complete callback if UART DMA Rx request if enabled. - Otherwise, set it to NULL */ - if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) - { - huart->hdmarx->XferAbortCallback = UART_DMARxAbortCallback; - } - else - { - huart->hdmarx->XferAbortCallback = NULL; - } - } - - /* Disable the UART DMA Tx request if enabled */ - if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) - { - /* Disable DMA Tx at UART level */ - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); - - /* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */ - if (huart->hdmatx != NULL) - { - /* UART Tx DMA Abort callback has already been initialised : - will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */ - - /* Abort DMA TX */ - if (HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK) - { - huart->hdmatx->XferAbortCallback = NULL; - } - else - { - abortcplt = 0U; - } - } - } - - /* Disable the UART DMA Rx request if enabled */ - if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) - { - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); - - /* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */ - if (huart->hdmarx != NULL) - { - /* UART Rx DMA Abort callback has already been initialised : - will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */ - - /* Abort DMA RX */ - if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) - { - huart->hdmarx->XferAbortCallback = NULL; - abortcplt = 1U; - } - else - { - abortcplt = 0U; - } - } - } - - /* if no DMA abort complete callback execution is required => call user Abort Complete callback */ - if (abortcplt == 1U) - { - /* Reset Tx and Rx transfer counters */ - huart->TxXferCount = 0U; - huart->RxXferCount = 0U; - - /* Clear ISR function pointers */ - huart->RxISR = NULL; - huart->TxISR = NULL; - - /* Reset errorCode */ - huart->ErrorCode = HAL_UART_ERROR_NONE; - - /* Clear the Error flags in the ICR register */ - __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); - - - /* Discard the received data */ - __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); - - /* Restore huart->gState and huart->RxState to Ready */ - huart->gState = HAL_UART_STATE_READY; - huart->RxState = HAL_UART_STATE_READY; - huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; - - /* As no DMA to be aborted, call directly user Abort complete callback */ -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /* Call registered Abort complete callback */ - huart->AbortCpltCallback(huart); -#else - /* Call legacy weak Abort complete callback */ - HAL_UART_AbortCpltCallback(huart); -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ - } - - return HAL_OK; -} - -/** - * @brief Abort ongoing Transmit transfer (Interrupt mode). - * @param huart UART handle. - * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode. - * This procedure performs following operations : - * - Disable UART Interrupts (Tx) - * - Disable the DMA transfer in the peripheral register (if enabled) - * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) - * - Set handle State to READY - * - At abort completion, call user abort complete callback - * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be - * considered as completed only when user abort complete callback is executed (not when exiting function). - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart) -{ - /* Disable interrupts */ - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); - - /* Disable the UART DMA Tx request if enabled */ - if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) - { - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); - - /* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */ - if (huart->hdmatx != NULL) - { - /* Set the UART DMA Abort callback : - will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */ - huart->hdmatx->XferAbortCallback = UART_DMATxOnlyAbortCallback; - - /* Abort DMA TX */ - if (HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK) - { - /* Call Directly huart->hdmatx->XferAbortCallback function in case of error */ - huart->hdmatx->XferAbortCallback(huart->hdmatx); - } - } - else - { - /* Reset Tx transfer counter */ - huart->TxXferCount = 0U; - - /* Clear TxISR function pointers */ - huart->TxISR = NULL; - - /* Restore huart->gState to Ready */ - huart->gState = HAL_UART_STATE_READY; - - /* As no DMA to be aborted, call directly user Abort complete callback */ -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /* Call registered Abort Transmit Complete Callback */ - huart->AbortTransmitCpltCallback(huart); -#else - /* Call legacy weak Abort Transmit Complete Callback */ - HAL_UART_AbortTransmitCpltCallback(huart); -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ - } - } - else - { - /* Reset Tx transfer counter */ - huart->TxXferCount = 0U; - - /* Clear TxISR function pointers */ - huart->TxISR = NULL; - - - /* Restore huart->gState to Ready */ - huart->gState = HAL_UART_STATE_READY; - - /* As no DMA to be aborted, call directly user Abort complete callback */ -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /* Call registered Abort Transmit Complete Callback */ - huart->AbortTransmitCpltCallback(huart); -#else - /* Call legacy weak Abort Transmit Complete Callback */ - HAL_UART_AbortTransmitCpltCallback(huart); -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ - } - - return HAL_OK; -} - -/** - * @brief Abort ongoing Receive transfer (Interrupt mode). - * @param huart UART handle. - * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode. - * This procedure performs following operations : - * - Disable UART Interrupts (Rx) - * - Disable the DMA transfer in the peripheral register (if enabled) - * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) - * - Set handle State to READY - * - At abort completion, call user abort complete callback - * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be - * considered as completed only when user abort complete callback is executed (not when exiting function). - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart) -{ - /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); - CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); - - /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */ - if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) - { - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); - } - - /* Disable the UART DMA Rx request if enabled */ - if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) - { - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); - - /* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */ - if (huart->hdmarx != NULL) - { - /* Set the UART DMA Abort callback : - will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */ - huart->hdmarx->XferAbortCallback = UART_DMARxOnlyAbortCallback; - - /* Abort DMA RX */ - if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) - { - /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */ - huart->hdmarx->XferAbortCallback(huart->hdmarx); - } - } - else - { - /* Reset Rx transfer counter */ - huart->RxXferCount = 0U; - - /* Clear RxISR function pointer */ - huart->pRxBuffPtr = NULL; - - /* Clear the Error flags in the ICR register */ - __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); - - /* Discard the received data */ - __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); - - /* Restore huart->RxState to Ready */ - huart->RxState = HAL_UART_STATE_READY; - huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; - - /* As no DMA to be aborted, call directly user Abort complete callback */ -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /* Call registered Abort Receive Complete Callback */ - huart->AbortReceiveCpltCallback(huart); -#else - /* Call legacy weak Abort Receive Complete Callback */ - HAL_UART_AbortReceiveCpltCallback(huart); -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ - } - } - else - { - /* Reset Rx transfer counter */ - huart->RxXferCount = 0U; - - /* Clear RxISR function pointer */ - huart->pRxBuffPtr = NULL; - - /* Clear the Error flags in the ICR register */ - __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); - - /* Restore huart->RxState to Ready */ - huart->RxState = HAL_UART_STATE_READY; - huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; - - /* As no DMA to be aborted, call directly user Abort complete callback */ -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /* Call registered Abort Receive Complete Callback */ - huart->AbortReceiveCpltCallback(huart); -#else - /* Call legacy weak Abort Receive Complete Callback */ - HAL_UART_AbortReceiveCpltCallback(huart); -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ - } - - return HAL_OK; -} - -/** - * @brief Handle UART interrupt request. - * @param huart UART handle. - * @retval None - */ -void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) -{ - uint32_t isrflags = READ_REG(huart->Instance->ISR); - uint32_t cr1its = READ_REG(huart->Instance->CR1); - uint32_t cr3its = READ_REG(huart->Instance->CR3); - - uint32_t errorflags; - uint32_t errorcode; - - /* If no error occurs */ - errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF)); - if (errorflags == 0U) - { - /* UART in mode Receiver ---------------------------------------------------*/ - if (((isrflags & USART_ISR_RXNE) != 0U) - && ((cr1its & USART_CR1_RXNEIE) != 0U)) - { - if (huart->RxISR != NULL) - { - huart->RxISR(huart); - } - return; - } - } - - /* If some errors occur */ - if ((errorflags != 0U) - && (((cr3its & USART_CR3_EIE) != 0U) - || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_RTOIE)) != 0U))) - { - /* UART parity error interrupt occurred -------------------------------------*/ - if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U)) - { - __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF); - - huart->ErrorCode |= HAL_UART_ERROR_PE; - } - - /* UART frame error interrupt occurred --------------------------------------*/ - if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) - { - __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF); - - huart->ErrorCode |= HAL_UART_ERROR_FE; - } - - /* UART noise error interrupt occurred --------------------------------------*/ - if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) - { - __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF); - - huart->ErrorCode |= HAL_UART_ERROR_NE; - } - - /* UART Over-Run interrupt occurred -----------------------------------------*/ - if (((isrflags & USART_ISR_ORE) != 0U) - && (((cr1its & USART_CR1_RXNEIE) != 0U) || - ((cr3its & USART_CR3_EIE) != 0U))) - { - __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF); - - huart->ErrorCode |= HAL_UART_ERROR_ORE; - } - - /* UART Receiver Timeout interrupt occurred ---------------------------------*/ - if (((isrflags & USART_ISR_RTOF) != 0U) && ((cr1its & USART_CR1_RTOIE) != 0U)) - { - __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF); - - huart->ErrorCode |= HAL_UART_ERROR_RTO; - } - - /* Call UART Error Call back function if need be ----------------------------*/ - if (huart->ErrorCode != HAL_UART_ERROR_NONE) - { - /* UART in mode Receiver --------------------------------------------------*/ - if (((isrflags & USART_ISR_RXNE) != 0U) - && ((cr1its & USART_CR1_RXNEIE) != 0U)) - { - if (huart->RxISR != NULL) - { - huart->RxISR(huart); - } - } - - /* If Error is to be considered as blocking : - - Receiver Timeout error in Reception - - Overrun error in Reception - - any error occurs in DMA mode reception - */ - errorcode = huart->ErrorCode; - if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) || - ((errorcode & (HAL_UART_ERROR_RTO | HAL_UART_ERROR_ORE)) != 0U)) - { - /* Blocking error : transfer is aborted - Set the UART state ready to be able to start again the process, - Disable Rx Interrupts, and disable Rx DMA request, if ongoing */ - UART_EndRxTransfer(huart); - - /* Disable the UART DMA Rx request if enabled */ - if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) - { - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); - - /* Abort the UART DMA Rx channel */ - if (huart->hdmarx != NULL) - { - /* Set the UART DMA Abort callback : - will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */ - huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError; - - /* Abort DMA RX */ - if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) - { - /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */ - huart->hdmarx->XferAbortCallback(huart->hdmarx); - } - } - else - { - /* Call user error callback */ -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /*Call registered error callback*/ - huart->ErrorCallback(huart); -#else - /*Call legacy weak error callback*/ - HAL_UART_ErrorCallback(huart); -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ - - } - } - else - { - /* Call user error callback */ -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /*Call registered error callback*/ - huart->ErrorCallback(huart); -#else - /*Call legacy weak error callback*/ - HAL_UART_ErrorCallback(huart); -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ - } - } - else - { - /* Non Blocking error : transfer could go on. - Error is notified to user through user error callback */ -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /*Call registered error callback*/ - huart->ErrorCallback(huart); -#else - /*Call legacy weak error callback*/ - HAL_UART_ErrorCallback(huart); -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ - huart->ErrorCode = HAL_UART_ERROR_NONE; - } - } - return; - - } /* End if some error occurs */ - - /* Check current reception Mode : - If Reception till IDLE event has been selected : */ - if ( (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) - &&((isrflags & USART_ISR_IDLE) != 0U) - &&((cr1its & USART_ISR_IDLE) != 0U)) - { - __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); - - /* Check if DMA mode is enabled in UART */ - if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) - { - /* DMA mode enabled */ - /* Check received length : If all expected data are received, do nothing, - (DMA cplt callback will be called). - Otherwise, if at least one data has already been received, IDLE event is to be notified to user */ - uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(huart->hdmarx); - if ( (nb_remaining_rx_data > 0U) - &&(nb_remaining_rx_data < huart->RxXferSize)) - { - /* Reception is not complete */ - huart->RxXferCount = nb_remaining_rx_data; - - /* In Normal mode, end DMA xfer and HAL UART Rx process*/ - if (HAL_IS_BIT_CLR(huart->hdmarx->Instance->CCR, DMA_CCR_CIRC)) - { - /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ - CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); - CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); - - /* Disable the DMA transfer for the receiver request by resetting the DMAR bit - in the UART CR3 register */ - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); - - /* At end of Rx process, restore huart->RxState to Ready */ - huart->RxState = HAL_UART_STATE_READY; - huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; - - CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); - - /* Last bytes received, so no need as the abort is immediate */ - (void)HAL_DMA_Abort(huart->hdmarx); - } -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /*Call registered Rx Event callback*/ - huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); -#else - /*Call legacy weak Rx Event callback*/ - HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); -#endif - } - return; - } - else - { - /* DMA mode not enabled */ - /* Check received length : If all expected data are received, do nothing. - Otherwise, if at least one data has already been received, IDLE event is to be notified to user */ - uint16_t nb_rx_data = huart->RxXferSize - huart->RxXferCount; - if ( (huart->RxXferCount > 0U) - &&(nb_rx_data > 0U) ) - { - /* Disable the UART Parity Error Interrupt and RXNE interrupts */ - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); - - /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ - CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); - - /* Rx process is completed, restore huart->RxState to Ready */ - huart->RxState = HAL_UART_STATE_READY; - huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; - - /* Clear RxISR function pointer */ - huart->RxISR = NULL; - - CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /*Call registered Rx complete callback*/ - huart->RxEventCallback(huart, nb_rx_data); -#else - /*Call legacy weak Rx Event callback*/ - HAL_UARTEx_RxEventCallback(huart, nb_rx_data); -#endif - } - return; - } - } - - /* UART wakeup from Stop mode interrupt occurred ---------------------------*/ - if (((isrflags & USART_ISR_WUF) != 0U) && ((cr3its & USART_CR3_WUFIE) != 0U)) - { - __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_WUF); - - /* UART Rx state is not reset as a reception process might be ongoing. - If UART handle state fields need to be reset to READY, this could be done in Wakeup callback */ - -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /* Call registered Wakeup Callback */ - huart->WakeupCallback(huart); -#else - /* Call legacy weak Wakeup Callback */ - HAL_UARTEx_WakeupCallback(huart); -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ - return; - } - - /* UART in mode Transmitter ------------------------------------------------*/ - if (((isrflags & USART_ISR_TXE) != 0U) - && ((cr1its & USART_CR1_TXEIE) != 0U)) - { - if (huart->TxISR != NULL) - { - huart->TxISR(huart); - } - return; - } - - /* UART in mode Transmitter (transmission end) -----------------------------*/ - if (((isrflags & USART_ISR_TC) != 0U) && ((cr1its & USART_CR1_TCIE) != 0U)) - { - UART_EndTransmit_IT(huart); - return; - } - -} - -/** - * @brief Tx Transfer completed callback. - * @param huart UART handle. - * @retval None - */ -__weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(huart); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_UART_TxCpltCallback can be implemented in the user file. - */ -} - -/** - * @brief Tx Half Transfer completed callback. - * @param huart UART handle. - * @retval None - */ -__weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(huart); - - /* NOTE: This function should not be modified, when the callback is needed, - the HAL_UART_TxHalfCpltCallback can be implemented in the user file. - */ -} - -/** - * @brief Rx Transfer completed callback. - * @param huart UART handle. - * @retval None - */ -__weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(huart); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_UART_RxCpltCallback can be implemented in the user file. - */ -} - -/** - * @brief Rx Half Transfer completed callback. - * @param huart UART handle. - * @retval None - */ -__weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(huart); - - /* NOTE: This function should not be modified, when the callback is needed, - the HAL_UART_RxHalfCpltCallback can be implemented in the user file. - */ -} - -/** - * @brief UART error callback. - * @param huart UART handle. - * @retval None - */ -__weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(huart); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_UART_ErrorCallback can be implemented in the user file. - */ -} - -/** - * @brief UART Abort Complete callback. - * @param huart UART handle. - * @retval None - */ -__weak void HAL_UART_AbortCpltCallback(UART_HandleTypeDef *huart) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(huart); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_UART_AbortCpltCallback can be implemented in the user file. - */ -} - -/** - * @brief UART Abort Complete callback. - * @param huart UART handle. - * @retval None - */ -__weak void HAL_UART_AbortTransmitCpltCallback(UART_HandleTypeDef *huart) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(huart); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_UART_AbortTransmitCpltCallback can be implemented in the user file. - */ -} - -/** - * @brief UART Abort Receive Complete callback. - * @param huart UART handle. - * @retval None - */ -__weak void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(huart); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_UART_AbortReceiveCpltCallback can be implemented in the user file. - */ -} - -/** - * @brief Reception Event Callback (Rx event notification called after use of advanced reception service). - * @param huart UART handle - * @param Size Number of data available in application reception buffer (indicates a position in - * reception buffer until which, data are available) - * @retval None - */ -__weak void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(huart); - UNUSED(Size); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_UARTEx_RxEventCallback can be implemented in the user file. - */ -} - -/** - * @} - */ - -/** @defgroup UART_Exported_Functions_Group3 Peripheral Control functions - * @brief UART control functions - * -@verbatim - =============================================================================== - ##### Peripheral Control functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to control the UART. - (+) HAL_UART_ReceiverTimeout_Config() API allows to configure the receiver timeout value on the fly - (+) HAL_UART_EnableReceiverTimeout() API enables the receiver timeout feature - (+) HAL_UART_DisableReceiverTimeout() API disables the receiver timeout feature - (+) HAL_MultiProcessor_EnableMuteMode() API enables mute mode - (+) HAL_MultiProcessor_DisableMuteMode() API disables mute mode - (+) HAL_MultiProcessor_EnterMuteMode() API enters mute mode - (+) UART_SetConfig() API configures the UART peripheral - (+) UART_AdvFeatureConfig() API optionally configures the UART advanced features - (+) UART_CheckIdleState() API ensures that TEACK and/or REACK are set after initialization - (+) HAL_HalfDuplex_EnableTransmitter() API disables receiver and enables transmitter - (+) HAL_HalfDuplex_EnableReceiver() API disables transmitter and enables receiver - (+) HAL_LIN_SendBreak() API transmits the break characters -@endverbatim - * @{ - */ - -/** - * @brief Update on the fly the receiver timeout value in RTOR register. - * @param huart Pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART module. - * @param TimeoutValue receiver timeout value in number of baud blocks. The timeout - * value must be less or equal to 0x0FFFFFFFF. - * @retval None - */ -void HAL_UART_ReceiverTimeout_Config(UART_HandleTypeDef *huart, uint32_t TimeoutValue) -{ - if (!(IS_LPUART_INSTANCE(huart->Instance))) - { - assert_param(IS_UART_RECEIVER_TIMEOUT_VALUE(TimeoutValue)); - MODIFY_REG(huart->Instance->RTOR, USART_RTOR_RTO, TimeoutValue); - } -} - -/** - * @brief Enable the UART receiver timeout feature. - * @param huart Pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UART_EnableReceiverTimeout(UART_HandleTypeDef *huart) -{ - if (!(IS_LPUART_INSTANCE(huart->Instance))) - { - if (huart->gState == HAL_UART_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(huart); - - huart->gState = HAL_UART_STATE_BUSY; - - /* Set the USART RTOEN bit */ - SET_BIT(huart->Instance->CR2, USART_CR2_RTOEN); - - huart->gState = HAL_UART_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } - } - else - { - return HAL_ERROR; - } -} - -/** - * @brief Disable the UART receiver timeout feature. - * @param huart Pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UART_DisableReceiverTimeout(UART_HandleTypeDef *huart) -{ - if (!(IS_LPUART_INSTANCE(huart->Instance))) - { - if (huart->gState == HAL_UART_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(huart); - - huart->gState = HAL_UART_STATE_BUSY; - - /* Clear the USART RTOEN bit */ - CLEAR_BIT(huart->Instance->CR2, USART_CR2_RTOEN); - - huart->gState = HAL_UART_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } - } - else - { - return HAL_ERROR; - } -} - -/** - * @brief Enable UART in mute mode (does not mean UART enters mute mode; - * to enter mute mode, HAL_MultiProcessor_EnterMuteMode() API must be called). - * @param huart UART handle. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart) -{ - __HAL_LOCK(huart); - - huart->gState = HAL_UART_STATE_BUSY; - - /* Enable USART mute mode by setting the MME bit in the CR1 register */ - SET_BIT(huart->Instance->CR1, USART_CR1_MME); - - huart->gState = HAL_UART_STATE_READY; - - return (UART_CheckIdleState(huart)); -} - -/** - * @brief Disable UART mute mode (does not mean the UART actually exits mute mode - * as it may not have been in mute mode at this very moment). - * @param huart UART handle. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart) -{ - __HAL_LOCK(huart); - - huart->gState = HAL_UART_STATE_BUSY; - - /* Disable USART mute mode by clearing the MME bit in the CR1 register */ - CLEAR_BIT(huart->Instance->CR1, USART_CR1_MME); - - huart->gState = HAL_UART_STATE_READY; - - return (UART_CheckIdleState(huart)); -} - -/** - * @brief Enter UART mute mode (means UART actually enters mute mode). - * @note To exit from mute mode, HAL_MultiProcessor_DisableMuteMode() API must be called. - * @param huart UART handle. - * @retval None - */ -void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart) -{ - __HAL_UART_SEND_REQ(huart, UART_MUTE_MODE_REQUEST); -} - -/** - * @brief Enable the UART transmitter and disable the UART receiver. - * @param huart UART handle. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart) -{ - __HAL_LOCK(huart); - huart->gState = HAL_UART_STATE_BUSY; - - /* Clear TE and RE bits */ - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE)); - - /* Enable the USART's transmit interface by setting the TE bit in the USART CR1 register */ - SET_BIT(huart->Instance->CR1, USART_CR1_TE); - - huart->gState = HAL_UART_STATE_READY; - - __HAL_UNLOCK(huart); - - return HAL_OK; -} - -/** - * @brief Enable the UART receiver and disable the UART transmitter. - * @param huart UART handle. - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart) -{ - __HAL_LOCK(huart); - huart->gState = HAL_UART_STATE_BUSY; - - /* Clear TE and RE bits */ - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE)); - - /* Enable the USART's receive interface by setting the RE bit in the USART CR1 register */ - SET_BIT(huart->Instance->CR1, USART_CR1_RE); - - huart->gState = HAL_UART_STATE_READY; - - __HAL_UNLOCK(huart); - - return HAL_OK; -} - - -/** - * @brief Transmit break characters. - * @param huart UART handle. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart) -{ - /* Check the parameters */ - assert_param(IS_UART_LIN_INSTANCE(huart->Instance)); - - __HAL_LOCK(huart); - - huart->gState = HAL_UART_STATE_BUSY; - - /* Send break characters */ - __HAL_UART_SEND_REQ(huart, UART_SENDBREAK_REQUEST); - - huart->gState = HAL_UART_STATE_READY; - - __HAL_UNLOCK(huart); - - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup UART_Exported_Functions_Group4 Peripheral State and Error functions - * @brief UART Peripheral State functions - * -@verbatim - ============================================================================== - ##### Peripheral State and Error functions ##### - ============================================================================== - [..] - This subsection provides functions allowing to : - (+) Return the UART handle state. - (+) Return the UART handle error code - -@endverbatim - * @{ - */ - -/** - * @brief Return the UART handle state. - * @param huart Pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART. - * @retval HAL state - */ -HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart) -{ - uint32_t temp1; - uint32_t temp2; - temp1 = huart->gState; - temp2 = huart->RxState; - - return (HAL_UART_StateTypeDef)(temp1 | temp2); -} - -/** - * @brief Return the UART handle error code. - * @param huart Pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART. - * @retval UART Error Code - */ -uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart) -{ - return huart->ErrorCode; -} -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup UART_Private_Functions UART Private Functions - * @{ - */ - -/** - * @brief Initialize the callbacks to their default values. - * @param huart UART handle. - * @retval none - */ -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) -void UART_InitCallbacksToDefault(UART_HandleTypeDef *huart) -{ - /* Init the UART Callback settings */ - huart->TxHalfCpltCallback = HAL_UART_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ - huart->TxCpltCallback = HAL_UART_TxCpltCallback; /* Legacy weak TxCpltCallback */ - huart->RxHalfCpltCallback = HAL_UART_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ - huart->RxCpltCallback = HAL_UART_RxCpltCallback; /* Legacy weak RxCpltCallback */ - huart->ErrorCallback = HAL_UART_ErrorCallback; /* Legacy weak ErrorCallback */ - huart->AbortCpltCallback = HAL_UART_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ - huart->AbortTransmitCpltCallback = HAL_UART_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */ - huart->AbortReceiveCpltCallback = HAL_UART_AbortReceiveCpltCallback; /* Legacy weak AbortReceiveCpltCallback */ - huart->WakeupCallback = HAL_UARTEx_WakeupCallback; /* Legacy weak WakeupCallback */ - huart->RxEventCallback = HAL_UARTEx_RxEventCallback; /* Legacy weak RxEventCallback */ - -} -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ - -/** - * @brief Configure the UART peripheral. - * @param huart UART handle. - * @retval HAL status - */ -HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) -{ - uint32_t tmpreg; - uint16_t brrtemp; - UART_ClockSourceTypeDef clocksource; - uint32_t usartdiv; - HAL_StatusTypeDef ret = HAL_OK; - uint32_t pclk; - - /* Check the parameters */ - assert_param(IS_UART_BAUDRATE(huart->Init.BaudRate)); - assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength)); - if (UART_INSTANCE_LOWPOWER(huart)) - { - assert_param(IS_LPUART_STOPBITS(huart->Init.StopBits)); - } - else - { - assert_param(IS_UART_STOPBITS(huart->Init.StopBits)); - assert_param(IS_UART_ONE_BIT_SAMPLE(huart->Init.OneBitSampling)); - } - - assert_param(IS_UART_PARITY(huart->Init.Parity)); - assert_param(IS_UART_MODE(huart->Init.Mode)); - assert_param(IS_UART_HARDWARE_FLOW_CONTROL(huart->Init.HwFlowCtl)); - assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling)); - - /*-------------------------- USART CR1 Configuration -----------------------*/ - /* Clear M, PCE, PS, TE, RE and OVER8 bits and configure - * the UART Word Length, Parity, Mode and oversampling: - * set the M bits according to huart->Init.WordLength value - * set PCE and PS bits according to huart->Init.Parity value - * set TE and RE bits according to huart->Init.Mode value - * set OVER8 bit according to huart->Init.OverSampling value */ - tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ; - MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg); - - /*-------------------------- USART CR2 Configuration -----------------------*/ - /* Configure the UART Stop Bits: Set STOP[13:12] bits according - * to huart->Init.StopBits value */ - MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits); - - /*-------------------------- USART CR3 Configuration -----------------------*/ - /* Configure - * - UART HardWare Flow Control: set CTSE and RTSE bits according - * to huart->Init.HwFlowCtl value - * - one-bit sampling method versus three samples' majority rule according - * to huart->Init.OneBitSampling (not applicable to LPUART) */ - tmpreg = (uint32_t)huart->Init.HwFlowCtl; - - if (!(UART_INSTANCE_LOWPOWER(huart))) - { - tmpreg |= huart->Init.OneBitSampling; - } - MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg); - - - /*-------------------------- USART BRR Configuration -----------------------*/ - UART_GETCLOCKSOURCE(huart, clocksource); - - /* Check LPUART instance */ - if (UART_INSTANCE_LOWPOWER(huart)) - { - /* Retrieve frequency clock */ - switch (clocksource) - { - case UART_CLOCKSOURCE_PCLK1: - pclk = HAL_RCC_GetPCLK1Freq(); - break; - case UART_CLOCKSOURCE_HSI: - if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) - { - pclk = (uint32_t)(HSI_VALUE >> 2U); - } - else - { - pclk = (uint32_t) HSI_VALUE; - } - break; - case UART_CLOCKSOURCE_SYSCLK: - pclk = HAL_RCC_GetSysClockFreq(); - break; - case UART_CLOCKSOURCE_LSE: - pclk = (uint32_t) LSE_VALUE; - break; - default: - pclk = 0U; - ret = HAL_ERROR; - break; - } - - /* If proper clock source reported */ - if (pclk != 0U) - { - /* No Prescaler applicable */ - /* Ensure that Frequency clock is in the range [3 * baudrate, 4096 * baudrate] */ - if ((pclk < (3U * huart->Init.BaudRate)) || - (pclk > (4096U * huart->Init.BaudRate))) - { - ret = HAL_ERROR; - } - else - { - usartdiv = (uint32_t)(UART_DIV_LPUART(pclk, huart->Init.BaudRate)); - if ((usartdiv >= LPUART_BRR_MIN) && (usartdiv <= LPUART_BRR_MAX)) - { - huart->Instance->BRR = usartdiv; - } - else - { - ret = HAL_ERROR; - } - } /* if ( (pclk < (3 * huart->Init.BaudRate) ) || (pclk > (4096 * huart->Init.BaudRate) )) */ - } /* if (pclk != 0) */ - } - /* Check UART Over Sampling to set Baud Rate Register */ - else if (huart->Init.OverSampling == UART_OVERSAMPLING_8) - { - switch (clocksource) - { - case UART_CLOCKSOURCE_PCLK1: - pclk = HAL_RCC_GetPCLK1Freq(); - break; - case UART_CLOCKSOURCE_PCLK2: - pclk = HAL_RCC_GetPCLK2Freq(); - break; - case UART_CLOCKSOURCE_HSI: - if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) - { - pclk = (uint32_t)(HSI_VALUE >> 2U); - } - else - { - pclk = (uint32_t) HSI_VALUE; - } - break; - case UART_CLOCKSOURCE_SYSCLK: - pclk = HAL_RCC_GetSysClockFreq(); - break; - case UART_CLOCKSOURCE_LSE: - pclk = (uint32_t) LSE_VALUE; - break; - default: - pclk = 0U; - ret = HAL_ERROR; - break; - } - - /* USARTDIV must be greater than or equal to 0d16 */ - if (pclk != 0U) - { - usartdiv = (uint16_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate)); - if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) - { - brrtemp = (uint16_t)(usartdiv & 0xFFF0U); - brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U); - huart->Instance->BRR = brrtemp; - } - else - { - ret = HAL_ERROR; - } - } - } - else - { - switch (clocksource) - { - case UART_CLOCKSOURCE_PCLK1: - pclk = HAL_RCC_GetPCLK1Freq(); - break; - case UART_CLOCKSOURCE_PCLK2: - pclk = HAL_RCC_GetPCLK2Freq(); - break; - case UART_CLOCKSOURCE_HSI: - if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U) - { - pclk = (uint32_t)(HSI_VALUE >> 2U); - } - else - { - pclk = (uint32_t) HSI_VALUE; - } - break; - case UART_CLOCKSOURCE_SYSCLK: - pclk = HAL_RCC_GetSysClockFreq(); - break; - case UART_CLOCKSOURCE_LSE: - pclk = (uint32_t) LSE_VALUE; - break; - default: - pclk = 0U; - ret = HAL_ERROR; - break; - } - - if (pclk != 0U) - { - /* USARTDIV must be greater than or equal to 0d16 */ - usartdiv = (uint16_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate)); - if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) - { - huart->Instance->BRR = usartdiv; - } - else - { - ret = HAL_ERROR; - } - } - } - - - /* Clear ISR function pointers */ - huart->RxISR = NULL; - huart->TxISR = NULL; - - return ret; -} - -/** - * @brief Configure the UART peripheral advanced features. - * @param huart UART handle. - * @retval None - */ -void UART_AdvFeatureConfig(UART_HandleTypeDef *huart) -{ - /* Check whether the set of advanced features to configure is properly set */ - assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit)); - - /* if required, configure TX pin active level inversion */ - if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT)) - { - assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert)); - MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert); - } - - /* if required, configure RX pin active level inversion */ - if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT)) - { - assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert)); - MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert); - } - - /* if required, configure data inversion */ - if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT)) - { - assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert)); - MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert); - } - - /* if required, configure RX/TX pins swap */ - if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT)) - { - assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap)); - MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap); - } - - /* if required, configure RX overrun detection disabling */ - if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT)) - { - assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable)); - MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable); - } - - /* if required, configure DMA disabling on reception error */ - if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT)) - { - assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError)); - MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError); - } - - /* if required, configure auto Baud rate detection scheme */ - if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT)) - { - assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance)); - assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable)); - MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable); - /* set auto Baudrate detection parameters if detection is enabled */ - if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE) - { - assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode)); - MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode); - } - } - - /* if required, configure MSB first on communication line */ - if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT)) - { - assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst)); - MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst); - } -} - -/** - * @brief Check the UART Idle State. - * @param huart UART handle. - * @retval HAL status - */ -HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart) -{ - uint32_t tickstart; - - /* Initialize the UART ErrorCode */ - huart->ErrorCode = HAL_UART_ERROR_NONE; - - /* Init tickstart for timeout management */ - tickstart = HAL_GetTick(); - - /* Check if the Transmitter is enabled */ - if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE) - { - /* Wait until TEACK flag is set */ - if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) - { - /* Timeout occurred */ - return HAL_TIMEOUT; - } - } - - /* Check if the Receiver is enabled */ - if ((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE) - { - /* Wait until REACK flag is set */ - if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) - { - /* Timeout occurred */ - return HAL_TIMEOUT; - } - } - - /* Initialize the UART State */ - huart->gState = HAL_UART_STATE_READY; - huart->RxState = HAL_UART_STATE_READY; - huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; - - __HAL_UNLOCK(huart); - - return HAL_OK; -} - -/** - * @brief Handle UART Communication Timeout. - * @param huart UART handle. - * @param Flag Specifies the UART flag to check - * @param Status Flag status (SET or RESET) - * @param Tickstart Tick start value - * @param Timeout Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, - uint32_t Tickstart, uint32_t Timeout) -{ - /* Wait until flag is set */ - while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) - { - /* Check for the Timeout */ - if (Timeout != HAL_MAX_DELAY) - { - if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) - { - /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) - interrupts for the interrupt process */ - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE)); - CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); - - huart->gState = HAL_UART_STATE_READY; - huart->RxState = HAL_UART_STATE_READY; - - __HAL_UNLOCK(huart); - - return HAL_TIMEOUT; - } - - if (READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) - { - if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET) - { - /* Clear Receiver Timeout flag*/ - __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF); - - /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) - interrupts for the interrupt process */ - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE)); - CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); - - huart->gState = HAL_UART_STATE_READY; - huart->RxState = HAL_UART_STATE_READY; - huart->ErrorCode = HAL_UART_ERROR_RTO; - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - return HAL_TIMEOUT; - } - } - } - } - return HAL_OK; -} - -/** - * @brief Start Receive operation in interrupt mode. - * @note This function could be called by all HAL UART API providing reception in Interrupt mode. - * @note When calling this function, parameters validity is considered as already checked, - * i.e. Rx State, buffer address, ... - * UART Handle is assumed as Locked. - * @param huart UART handle. - * @param pData Pointer to data buffer (u8 or u16 data elements). - * @param Size Amount of data elements (u8 or u16) to be received. - * @retval HAL status - */ -HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) -{ - huart->pRxBuffPtr = pData; - huart->RxXferSize = Size; - huart->RxXferCount = Size; - huart->RxISR = NULL; - - /* Computation of UART mask to apply to RDR register */ - UART_MASK_COMPUTATION(huart); - - huart->ErrorCode = HAL_UART_ERROR_NONE; - huart->RxState = HAL_UART_STATE_BUSY_RX; - - /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ - SET_BIT(huart->Instance->CR3, USART_CR3_EIE); - - /* Set the Rx ISR function pointer according to the data word length */ - if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) - { - huart->RxISR = UART_RxISR_16BIT; - } - else - { - huart->RxISR = UART_RxISR_8BIT; - } - - __HAL_UNLOCK(huart); - - /* Enable the UART Parity Error interrupt and Data Register Not Empty interrupt */ - SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE); - return HAL_OK; -} - -/** - * @brief Start Receive operation in DMA mode. - * @note This function could be called by all HAL UART API providing reception in DMA mode. - * @note When calling this function, parameters validity is considered as already checked, - * i.e. Rx State, buffer address, ... - * UART Handle is assumed as Locked. - * @param huart UART handle. - * @param pData Pointer to data buffer (u8 or u16 data elements). - * @param Size Amount of data elements (u8 or u16) to be received. - * @retval HAL status - */ -HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) -{ - huart->pRxBuffPtr = pData; - huart->RxXferSize = Size; - - huart->ErrorCode = HAL_UART_ERROR_NONE; - huart->RxState = HAL_UART_STATE_BUSY_RX; - - if (huart->hdmarx != NULL) - { - /* Set the UART DMA transfer complete callback */ - huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt; - - /* Set the UART DMA Half transfer complete callback */ - huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt; - - /* Set the DMA error callback */ - huart->hdmarx->XferErrorCallback = UART_DMAError; - - /* Set the DMA abort callback */ - huart->hdmarx->XferAbortCallback = NULL; - - /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->RDR, (uint32_t)huart->pRxBuffPtr, Size) != HAL_OK) - { - /* Set error code to DMA */ - huart->ErrorCode = HAL_UART_ERROR_DMA; - - __HAL_UNLOCK(huart); - - /* Restore huart->gState to ready */ - huart->gState = HAL_UART_STATE_READY; - - return HAL_ERROR; - } - } - __HAL_UNLOCK(huart); - - /* Enable the UART Parity Error Interrupt */ - SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); - - /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ - SET_BIT(huart->Instance->CR3, USART_CR3_EIE); - - /* Enable the DMA transfer for the receiver request by setting the DMAR bit - in the UART CR3 register */ - SET_BIT(huart->Instance->CR3, USART_CR3_DMAR); - - return HAL_OK; -} - - -/** - * @brief End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion). - * @param huart UART handle. - * @retval None - */ -static void UART_EndTxTransfer(UART_HandleTypeDef *huart) -{ - /* Disable TXEIE and TCIE interrupts */ - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); - - /* At end of Tx process, restore huart->gState to Ready */ - huart->gState = HAL_UART_STATE_READY; -} - - -/** - * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion). - * @param huart UART handle. - * @retval None - */ -static void UART_EndRxTransfer(UART_HandleTypeDef *huart) -{ - /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); - CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); - - /* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */ - if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) - { - CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); - } - - /* At end of Rx process, restore huart->RxState to Ready */ - huart->RxState = HAL_UART_STATE_READY; - huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; - - /* Reset RxIsr function pointer */ - huart->RxISR = NULL; -} - - -/** - * @brief DMA UART transmit process complete callback. - * @param hdma DMA handle. - * @retval None - */ -static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma) -{ - UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); - - /* DMA Normal mode */ - if (HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC)) - { - huart->TxXferCount = 0U; - - /* Disable the DMA transfer for transmit request by resetting the DMAT bit - in the UART CR3 register */ - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); - - /* Enable the UART Transmit Complete Interrupt */ - SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); - } - /* DMA Circular mode */ - else - { -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /*Call registered Tx complete callback*/ - huart->TxCpltCallback(huart); -#else - /*Call legacy weak Tx complete callback*/ - HAL_UART_TxCpltCallback(huart); -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ - } -} - -/** - * @brief DMA UART transmit process half complete callback. - * @param hdma DMA handle. - * @retval None - */ -static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma) -{ - UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); - -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /*Call registered Tx Half complete callback*/ - huart->TxHalfCpltCallback(huart); -#else - /*Call legacy weak Tx Half complete callback*/ - HAL_UART_TxHalfCpltCallback(huart); -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ -} - -/** - * @brief DMA UART receive process complete callback. - * @param hdma DMA handle. - * @retval None - */ -static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) -{ - UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); - - /* DMA Normal mode */ - if (HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC)) - { - huart->RxXferCount = 0U; - - /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ - CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); - CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); - - /* Disable the DMA transfer for the receiver request by resetting the DMAR bit - in the UART CR3 register */ - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); - - /* At end of Rx process, restore huart->RxState to Ready */ - huart->RxState = HAL_UART_STATE_READY; - - /* If Reception till IDLE event has been selected, Disable IDLE Interrupt */ - if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) - { - CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); - } - } - - /* Check current reception Mode : - If Reception till IDLE event has been selected : use Rx Event callback */ - if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) - { -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /*Call registered Rx Event callback*/ - huart->RxEventCallback(huart, huart->RxXferSize); -#else - /*Call legacy weak Rx Event callback*/ - HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ - } - else - { - /* In other cases : use Rx Complete callback */ -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /*Call registered Rx complete callback*/ - huart->RxCpltCallback(huart); -#else - /*Call legacy weak Rx complete callback*/ - HAL_UART_RxCpltCallback(huart); -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ - } -} - -/** - * @brief DMA UART receive process half complete callback. - * @param hdma DMA handle. - * @retval None - */ -static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma) -{ - UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); - - /* Check current reception Mode : - If Reception till IDLE event has been selected : use Rx Event callback */ - if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) - { -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /*Call registered Rx Event callback*/ - huart->RxEventCallback(huart, huart->RxXferSize/2U); -#else - /*Call legacy weak Rx Event callback*/ - HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize/2U); -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ - } - else - { - /* In other cases : use Rx Half Complete callback */ -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /*Call registered Rx Half complete callback*/ - huart->RxHalfCpltCallback(huart); -#else - /*Call legacy weak Rx Half complete callback*/ - HAL_UART_RxHalfCpltCallback(huart); -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ - } -} - -/** - * @brief DMA UART communication error callback. - * @param hdma DMA handle. - * @retval None - */ -static void UART_DMAError(DMA_HandleTypeDef *hdma) -{ - UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); - - const HAL_UART_StateTypeDef gstate = huart->gState; - const HAL_UART_StateTypeDef rxstate = huart->RxState; - - /* Stop UART DMA Tx request if ongoing */ - if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) && - (gstate == HAL_UART_STATE_BUSY_TX)) - { - huart->TxXferCount = 0U; - UART_EndTxTransfer(huart); - } - - /* Stop UART DMA Rx request if ongoing */ - if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) && - (rxstate == HAL_UART_STATE_BUSY_RX)) - { - huart->RxXferCount = 0U; - UART_EndRxTransfer(huart); - } - - huart->ErrorCode |= HAL_UART_ERROR_DMA; - -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /*Call registered error callback*/ - huart->ErrorCallback(huart); -#else - /*Call legacy weak error callback*/ - HAL_UART_ErrorCallback(huart); -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ -} - -/** - * @brief DMA UART communication abort callback, when initiated by HAL services on Error - * (To be called at end of DMA Abort procedure following error occurrence). - * @param hdma DMA handle. - * @retval None - */ -static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma) -{ - UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); - huart->RxXferCount = 0U; - huart->TxXferCount = 0U; - -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /*Call registered error callback*/ - huart->ErrorCallback(huart); -#else - /*Call legacy weak error callback*/ - HAL_UART_ErrorCallback(huart); -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ -} - -/** - * @brief DMA UART Tx communication abort callback, when initiated by user - * (To be called at end of DMA Tx Abort procedure following user abort request). - * @note When this callback is executed, User Abort complete call back is called only if no - * Abort still ongoing for Rx DMA Handle. - * @param hdma DMA handle. - * @retval None - */ -static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma) -{ - UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); - - huart->hdmatx->XferAbortCallback = NULL; - - /* Check if an Abort process is still ongoing */ - if (huart->hdmarx != NULL) - { - if (huart->hdmarx->XferAbortCallback != NULL) - { - return; - } - } - - /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ - huart->TxXferCount = 0U; - huart->RxXferCount = 0U; - - /* Reset errorCode */ - huart->ErrorCode = HAL_UART_ERROR_NONE; - - /* Clear the Error flags in the ICR register */ - __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); - - - /* Restore huart->gState and huart->RxState to Ready */ - huart->gState = HAL_UART_STATE_READY; - huart->RxState = HAL_UART_STATE_READY; - huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; - - /* Call user Abort complete callback */ -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /* Call registered Abort complete callback */ - huart->AbortCpltCallback(huart); -#else - /* Call legacy weak Abort complete callback */ - HAL_UART_AbortCpltCallback(huart); -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ -} - - -/** - * @brief DMA UART Rx communication abort callback, when initiated by user - * (To be called at end of DMA Rx Abort procedure following user abort request). - * @note When this callback is executed, User Abort complete call back is called only if no - * Abort still ongoing for Tx DMA Handle. - * @param hdma DMA handle. - * @retval None - */ -static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma) -{ - UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); - - huart->hdmarx->XferAbortCallback = NULL; - - /* Check if an Abort process is still ongoing */ - if (huart->hdmatx != NULL) - { - if (huart->hdmatx->XferAbortCallback != NULL) - { - return; - } - } - - /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ - huart->TxXferCount = 0U; - huart->RxXferCount = 0U; - - /* Reset errorCode */ - huart->ErrorCode = HAL_UART_ERROR_NONE; - - /* Clear the Error flags in the ICR register */ - __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); - - /* Discard the received data */ - __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); - - /* Restore huart->gState and huart->RxState to Ready */ - huart->gState = HAL_UART_STATE_READY; - huart->RxState = HAL_UART_STATE_READY; - huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; - - /* Call user Abort complete callback */ -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /* Call registered Abort complete callback */ - huart->AbortCpltCallback(huart); -#else - /* Call legacy weak Abort complete callback */ - HAL_UART_AbortCpltCallback(huart); -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ -} - - -/** - * @brief DMA UART Tx communication abort callback, when initiated by user by a call to - * HAL_UART_AbortTransmit_IT API (Abort only Tx transfer) - * (This callback is executed at end of DMA Tx Abort procedure following user abort request, - * and leads to user Tx Abort Complete callback execution). - * @param hdma DMA handle. - * @retval None - */ -static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma) -{ - UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); - - huart->TxXferCount = 0U; - - - /* Restore huart->gState to Ready */ - huart->gState = HAL_UART_STATE_READY; - - /* Call user Abort complete callback */ -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /* Call registered Abort Transmit Complete Callback */ - huart->AbortTransmitCpltCallback(huart); -#else - /* Call legacy weak Abort Transmit Complete Callback */ - HAL_UART_AbortTransmitCpltCallback(huart); -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ -} - -/** - * @brief DMA UART Rx communication abort callback, when initiated by user by a call to - * HAL_UART_AbortReceive_IT API (Abort only Rx transfer) - * (This callback is executed at end of DMA Rx Abort procedure following user abort request, - * and leads to user Rx Abort Complete callback execution). - * @param hdma DMA handle. - * @retval None - */ -static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma) -{ - UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - - huart->RxXferCount = 0U; - - /* Clear the Error flags in the ICR register */ - __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); - - /* Discard the received data */ - __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); - - /* Restore huart->RxState to Ready */ - huart->RxState = HAL_UART_STATE_READY; - huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; - - /* Call user Abort complete callback */ -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /* Call registered Abort Receive Complete Callback */ - huart->AbortReceiveCpltCallback(huart); -#else - /* Call legacy weak Abort Receive Complete Callback */ - HAL_UART_AbortReceiveCpltCallback(huart); -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ -} - -/** - * @brief TX interrupt handler for 7 or 8 bits data word length . - * @note Function is called under interruption only, once - * interruptions have been enabled by HAL_UART_Transmit_IT(). - * @param huart UART handle. - * @retval None - */ -static void UART_TxISR_8BIT(UART_HandleTypeDef *huart) -{ - /* Check that a Tx process is ongoing */ - if (huart->gState == HAL_UART_STATE_BUSY_TX) - { - if (huart->TxXferCount == 0U) - { - /* Disable the UART Transmit Data Register Empty Interrupt */ - CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE); - - /* Enable the UART Transmit Complete Interrupt */ - SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); - } - else - { - huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr & (uint8_t)0xFF); - huart->pTxBuffPtr++; - huart->TxXferCount--; - } - } -} - -/** - * @brief TX interrupt handler for 9 bits data word length. - * @note Function is called under interruption only, once - * interruptions have been enabled by HAL_UART_Transmit_IT(). - * @param huart UART handle. - * @retval None - */ -static void UART_TxISR_16BIT(UART_HandleTypeDef *huart) -{ - uint16_t *tmp; - - /* Check that a Tx process is ongoing */ - if (huart->gState == HAL_UART_STATE_BUSY_TX) - { - if (huart->TxXferCount == 0U) - { - /* Disable the UART Transmit Data Register Empty Interrupt */ - CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE); - - /* Enable the UART Transmit Complete Interrupt */ - SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); - } - else - { - tmp = (uint16_t *) huart->pTxBuffPtr; - huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL); - huart->pTxBuffPtr += 2U; - huart->TxXferCount--; - } - } -} - - -/** - * @brief Wrap up transmission in non-blocking mode. - * @param huart pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART module. - * @retval None - */ -static void UART_EndTransmit_IT(UART_HandleTypeDef *huart) -{ - /* Disable the UART Transmit Complete Interrupt */ - CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE); - - /* Tx process is ended, restore huart->gState to Ready */ - huart->gState = HAL_UART_STATE_READY; - - /* Cleat TxISR function pointer */ - huart->TxISR = NULL; - -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /*Call registered Tx complete callback*/ - huart->TxCpltCallback(huart); -#else - /*Call legacy weak Tx complete callback*/ - HAL_UART_TxCpltCallback(huart); -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ -} - -/** - * @brief RX interrupt handler for 7 or 8 bits data word length . - * @param huart UART handle. - * @retval None - */ -static void UART_RxISR_8BIT(UART_HandleTypeDef *huart) -{ - uint16_t uhMask = huart->Mask; - uint16_t uhdata; - - /* Check that a Rx process is ongoing */ - if (huart->RxState == HAL_UART_STATE_BUSY_RX) - { - uhdata = (uint16_t) READ_REG(huart->Instance->RDR); - *huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask); - huart->pRxBuffPtr++; - huart->RxXferCount--; - - if (huart->RxXferCount == 0U) - { - /* Disable the UART Parity Error Interrupt and RXNE interrupts */ - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); - - /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ - CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); - - /* Rx process is completed, restore huart->RxState to Ready */ - huart->RxState = HAL_UART_STATE_READY; - - /* Clear RxISR function pointer */ - huart->RxISR = NULL; - - /* Check current reception Mode : - If Reception till IDLE event has been selected : */ - if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) - { - /* Disable IDLE interrupt */ - CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); - -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /*Call registered Rx Event callback*/ - huart->RxEventCallback(huart, huart->RxXferSize); -#else - /*Call legacy weak Rx Event callback*/ - HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); -#endif - } - else - { - /* Standard reception API called */ -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /*Call registered Rx complete callback*/ - huart->RxCpltCallback(huart); -#else - /*Call legacy weak Rx complete callback*/ - HAL_UART_RxCpltCallback(huart); -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ - } - huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; - } - } - else - { - /* Clear RXNE interrupt flag */ - __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); - } -} - -/** - * @brief RX interrupt handler for 9 bits data word length . - * @note Function is called under interruption only, once - * interruptions have been enabled by HAL_UART_Receive_IT() - * @param huart UART handle. - * @retval None - */ -static void UART_RxISR_16BIT(UART_HandleTypeDef *huart) -{ - uint16_t *tmp; - uint16_t uhMask = huart->Mask; - uint16_t uhdata; - - /* Check that a Rx process is ongoing */ - if (huart->RxState == HAL_UART_STATE_BUSY_RX) - { - uhdata = (uint16_t) READ_REG(huart->Instance->RDR); - tmp = (uint16_t *) huart->pRxBuffPtr ; - *tmp = (uint16_t)(uhdata & uhMask); - huart->pRxBuffPtr += 2U; - huart->RxXferCount--; - - if (huart->RxXferCount == 0U) - { - /* Disable the UART Parity Error Interrupt and RXNE interrupt*/ - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); - - /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ - CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); - - /* Rx process is completed, restore huart->RxState to Ready */ - huart->RxState = HAL_UART_STATE_READY; - - /* Clear RxISR function pointer */ - huart->RxISR = NULL; - - /* Check current reception Mode : - If Reception till IDLE event has been selected : */ - if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) - { - /* Disable IDLE interrupt */ - CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); - -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /*Call registered Rx Event callback*/ - huart->RxEventCallback(huart, huart->RxXferSize); -#else - /*Call legacy weak Rx Event callback*/ - HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); -#endif - } - else - { - /* Standard reception API called */ -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /*Call registered Rx complete callback*/ - huart->RxCpltCallback(huart); -#else - /*Call legacy weak Rx complete callback*/ - HAL_UART_RxCpltCallback(huart); -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ - } - huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; - } - } - else - { - /* Clear RXNE interrupt flag */ - __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); - } -} - - -/** - * @} - */ - -#endif /* HAL_UART_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/fw/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c b/fw/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c deleted file mode 100644 index 085701a..0000000 --- a/fw/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.c +++ /dev/null @@ -1,834 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l0xx_hal_uart_ex.c - * @author MCD Application Team - * @brief Extended UART HAL module driver. - * This file provides firmware functions to manage the following extended - * functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART). - * + Initialization and de-initialization functions - * + Peripheral Control functions - * - * - @verbatim - ============================================================================== - ##### UART peripheral extended features ##### - ============================================================================== - - (#) Declare a UART_HandleTypeDef handle structure. - - (#) For the UART RS485 Driver Enable mode, initialize the UART registers - by calling the HAL_RS485Ex_Init() API. - - @endverbatim - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l0xx_hal.h" - -/** @addtogroup STM32L0xx_HAL_Driver - * @{ - */ - -/** @defgroup UARTEx UARTEx - * @brief UART Extended HAL module driver - * @{ - */ - -#ifdef HAL_UART_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -/* Private macros ------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/** @defgroup UARTEx_Private_Functions UARTEx Private Functions - * @{ - */ -static void UARTEx_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection); -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ - -/** @defgroup UARTEx_Exported_Functions UARTEx Exported Functions - * @{ - */ - -/** @defgroup UARTEx_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Extended Initialization and Configuration Functions - * -@verbatim -=============================================================================== - ##### Initialization and Configuration functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to initialize the USARTx or the UARTy - in asynchronous mode. - (+) For the asynchronous mode the parameters below can be configured: - (++) Baud Rate - (++) Word Length - (++) Stop Bit - (++) Parity: If the parity is enabled, then the MSB bit of the data written - in the data register is transmitted but is changed by the parity bit. - (++) Hardware flow control - (++) Receiver/transmitter modes - (++) Over Sampling Method - (++) One-Bit Sampling Method - (+) For the asynchronous mode, the following advanced features can be configured as well: - (++) TX and/or RX pin level inversion - (++) data logical level inversion - (++) RX and TX pins swap - (++) RX overrun detection disabling - (++) DMA disabling on RX error - (++) MSB first on communication line - (++) auto Baud rate detection - [..] - The HAL_RS485Ex_Init() API follows the UART RS485 mode configuration - procedures (details for the procedures are available in reference manual). - -@endverbatim - - Depending on the frame length defined by the M1 and M0 bits (7-bit, - 8-bit or 9-bit), the possible UART formats are listed in the - following table. - - Table 1. UART frame format. - +-----------------------------------------------------------------------+ - | M1 bit | M0 bit | PCE bit | UART frame | - |---------|---------|-----------|---------------------------------------| - | 0 | 0 | 0 | | SB | 8 bit data | STB | | - |---------|---------|-----------|---------------------------------------| - | 0 | 0 | 1 | | SB | 7 bit data | PB | STB | | - |---------|---------|-----------|---------------------------------------| - | 0 | 1 | 0 | | SB | 9 bit data | STB | | - |---------|---------|-----------|---------------------------------------| - | 0 | 1 | 1 | | SB | 8 bit data | PB | STB | | - |---------|---------|-----------|---------------------------------------| - | 1 | 0 | 0 | | SB | 7 bit data | STB | | - |---------|---------|-----------|---------------------------------------| - | 1 | 0 | 1 | | SB | 6 bit data | PB | STB | | - +-----------------------------------------------------------------------+ - - * @{ - */ - -/** - * @brief Initialize the RS485 Driver enable feature according to the specified - * parameters in the UART_InitTypeDef and creates the associated handle. - * @param huart UART handle. - * @param Polarity Select the driver enable polarity. - * This parameter can be one of the following values: - * @arg @ref UART_DE_POLARITY_HIGH DE signal is active high - * @arg @ref UART_DE_POLARITY_LOW DE signal is active low - * @param AssertionTime Driver Enable assertion time: - * 5-bit value defining the time between the activation of the DE (Driver Enable) - * signal and the beginning of the start bit. It is expressed in sample time - * units (1/8 or 1/16 bit time, depending on the oversampling rate) - * @param DeassertionTime Driver Enable deassertion time: - * 5-bit value defining the time between the end of the last stop bit, in a - * transmitted message, and the de-activation of the DE (Driver Enable) signal. - * It is expressed in sample time units (1/8 or 1/16 bit time, depending on the - * oversampling rate). - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, - uint32_t DeassertionTime) -{ - uint32_t temp; - - /* Check the UART handle allocation */ - if (huart == NULL) - { - return HAL_ERROR; - } - /* Check the Driver Enable UART instance */ - assert_param(IS_UART_DRIVER_ENABLE_INSTANCE(huart->Instance)); - - /* Check the Driver Enable polarity */ - assert_param(IS_UART_DE_POLARITY(Polarity)); - - /* Check the Driver Enable assertion time */ - assert_param(IS_UART_ASSERTIONTIME(AssertionTime)); - - /* Check the Driver Enable deassertion time */ - assert_param(IS_UART_DEASSERTIONTIME(DeassertionTime)); - - if (huart->gState == HAL_UART_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - huart->Lock = HAL_UNLOCKED; - -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - UART_InitCallbacksToDefault(huart); - - if (huart->MspInitCallback == NULL) - { - huart->MspInitCallback = HAL_UART_MspInit; - } - - /* Init the low level hardware */ - huart->MspInitCallback(huart); -#else - /* Init the low level hardware : GPIO, CLOCK, CORTEX */ - HAL_UART_MspInit(huart); -#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ - } - - huart->gState = HAL_UART_STATE_BUSY; - - /* Disable the Peripheral */ - __HAL_UART_DISABLE(huart); - - /* Set the UART Communication parameters */ - if (UART_SetConfig(huart) == HAL_ERROR) - { - return HAL_ERROR; - } - - if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) - { - UART_AdvFeatureConfig(huart); - } - - /* Enable the Driver Enable mode by setting the DEM bit in the CR3 register */ - SET_BIT(huart->Instance->CR3, USART_CR3_DEM); - - /* Set the Driver Enable polarity */ - MODIFY_REG(huart->Instance->CR3, USART_CR3_DEP, Polarity); - - /* Set the Driver Enable assertion and deassertion times */ - temp = (AssertionTime << UART_CR1_DEAT_ADDRESS_LSB_POS); - temp |= (DeassertionTime << UART_CR1_DEDT_ADDRESS_LSB_POS); - MODIFY_REG(huart->Instance->CR1, (USART_CR1_DEDT | USART_CR1_DEAT), temp); - - /* Enable the Peripheral */ - __HAL_UART_ENABLE(huart); - - /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ - return (UART_CheckIdleState(huart)); -} - -/** - * @} - */ - -/** @defgroup UARTEx_Exported_Functions_Group2 IO operation functions - * @brief Extended functions - * -@verbatim - =============================================================================== - ##### IO operation functions ##### - =============================================================================== - This subsection provides a set of Wakeup and FIFO mode related callback functions. - - (#) Wakeup from Stop mode Callback: - (+) HAL_UARTEx_WakeupCallback() - -@endverbatim - * @{ - */ - -/** - * @brief UART wakeup from Stop mode callback. - * @param huart UART handle. - * @retval None - */ -__weak void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(huart); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_UARTEx_WakeupCallback can be implemented in the user file. - */ -} - - -/** - * @} - */ - -/** @defgroup UARTEx_Exported_Functions_Group3 Peripheral Control functions - * @brief Extended Peripheral Control functions - * -@verbatim - =============================================================================== - ##### Peripheral Control functions ##### - =============================================================================== - [..] This section provides the following functions: - (+) HAL_UARTEx_EnableClockStopMode() API enables the UART clock (HSI or LSE only) during stop mode - (+) HAL_UARTEx_DisableClockStopMode() API disables the above functionality - (+) HAL_MultiProcessorEx_AddressLength_Set() API optionally sets the UART node address - detection length to more than 4 bits for multiprocessor address mark wake up. - (+) HAL_UARTEx_StopModeWakeUpSourceConfig() API defines the wake-up from stop mode - trigger: address match, Start Bit detection or RXNE bit status. - (+) HAL_UARTEx_EnableStopMode() API enables the UART to wake up the MCU from stop mode - (+) HAL_UARTEx_DisableStopMode() API disables the above functionality - - [..] This subsection also provides a set of additional functions providing enhanced reception - services to user. (For example, these functions allow application to handle use cases - where number of data to be received is unknown). - - (#) Compared to standard reception services which only consider number of received - data elements as reception completion criteria, these functions also consider additional events - as triggers for updating reception status to caller : - (+) Detection of inactivity period (RX line has not been active for a given period). - (++) RX inactivity detected by IDLE event, i.e. RX line has been in idle state (normally high state) - for 1 frame time, after last received byte. - (++) RX inactivity detected by RTO, i.e. line has been in idle state - for a programmable time, after last received byte. - (+) Detection that a specific character has been received. - - (#) There are two mode of transfer: - (+) Blocking mode: The reception is performed in polling mode, until either expected number of data is received, - or till IDLE event occurs. Reception is handled only during function execution. - When function exits, no data reception could occur. HAL status and number of actually received data elements, - are returned by function after finishing transfer. - (+) Non-Blocking mode: The reception is performed using Interrupts or DMA. - These API's return the HAL status. - The end of the data processing will be indicated through the - dedicated UART IRQ when using Interrupt mode or the DMA IRQ when using DMA mode. - The HAL_UARTEx_RxEventCallback() user callback will be executed during Receive process - The HAL_UART_ErrorCallback()user callback will be executed when a reception error is detected. - - (#) Blocking mode API: - (+) HAL_UARTEx_ReceiveToIdle() - - (#) Non-Blocking mode API with Interrupt: - (+) HAL_UARTEx_ReceiveToIdle_IT() - - (#) Non-Blocking mode API with DMA: - (+) HAL_UARTEx_ReceiveToIdle_DMA() - -@endverbatim - * @{ - */ - -/** - * @brief Keep UART Clock enabled when in Stop Mode. - * @note When the USART clock source is configured to be LSE or HSI, it is possible to keep enabled - * this clock during STOP mode by setting the UCESM bit in USART_CR3 control register. - * @note When LPUART is used to wakeup from stop with LSE is selected as LPUART clock source, - * and desired baud rate is 9600 baud, the bit UCESM bit in LPUART_CR3 control register must be set. - * @param huart UART handle. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UARTEx_EnableClockStopMode(UART_HandleTypeDef *huart) -{ - /* Process Locked */ - __HAL_LOCK(huart); - - /* Set UCESM bit */ - SET_BIT(huart->Instance->CR3, USART_CR3_UCESM); - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - return HAL_OK; -} - -/** - * @brief Disable UART Clock when in Stop Mode. - * @param huart UART handle. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UARTEx_DisableClockStopMode(UART_HandleTypeDef *huart) -{ - /* Process Locked */ - __HAL_LOCK(huart); - - /* Clear UCESM bit */ - CLEAR_BIT(huart->Instance->CR3, USART_CR3_UCESM); - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - return HAL_OK; -} - -/** - * @brief By default in multiprocessor mode, when the wake up method is set - * to address mark, the UART handles only 4-bit long addresses detection; - * this API allows to enable longer addresses detection (6-, 7- or 8-bit - * long). - * @note Addresses detection lengths are: 6-bit address detection in 7-bit data mode, - * 7-bit address detection in 8-bit data mode, 8-bit address detection in 9-bit data mode. - * @param huart UART handle. - * @param AddressLength This parameter can be one of the following values: - * @arg @ref UART_ADDRESS_DETECT_4B 4-bit long address - * @arg @ref UART_ADDRESS_DETECT_7B 6-, 7- or 8-bit long address - * @retval HAL status - */ -HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength) -{ - /* Check the UART handle allocation */ - if (huart == NULL) - { - return HAL_ERROR; - } - - /* Check the address length parameter */ - assert_param(IS_UART_ADDRESSLENGTH_DETECT(AddressLength)); - - huart->gState = HAL_UART_STATE_BUSY; - - /* Disable the Peripheral */ - __HAL_UART_DISABLE(huart); - - /* Set the address length */ - MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, AddressLength); - - /* Enable the Peripheral */ - __HAL_UART_ENABLE(huart); - - /* TEACK and/or REACK to check before moving huart->gState to Ready */ - return (UART_CheckIdleState(huart)); -} - -/** - * @brief Set Wakeup from Stop mode interrupt flag selection. - * @note It is the application responsibility to enable the interrupt used as - * usart_wkup interrupt source before entering low-power mode. - * @param huart UART handle. - * @param WakeUpSelection Address match, Start Bit detection or RXNE/RXFNE bit status. - * This parameter can be one of the following values: - * @arg @ref UART_WAKEUP_ON_ADDRESS - * @arg @ref UART_WAKEUP_ON_STARTBIT - * @arg @ref UART_WAKEUP_ON_READDATA_NONEMPTY - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection) -{ - HAL_StatusTypeDef status = HAL_OK; - uint32_t tickstart; - - /* check the wake-up from stop mode UART instance */ - assert_param(IS_UART_WAKEUP_FROMSTOP_INSTANCE(huart->Instance)); - /* check the wake-up selection parameter */ - assert_param(IS_UART_WAKEUP_SELECTION(WakeUpSelection.WakeUpEvent)); - - /* Process Locked */ - __HAL_LOCK(huart); - - huart->gState = HAL_UART_STATE_BUSY; - - /* Disable the Peripheral */ - __HAL_UART_DISABLE(huart); - - /* Set the wake-up selection scheme */ - MODIFY_REG(huart->Instance->CR3, USART_CR3_WUS, WakeUpSelection.WakeUpEvent); - - if (WakeUpSelection.WakeUpEvent == UART_WAKEUP_ON_ADDRESS) - { - UARTEx_Wakeup_AddressConfig(huart, WakeUpSelection); - } - - /* Enable the Peripheral */ - __HAL_UART_ENABLE(huart); - - /* Init tickstart for timeout management */ - tickstart = HAL_GetTick(); - - /* Wait until REACK flag is set */ - if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) - { - status = HAL_TIMEOUT; - } - else - { - /* Initialize the UART State */ - huart->gState = HAL_UART_STATE_READY; - } - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - return status; -} - -/** - * @brief Enable UART Stop Mode. - * @note The UART is able to wake up the MCU from Stop 1 mode as long as UART clock is HSI or LSE. - * @param huart UART handle. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart) -{ - /* Process Locked */ - __HAL_LOCK(huart); - - /* Set UESM bit */ - SET_BIT(huart->Instance->CR1, USART_CR1_UESM); - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - return HAL_OK; -} - -/** - * @brief Disable UART Stop Mode. - * @param huart UART handle. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart) -{ - /* Process Locked */ - __HAL_LOCK(huart); - - /* Clear UESM bit */ - CLEAR_BIT(huart->Instance->CR1, USART_CR1_UESM); - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - return HAL_OK; -} - -/** - * @brief Receive an amount of data in blocking mode till either the expected number of data is received or an IDLE event occurs. - * @note HAL_OK is returned if reception is completed (expected number of data has been received) - * or if reception is stopped after IDLE event (less than the expected number of data has been received) - * In this case, RxLen output parameter indicates number of data available in reception buffer. - * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), - * the received data is handled as a set of uint16_t. In this case, Size must indicate the number - * of uint16_t available through pData. - * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), - * address of user data buffer for storing data to be received, should be aligned on a half word frontier (16 bits) - * (as received data will be handled using uint16_t pointer cast). Depending on compilation chain, - * use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pData. - * @param huart UART handle. - * @param pData Pointer to data buffer (uint8_t or uint16_t data elements). - * @param Size Amount of data elements (uint8_t or uint16_t) to be received. - * @param RxLen Number of data elements finally received (could be lower than Size, in case reception ends on IDLE event) - * @param Timeout Timeout duration expressed in ms (covers the whole reception sequence). - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint16_t *RxLen, uint32_t Timeout) -{ - uint8_t *pdata8bits; - uint16_t *pdata16bits; - uint16_t uhMask; - uint32_t tickstart; - - /* Check that a Rx process is not already ongoing */ - if (huart->RxState == HAL_UART_STATE_READY) - { - if ((pData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - - /* In case of 9bits/No Parity transfer, pData buffer provided as input parameter - should be aligned on a uint16_t frontier, as data to be received from RDR will be - handled through a uint16_t cast. */ - if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) - { - if ((((uint32_t)pData) & 1U) != 0U) - { - return HAL_ERROR; - } - } - - __HAL_LOCK(huart); - - huart->ErrorCode = HAL_UART_ERROR_NONE; - huart->RxState = HAL_UART_STATE_BUSY_RX; - huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; - - /* Init tickstart for timeout management */ - tickstart = HAL_GetTick(); - - huart->RxXferSize = Size; - huart->RxXferCount = Size; - - /* Computation of UART mask to apply to RDR register */ - UART_MASK_COMPUTATION(huart); - uhMask = huart->Mask; - - /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */ - if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) - { - pdata8bits = NULL; - pdata16bits = (uint16_t *) pData; - } - else - { - pdata8bits = pData; - pdata16bits = NULL; - } - - __HAL_UNLOCK(huart); - - /* Initialize output number of received elements */ - *RxLen = 0U; - - /* as long as data have to be received */ - while (huart->RxXferCount > 0U) - { - /* Check if IDLE flag is set */ - if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE)) - { - /* Clear IDLE flag in ISR */ - __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); - - /* If Set, but no data ever received, clear flag without exiting loop */ - /* If Set, and data has already been received, this means Idle Event is valid : End reception */ - if (*RxLen > 0U) - { - huart->RxState = HAL_UART_STATE_READY; - - return HAL_OK; - } - } - - /* Check if RXNE flag is set */ - if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RXNE)) - { - if (pdata8bits == NULL) - { - *pdata16bits = (uint16_t)(huart->Instance->RDR & uhMask); - pdata16bits++; - } - else - { - *pdata8bits = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask); - pdata8bits++; - } - /* Increment number of received elements */ - *RxLen += 1U; - huart->RxXferCount--; - } - - /* Check for the Timeout */ - if (Timeout != HAL_MAX_DELAY) - { - if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) - { - huart->RxState = HAL_UART_STATE_READY; - - return HAL_TIMEOUT; - } - } - } - - /* Set number of received elements in output parameter : RxLen */ - *RxLen = huart->RxXferSize - huart->RxXferCount; - /* At end of Rx process, restore huart->RxState to Ready */ - huart->RxState = HAL_UART_STATE_READY; - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Receive an amount of data in interrupt mode till either the expected number of data is received or an IDLE event occurs. - * @note Reception is initiated by this function call. Further progress of reception is achieved thanks - * to UART interrupts raised by RXNE and IDLE events. Callback is called at end of reception indicating - * number of received data elements. - * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), - * the received data is handled as a set of uint16_t. In this case, Size must indicate the number - * of uint16_t available through pData. - * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), - * address of user data buffer for storing data to be received, should be aligned on a half word frontier (16 bits) - * (as received data will be handled using uint16_t pointer cast). Depending on compilation chain, - * use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pData. - * @param huart UART handle. - * @param pData Pointer to data buffer (uint8_t or uint16_t data elements). - * @param Size Amount of data elements (uint8_t or uint16_t) to be received. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) -{ - HAL_StatusTypeDef status; - - /* Check that a Rx process is not already ongoing */ - if (huart->RxState == HAL_UART_STATE_READY) - { - if ((pData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - - /* In case of 9bits/No Parity transfer, pData buffer provided as input parameter - should be aligned on a uint16_t frontier, as data to be received from RDR will be - handled through a uint16_t cast. */ - if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) - { - if ((((uint32_t)pData) & 1U) != 0U) - { - return HAL_ERROR; - } - } - - __HAL_LOCK(huart); - - /* Set Reception type to reception till IDLE Event*/ - huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; - - status = UART_Start_Receive_IT(huart, pData, Size); - - /* Check Rx process has been successfully started */ - if (status == HAL_OK) - { - if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) - { - __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); - SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); - } - else - { - /* In case of errors already pending when reception is started, - Interrupts may have already been raised and lead to reception abortion. - (Overrun error for instance). - In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */ - status = HAL_ERROR; - } - } - - return status; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Receive an amount of data in DMA mode till either the expected number of data is received or an IDLE event occurs. - * @note Reception is initiated by this function call. Further progress of reception is achieved thanks - * to DMA services, transferring automatically received data elements in user reception buffer and - * calling registered callbacks at half/end of reception. UART IDLE events are also used to consider - * reception phase as ended. In all cases, callback execution will indicate number of received data elements. - * @note When the UART parity is enabled (PCE = 1), the received data contain - * the parity bit (MSB position). - * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), - * the received data is handled as a set of uint16_t. In this case, Size must indicate the number - * of uint16_t available through pData. - * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), - * address of user data buffer for storing data to be received, should be aligned on a half word frontier (16 bits) - * (as received data will be handled by DMA from halfword frontier). Depending on compilation chain, - * use of specific alignment compilation directives or pragmas might be required to ensure proper alignment for pData. - * @param huart UART handle. - * @param pData Pointer to data buffer (uint8_t or uint16_t data elements). - * @param Size Amount of data elements (uint8_t or uint16_t) to be received. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) -{ - HAL_StatusTypeDef status; - - /* Check that a Rx process is not already ongoing */ - if (huart->RxState == HAL_UART_STATE_READY) - { - if ((pData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - - /* In case of 9bits/No Parity transfer, pData buffer provided as input parameter - should be aligned on a uint16_t frontier, as data copy from RDR will be - handled by DMA from a uint16_t frontier. */ - if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) - { - if ((((uint32_t)pData) & 1U) != 0U) - { - return HAL_ERROR; - } - } - - __HAL_LOCK(huart); - - /* Set Reception type to reception till IDLE Event*/ - huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; - - status = UART_Start_Receive_DMA(huart, pData, Size); - - /* Check Rx process has been successfully started */ - if (status == HAL_OK) - { - if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) - { - __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); - SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); - } - else - { - /* In case of errors already pending when reception is started, - Interrupts may have already been raised and lead to reception abortion. - (Overrun error for instance). - In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */ - status = HAL_ERROR; - } - } - - return status; - } - else - { - return HAL_BUSY; - } -} - -/** - * @} - */ - -/** - * @} - */ - -/** @addtogroup UARTEx_Private_Functions - * @{ - */ - -/** - * @brief Initialize the UART wake-up from stop mode parameters when triggered by address detection. - * @param huart UART handle. - * @param WakeUpSelection UART wake up from stop mode parameters. - * @retval None - */ -static void UARTEx_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection) -{ - assert_param(IS_UART_ADDRESSLENGTH_DETECT(WakeUpSelection.AddressLength)); - - /* Set the USART address length */ - MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, WakeUpSelection.AddressLength); - - /* Set the USART address node */ - MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, ((uint32_t)WakeUpSelection.Address << UART_CR2_ADDRESS_LSB_POS)); -} - -/** - * @} - */ - -#endif /* HAL_UART_MODULE_ENABLED */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/fw/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c b/fw/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c new file mode 100644 index 0000000..f1b473f --- /dev/null +++ b/fw/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c @@ -0,0 +1,379 @@ +/** + ****************************************************************************** + * @file stm32l0xx_ll_dma.c + * @author MCD Application Team + * @brief DMA LL module driver. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ +#if defined(USE_FULL_LL_DRIVER) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l0xx_ll_dma.h" +#include "stm32l0xx_ll_bus.h" +#ifdef USE_FULL_ASSERT +#include "stm32_assert.h" +#else +#define assert_param(expr) ((void)0U) +#endif + +/** @addtogroup STM32L0xx_LL_Driver + * @{ + */ + +#if defined (DMA1) + +/** @defgroup DMA_LL DMA + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup DMA_LL_Private_Macros + * @{ + */ +#define IS_LL_DMA_DIRECTION(__VALUE__) (((__VALUE__) == LL_DMA_DIRECTION_PERIPH_TO_MEMORY) || \ + ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) || \ + ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_MEMORY)) + +#define IS_LL_DMA_MODE(__VALUE__) (((__VALUE__) == LL_DMA_MODE_NORMAL) || \ + ((__VALUE__) == LL_DMA_MODE_CIRCULAR)) + +#define IS_LL_DMA_PERIPHINCMODE(__VALUE__) (((__VALUE__) == LL_DMA_PERIPH_INCREMENT) || \ + ((__VALUE__) == LL_DMA_PERIPH_NOINCREMENT)) + +#define IS_LL_DMA_MEMORYINCMODE(__VALUE__) (((__VALUE__) == LL_DMA_MEMORY_INCREMENT) || \ + ((__VALUE__) == LL_DMA_MEMORY_NOINCREMENT)) + +#define IS_LL_DMA_PERIPHDATASIZE(__VALUE__) (((__VALUE__) == LL_DMA_PDATAALIGN_BYTE) || \ + ((__VALUE__) == LL_DMA_PDATAALIGN_HALFWORD) || \ + ((__VALUE__) == LL_DMA_PDATAALIGN_WORD)) + +#define IS_LL_DMA_MEMORYDATASIZE(__VALUE__) (((__VALUE__) == LL_DMA_MDATAALIGN_BYTE) || \ + ((__VALUE__) == LL_DMA_MDATAALIGN_HALFWORD) || \ + ((__VALUE__) == LL_DMA_MDATAALIGN_WORD)) + +#define IS_LL_DMA_NBDATA(__VALUE__) ((__VALUE__) <= 0x0000FFFFU) + +#define IS_LL_DMA_PERIPHREQUEST(__VALUE__) (((__VALUE__) == LL_DMA_REQUEST_0) || \ + ((__VALUE__) == LL_DMA_REQUEST_1) || \ + ((__VALUE__) == LL_DMA_REQUEST_2) || \ + ((__VALUE__) == LL_DMA_REQUEST_3) || \ + ((__VALUE__) == LL_DMA_REQUEST_4) || \ + ((__VALUE__) == LL_DMA_REQUEST_5) || \ + ((__VALUE__) == LL_DMA_REQUEST_6) || \ + ((__VALUE__) == LL_DMA_REQUEST_7) || \ + ((__VALUE__) == LL_DMA_REQUEST_8) || \ + ((__VALUE__) == LL_DMA_REQUEST_9) || \ + ((__VALUE__) == LL_DMA_REQUEST_10) || \ + ((__VALUE__) == LL_DMA_REQUEST_11) || \ + ((__VALUE__) == LL_DMA_REQUEST_12) || \ + ((__VALUE__) == LL_DMA_REQUEST_13) || \ + ((__VALUE__) == LL_DMA_REQUEST_14) || \ + ((__VALUE__) == LL_DMA_REQUEST_15)) + +#define IS_LL_DMA_PRIORITY(__VALUE__) (((__VALUE__) == LL_DMA_PRIORITY_LOW) || \ + ((__VALUE__) == LL_DMA_PRIORITY_MEDIUM) || \ + ((__VALUE__) == LL_DMA_PRIORITY_HIGH) || \ + ((__VALUE__) == LL_DMA_PRIORITY_VERYHIGH)) + +#if defined (DMA1_Channel6) && defined (DMA1_Channel7) +#define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) ((((INSTANCE) == DMA1) && \ + (((CHANNEL) == LL_DMA_CHANNEL_1)|| \ + ((CHANNEL) == LL_DMA_CHANNEL_2) || \ + ((CHANNEL) == LL_DMA_CHANNEL_3) || \ + ((CHANNEL) == LL_DMA_CHANNEL_4) || \ + ((CHANNEL) == LL_DMA_CHANNEL_5) || \ + ((CHANNEL) == LL_DMA_CHANNEL_6) || \ + ((CHANNEL) == LL_DMA_CHANNEL_7)))) +#elif defined (DMA1_Channel6) +#define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) ((((INSTANCE) == DMA1) && \ + (((CHANNEL) == LL_DMA_CHANNEL_1)|| \ + ((CHANNEL) == LL_DMA_CHANNEL_2) || \ + ((CHANNEL) == LL_DMA_CHANNEL_3) || \ + ((CHANNEL) == LL_DMA_CHANNEL_4) || \ + ((CHANNEL) == LL_DMA_CHANNEL_5) || \ + ((CHANNEL) == LL_DMA_CHANNEL_6)))) +#else +#define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) ((((INSTANCE) == DMA1) && \ + (((CHANNEL) == LL_DMA_CHANNEL_1)|| \ + ((CHANNEL) == LL_DMA_CHANNEL_2) || \ + ((CHANNEL) == LL_DMA_CHANNEL_3) || \ + ((CHANNEL) == LL_DMA_CHANNEL_4) || \ + ((CHANNEL) == LL_DMA_CHANNEL_5)))) +#endif /* DMA1_Channel6 && DMA1_Channel7 */ +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup DMA_LL_Exported_Functions + * @{ + */ + +/** @addtogroup DMA_LL_EF_Init + * @{ + */ + +/** + * @brief De-initialize the DMA registers to their default reset values. + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 (*) + * @arg @ref LL_DMA_CHANNEL_7 (*) + * @arg @ref LL_DMA_CHANNEL_ALL + * + * (*) value not defined in all devices + * @retval An ErrorStatus enumeration value: + * - SUCCESS: DMA registers are de-initialized + * - ERROR: DMA registers are not de-initialized + */ +ErrorStatus LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel) +{ + DMA_Channel_TypeDef *tmp = (DMA_Channel_TypeDef *)DMA1_Channel1; + ErrorStatus status = SUCCESS; + + /* Check the DMA Instance DMAx and Channel parameters*/ + assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel) || (Channel == LL_DMA_CHANNEL_ALL)); + + if (Channel == LL_DMA_CHANNEL_ALL) + { + if (DMAx == DMA1) + { + /* Force reset of DMA clock */ + LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA1); + + /* Release reset of DMA clock */ + LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA1); + } +#if defined(DMA2) + else if (DMAx == DMA2) + { + /* Force reset of DMA clock */ + LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA2); + + /* Release reset of DMA clock */ + LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA2); + } +#endif + else + { + status = ERROR; + } + } + else + { + tmp = (DMA_Channel_TypeDef *)(__LL_DMA_GET_CHANNEL_INSTANCE(DMAx, Channel)); + + /* Disable the selected DMAx_Channely */ + CLEAR_BIT(tmp->CCR, DMA_CCR_EN); + + /* Reset DMAx_Channely control register */ + LL_DMA_WriteReg(tmp, CCR, 0U); + + /* Reset DMAx_Channely remaining bytes register */ + LL_DMA_WriteReg(tmp, CNDTR, 0U); + + /* Reset DMAx_Channely peripheral address register */ + LL_DMA_WriteReg(tmp, CPAR, 0U); + + /* Reset DMAx_Channely memory address register */ + LL_DMA_WriteReg(tmp, CMAR, 0U); + + /* Reset Request register field for DMAx Channel */ + LL_DMA_SetPeriphRequest(DMAx, Channel, LL_DMA_REQUEST_0); + + if (Channel == LL_DMA_CHANNEL_1) + { + /* Reset interrupt pending bits for DMAx Channel1 */ + LL_DMA_ClearFlag_GI1(DMAx); + } + else if (Channel == LL_DMA_CHANNEL_2) + { + /* Reset interrupt pending bits for DMAx Channel2 */ + LL_DMA_ClearFlag_GI2(DMAx); + } + else if (Channel == LL_DMA_CHANNEL_3) + { + /* Reset interrupt pending bits for DMAx Channel3 */ + LL_DMA_ClearFlag_GI3(DMAx); + } + else if (Channel == LL_DMA_CHANNEL_4) + { + /* Reset interrupt pending bits for DMAx Channel4 */ + LL_DMA_ClearFlag_GI4(DMAx); + } + else if (Channel == LL_DMA_CHANNEL_5) + { + /* Reset interrupt pending bits for DMAx Channel5 */ + LL_DMA_ClearFlag_GI5(DMAx); + } + +#if defined(DMA1_Channel6) + else if (Channel == LL_DMA_CHANNEL_6) + { + /* Reset interrupt pending bits for DMAx Channel6 */ + LL_DMA_ClearFlag_GI6(DMAx); + } +#endif +#if defined(DMA1_Channel7) + else if (Channel == LL_DMA_CHANNEL_7) + { + /* Reset interrupt pending bits for DMAx Channel7 */ + LL_DMA_ClearFlag_GI7(DMAx); + } +#endif + else + { + status = ERROR; + } + } + + return status; +} + +/** + * @brief Initialize the DMA registers according to the specified parameters in DMA_InitStruct. + * @note To convert DMAx_Channely Instance to DMAx Instance and Channely, use helper macros : + * @arg @ref __LL_DMA_GET_INSTANCE + * @arg @ref __LL_DMA_GET_CHANNEL + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 (*) + * @arg @ref LL_DMA_CHANNEL_7 (*) + * + * (*) value not defined in all devices + * @param DMA_InitStruct pointer to a @ref LL_DMA_InitTypeDef structure. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: DMA registers are initialized + * - ERROR: Not applicable + */ +ErrorStatus LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct) +{ + /* Check the DMA Instance DMAx and Channel parameters*/ + assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel)); + + /* Check the DMA parameters from DMA_InitStruct */ + assert_param(IS_LL_DMA_DIRECTION(DMA_InitStruct->Direction)); + assert_param(IS_LL_DMA_MODE(DMA_InitStruct->Mode)); + assert_param(IS_LL_DMA_PERIPHINCMODE(DMA_InitStruct->PeriphOrM2MSrcIncMode)); + assert_param(IS_LL_DMA_MEMORYINCMODE(DMA_InitStruct->MemoryOrM2MDstIncMode)); + assert_param(IS_LL_DMA_PERIPHDATASIZE(DMA_InitStruct->PeriphOrM2MSrcDataSize)); + assert_param(IS_LL_DMA_MEMORYDATASIZE(DMA_InitStruct->MemoryOrM2MDstDataSize)); + assert_param(IS_LL_DMA_NBDATA(DMA_InitStruct->NbData)); + assert_param(IS_LL_DMA_PERIPHREQUEST(DMA_InitStruct->PeriphRequest)); + assert_param(IS_LL_DMA_PRIORITY(DMA_InitStruct->Priority)); + + /*---------------------------- DMAx CCR Configuration ------------------------ + * Configure DMAx_Channely: data transfer direction, data transfer mode, + * peripheral and memory increment mode, + * data size alignment and priority level with parameters : + * - Direction: DMA_CCR_DIR and DMA_CCR_MEM2MEM bits + * - Mode: DMA_CCR_CIRC bit + * - PeriphOrM2MSrcIncMode: DMA_CCR_PINC bit + * - MemoryOrM2MDstIncMode: DMA_CCR_MINC bit + * - PeriphOrM2MSrcDataSize: DMA_CCR_PSIZE[1:0] bits + * - MemoryOrM2MDstDataSize: DMA_CCR_MSIZE[1:0] bits + * - Priority: DMA_CCR_PL[1:0] bits + */ + LL_DMA_ConfigTransfer(DMAx, Channel, DMA_InitStruct->Direction | \ + DMA_InitStruct->Mode | \ + DMA_InitStruct->PeriphOrM2MSrcIncMode | \ + DMA_InitStruct->MemoryOrM2MDstIncMode | \ + DMA_InitStruct->PeriphOrM2MSrcDataSize | \ + DMA_InitStruct->MemoryOrM2MDstDataSize | \ + DMA_InitStruct->Priority); + + /*-------------------------- DMAx CMAR Configuration ------------------------- + * Configure the memory or destination base address with parameter : + * - MemoryOrM2MDstAddress: DMA_CMAR_MA[31:0] bits + */ + LL_DMA_SetMemoryAddress(DMAx, Channel, DMA_InitStruct->MemoryOrM2MDstAddress); + + /*-------------------------- DMAx CPAR Configuration ------------------------- + * Configure the peripheral or source base address with parameter : + * - PeriphOrM2MSrcAddress: DMA_CPAR_PA[31:0] bits + */ + LL_DMA_SetPeriphAddress(DMAx, Channel, DMA_InitStruct->PeriphOrM2MSrcAddress); + + /*--------------------------- DMAx CNDTR Configuration ----------------------- + * Configure the peripheral base address with parameter : + * - NbData: DMA_CNDTR_NDT[15:0] bits + */ + LL_DMA_SetDataLength(DMAx, Channel, DMA_InitStruct->NbData); + + /*--------------------------- DMAx CSELR Configuration ----------------------- + * Configure the DMA request for DMA instance on Channel x with parameter : + * - PeriphRequest: DMA_CSELR[31:0] bits + */ + LL_DMA_SetPeriphRequest(DMAx, Channel, DMA_InitStruct->PeriphRequest); + + return SUCCESS; +} + +/** + * @brief Set each @ref LL_DMA_InitTypeDef field to default value. + * @param DMA_InitStruct Pointer to a @ref LL_DMA_InitTypeDef structure. + * @retval None + */ +void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct) +{ + /* Set DMA_InitStruct fields to default values */ + DMA_InitStruct->PeriphOrM2MSrcAddress = 0x00000000U; + DMA_InitStruct->MemoryOrM2MDstAddress = 0x00000000U; + DMA_InitStruct->Direction = LL_DMA_DIRECTION_PERIPH_TO_MEMORY; + DMA_InitStruct->Mode = LL_DMA_MODE_NORMAL; + DMA_InitStruct->PeriphOrM2MSrcIncMode = LL_DMA_PERIPH_NOINCREMENT; + DMA_InitStruct->MemoryOrM2MDstIncMode = LL_DMA_MEMORY_NOINCREMENT; + DMA_InitStruct->PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_BYTE; + DMA_InitStruct->MemoryOrM2MDstDataSize = LL_DMA_MDATAALIGN_BYTE; + DMA_InitStruct->NbData = 0x00000000U; + DMA_InitStruct->PeriphRequest = LL_DMA_REQUEST_0; + DMA_InitStruct->Priority = LL_DMA_PRIORITY_LOW; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* DMA1 */ + +/** + * @} + */ + +#endif /* USE_FULL_LL_DRIVER */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/fw/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c b/fw/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c new file mode 100644 index 0000000..8669e5d --- /dev/null +++ b/fw/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c @@ -0,0 +1,214 @@ +/** + ****************************************************************************** + * @file stm32l0xx_ll_exti.c + * @author MCD Application Team + * @brief EXTI LL module driver. + ****************************************************************************** + * @attention + * + *

© Copyright(c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ +#if defined(USE_FULL_LL_DRIVER) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l0xx_ll_exti.h" +#ifdef USE_FULL_ASSERT +#include "stm32_assert.h" +#else +#define assert_param(expr) ((void)0U) +#endif + +/** @addtogroup STM32L0xx_LL_Driver + * @{ + */ + +#if defined (EXTI) + +/** @defgroup EXTI_LL EXTI + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup EXTI_LL_Private_Macros + * @{ + */ + +#define IS_LL_EXTI_LINE_0_31(__VALUE__) (((__VALUE__) & ~LL_EXTI_LINE_ALL_0_31) == 0x00000000U) + +#define IS_LL_EXTI_MODE(__VALUE__) (((__VALUE__) == LL_EXTI_MODE_IT) \ + || ((__VALUE__) == LL_EXTI_MODE_EVENT) \ + || ((__VALUE__) == LL_EXTI_MODE_IT_EVENT)) + + +#define IS_LL_EXTI_TRIGGER(__VALUE__) (((__VALUE__) == LL_EXTI_TRIGGER_NONE) \ + || ((__VALUE__) == LL_EXTI_TRIGGER_RISING) \ + || ((__VALUE__) == LL_EXTI_TRIGGER_FALLING) \ + || ((__VALUE__) == LL_EXTI_TRIGGER_RISING_FALLING)) + +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup EXTI_LL_Exported_Functions + * @{ + */ + +/** @addtogroup EXTI_LL_EF_Init + * @{ + */ + +/** + * @brief De-initialize the EXTI registers to their default reset values. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: EXTI registers are de-initialized + * - ERROR: not applicable + */ +uint32_t LL_EXTI_DeInit(void) +{ + /* Interrupt mask register set to default reset values */ + LL_EXTI_WriteReg(IMR, 0x3F840000U); + /* Event mask register set to default reset values */ + LL_EXTI_WriteReg(EMR, 0x00000000U); + /* Rising Trigger selection register set to default reset values */ + LL_EXTI_WriteReg(RTSR, 0x00000000U); + /* Falling Trigger selection register set to default reset values */ + LL_EXTI_WriteReg(FTSR, 0x00000000U); + /* Software interrupt event register set to default reset values */ + LL_EXTI_WriteReg(SWIER, 0x00000000U); + /* Pending register set to default reset values */ + LL_EXTI_WriteReg(PR, 0x007BFFFFU); + + return SUCCESS; +} + +/** + * @brief Initialize the EXTI registers according to the specified parameters in EXTI_InitStruct. + * @param EXTI_InitStruct pointer to a @ref LL_EXTI_InitTypeDef structure. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: EXTI registers are initialized + * - ERROR: not applicable + */ +uint32_t LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct) +{ + ErrorStatus status = SUCCESS; + /* Check the parameters */ + assert_param(IS_LL_EXTI_LINE_0_31(EXTI_InitStruct->Line_0_31)); + assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->LineCommand)); + assert_param(IS_LL_EXTI_MODE(EXTI_InitStruct->Mode)); + + /* ENABLE LineCommand */ + if (EXTI_InitStruct->LineCommand != DISABLE) + { + assert_param(IS_LL_EXTI_TRIGGER(EXTI_InitStruct->Trigger)); + + /* Configure EXTI Lines in range from 0 to 31 */ + if (EXTI_InitStruct->Line_0_31 != LL_EXTI_LINE_NONE) + { + switch (EXTI_InitStruct->Mode) + { + case LL_EXTI_MODE_IT: + /* First Disable Event on provided Lines */ + LL_EXTI_DisableEvent_0_31(EXTI_InitStruct->Line_0_31); + /* Then Enable IT on provided Lines */ + LL_EXTI_EnableIT_0_31(EXTI_InitStruct->Line_0_31); + break; + case LL_EXTI_MODE_EVENT: + /* First Disable IT on provided Lines */ + LL_EXTI_DisableIT_0_31(EXTI_InitStruct->Line_0_31); + /* Then Enable Event on provided Lines */ + LL_EXTI_EnableEvent_0_31(EXTI_InitStruct->Line_0_31); + break; + case LL_EXTI_MODE_IT_EVENT: + /* Directly Enable IT & Event on provided Lines */ + LL_EXTI_EnableIT_0_31(EXTI_InitStruct->Line_0_31); + LL_EXTI_EnableEvent_0_31(EXTI_InitStruct->Line_0_31); + break; + default: + status = ERROR; + break; + } + if (EXTI_InitStruct->Trigger != LL_EXTI_TRIGGER_NONE) + { + switch (EXTI_InitStruct->Trigger) + { + case LL_EXTI_TRIGGER_RISING: + /* First Disable Falling Trigger on provided Lines */ + LL_EXTI_DisableFallingTrig_0_31(EXTI_InitStruct->Line_0_31); + /* Then Enable Rising Trigger on provided Lines */ + LL_EXTI_EnableRisingTrig_0_31(EXTI_InitStruct->Line_0_31); + break; + case LL_EXTI_TRIGGER_FALLING: + /* First Disable Rising Trigger on provided Lines */ + LL_EXTI_DisableRisingTrig_0_31(EXTI_InitStruct->Line_0_31); + /* Then Enable Falling Trigger on provided Lines */ + LL_EXTI_EnableFallingTrig_0_31(EXTI_InitStruct->Line_0_31); + break; + case LL_EXTI_TRIGGER_RISING_FALLING: + LL_EXTI_EnableRisingTrig_0_31(EXTI_InitStruct->Line_0_31); + LL_EXTI_EnableFallingTrig_0_31(EXTI_InitStruct->Line_0_31); + break; + default: + status = ERROR; + break; + } + } + } + } + /* DISABLE LineCommand */ + else + { + /* De-configure EXTI Lines in range from 0 to 31 */ + LL_EXTI_DisableIT_0_31(EXTI_InitStruct->Line_0_31); + LL_EXTI_DisableEvent_0_31(EXTI_InitStruct->Line_0_31); + } + return status; +} + +/** + * @brief Set each @ref LL_EXTI_InitTypeDef field to default value. + * @param EXTI_InitStruct Pointer to a @ref LL_EXTI_InitTypeDef structure. + * @retval None + */ +void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct) +{ + EXTI_InitStruct->Line_0_31 = LL_EXTI_LINE_NONE; + EXTI_InitStruct->LineCommand = DISABLE; + EXTI_InitStruct->Mode = LL_EXTI_MODE_IT; + EXTI_InitStruct->Trigger = LL_EXTI_TRIGGER_FALLING; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined (EXTI) */ + +/** + * @} + */ + +#endif /* USE_FULL_LL_DRIVER */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/fw/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c b/fw/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c new file mode 100644 index 0000000..611e456 --- /dev/null +++ b/fw/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c @@ -0,0 +1,263 @@ +/** + ****************************************************************************** + * @file stm32l0xx_ll_gpio.c + * @author MCD Application Team + * @brief GPIO LL module driver. + ****************************************************************************** + * @attention + * + *

© Copyright(c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ +#if defined(USE_FULL_LL_DRIVER) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l0xx_ll_gpio.h" +#include "stm32l0xx_ll_bus.h" +#ifdef USE_FULL_ASSERT +#include "stm32_assert.h" +#else +#define assert_param(expr) ((void)0U) +#endif + +/** @addtogroup STM32L0xx_LL_Driver + * @{ + */ + +#if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOH) + +/** @addtogroup GPIO_LL + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup GPIO_LL_Private_Macros + * @{ + */ +#define IS_LL_GPIO_PIN(__VALUE__) (((0x00000000UL) < (__VALUE__)) && ((__VALUE__) <= (LL_GPIO_PIN_ALL))) + +#define IS_LL_GPIO_MODE(__VALUE__) (((__VALUE__) == LL_GPIO_MODE_INPUT) ||\ + ((__VALUE__) == LL_GPIO_MODE_OUTPUT) ||\ + ((__VALUE__) == LL_GPIO_MODE_ALTERNATE) ||\ + ((__VALUE__) == LL_GPIO_MODE_ANALOG)) + +#define IS_LL_GPIO_OUTPUT_TYPE(__VALUE__) (((__VALUE__) == LL_GPIO_OUTPUT_PUSHPULL) ||\ + ((__VALUE__) == LL_GPIO_OUTPUT_OPENDRAIN)) + +#define IS_LL_GPIO_SPEED(__VALUE__) (((__VALUE__) == LL_GPIO_SPEED_FREQ_LOW) ||\ + ((__VALUE__) == LL_GPIO_SPEED_FREQ_MEDIUM) ||\ + ((__VALUE__) == LL_GPIO_SPEED_FREQ_HIGH) ||\ + ((__VALUE__) == LL_GPIO_SPEED_FREQ_VERY_HIGH)) + +#define IS_LL_GPIO_PULL(__VALUE__) (((__VALUE__) == LL_GPIO_PULL_NO) ||\ + ((__VALUE__) == LL_GPIO_PULL_UP) ||\ + ((__VALUE__) == LL_GPIO_PULL_DOWN)) + +#define IS_LL_GPIO_ALTERNATE(__VALUE__) (((__VALUE__) == LL_GPIO_AF_0 ) ||\ + ((__VALUE__) == LL_GPIO_AF_1 ) ||\ + ((__VALUE__) == LL_GPIO_AF_2 ) ||\ + ((__VALUE__) == LL_GPIO_AF_3 ) ||\ + ((__VALUE__) == LL_GPIO_AF_4 ) ||\ + ((__VALUE__) == LL_GPIO_AF_5 ) ||\ + ((__VALUE__) == LL_GPIO_AF_6 ) ||\ + ((__VALUE__) == LL_GPIO_AF_7 )) +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup GPIO_LL_Exported_Functions + * @{ + */ + +/** @addtogroup GPIO_LL_EF_Init + * @{ + */ + +/** + * @brief De-initialize GPIO registers (Registers restored to their default values). + * @param GPIOx GPIO Port + * @retval An ErrorStatus enumeration value: + * - SUCCESS: GPIO registers are de-initialized + * - ERROR: Wrong GPIO Port + */ +ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx) +{ + ErrorStatus status = SUCCESS; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + + /* Force and Release reset on clock of GPIOx Port */ + if (GPIOx == GPIOA) + { + LL_IOP_GRP1_ForceReset(LL_IOP_GRP1_PERIPH_GPIOA); + LL_IOP_GRP1_ReleaseReset(LL_IOP_GRP1_PERIPH_GPIOA); + } + else if (GPIOx == GPIOB) + { + LL_IOP_GRP1_ForceReset(LL_IOP_GRP1_PERIPH_GPIOB); + LL_IOP_GRP1_ReleaseReset(LL_IOP_GRP1_PERIPH_GPIOB); + } + else if (GPIOx == GPIOC) + { + LL_IOP_GRP1_ForceReset(LL_IOP_GRP1_PERIPH_GPIOC); + LL_IOP_GRP1_ReleaseReset(LL_IOP_GRP1_PERIPH_GPIOC); + } +#if defined(GPIOD) + else if (GPIOx == GPIOD) + { + LL_IOP_GRP1_ForceReset(LL_IOP_GRP1_PERIPH_GPIOD); + LL_IOP_GRP1_ReleaseReset(LL_IOP_GRP1_PERIPH_GPIOD); + } +#endif /* GPIOD */ +#if defined(GPIOE) + else if (GPIOx == GPIOE) + { + LL_IOP_GRP1_ForceReset(LL_IOP_GRP1_PERIPH_GPIOE); + LL_IOP_GRP1_ReleaseReset(LL_IOP_GRP1_PERIPH_GPIOE); + } +#endif /* GPIOE */ +#if defined(GPIOH) + else if (GPIOx == GPIOH) + { + LL_IOP_GRP1_ForceReset(LL_IOP_GRP1_PERIPH_GPIOH); + LL_IOP_GRP1_ReleaseReset(LL_IOP_GRP1_PERIPH_GPIOH); + } +#endif /* GPIOH */ + else + { + status = ERROR; + } + + return (status); +} + +/** + * @brief Initialize GPIO registers according to the specified parameters in GPIO_InitStruct. + * @param GPIOx GPIO Port + * @param GPIO_InitStruct pointer to a @ref LL_GPIO_InitTypeDef structure + * that contains the configuration information for the specified GPIO peripheral. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: GPIO registers are initialized according to GPIO_InitStruct content + * - ERROR: Not applicable + */ +ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct) +{ + uint32_t pinpos = 0x00000000U; + uint32_t currentpin = 0x00000000U; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + assert_param(IS_LL_GPIO_PIN(GPIO_InitStruct->Pin)); + assert_param(IS_LL_GPIO_MODE(GPIO_InitStruct->Mode)); + assert_param(IS_LL_GPIO_PULL(GPIO_InitStruct->Pull)); + + /* ------------------------- Configure the port pins ---------------- */ + /* Initialize pinpos on first pin set */ + /* pinpos = 0; useless as already done in default initialization */ + + /* Configure the port pins */ + while (((GPIO_InitStruct->Pin) >> pinpos) != 0x00000000U) + { + /* Get current io position */ + currentpin = (GPIO_InitStruct->Pin) & (0x00000001U << pinpos); + + if (currentpin) + { + if ((GPIO_InitStruct->Mode == LL_GPIO_MODE_OUTPUT) || (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE)) + { + /* Check Speed mode parameters */ + assert_param(IS_LL_GPIO_SPEED(GPIO_InitStruct->Speed)); + + /* Speed mode configuration */ + LL_GPIO_SetPinSpeed(GPIOx, currentpin, GPIO_InitStruct->Speed); + + /* Check Output mode parameters */ + assert_param(IS_LL_GPIO_OUTPUT_TYPE(GPIO_InitStruct->OutputType)); + + /* Output mode configuration*/ + LL_GPIO_SetPinOutputType(GPIOx, GPIO_InitStruct->Pin, GPIO_InitStruct->OutputType); + } + + /* Pull-up Pull down resistor configuration*/ + LL_GPIO_SetPinPull(GPIOx, currentpin, GPIO_InitStruct->Pull); + + if (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE) + { + /* Check Alternate parameter */ + assert_param(IS_LL_GPIO_ALTERNATE(GPIO_InitStruct->Alternate)); + + /* Speed mode configuration */ + if (currentpin < LL_GPIO_PIN_8) + { + LL_GPIO_SetAFPin_0_7(GPIOx, currentpin, GPIO_InitStruct->Alternate); + } + else + { + LL_GPIO_SetAFPin_8_15(GPIOx, currentpin, GPIO_InitStruct->Alternate); + } + } + + /* Pin Mode configuration */ + LL_GPIO_SetPinMode(GPIOx, currentpin, GPIO_InitStruct->Mode); + } + pinpos++; + } + + + return (SUCCESS); +} + +/** + * @brief Set each @ref LL_GPIO_InitTypeDef field to default value. + * @param GPIO_InitStruct: pointer to a @ref LL_GPIO_InitTypeDef structure + * whose fields will be set to default values. + * @retval None + */ + +void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct) +{ + /* Reset GPIO init structure parameters values */ + GPIO_InitStruct->Pin = LL_GPIO_PIN_ALL; + GPIO_InitStruct->Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct->Speed = LL_GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct->OutputType = LL_GPIO_OUTPUT_PUSHPULL; + GPIO_InitStruct->Pull = LL_GPIO_PULL_NO; + GPIO_InitStruct->Alternate = LL_GPIO_AF_0; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOH) */ + +/** + * @} + */ + +#endif /* USE_FULL_LL_DRIVER */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/fw/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c b/fw/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c new file mode 100644 index 0000000..58ccb6c --- /dev/null +++ b/fw/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c @@ -0,0 +1,239 @@ +/** + ****************************************************************************** + * @file stm32l0xx_ll_i2c.c + * @author MCD Application Team + * @brief I2C LL module driver. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ +#if defined(USE_FULL_LL_DRIVER) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l0xx_ll_i2c.h" +#include "stm32l0xx_ll_bus.h" +#ifdef USE_FULL_ASSERT +#include "stm32_assert.h" +#else +#define assert_param(expr) ((void)0U) +#endif + +/** @addtogroup STM32L0xx_LL_Driver + * @{ + */ + +#if defined (I2C1) || defined (I2C2) || defined (I2C3) + +/** @defgroup I2C_LL I2C + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup I2C_LL_Private_Macros + * @{ + */ + +#define IS_LL_I2C_PERIPHERAL_MODE(__VALUE__) (((__VALUE__) == LL_I2C_MODE_I2C) || \ + ((__VALUE__) == LL_I2C_MODE_SMBUS_HOST) || \ + ((__VALUE__) == LL_I2C_MODE_SMBUS_DEVICE) || \ + ((__VALUE__) == LL_I2C_MODE_SMBUS_DEVICE_ARP)) + +#define IS_LL_I2C_ANALOG_FILTER(__VALUE__) (((__VALUE__) == LL_I2C_ANALOGFILTER_ENABLE) || \ + ((__VALUE__) == LL_I2C_ANALOGFILTER_DISABLE)) + +#define IS_LL_I2C_DIGITAL_FILTER(__VALUE__) ((__VALUE__) <= 0x0000000FU) + +#define IS_LL_I2C_OWN_ADDRESS1(__VALUE__) ((__VALUE__) <= 0x000003FFU) + +#define IS_LL_I2C_TYPE_ACKNOWLEDGE(__VALUE__) (((__VALUE__) == LL_I2C_ACK) || \ + ((__VALUE__) == LL_I2C_NACK)) + +#define IS_LL_I2C_OWN_ADDRSIZE(__VALUE__) (((__VALUE__) == LL_I2C_OWNADDRESS1_7BIT) || \ + ((__VALUE__) == LL_I2C_OWNADDRESS1_10BIT)) +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup I2C_LL_Exported_Functions + * @{ + */ + +/** @addtogroup I2C_LL_EF_Init + * @{ + */ + +/** + * @brief De-initialize the I2C registers to their default reset values. + * @param I2Cx I2C Instance. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: I2C registers are de-initialized + * - ERROR: I2C registers are not de-initialized + */ +ErrorStatus LL_I2C_DeInit(I2C_TypeDef *I2Cx) +{ + ErrorStatus status = SUCCESS; + + /* Check the I2C Instance I2Cx */ + assert_param(IS_I2C_ALL_INSTANCE(I2Cx)); + + if (I2Cx == I2C1) + { + /* Force reset of I2C clock */ + LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I2C1); + + /* Release reset of I2C clock */ + LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C1); + } +#if defined(I2C2) + else if (I2Cx == I2C2) + { + /* Force reset of I2C clock */ + LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I2C2); + + /* Release reset of I2C clock */ + LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C2); + + } +#endif +#if defined(I2C3) + else if (I2Cx == I2C3) + { + /* Force reset of I2C clock */ + LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I2C3); + + /* Release reset of I2C clock */ + LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C3); + } +#endif + else + { + status = ERROR; + } + + return status; +} + +/** + * @brief Initialize the I2C registers according to the specified parameters in I2C_InitStruct. + * @param I2Cx I2C Instance. + * @param I2C_InitStruct pointer to a @ref LL_I2C_InitTypeDef structure. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: I2C registers are initialized + * - ERROR: Not applicable + */ +ErrorStatus LL_I2C_Init(I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct) +{ + /* Check the I2C Instance I2Cx */ + assert_param(IS_I2C_ALL_INSTANCE(I2Cx)); + + /* Check the I2C parameters from I2C_InitStruct */ + assert_param(IS_LL_I2C_PERIPHERAL_MODE(I2C_InitStruct->PeripheralMode)); + assert_param(IS_LL_I2C_ANALOG_FILTER(I2C_InitStruct->AnalogFilter)); + assert_param(IS_LL_I2C_DIGITAL_FILTER(I2C_InitStruct->DigitalFilter)); + assert_param(IS_LL_I2C_OWN_ADDRESS1(I2C_InitStruct->OwnAddress1)); + assert_param(IS_LL_I2C_TYPE_ACKNOWLEDGE(I2C_InitStruct->TypeAcknowledge)); + assert_param(IS_LL_I2C_OWN_ADDRSIZE(I2C_InitStruct->OwnAddrSize)); + + /* Disable the selected I2Cx Peripheral */ + LL_I2C_Disable(I2Cx); + + /*---------------------------- I2Cx CR1 Configuration ------------------------ + * Configure the analog and digital noise filters with parameters : + * - AnalogFilter: I2C_CR1_ANFOFF bit + * - DigitalFilter: I2C_CR1_DNF[3:0] bits + */ + LL_I2C_ConfigFilters(I2Cx, I2C_InitStruct->AnalogFilter, I2C_InitStruct->DigitalFilter); + + /*---------------------------- I2Cx TIMINGR Configuration -------------------- + * Configure the SDA setup, hold time and the SCL high, low period with parameter : + * - Timing: I2C_TIMINGR_PRESC[3:0], I2C_TIMINGR_SCLDEL[3:0], I2C_TIMINGR_SDADEL[3:0], + * I2C_TIMINGR_SCLH[7:0] and I2C_TIMINGR_SCLL[7:0] bits + */ + LL_I2C_SetTiming(I2Cx, I2C_InitStruct->Timing); + + /* Enable the selected I2Cx Peripheral */ + LL_I2C_Enable(I2Cx); + + /*---------------------------- I2Cx OAR1 Configuration ----------------------- + * Disable, Configure and Enable I2Cx device own address 1 with parameters : + * - OwnAddress1: I2C_OAR1_OA1[9:0] bits + * - OwnAddrSize: I2C_OAR1_OA1MODE bit + */ + LL_I2C_DisableOwnAddress1(I2Cx); + LL_I2C_SetOwnAddress1(I2Cx, I2C_InitStruct->OwnAddress1, I2C_InitStruct->OwnAddrSize); + + /* OwnAdress1 == 0 is reserved for General Call address */ + if (I2C_InitStruct->OwnAddress1 != 0U) + { + LL_I2C_EnableOwnAddress1(I2Cx); + } + + /*---------------------------- I2Cx MODE Configuration ----------------------- + * Configure I2Cx peripheral mode with parameter : + * - PeripheralMode: I2C_CR1_SMBDEN and I2C_CR1_SMBHEN bits + */ + LL_I2C_SetMode(I2Cx, I2C_InitStruct->PeripheralMode); + + /*---------------------------- I2Cx CR2 Configuration ------------------------ + * Configure the ACKnowledge or Non ACKnowledge condition + * after the address receive match code or next received byte with parameter : + * - TypeAcknowledge: I2C_CR2_NACK bit + */ + LL_I2C_AcknowledgeNextData(I2Cx, I2C_InitStruct->TypeAcknowledge); + + return SUCCESS; +} + +/** + * @brief Set each @ref LL_I2C_InitTypeDef field to default value. + * @param I2C_InitStruct Pointer to a @ref LL_I2C_InitTypeDef structure. + * @retval None + */ +void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct) +{ + /* Set I2C_InitStruct fields to default values */ + I2C_InitStruct->PeripheralMode = LL_I2C_MODE_I2C; + I2C_InitStruct->Timing = 0U; + I2C_InitStruct->AnalogFilter = LL_I2C_ANALOGFILTER_ENABLE; + I2C_InitStruct->DigitalFilter = 0U; + I2C_InitStruct->OwnAddress1 = 0U; + I2C_InitStruct->TypeAcknowledge = LL_I2C_NACK; + I2C_InitStruct->OwnAddrSize = LL_I2C_OWNADDRESS1_7BIT; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* I2C1 || I2C2 || I2C3 */ + +/** + * @} + */ + +#endif /* USE_FULL_LL_DRIVER */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/fw/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c b/fw/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c new file mode 100644 index 0000000..e84dcfd --- /dev/null +++ b/fw/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c @@ -0,0 +1,264 @@ +/** + ****************************************************************************** + * @file stm32l0xx_ll_lpuart.c + * @author MCD Application Team + * @brief LPUART LL module driver. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ +#if defined(USE_FULL_LL_DRIVER) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l0xx_ll_lpuart.h" +#include "stm32l0xx_ll_rcc.h" +#include "stm32l0xx_ll_bus.h" +#ifdef USE_FULL_ASSERT +#include "stm32_assert.h" +#else +#define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +/** @addtogroup STM32L0xx_LL_Driver + * @{ + */ + +#if defined (LPUART1) + +/** @addtogroup LPUART_LL + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @addtogroup LPUART_LL_Private_Constants + * @{ + */ + +/** + * @} + */ + + +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup LPUART_LL_Private_Macros + * @{ + */ + +/* Check of parameters for configuration of LPUART registers */ + +/* __BAUDRATE__ Depending on constraints applicable for LPUART BRR register */ +/* value : */ +/* - fck must be in the range [3 x baudrate, 4096 x baudrate] */ +/* - LPUART_BRR register value should be >= 0x300 */ +/* - LPUART_BRR register value should be <= 0xFFFFF (20 bits) */ +/* Baudrate specified by the user should belong to [8, 10600000].*/ +#define IS_LL_LPUART_BAUDRATE(__BAUDRATE__) (((__BAUDRATE__) <= 10600000U) && ((__BAUDRATE__) >= 8U)) + +/* __VALUE__ BRR content must be greater than or equal to 0x300. */ +#define IS_LL_LPUART_BRR_MIN(__VALUE__) ((__VALUE__) >= 0x300U) + +/* __VALUE__ BRR content must be lower than or equal to 0xFFFFF. */ +#define IS_LL_LPUART_BRR_MAX(__VALUE__) ((__VALUE__) <= 0x000FFFFFU) + +#define IS_LL_LPUART_DIRECTION(__VALUE__) (((__VALUE__) == LL_LPUART_DIRECTION_NONE) \ + || ((__VALUE__) == LL_LPUART_DIRECTION_RX) \ + || ((__VALUE__) == LL_LPUART_DIRECTION_TX) \ + || ((__VALUE__) == LL_LPUART_DIRECTION_TX_RX)) + +#define IS_LL_LPUART_PARITY(__VALUE__) (((__VALUE__) == LL_LPUART_PARITY_NONE) \ + || ((__VALUE__) == LL_LPUART_PARITY_EVEN) \ + || ((__VALUE__) == LL_LPUART_PARITY_ODD)) + +#define IS_LL_LPUART_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_LPUART_DATAWIDTH_7B) \ + || ((__VALUE__) == LL_LPUART_DATAWIDTH_8B) \ + || ((__VALUE__) == LL_LPUART_DATAWIDTH_9B)) + +#define IS_LL_LPUART_STOPBITS(__VALUE__) (((__VALUE__) == LL_LPUART_STOPBITS_1) \ + || ((__VALUE__) == LL_LPUART_STOPBITS_2)) + +#define IS_LL_LPUART_HWCONTROL(__VALUE__) (((__VALUE__) == LL_LPUART_HWCONTROL_NONE) \ + || ((__VALUE__) == LL_LPUART_HWCONTROL_RTS) \ + || ((__VALUE__) == LL_LPUART_HWCONTROL_CTS) \ + || ((__VALUE__) == LL_LPUART_HWCONTROL_RTS_CTS)) + +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup LPUART_LL_Exported_Functions + * @{ + */ + +/** @addtogroup LPUART_LL_EF_Init + * @{ + */ + +/** + * @brief De-initialize LPUART registers (Registers restored to their default values). + * @param LPUARTx LPUART Instance + * @retval An ErrorStatus enumeration value: + * - SUCCESS: LPUART registers are de-initialized + * - ERROR: not applicable + */ +ErrorStatus LL_LPUART_DeInit(USART_TypeDef *LPUARTx) +{ + ErrorStatus status = SUCCESS; + + /* Check the parameters */ + assert_param(IS_LPUART_INSTANCE(LPUARTx)); + + if (LPUARTx == LPUART1) + { + /* Force reset of LPUART peripheral */ + LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_LPUART1); + + /* Release reset of LPUART peripheral */ + LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_LPUART1); + } + else + { + status = ERROR; + } + + return (status); +} + +/** + * @brief Initialize LPUART registers according to the specified + * parameters in LPUART_InitStruct. + * @note As some bits in LPUART configuration registers can only be written when + * the LPUART is disabled (USART_CR1_UE bit =0), + * LPUART Peripheral should be in disabled state prior calling this function. + * Otherwise, ERROR result will be returned. + * @note Baud rate value stored in LPUART_InitStruct BaudRate field, should be valid (different from 0). + * @param LPUARTx LPUART Instance + * @param LPUART_InitStruct pointer to a @ref LL_LPUART_InitTypeDef structure + * that contains the configuration information for the specified LPUART peripheral. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: LPUART registers are initialized according to LPUART_InitStruct content + * - ERROR: Problem occurred during LPUART Registers initialization + */ +ErrorStatus LL_LPUART_Init(USART_TypeDef *LPUARTx, LL_LPUART_InitTypeDef *LPUART_InitStruct) +{ + ErrorStatus status = ERROR; + uint32_t periphclk; + + /* Check the parameters */ + assert_param(IS_LPUART_INSTANCE(LPUARTx)); + assert_param(IS_LL_LPUART_BAUDRATE(LPUART_InitStruct->BaudRate)); + assert_param(IS_LL_LPUART_DATAWIDTH(LPUART_InitStruct->DataWidth)); + assert_param(IS_LL_LPUART_STOPBITS(LPUART_InitStruct->StopBits)); + assert_param(IS_LL_LPUART_PARITY(LPUART_InitStruct->Parity)); + assert_param(IS_LL_LPUART_DIRECTION(LPUART_InitStruct->TransferDirection)); + assert_param(IS_LL_LPUART_HWCONTROL(LPUART_InitStruct->HardwareFlowControl)); + + /* LPUART needs to be in disabled state, in order to be able to configure some bits in + CRx registers. Otherwise (LPUART not in Disabled state) => return ERROR */ + if (LL_LPUART_IsEnabled(LPUARTx) == 0U) + { + /*---------------------------- LPUART CR1 Configuration ----------------------- + * Configure LPUARTx CR1 (LPUART Word Length, Parity and Transfer Direction bits) with parameters: + * - DataWidth: USART_CR1_M bits according to LPUART_InitStruct->DataWidth value + * - Parity: USART_CR1_PCE, USART_CR1_PS bits according to LPUART_InitStruct->Parity value + * - TransferDirection: USART_CR1_TE, USART_CR1_RE bits according to LPUART_InitStruct->TransferDirection value + */ + MODIFY_REG(LPUARTx->CR1, + (USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE), + (LPUART_InitStruct->DataWidth | LPUART_InitStruct->Parity | LPUART_InitStruct->TransferDirection)); + + /*---------------------------- LPUART CR2 Configuration ----------------------- + * Configure LPUARTx CR2 (Stop bits) with parameters: + * - Stop Bits: USART_CR2_STOP bits according to LPUART_InitStruct->StopBits value. + */ + LL_LPUART_SetStopBitsLength(LPUARTx, LPUART_InitStruct->StopBits); + + /*---------------------------- LPUART CR3 Configuration ----------------------- + * Configure LPUARTx CR3 (Hardware Flow Control) with parameters: + * - HardwareFlowControl: USART_CR3_RTSE, USART_CR3_CTSE bits according + * to LPUART_InitStruct->HardwareFlowControl value. + */ + LL_LPUART_SetHWFlowCtrl(LPUARTx, LPUART_InitStruct->HardwareFlowControl); + + /*---------------------------- LPUART BRR Configuration ----------------------- + * Retrieve Clock frequency used for LPUART Peripheral + */ + periphclk = LL_RCC_GetLPUARTClockFreq(LL_RCC_LPUART1_CLKSOURCE); + + /* Configure the LPUART Baud Rate : + - valid baud rate value (different from 0) is required + - Peripheral clock as returned by RCC service, should be valid (different from 0). + */ + if ((periphclk != LL_RCC_PERIPH_FREQUENCY_NO) + && (LPUART_InitStruct->BaudRate != 0U)) + { + status = SUCCESS; + LL_LPUART_SetBaudRate(LPUARTx, + periphclk, + LPUART_InitStruct->BaudRate); + + /* Check BRR is greater than or equal to 0x300 */ + assert_param(IS_LL_LPUART_BRR_MIN(LPUARTx->BRR)); + + /* Check BRR is lower than or equal to 0xFFFFF */ + assert_param(IS_LL_LPUART_BRR_MAX(LPUARTx->BRR)); + } + + } + + return (status); +} + +/** + * @brief Set each @ref LL_LPUART_InitTypeDef field to default value. + * @param LPUART_InitStruct pointer to a @ref LL_LPUART_InitTypeDef structure + * whose fields will be set to default values. + * @retval None + */ + +void LL_LPUART_StructInit(LL_LPUART_InitTypeDef *LPUART_InitStruct) +{ + /* Set LPUART_InitStruct fields to default values */ + LPUART_InitStruct->BaudRate = 9600U; + LPUART_InitStruct->DataWidth = LL_LPUART_DATAWIDTH_8B; + LPUART_InitStruct->StopBits = LL_LPUART_STOPBITS_1; + LPUART_InitStruct->Parity = LL_LPUART_PARITY_NONE ; + LPUART_InitStruct->TransferDirection = LL_LPUART_DIRECTION_TX_RX; + LPUART_InitStruct->HardwareFlowControl = LL_LPUART_HWCONTROL_NONE; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* LPUART1 */ + +/** + * @} + */ + +#endif /* USE_FULL_LL_DRIVER */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/fw/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c b/fw/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c new file mode 100644 index 0000000..2bd1b44 --- /dev/null +++ b/fw/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c @@ -0,0 +1,698 @@ +/** + ****************************************************************************** + * @file stm32l0xx_ll_rcc.c + * @author MCD Application Team + * @brief RCC LL module driver. + ****************************************************************************** + * @attention + * + *

© Copyright(c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ +#if defined(USE_FULL_LL_DRIVER) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l0xx_ll_rcc.h" +#ifdef USE_FULL_ASSERT + #include "stm32_assert.h" +#else + #define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ +/** @addtogroup STM32L0xx_LL_Driver + * @{ + */ + +#if defined(RCC) + +/** @defgroup RCC_LL RCC + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup RCC_LL_Private_Macros + * @{ + */ +#if defined(RCC_CCIPR_USART1SEL) && defined(RCC_CCIPR_USART2SEL) +#define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART1_CLKSOURCE) \ + || ((__VALUE__) == LL_RCC_USART2_CLKSOURCE)) +#elif defined(RCC_CCIPR_USART1SEL) && !defined(RCC_CCIPR_USART2SEL) +#define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART1_CLKSOURCE)) +#else +#define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART2_CLKSOURCE)) +#endif /* RCC_CCIPR_USART1SEL && RCC_CCIPR_USART2SEL */ + +#define IS_LL_RCC_LPUART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_LPUART1_CLKSOURCE)) + +#if defined(RCC_CCIPR_I2C3SEL) +#define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) \ + || ((__VALUE__) == LL_RCC_I2C3_CLKSOURCE)) +#else +#define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) +#endif /* RCC_CCIPR_I2C3SEL */ + +#define IS_LL_RCC_LPTIM_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_LPTIM1_CLKSOURCE) + +#if defined(USB) +#define IS_LL_RCC_USB_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USB_CLKSOURCE)) +#endif /* USB */ + +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup RCC_LL_Private_Functions RCC Private functions + * @{ + */ +uint32_t RCC_GetSystemClockFreq(void); +uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency); +uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency); +uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency); +uint32_t RCC_PLL_GetFreqDomain_SYS(void); +/** + * @} + */ + + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup RCC_LL_Exported_Functions + * @{ + */ + +/** @addtogroup RCC_LL_EF_Init + * @{ + */ + +/** + * @brief Reset the RCC clock configuration to the default reset state. + * @note The default reset state of the clock configuration is given below: + * - MSI ON and used as system clock source + * - HSE, HSI and PLL OFF + * - AHB, APB1 and APB2 prescaler set to 1. + * - CSS, MCO OFF + * - All interrupts disabled + * @note This function doesn't modify the configuration of the + * - Peripheral clocks + * - LSI, LSE and RTC clocks + * @retval An ErrorStatus enumeration value: + * - SUCCESS: RCC registers are de-initialized + * - ERROR: not applicable + */ +ErrorStatus LL_RCC_DeInit(void) +{ + __IO uint32_t vl_mask; + + /* Set MSION bit */ + LL_RCC_MSI_Enable(); + + /* Insure MSIRDY bit is set before writing default MSIRANGE value */ + while (LL_RCC_MSI_IsReady() == 0U) + { + __NOP(); + } + + /* Set MSIRANGE default value */ + LL_RCC_MSI_SetRange(LL_RCC_MSIRANGE_5); + /* Set MSITRIM bits to the reset value*/ + LL_RCC_MSI_SetCalibTrimming(0U); + + /* Set HSITRIM bits to the reset value*/ + LL_RCC_HSI_SetCalibTrimming(0x10U); + + /* Reset SW, HPRE, PPRE1, PPRE2, MCOSEL and MCOPRE bits */ + vl_mask = 0xFFFFFFFFU; + CLEAR_BIT(vl_mask, RCC_CFGR_SW | RCC_CFGR_HPRE | RCC_CFGR_PPRE1 | RCC_CFGR_PPRE2 | \ + RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE); + LL_RCC_WriteReg(CFGR, vl_mask); + + /* Reset HSI, HSE, PLL */ + vl_mask = LL_RCC_ReadReg(CR); +#if defined(RCC_CR_HSIOUTEN) + CLEAR_BIT(vl_mask, RCC_CR_HSION| RCC_CR_HSIKERON| RCC_CR_HSIDIVEN | RCC_CR_HSIOUTEN | \ + RCC_CR_HSEON | RCC_CR_PLLON); +#else + CLEAR_BIT(vl_mask, RCC_CR_HSION| RCC_CR_HSIKERON| RCC_CR_HSIDIVEN | \ + RCC_CR_HSEON | RCC_CR_PLLON); +#endif + LL_RCC_WriteReg(CR, vl_mask); + /* Delay after an RCC peripheral clock */ + vl_mask = LL_RCC_ReadReg(CR); + + /* Reset HSEBYP bit */ + LL_RCC_HSE_DisableBypass(); + + /* Set RCC_CR_RTCPRE to 0b00*/ + CLEAR_BIT(vl_mask, RCC_CR_RTCPRE); + LL_RCC_WriteReg(CR, vl_mask); + + /* Insure PLL is disabled before to reset PLLSRC/PLLMUL/PLLDIV in CFGR register */ + while(LL_RCC_PLL_IsReady() != 0U) {}; + + /* Reset CFGR register */ + LL_RCC_WriteReg(CFGR, 0x00000000U); + +#if defined(RCC_HSI48_SUPPORT) + + /* Reset CRRCR register to disable HSI48 */ +#if defined(RCC_CRRCR_HSI48DIV6OUTEN) + CLEAR_BIT(RCC->CRRCR, (RCC_CRRCR_HSI48ON | RCC_CRRCR_HSI48DIV6OUTEN)); +#else + CLEAR_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON); +#endif + +#endif /*RCC_HSI48_SUPPORT*/ + + /* Disable all interrupts */ + LL_RCC_WriteReg(CIER, 0x00000000U); + + /* Disable all interrupt flags */ + LL_RCC_WriteReg(CICR, 0xFFFFFFFFU); + + /* Clear reset flags */ + LL_RCC_ClearResetFlags(); + + return SUCCESS; +} + +/** + * @} + */ + +/** @addtogroup RCC_LL_EF_Get_Freq + * @brief Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks + * and different peripheral clocks available on the device. + * @note If SYSCLK source is MSI, function returns values based on MSI clock(*) + * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(**) + * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(***) + * @note If SYSCLK source is PLL, function returns values based on + * HSI_VALUE(**) or HSE_VALUE(***) multiplied/divided by the PLL factors. + * @note (*) MSI clock depends on the selected MSI range but the real value + * may vary depending on the variations in voltage and temperature. + * @note (**) HSI_VALUE is a defined constant but the real value may vary + * depending on the variations in voltage and temperature. + * @note (***) HSE_VALUE is a defined constant, user has to ensure that + * HSE_VALUE is same as the real frequency of the crystal used. + * Otherwise, this function may have wrong result. + * @note The result of this function could be incorrect when using fractional + * value for HSE crystal. + * @note This function can be used by the user application to compute the + * baud-rate for the communication peripherals or configure other parameters. + * @{ + */ + +/** + * @brief Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks + * @note Each time SYSCLK, HCLK, PCLK1 and/or PCLK2 clock changes, this function + * must be called to update structure fields. Otherwise, any + * configuration based on this function will be incorrect. + * @param RCC_Clocks pointer to a @ref LL_RCC_ClocksTypeDef structure which will hold the clocks frequencies + * @retval None + */ +void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks) +{ + /* Get SYSCLK frequency */ + RCC_Clocks->SYSCLK_Frequency = RCC_GetSystemClockFreq(); + + /* HCLK clock frequency */ + RCC_Clocks->HCLK_Frequency = RCC_GetHCLKClockFreq(RCC_Clocks->SYSCLK_Frequency); + + /* PCLK1 clock frequency */ + RCC_Clocks->PCLK1_Frequency = RCC_GetPCLK1ClockFreq(RCC_Clocks->HCLK_Frequency); + + /* PCLK2 clock frequency */ + RCC_Clocks->PCLK2_Frequency = RCC_GetPCLK2ClockFreq(RCC_Clocks->HCLK_Frequency); +} + +/** + * @brief Return USARTx clock frequency + * @param USARTxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_USART1_CLKSOURCE + * @arg @ref LL_RCC_USART2_CLKSOURCE (*) + * + * (*) value not defined in all devices. + * @retval USART clock frequency (in Hz) + * @arg @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready + */ +uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource) +{ + uint32_t usart_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + + /* Check parameter */ + assert_param(IS_LL_RCC_USART_CLKSOURCE(USARTxSource)); +#if defined(RCC_CCIPR_USART1SEL) + if (USARTxSource == LL_RCC_USART1_CLKSOURCE) + { + /* USART1CLK clock frequency */ + switch (LL_RCC_GetUSARTClockSource(USARTxSource)) + { + case LL_RCC_USART1_CLKSOURCE_SYSCLK: /* USART1 Clock is System Clock */ + usart_frequency = RCC_GetSystemClockFreq(); + break; + + case LL_RCC_USART1_CLKSOURCE_HSI: /* USART1 Clock is HSI Osc. */ + if (LL_RCC_HSI_IsReady() != 0U) + { + if (LL_RCC_IsActiveFlag_HSIDIV() != 0U) + { + usart_frequency = (HSI_VALUE >> 2U); + } + else + { + usart_frequency = HSI_VALUE; + } + } + break; + + case LL_RCC_USART1_CLKSOURCE_LSE: /* USART1 Clock is LSE Osc. */ + if (LL_RCC_LSE_IsReady() != 0U) + { + usart_frequency = LSE_VALUE; + } + break; + + case LL_RCC_USART1_CLKSOURCE_PCLK2: /* USART1 Clock is PCLK2 */ + default: + usart_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); + break; + } + } +#endif /* RCC_CCIPR_USART1SEL */ + +#if defined(RCC_CCIPR_USART2SEL) + if (USARTxSource == LL_RCC_USART2_CLKSOURCE) + { + /* USART2CLK clock frequency */ + switch (LL_RCC_GetUSARTClockSource(USARTxSource)) + { + case LL_RCC_USART2_CLKSOURCE_SYSCLK: /* USART2 Clock is System Clock */ + usart_frequency = RCC_GetSystemClockFreq(); + break; + + case LL_RCC_USART2_CLKSOURCE_HSI: /* USART2 Clock is HSI Osc. */ + if (LL_RCC_HSI_IsReady() != 0U) + { + if (LL_RCC_IsActiveFlag_HSIDIV() != 0U) + { + usart_frequency = (HSI_VALUE >> 2U); + } + else + { + usart_frequency = HSI_VALUE; + } + } + break; + + case LL_RCC_USART2_CLKSOURCE_LSE: /* USART2 Clock is LSE Osc. */ + if (LL_RCC_LSE_IsReady() != 0U) + { + usart_frequency = LSE_VALUE; + } + break; + + case LL_RCC_USART2_CLKSOURCE_PCLK1: /* USART2 Clock is PCLK1 */ + default: + usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); + break; + } + } +#endif /* RCC_CCIPR_USART2SEL */ + + return usart_frequency; +} + +/** + * @brief Return I2Cx clock frequency + * @param I2CxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_I2C1_CLKSOURCE + * @arg @ref LL_RCC_I2C3_CLKSOURCE (*) + * + * (*) value not defined in all devices + * @retval I2C clock frequency (in Hz) + * @arg @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that HSI oscillator is not ready + */ +uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource) +{ + uint32_t i2c_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + + /* Check parameter */ + assert_param(IS_LL_RCC_I2C_CLKSOURCE(I2CxSource)); + + /* I2C1 CLK clock frequency */ + if (I2CxSource == LL_RCC_I2C1_CLKSOURCE) + { + switch (LL_RCC_GetI2CClockSource(I2CxSource)) + { + case LL_RCC_I2C1_CLKSOURCE_SYSCLK: /* I2C1 Clock is System Clock */ + i2c_frequency = RCC_GetSystemClockFreq(); + break; + + case LL_RCC_I2C1_CLKSOURCE_HSI: /* I2C1 Clock is HSI Osc. */ + if (LL_RCC_HSI_IsReady() != 0U) + { + if (LL_RCC_IsActiveFlag_HSIDIV() != 0U) + { + i2c_frequency = (HSI_VALUE >> 2U); + } + else + { + i2c_frequency = HSI_VALUE; + } + } + break; + + case LL_RCC_I2C1_CLKSOURCE_PCLK1: /* I2C1 Clock is PCLK1 */ + default: + i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); + break; + } + } + +#if defined(RCC_CCIPR_I2C3SEL) + /* I2C3 CLK clock frequency */ + if (I2CxSource == LL_RCC_I2C3_CLKSOURCE) + { + switch (LL_RCC_GetI2CClockSource(I2CxSource)) + { + case LL_RCC_I2C3_CLKSOURCE_SYSCLK: /* I2C3 Clock is System Clock */ + i2c_frequency = RCC_GetSystemClockFreq(); + break; + + case LL_RCC_I2C3_CLKSOURCE_HSI: /* I2C3 Clock is HSI Osc. */ + if (LL_RCC_HSI_IsReady() != 0U) + { + if (LL_RCC_IsActiveFlag_HSIDIV() != 0U) + { + i2c_frequency = (HSI_VALUE >> 2U); + } + else + { + i2c_frequency = HSI_VALUE; + } + } + break; + + case LL_RCC_I2C3_CLKSOURCE_PCLK1: /* I2C3 Clock is PCLK1 */ + default: + i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); + break; + } + } +#endif /*RCC_CCIPR_I2C3SEL*/ + + return i2c_frequency; +} + +/** + * @brief Return LPUARTx clock frequency + * @param LPUARTxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_LPUART1_CLKSOURCE + * @retval LPUART clock frequency (in Hz) + * @arg @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready + */ +uint32_t LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource) +{ + uint32_t lpuart_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + + /* Check parameter */ + assert_param(IS_LL_RCC_LPUART_CLKSOURCE(LPUARTxSource)); + + /* LPUART1CLK clock frequency */ + switch (LL_RCC_GetLPUARTClockSource(LPUARTxSource)) + { + case LL_RCC_LPUART1_CLKSOURCE_SYSCLK: /* LPUART1 Clock is System Clock */ + lpuart_frequency = RCC_GetSystemClockFreq(); + break; + + case LL_RCC_LPUART1_CLKSOURCE_HSI: /* LPUART1 Clock is HSI Osc. */ + if (LL_RCC_HSI_IsReady() != 0U) + { + if (LL_RCC_IsActiveFlag_HSIDIV() != 0U) + { + lpuart_frequency = (HSI_VALUE >> 2U); + } + else + { + lpuart_frequency = HSI_VALUE; + } + } + break; + + case LL_RCC_LPUART1_CLKSOURCE_LSE: /* LPUART1 Clock is LSE Osc. */ + if (LL_RCC_LSE_IsReady() != 0U) + { + lpuart_frequency = LSE_VALUE; + } + break; + + case LL_RCC_LPUART1_CLKSOURCE_PCLK1: /* LPUART1 Clock is PCLK1 */ + default: + lpuart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); + break; + } + + return lpuart_frequency; +} + +/** + * @brief Return LPTIMx clock frequency + * @param LPTIMxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE + * @retval LPTIM clock frequency (in Hz) + * @arg @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready + */ +uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource) +{ + uint32_t lptim_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + + /* Check parameter */ + assert_param(IS_LL_RCC_LPTIM_CLKSOURCE(LPTIMxSource)); + + if (LPTIMxSource == LL_RCC_LPTIM1_CLKSOURCE) + { + /* LPTIM1CLK clock frequency */ + switch (LL_RCC_GetLPTIMClockSource(LPTIMxSource)) + { + case LL_RCC_LPTIM1_CLKSOURCE_LSI: /* LPTIM1 Clock is LSI Osc. */ + if (LL_RCC_LSI_IsReady() != 0U) + { + lptim_frequency = LSI_VALUE; + } + break; + + case LL_RCC_LPTIM1_CLKSOURCE_HSI: /* LPTIM1 Clock is HSI Osc. */ + if (LL_RCC_HSI_IsReady() != 0U) + { + if (LL_RCC_IsActiveFlag_HSIDIV() != 0U) + { + lptim_frequency = (HSI_VALUE >> 2U); + } + else + { + lptim_frequency = HSI_VALUE; + } + } + break; + + case LL_RCC_LPTIM1_CLKSOURCE_LSE: /* LPTIM1 Clock is LSE Osc. */ + if (LL_RCC_LSE_IsReady() != 0U) + { + lptim_frequency = LSE_VALUE; + } + break; + + case LL_RCC_LPTIM1_CLKSOURCE_PCLK1: /* LPTIM1 Clock is PCLK1 */ + default: + lptim_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); + break; + } + } + + return lptim_frequency; +} + +#if defined(USB) +/** + * @brief Return USBx clock frequency + * @param USBxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_USB_CLKSOURCE + * @retval USB clock frequency (in Hz) + * @arg @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI48) or PLL is not ready + * @arg @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that no clock source selected + */ +uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource) +{ + uint32_t usb_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + + /* Check parameter */ + assert_param(IS_LL_RCC_USB_CLKSOURCE(USBxSource)); + + /* USBCLK clock frequency */ + switch (LL_RCC_GetUSBClockSource(USBxSource)) + { + case LL_RCC_USB_CLKSOURCE_PLL: /* PLL clock used as USB clock source */ + if (LL_RCC_PLL_IsReady() != 0U) + { + usb_frequency = RCC_PLL_GetFreqDomain_SYS(); + } + break; + + case LL_RCC_USB_CLKSOURCE_HSI48: /* HSI48 clock used as USB clock source */ + default: + if (LL_RCC_HSI48_IsReady() != 0U) + { + usb_frequency = HSI48_VALUE; + } + break; + } + + return usb_frequency; +} +#endif /* USB */ + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup RCC_LL_Private_Functions + * @{ + */ + +/** + * @brief Return SYSTEM clock frequency + * @retval SYSTEM clock frequency (in Hz) + */ +uint32_t RCC_GetSystemClockFreq(void) +{ + uint32_t frequency; + + /* Get SYSCLK source -------------------------------------------------------*/ + switch (LL_RCC_GetSysClkSource()) + { + case LL_RCC_SYS_CLKSOURCE_STATUS_MSI: /* MSI used as system clock source */ + frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_GetRange()); + break; + + case LL_RCC_SYS_CLKSOURCE_STATUS_HSI: /* HSI used as system clock source */ + if (LL_RCC_IsActiveFlag_HSIDIV() != 0U) + { + frequency = (HSI_VALUE >> 2U); + } + else + { + frequency = HSI_VALUE; + } + break; + + case LL_RCC_SYS_CLKSOURCE_STATUS_HSE: /* HSE used as system clock source */ + frequency = HSE_VALUE; + break; + + case LL_RCC_SYS_CLKSOURCE_STATUS_PLL: /* PLL used as system clock source */ + frequency = RCC_PLL_GetFreqDomain_SYS(); + break; + + default: + frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_GetRange()); + break; + } + + return frequency; +} + +/** + * @brief Return HCLK clock frequency + * @param SYSCLK_Frequency SYSCLK clock frequency + * @retval HCLK clock frequency (in Hz) + */ +uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency) +{ + /* HCLK clock frequency */ + return __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, LL_RCC_GetAHBPrescaler()); +} + +/** + * @brief Return PCLK1 clock frequency + * @param HCLK_Frequency HCLK clock frequency + * @retval PCLK1 clock frequency (in Hz) + */ +uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency) +{ + /* PCLK1 clock frequency */ + return __LL_RCC_CALC_PCLK1_FREQ(HCLK_Frequency, LL_RCC_GetAPB1Prescaler()); +} + +/** + * @brief Return PCLK2 clock frequency + * @param HCLK_Frequency HCLK clock frequency + * @retval PCLK2 clock frequency (in Hz) + */ +uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency) +{ + /* PCLK2 clock frequency */ + return __LL_RCC_CALC_PCLK2_FREQ(HCLK_Frequency, LL_RCC_GetAPB2Prescaler()); +} + +/** + * @brief Return PLL clock frequency used for system domain + * @retval PLL clock frequency (in Hz) + */ +uint32_t RCC_PLL_GetFreqDomain_SYS(void) +{ + uint32_t pllinputfreq, pllsource; + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL divider) * PLL Multiplicator */ + + /* Get PLL source */ + pllsource = LL_RCC_PLL_GetMainSource(); + + switch (pllsource) + { + case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ + if (LL_RCC_IsActiveFlag_HSIDIV() != 0U) + { + pllinputfreq = (HSI_VALUE >> 2U); + } + else + { + pllinputfreq = HSI_VALUE; + } + break; + + default: /* HSE used as PLL clock source */ + pllinputfreq = HSE_VALUE; + break; + } + return __LL_RCC_CALC_PLLCLK_FREQ(pllinputfreq, LL_RCC_PLL_GetMultiplicator(), LL_RCC_PLL_GetDivider()); +} +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined(RCC) */ + +/** + * @} + */ + +#endif /* USE_FULL_LL_DRIVER */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/fw/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c b/fw/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c new file mode 100644 index 0000000..536bba5 --- /dev/null +++ b/fw/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c @@ -0,0 +1,591 @@ +/** + ****************************************************************************** + * @file stm32l0xx_ll_utils.c + * @author MCD Application Team + * @brief UTILS LL module driver. + ****************************************************************************** + * @attention + * + *

© Copyright(c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ +/* Includes ------------------------------------------------------------------*/ +#include "stm32l0xx_ll_rcc.h" +#include "stm32l0xx_ll_utils.h" +#include "stm32l0xx_ll_system.h" +#include "stm32l0xx_ll_pwr.h" +#ifdef USE_FULL_ASSERT +#include "stm32_assert.h" +#else +#define assert_param(expr) ((void)0U) +#endif + +/** @addtogroup STM32L0xx_LL_Driver + * @{ + */ + +/** @addtogroup UTILS_LL + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @addtogroup UTILS_LL_Private_Constants + * @{ + */ +#define UTILS_MAX_FREQUENCY_SCALE1 (32000000U) /*!< Maximum frequency for system clock at power scale1, in Hz */ +#define UTILS_MAX_FREQUENCY_SCALE2 (16000000U) /*!< Maximum frequency for system clock at power scale2, in Hz */ +#define UTILS_MAX_FREQUENCY_SCALE3 (4194304U) /*!< Maximum frequency for system clock at power scale3, in Hz */ + +/* Defines used for PLL range */ +#define UTILS_PLLVCO_OUTPUT_SCALE1 (96000000U) /*!< Frequency max for PLLVCO output at power scale1, in Hz */ +#define UTILS_PLLVCO_OUTPUT_SCALE2 (48000000U) /*!< Frequency max for PLLVCO output at power scale2, in Hz */ +#define UTILS_PLLVCO_OUTPUT_SCALE3 (24000000U) /*!< Frequency max for PLLVCO output at power scale3, in Hz */ + +/* Defines used for HSE range */ +#define UTILS_HSE_FREQUENCY_MIN (1000000U) /*!< Frequency min for HSE frequency, in Hz */ +#define UTILS_HSE_FREQUENCY_MAX (24000000U) /*!< Frequency max for HSE frequency, in Hz */ + +/* Defines used for FLASH latency according to HCLK Frequency */ +#define UTILS_SCALE1_LATENCY1_FREQ (16000000U) /*!< HCLK frequency to set FLASH latency 1 in power scale 1 */ +#define UTILS_SCALE2_LATENCY1_FREQ (8000000U) /*!< HCLK frequency to set FLASH latency 1 in power scale 2 */ +#define UTILS_SCALE3_LATENCY1_FREQ (2000000U) /*!< HCLK frequency to set FLASH latency 1 in power scale 3 */ +/** + * @} + */ +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup UTILS_LL_Private_Macros + * @{ + */ +#define IS_LL_UTILS_SYSCLK_DIV(__VALUE__) (((__VALUE__) == LL_RCC_SYSCLK_DIV_1) \ + || ((__VALUE__) == LL_RCC_SYSCLK_DIV_2) \ + || ((__VALUE__) == LL_RCC_SYSCLK_DIV_4) \ + || ((__VALUE__) == LL_RCC_SYSCLK_DIV_8) \ + || ((__VALUE__) == LL_RCC_SYSCLK_DIV_16) \ + || ((__VALUE__) == LL_RCC_SYSCLK_DIV_64) \ + || ((__VALUE__) == LL_RCC_SYSCLK_DIV_128) \ + || ((__VALUE__) == LL_RCC_SYSCLK_DIV_256) \ + || ((__VALUE__) == LL_RCC_SYSCLK_DIV_512)) + +#define IS_LL_UTILS_APB1_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB1_DIV_1) \ + || ((__VALUE__) == LL_RCC_APB1_DIV_2) \ + || ((__VALUE__) == LL_RCC_APB1_DIV_4) \ + || ((__VALUE__) == LL_RCC_APB1_DIV_8) \ + || ((__VALUE__) == LL_RCC_APB1_DIV_16)) + +#define IS_LL_UTILS_APB2_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB2_DIV_1) \ + || ((__VALUE__) == LL_RCC_APB2_DIV_2) \ + || ((__VALUE__) == LL_RCC_APB2_DIV_4) \ + || ((__VALUE__) == LL_RCC_APB2_DIV_8) \ + || ((__VALUE__) == LL_RCC_APB2_DIV_16)) + +#define IS_LL_UTILS_PLLMUL_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLL_MUL_3) \ + || ((__VALUE__) == LL_RCC_PLL_MUL_4) \ + || ((__VALUE__) == LL_RCC_PLL_MUL_6) \ + || ((__VALUE__) == LL_RCC_PLL_MUL_8) \ + || ((__VALUE__) == LL_RCC_PLL_MUL_12) \ + || ((__VALUE__) == LL_RCC_PLL_MUL_16) \ + || ((__VALUE__) == LL_RCC_PLL_MUL_24) \ + || ((__VALUE__) == LL_RCC_PLL_MUL_32) \ + || ((__VALUE__) == LL_RCC_PLL_MUL_48)) + +#define IS_LL_UTILS_PLLDIV_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLL_DIV_2) || ((__VALUE__) == LL_RCC_PLL_DIV_3) || \ + ((__VALUE__) == LL_RCC_PLL_DIV_4)) + +#define IS_LL_UTILS_PLLVCO_OUTPUT(__VALUE__) ((LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1) ? ((__VALUE__) <= UTILS_PLLVCO_OUTPUT_SCALE1) : \ + ((LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE2) ? ((__VALUE__) <= UTILS_PLLVCO_OUTPUT_SCALE2) : \ + ((__VALUE__) <= UTILS_PLLVCO_OUTPUT_SCALE3))) + +#define IS_LL_UTILS_PLL_FREQUENCY(__VALUE__) ((LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1) ? ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE1) : \ + ((LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE2) ? ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE2) : \ + ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE3))) + +#define IS_LL_UTILS_HSE_BYPASS(__STATE__) (((__STATE__) == LL_UTILS_HSEBYPASS_ON) \ + || ((__STATE__) == LL_UTILS_HSEBYPASS_OFF)) + +#define IS_LL_UTILS_HSE_FREQUENCY(__FREQUENCY__) (((__FREQUENCY__) >= UTILS_HSE_FREQUENCY_MIN) && ((__FREQUENCY__) <= UTILS_HSE_FREQUENCY_MAX)) +/** + * @} + */ +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup UTILS_LL_Private_Functions UTILS Private functions + * @{ + */ +static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, + LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct); +static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct); +static ErrorStatus UTILS_PLL_IsBusy(void); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup UTILS_LL_Exported_Functions + * @{ + */ + +/** @addtogroup UTILS_LL_EF_DELAY + * @{ + */ + +/** + * @brief This function configures the Cortex-M SysTick source to have 1ms time base. + * @note When a RTOS is used, it is recommended to avoid changing the Systick + * configuration by calling this function, for a delay use rather osDelay RTOS service. + * @param HCLKFrequency HCLK frequency in Hz + * @note HCLK frequency can be calculated thanks to RCC helper macro or function @ref LL_RCC_GetSystemClocksFreq + * @retval None + */ +void LL_Init1msTick(uint32_t HCLKFrequency) +{ + /* Use frequency provided in argument */ + LL_InitTick(HCLKFrequency, 1000U); +} + +/** + * @brief This function provides accurate delay (in milliseconds) based + * on SysTick counter flag + * @note When a RTOS is used, it is recommended to avoid using blocking delay + * and use rather osDelay service. + * @note To respect 1ms timebase, user should call @ref LL_Init1msTick function which + * will configure Systick to 1ms + * @param Delay specifies the delay time length, in milliseconds. + * @retval None + */ +void LL_mDelay(uint32_t Delay) +{ + __IO uint32_t tmp = SysTick->CTRL; /* Clear the COUNTFLAG first */ + /* Add this code to indicate that local variable is not used */ + ((void)tmp); + + /* Add a period to guaranty minimum wait */ + if (Delay < LL_MAX_DELAY) + { + Delay++; + } + + while (Delay) + { + if ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) != 0U) + { + Delay--; + } + } +} + +/** + * @} + */ + +/** @addtogroup UTILS_EF_SYSTEM + * @brief System Configuration functions + * + @verbatim + =============================================================================== + ##### System Configuration functions ##### + =============================================================================== + [..] + System, AHB and APB buses clocks configuration + + (+) The maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is 32000000 Hz. + @endverbatim + @internal + Depending on the device voltage range, the maximum frequency should be + adapted accordingly: + (++) +----------------------------------------------------------------+ + (++) | Wait states | HCLK clock frequency (MHz) | + (++) | |------------------------------------------------| + (++) | (Latency) | voltage range | voltage range | + (++) | | 1.65 V - 3.6 V | 2.0 V - 3.6 V | + (++) | |----------------|---------------|---------------| + (++) | | VCORE = 1.2 V | VCORE = 1.5 V | VCORE = 1.8 V | + (++) |-------------- |----------------|---------------|---------------| + (++) |0WS(1CPU cycle)|0 < HCLK <= 2 |0 < HCLK <= 8 |0 < HCLK <= 16 | + (++) |---------------|----------------|---------------|---------------| + (++) |1WS(2CPU cycle)|2 < HCLK <= 4 |8 < HCLK <= 16 |16 < HCLK <= 32| + (++) +----------------------------------------------------------------+ + @endinternal + * @{ + */ + +/** + * @brief This function sets directly SystemCoreClock CMSIS variable. + * @note Variable can be calculated also through SystemCoreClockUpdate function. + * @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro) + * @retval None + */ +void LL_SetSystemCoreClock(uint32_t HCLKFrequency) +{ + /* HCLK clock frequency */ + SystemCoreClock = HCLKFrequency; +} + +/** + * @brief Update number of Flash wait states in line with new frequency and current + voltage range. + * @param Frequency HCLK frequency + * @retval An ErrorStatus enumeration value: + * - SUCCESS: Latency has been modified + * - ERROR: Latency cannot be modified + */ +ErrorStatus LL_SetFlashLatency(uint32_t Frequency) +{ + uint32_t timeout; + uint32_t getlatency; + uint32_t latency; + ErrorStatus status = SUCCESS; + + /* Frequency cannot be equal to 0 */ + if ((Frequency == 0U) || (Frequency > UTILS_MAX_FREQUENCY_SCALE1)) + { + status = ERROR; + } + else + { + if (LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1) + { + if (Frequency > UTILS_SCALE1_LATENCY1_FREQ) + { + /* 16 < HCLK <= 32 => 1WS (2 CPU cycles) */ + latency = LL_FLASH_LATENCY_1; + } + else + { + /* else HCLK < 16MHz default LL_FLASH_LATENCY_0 0WS */ + latency = LL_FLASH_LATENCY_0; + } + } + else if (LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE2) + { + if (Frequency > UTILS_SCALE2_LATENCY1_FREQ) + { + /* 8 < HCLK <= 16 => 1WS (2 CPU cycles) */ + latency = LL_FLASH_LATENCY_1; + } + else + { + /* else HCLK < 8MHz default LL_FLASH_LATENCY_0 0WS */ + latency = LL_FLASH_LATENCY_0; + } + } + else + { + if (Frequency > UTILS_SCALE3_LATENCY1_FREQ) + { + /* 2 < HCLK <= 4 => 1WS (2 CPU cycles) */ + latency = LL_FLASH_LATENCY_1; + } + else + { + /* else HCLK < 2MHz default LL_FLASH_LATENCY_0 0WS */ + latency = LL_FLASH_LATENCY_0; + } + } + + if (status != ERROR) + { + LL_FLASH_SetLatency(latency); + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + timeout = 2; + do + { + /* Wait for Flash latency to be updated */ + getlatency = LL_FLASH_GetLatency(); + timeout--; + } while ((getlatency != latency) && (timeout > 0)); + + if(getlatency != latency) + { + status = ERROR; + } + else + { + status = SUCCESS; + } + } + } + return status; +} + +/** + * @brief This function configures system clock with HSI as clock source of the PLL + * @note The application need to ensure that PLL is disabled. + * @note Function is based on the following formula: + * - PLL output frequency = ((HSI frequency * PLLMul) / PLLDiv) + * - PLLMul: The application software must set correctly the PLL multiplication factor to ensure + * - PLLVCO does not exceed 96 MHz when the product is in range 1, + * - PLLVCO does not exceed 48 MHz when the product is in range 2, + * - PLLVCO does not exceed 24 MHz when the product is in range 3 + * @note FLASH latency can be modified through this function. + * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains + * the configuration information for the PLL. + * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains + * the configuration information for the BUS prescalers. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: Max frequency configuration done + * - ERROR: Max frequency configuration not done + */ +ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, + LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct) +{ + ErrorStatus status = SUCCESS; + uint32_t pllfreq = 0U; + + /* Check if one of the PLL is enabled */ + if (UTILS_PLL_IsBusy() == SUCCESS) + { + /* Calculate the new PLL output frequency */ + pllfreq = UTILS_GetPLLOutputFrequency(HSI_VALUE, UTILS_PLLInitStruct); + + /* Enable HSI if not enabled */ + if (LL_RCC_HSI_IsReady() != 1U) + { + LL_RCC_HSI_Enable(); + while (LL_RCC_HSI_IsReady() != 1U) + { + /* Wait for HSI ready */ + } + } + + /* Configure PLL */ + LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI, UTILS_PLLInitStruct->PLLMul, UTILS_PLLInitStruct->PLLDiv); + + /* Enable PLL and switch system clock to PLL */ + status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct); + } + else + { + /* Current PLL configuration cannot be modified */ + status = ERROR; + } + + return status; +} + +/** + * @brief This function configures system clock with HSE as clock source of the PLL + * @note The application need to ensure that PLL is disabled. + * @note Function is based on the following formula: + * - PLL output frequency = ((HSE frequency * PLLMul) / PLLDiv) + * - PLLMul: The application software must set correctly the PLL multiplication factor to to ensure + * - PLLVCO does not exceed 96 MHz when the product is in range 1, + * - PLLVCO does not exceed 48 MHz when the product is in range 2, + * - PLLVCO does not exceed 24 MHz when the product is in range 3 + * @note FLASH latency can be modified through this function. + * @param HSEFrequency Value between Min_Data = 1000000 and Max_Data = 24000000 + * @param HSEBypass This parameter can be one of the following values: + * @arg @ref LL_UTILS_HSEBYPASS_ON + * @arg @ref LL_UTILS_HSEBYPASS_OFF + * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains + * the configuration information for the PLL. + * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains + * the configuration information for the BUS prescalers. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: Max frequency configuration done + * - ERROR: Max frequency configuration not done + */ +ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass, + LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct) +{ + ErrorStatus status = SUCCESS; + uint32_t pllfreq = 0U; + + /* Check the parameters */ + assert_param(IS_LL_UTILS_HSE_FREQUENCY(HSEFrequency)); + assert_param(IS_LL_UTILS_HSE_BYPASS(HSEBypass)); + + /* Check if one of the PLL is enabled */ + if (UTILS_PLL_IsBusy() == SUCCESS) + { + /* Calculate the new PLL output frequency */ + pllfreq = UTILS_GetPLLOutputFrequency(HSEFrequency, UTILS_PLLInitStruct); + + /* Enable HSE if not enabled */ + if (LL_RCC_HSE_IsReady() != 1U) + { + /* Check if need to enable HSE bypass feature or not */ + if (HSEBypass == LL_UTILS_HSEBYPASS_ON) + { + LL_RCC_HSE_EnableBypass(); + } + else + { + LL_RCC_HSE_DisableBypass(); + } + + /* Enable HSE */ + LL_RCC_HSE_Enable(); + while (LL_RCC_HSE_IsReady() != 1U) + { + /* Wait for HSE ready */ + } + } + + /* Configure PLL */ + LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSE, UTILS_PLLInitStruct->PLLMul, UTILS_PLLInitStruct->PLLDiv); + + /* Enable PLL and switch system clock to PLL */ + status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct); + } + else + { + /* Current PLL configuration cannot be modified */ + status = ERROR; + } + + return status; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup UTILS_LL_Private_Functions + * @{ + */ +/** + * @brief Function to check that PLL can be modified + * @param PLL_InputFrequency PLL input frequency (in Hz) + * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains + * the configuration information for the PLL. + * @retval PLL output frequency (in Hz) + */ +static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct) +{ + uint32_t pllfreq = 0U; + + /* Check the parameters */ + assert_param(IS_LL_UTILS_PLLMUL_VALUE(UTILS_PLLInitStruct->PLLMul)); + assert_param(IS_LL_UTILS_PLLDIV_VALUE(UTILS_PLLInitStruct->PLLDiv)); + + /* Check different PLL parameters according to RM */ + /* The application software must set correctly the PLL multiplication factor to avoid exceeding + 96 MHz as PLLVCO when the product is in range 1, + 48 MHz as PLLVCO when the product is in range 2, + 24 MHz when the product is in range 3. */ + pllfreq = PLL_InputFrequency * (PLLMulTable[UTILS_PLLInitStruct->PLLMul >> RCC_CFGR_PLLMUL_Pos]); + assert_param(IS_LL_UTILS_PLLVCO_OUTPUT(pllfreq)); + + /* The application software must set correctly the PLL multiplication factor to avoid exceeding + maximum frequency 32000000 in range 1 */ + pllfreq = pllfreq / ((UTILS_PLLInitStruct->PLLDiv >> RCC_CFGR_PLLDIV_Pos)+1U); + assert_param(IS_LL_UTILS_PLL_FREQUENCY(pllfreq)); + + return pllfreq; +} + +/** + * @brief Function to check that PLL can be modified + * @retval An ErrorStatus enumeration value: + * - SUCCESS: PLL modification can be done + * - ERROR: PLL is busy + */ +static ErrorStatus UTILS_PLL_IsBusy(void) +{ + ErrorStatus status = SUCCESS; + + /* Check if PLL is busy*/ + if (LL_RCC_PLL_IsReady() != 0U) + { + /* PLL configuration cannot be modified */ + status = ERROR; + } + + + return status; +} + +/** + * @brief Function to enable PLL and switch system clock to PLL + * @param SYSCLK_Frequency SYSCLK frequency + * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains + * the configuration information for the BUS prescalers. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: No problem to switch system to PLL + * - ERROR: Problem to switch system to PLL + */ +static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct) +{ + ErrorStatus status = SUCCESS; + uint32_t hclk_frequency = 0U; + + assert_param(IS_LL_UTILS_SYSCLK_DIV(UTILS_ClkInitStruct->AHBCLKDivider)); + assert_param(IS_LL_UTILS_APB1_DIV(UTILS_ClkInitStruct->APB1CLKDivider)); + assert_param(IS_LL_UTILS_APB2_DIV(UTILS_ClkInitStruct->APB2CLKDivider)); + + /* Calculate HCLK frequency */ + hclk_frequency = __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, UTILS_ClkInitStruct->AHBCLKDivider); + + /* Increasing the number of wait states because of higher CPU frequency */ + if (SystemCoreClock < hclk_frequency) + { + /* Set FLASH latency to highest latency */ + status = LL_SetFlashLatency(hclk_frequency); + } + + /* Update system clock configuration */ + if (status == SUCCESS) + { + /* Enable PLL */ + LL_RCC_PLL_Enable(); + while (LL_RCC_PLL_IsReady() != 1U) + { + /* Wait for PLL ready */ + } + + /* Sysclk activation on the main PLL */ + LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider); + LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL); + while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL) + { + /* Wait for system clock switch to PLL */ + } + + /* Set APB1 & APB2 prescaler*/ + LL_RCC_SetAPB1Prescaler(UTILS_ClkInitStruct->APB1CLKDivider); + LL_RCC_SetAPB2Prescaler(UTILS_ClkInitStruct->APB2CLKDivider); + } + + /* Decreasing the number of wait states because of lower CPU frequency */ + if (SystemCoreClock > hclk_frequency) + { + /* Set FLASH latency to lowest latency */ + status = LL_SetFlashLatency(hclk_frequency); + } + + /* Update SystemCoreClock variable */ + if (status == SUCCESS) + { + LL_SetSystemCoreClock(hclk_frequency); + } + + return status; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/fw/iaq_wired_sensor.ioc b/fw/iaq_wired_sensor.ioc index 310fb6c..c9fcb34 100644 --- a/fw/iaq_wired_sensor.ioc +++ b/fw/iaq_wired_sensor.ioc @@ -1,121 +1,145 @@ #MicroXplorer Configuration settings - do not modify -File.Version=6 -GPIO.groupedBy=Group By Peripherals -KeepUserPlacement=false Mcu.Family=STM32L0 -Mcu.IP0=I2C1 -Mcu.IP1=LPUART1 -Mcu.IP2=NVIC -Mcu.IP3=RCC -Mcu.IP4=SYS -Mcu.IPNb=5 -Mcu.Name=STM32L011F(3-4)Ux -Mcu.Package=UFQFPN20 +PA6.GPIOParameters=PinState,GPIO_Label +RCC.MSI_VALUE=2097000 +ProjectManager.MainLocation=Core/Src +ProjectManager.ProjectFileName=iaq_wired_sensor.ioc +ProjectManager.KeepUserCode=true +PA10.Mode=I2C +Mcu.UserName=STM32L011F4Ux +Mcu.PinsNb=11 +ProjectManager.NoMain=false +PA0-CK_IN.Mode=Asynchronous +RCC.LPUARTFreq_Value=2097000 +RCC.PLLCLKFreq_Value=24000000 +ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-LL-true,2-MX_DMA_Init-DMA-false-LL-true,3-SystemClock_Config-RCC-false-HAL-false,4-MX_I2C1_Init-I2C1-false-LL-true,5-MX_LPUART1_UART_Init-LPUART1-false-LL-true +Dma.LPUART1_RX.0.MemDataAlignment=DMA_MDATAALIGN_BYTE +RCC.RTCFreq_Value=37000 +LPUART1.WordLength=UART_WORDLENGTH_8B +ProjectManager.DefaultFWLocation=true +PA6.GPIO_Label=LED_G +PA6.PinState=GPIO_PIN_SET +RCC.USART2Freq_Value=2097000 +Dma.LPUART1_RX.0.Direction=DMA_PERIPH_TO_MEMORY +Dma.LPUART1_RX.0.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority +NVIC.SVC_IRQn=true\:0\:0\:false\:false\:true\:false\:false +ProjectManager.DeletePrevious=true +PA5.PinState=GPIO_PIN_SET +LPUART1.UART_DEDeassertionTime=20 +Dma.LPUART1_RX.0.Instance=DMA1_Channel3 +LPUART1.IPParameters=BaudRate,SwapParam,OneBitSampling,UART_DEAssertionTime,UART_DEDeassertionTime,UART_DEPolarity,WordLength +PinOutPanel.RotationAngle=0 +RCC.FamilyName=M +ProjectManager.StackSize=0x400 +Dma.LPUART1_RX.0.PeriphInc=DMA_PINC_DISABLE +RCC.WatchDogFreq_Value=37000 +LPUART1.UART_DEAssertionTime=20 +PA13.Signal=SYS_SWDIO +Mcu.IP4=RCC +RCC.HSI16_VALUE=16000000 +Mcu.IP5=SYS +Mcu.IP2=LPUART1 +Mcu.IP3=NVIC +LPUART1.UART_DEPolarity=UART_DE_POLARITY_HIGH +LPUART1.OneBitSampling=UART_ONE_BIT_SAMPLE_ENABLE +Mcu.IP0=DMA +PA9.Mode=I2C +Mcu.IP1=I2C1 +Mcu.UserConstants= +PA7.PinState=GPIO_PIN_SET +ProjectManager.TargetToolchain=STM32CubeIDE +Mcu.ThirdPartyNb=0 +Mcu.IPNb=6 +ProjectManager.PreviousToolchain= +RCC.APB2TimFreq_Value=2097000 +PA9.Signal=I2C1_SCL +Mcu.Pin6=PA9 +Mcu.Pin7=PA10 +ProjectManager.RegisterCallBack= +Mcu.Pin8=PA13 +Mcu.Pin9=PA14 +RCC.LSE_VALUE=32768 +PA1.Signal=LPUART1_TX +RCC.AHBFreq_Value=2097000 Mcu.Pin0=PA0-CK_IN Mcu.Pin1=PA1 +GPIO.groupedBy=Group By Peripherals Mcu.Pin2=PA5 Mcu.Pin3=PA6 Mcu.Pin4=PA7 -Mcu.Pin5=PA9 -Mcu.Pin6=PA10 -Mcu.Pin7=PA13 -Mcu.Pin8=PA14 -Mcu.Pin9=VP_SYS_VS_Systick -Mcu.PinsNb=10 -Mcu.ThirdPartyNb=0 -Mcu.UserConstants= -Mcu.UserName=STM32L011F4Ux -MxCube.Version=6.1.0 -MxDb.Version=DB.6.0.10 -NVIC.ForceEnableDMAVector=true -NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false -NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false -NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false -NVIC.SVC_IRQn=true\:0\:0\:false\:false\:true\:false\:false -NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false\:true -PA0-CK_IN.Mode=Asynchronous -PA0-CK_IN.Signal=LPUART1_RX -PA1.Mode=Asynchronous -PA1.Signal=LPUART1_TX -PA10.Mode=I2C -PA10.Signal=I2C1_SDA -PA13.Mode=Serial_Wire -PA13.Signal=SYS_SWDIO -PA14.Mode=Serial_Wire -PA14.Signal=SYS_SWCLK -PA5.GPIOParameters=PinState,GPIO_Label -PA5.GPIO_Label=LED_B -PA5.Locked=true -PA5.PinState=GPIO_PIN_SET +Mcu.Pin5=PB1 +Dma.LPUART1_RX.0.PeriphDataAlignment=DMA_PDATAALIGN_BYTE PA5.Signal=GPIO_Output -PA6.GPIOParameters=PinState,GPIO_Label -PA6.GPIO_Label=LED_G -PA6.Locked=true -PA6.PinState=GPIO_PIN_SET -PA6.Signal=GPIO_Output -PA7.GPIOParameters=PinState,GPIO_Label -PA7.GPIO_Label=LED_R -PA7.Locked=true -PA7.PinState=GPIO_PIN_SET -PA7.Signal=GPIO_Output -PA9.Locked=true -PA9.Mode=I2C -PA9.Signal=I2C1_SCL -PinOutPanel.RotationAngle=0 -ProjectManager.AskForMigrate=true -ProjectManager.BackupPrevious=false -ProjectManager.CompilerOptimize=6 -ProjectManager.ComputerToolchain=false -ProjectManager.CoupleFile=false -ProjectManager.CustomerFirmwarePackage= -ProjectManager.DefaultFWLocation=true -ProjectManager.DeletePrevious=true -ProjectManager.DeviceId=STM32L011F4Ux -ProjectManager.FirmwarePackage=STM32Cube FW_L0 V1.12.0 -ProjectManager.FreePins=false -ProjectManager.HalAssertFull=false -ProjectManager.HeapSize=0x200 -ProjectManager.KeepUserCode=true -ProjectManager.LastFirmware=true -ProjectManager.LibraryCopy=1 -ProjectManager.MainLocation=Core/Src -ProjectManager.NoMain=false -ProjectManager.PreviousToolchain= ProjectManager.ProjectBuild=false -ProjectManager.ProjectFileName=iaq_wired_sensor.ioc -ProjectManager.ProjectName=iaq_wired_sensor -ProjectManager.RegisterCallBack= -ProjectManager.StackSize=0x400 -ProjectManager.TargetToolchain=STM32CubeIDE -ProjectManager.ToolChainLocation= -ProjectManager.UnderRoot=true -ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_I2C1_Init-I2C1-false-HAL-true,4-MX_LPUART1_UART_Init-LPUART1-false-HAL-true,5-MX_LPTIM1_Init-LPTIM1-false-HAL-true -RCC.AHBFreq_Value=2097000 -RCC.APB1Freq_Value=2097000 -RCC.APB1TimFreq_Value=2097000 -RCC.APB2Freq_Value=2097000 -RCC.APB2TimFreq_Value=2097000 -RCC.FamilyName=M RCC.HSE_VALUE=8000000 -RCC.HSI16_VALUE=16000000 -RCC.HSI_VALUE=16000000 -RCC.I2C1Freq_Value=2097000 -RCC.IPParameters=AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,FamilyName,HSE_VALUE,HSI16_VALUE,HSI_VALUE,I2C1Freq_Value,LPTIMFreq_Value,LPUARTFreq_Value,LSE_VALUE,LSI_VALUE,MSI_VALUE,PLLCLKFreq_Value,PWRFreq_Value,RTCFreq_Value,RTCHSEDivFreq_Value,SYSCLKFreq_VALUE,TIMFreq_Value,USART2Freq_Value,VCOOutputFreq_Value,WatchDogFreq_Value -RCC.LPTIMFreq_Value=2097000 -RCC.LPUARTFreq_Value=2097000 -RCC.LSE_VALUE=32768 -RCC.LSI_VALUE=37000 -RCC.MSI_VALUE=2097000 -RCC.PLLCLKFreq_Value=24000000 -RCC.PWRFreq_Value=2097000 -RCC.RTCFreq_Value=37000 -RCC.RTCHSEDivFreq_Value=4000000 -RCC.SYSCLKFreq_VALUE=2097000 -RCC.TIMFreq_Value=2097000 -RCC.USART2Freq_Value=2097000 -RCC.VCOOutputFreq_Value=48000000 -RCC.WatchDogFreq_Value=37000 -VP_SYS_VS_Systick.Mode=SysTick -VP_SYS_VS_Systick.Signal=SYS_VS_Systick board=custom +RCC.VCOOutputFreq_Value=48000000 +Dma.LPUART1_RX.0.MemInc=DMA_MINC_ENABLE +NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false\:true +ProjectManager.LastFirmware=true +ProjectManager.FirmwarePackage=STM32Cube FW_L0 V1.12.0 +PA0-CK_IN.Signal=LPUART1_RX +MxDb.Version=DB.6.0.10 +RCC.APB2Freq_Value=2097000 +PA1.Mode=Asynchronous +ProjectManager.BackupPrevious=false +MxCube.Version=6.1.0 +RCC.I2C1Freq_Value=2097000 +PA14.Mode=Serial_Wire +File.Version=6 +VP_SYS_VS_Systick.Mode=SysTick +PA9.Locked=true +NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false +Dma.LPUART1_RX.0.Priority=DMA_PRIORITY_MEDIUM +NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false +PA13.Mode=Serial_Wire +ProjectManager.FreePins=false +RCC.IPParameters=AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,FamilyName,HSE_VALUE,HSI16_VALUE,HSI_VALUE,I2C1Freq_Value,LPTIMFreq_Value,LPUARTFreq_Value,LSE_VALUE,LSI_VALUE,MSI_VALUE,PLLCLKFreq_Value,PWRFreq_Value,RTCFreq_Value,RTCHSEDivFreq_Value,SYSCLKFreq_VALUE,TIMFreq_Value,USART2Freq_Value,VCOOutputFreq_Value,WatchDogFreq_Value +ProjectManager.AskForMigrate=true +Mcu.Name=STM32L011F(3-4)Ux +Dma.RequestsNb=1 +ProjectManager.HalAssertFull=false +LPUART1.BaudRate=115200 +RCC.RTCHSEDivFreq_Value=4000000 +ProjectManager.ProjectName=iaq_wired_sensor +ProjectManager.UnderRoot=true +ProjectManager.CoupleFile=false +RCC.SYSCLKFreq_VALUE=2097000 +Mcu.Package=UFQFPN20 +PB1.Signal=LPUART1_DE +PA6.Signal=GPIO_Output +PA7.GPIO_Label=LED_R +Dma.LPUART1_RX.0.Mode=DMA_CIRCULAR +PA7.Locked=true +PA5.Locked=true +LPUART1.SwapParam=UART_ADVFEATURE_SWAP_DISABLE +PA5.GPIO_Label=LED_B +NVIC.ForceEnableDMAVector=true +KeepUserPlacement=false +ProjectManager.CompilerOptimize=6 +ProjectManager.ToolChainLocation= +RCC.LSI_VALUE=37000 +VP_SYS_VS_Systick.Signal=SYS_VS_Systick +PA10.Signal=I2C1_SDA +PA14.Signal=SYS_SWCLK +ProjectManager.HeapSize=0x200 +NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false +PB1.Mode=Hardware Flow Control (RS485) +PA5.GPIOParameters=PinState,GPIO_Label +ProjectManager.ComputerToolchain=false +RCC.HSI_VALUE=16000000 +Mcu.Pin10=VP_SYS_VS_Systick +NVIC.DMA1_Channel2_3_IRQn=true\:0\:0\:false\:false\:true\:false\:true +RCC.APB1TimFreq_Value=2097000 +RCC.PWRFreq_Value=2097000 +RCC.APB1Freq_Value=2097000 +Dma.Request0=LPUART1_RX +PA7.GPIOParameters=PinState,GPIO_Label +ProjectManager.CustomerFirmwarePackage= +ProjectManager.DeviceId=STM32L011F4Ux +ProjectManager.LibraryCopy=1 +RCC.LPTIMFreq_Value=2097000 +PA7.Signal=GPIO_Output +RCC.TIMFreq_Value=2097000 +PA6.Locked=true isbadioc=false