From 995d6f4e5707b821f62f452f2f81c95bcd74a025 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?David=20=C5=BDaitl=C3=ADk?= <d.zaitlik@protonmail.com>
Date: Sun, 7 Nov 2021 11:23:52 +0100
Subject: [PATCH] Minor tweaks trying to get the i2c working. SCD4x still not
working.
---
fw_hal/Core/Src/scd4x.c | 2 +-
fw_hal/Debug/Core/Src/i2c.o | Bin 584816 -> 584840 bytes
fw_hal/Debug/Core/Src/i2c.su | 4 +-
fw_hal/Debug/iaq_wired_sensor_hal.bin | Bin 17360 -> 17376 bytes
fw_hal/Debug/iaq_wired_sensor_hal.elf | Bin 766504 -> 766504 bytes
fw_hal/Debug/iaq_wired_sensor_hal.list | 15079 ++++++++++++-----------
fw_hal/Debug/iaq_wired_sensor_hal.map | 442 +-
fw_hal/iaq_wired_sensor_hal.ioc | 3 +-
8 files changed, 7769 insertions(+), 7761 deletions(-)
diff --git a/fw_hal/Core/Src/scd4x.c b/fw_hal/Core/Src/scd4x.c
index 64722be..0ba185f 100644
--- a/fw_hal/Core/Src/scd4x.c
+++ b/fw_hal/Core/Src/scd4x.c
@@ -88,7 +88,7 @@ int8_t scd4x_read_measurement(uint16_t * co2, int16_t *temperature, uint16_t *re
// {
// return SCD4X_ERROR;
// }
- result = i2c_transmit_receive(SCD4X_I2C_ADDRESS<<1, SCD4X_READ_MEASUREMENT, 2, buffer, 9);
+ result = i2c_transmit_receive(SCD4X_I2C_ADDRESS<<1, SCD4X_READ_MEASUREMENT, I2C_MEMADD_SIZE_16BIT, buffer, 9);
if (result != I2C_OK)
{
return SCD4X_ERROR;
diff --git a/fw_hal/Debug/Core/Src/i2c.o b/fw_hal/Debug/Core/Src/i2c.o
index e5fa18b5bd6653863598ee9fed5c318c322eecae..0419a6a2bfdf59ea042d01e2186586c758defb9c 100644
GIT binary patch
delta 1412
zcmb8uZD?C%6bJC<xi?vEvrxG*F-a5bi&)EQU06RXw(24>SLaIt`BD&EL1AT4Rt&Nr
zVoN)k>6FG)|5oj!19ia`7dMHq6|C$_aTAL})^?j_cI)CMSSU!DA3Xmy1yR3v;qbf9
zIp;p--UsgQ=Nr;<4MVlMHeZ)Anh%{YJ`L}+)y<$0@E>Rkx&!`R&mQl-o57lcBcHkV
z)T9HdEm)JjZ=V{@_L^JT%@adkeZ5OnuA$HW?*`h;HkjM}w#<0R#~HWCjG$`s1=5o~
zf7*B}n=rSXe8-%0>0~y(`B@#!e!02D|KOBNG%^VlIQxXDwAcEe@&?hY;c2mUR>~)L
zcy2Yq(T!TgWW^2I|54xQPxkj$7y7I9f}tnyw5@}}%eJm}4>{fSA*bGESc5rROBfQS
zghRq9v8j-=UGMcqxKpIsGhhxHZ|F#MZN%g91~$fu|5dO3TRn+GZ@QNBZakND-7Ace
zMB!}K)nBEfh>g1L5PC?mkQsIT;NI0DkGpe9?G}v>m3oYRq|{pelYi&q?4M97QRzRh
z)<1acxT|pNxb=Jpd*>|&w#-|1%cT3~tp=S$*Syu}yk^Mz<8@|^AkWMWQ>i2_N(Rvd
z%b~q+E=YA8O$%0|o<fYgf)sfGW8@5G$ctDeEAU+qjv_)@(M`TZW_?v89Vn4zR9zJI
zBShlpB&+BnE69;YF}q${C6A--k}!Y{Qb3Pjc&730CF?HzHl~?vMVU;({z(`{n3T~)
z&fqYyktcs*j@$$Nvk*WNc@i=5FjB%MN4-)LCVspur!m8P9?K*SUukU>AxU(T+mRuQ
zD3TXYA^}ug7M2hqr_o6sLLX^Gj{JdH(vDTKA9cS7adeOs^pIwZknNZz<0zAzuos03
z2$OHnMG`nnqR5jt=Ey<lE5ZPp$QWW|5h-#7W8?^Ch>c~za1`OcDrcHN<f>%l1Bs0c
zX-1J8MM*FmQ*bXy>nVhmBpW~{X+$4+A35?HX4hA%<YUxb6YfL@xsD!^#0a?!)8rh=
zWGn2la06lT2)YEr^BrC-%fRlnr5xfMi?2cdDm;ZIQbvrNLyGt?MxMb8iC~!w!*^Yn
mLWG<~H}N7vPN7J~Q6lG2bwl_9A;G)yy`{El`M)aH#_eC(qqIH%
delta 1585
zcmbW0UrgIo6vxl~b-(^DUB~ERSfOR3Epu#hNHxZ6bDK5GGBY+MnGb|z84;IisvD7q
zO%TMX-~$b{E+<BqApvFC(7{+Lu$l2<)MO9D7zJ9Otb!n#5&ujd-2C45$297bO>Vw9
zpL5Q==g+S#W4@c;_}U7E?DL$`8k;X_9}OOT>F8=tol|q?pRn(D2J4)zlkfD`1>5_x
z_Pbh!f)w@9om;o>Sk{SA@`-8Tt9;B!SNG}{+pb>QOXjcb^8dKY_Sa?6EtUs!bJX*B
z>iHdc?v~-a{1%%}i$+gcN-tfo#0(LNR<C?UltsT-S(3j!f|s>OHMy@Jw2*Mh_smMl
zqHF9Wa);@@w9mdq+g7&hGc{!DvOMw+|8jijbTm5_%@z}yi12ZTD1fv&gx6N9+q`~V
zlxo)IL5IN6a4a}0aC97NY|vr6`$|CF6v(!}W@*;KB9L7iup5Q$<!7P)<uCl3Kg4I=
zGUmh{emQE~59w7Bj3uJR=`2ykRUO89NRyIKth2-T(za_e(rxF6_CU36qJ2u=Crb14
z|K?As_+Fx5I=*?R$A}H}$QS(L5N{fnTX6kT<I*Rp`P8`FsHZd(&E1OB^XH0`T8KjY
z3yA)9k3l(HFac*f2PWi3(Z$ayInEI!B|NBPfRjp&aaJ4>XTOp#S156F6T~{4L)2j7
zb<@(vqY7+u5qXI}j7zV$hdl|PN}w?Dk28p=0nq0G%6V%_7V(G**p5kCL?*y739z$(
z=sDts6f&w5_yAx^@Y#g)*{>N?jOH*YdV*Wy(q(;PJ<$e{DMCyk{Cpu%iCIKFmn$>|
zRBWOF?o>#4h}=L)ys`wK7XWy9)hy}?OvBy{`!fF#haG`!{TX(zg~O9bNGi~|0Yx-s
z3il_G(b+|Gj0+Z!(FEISV6TTC;)W??j4JT-I8m+O>{$TM48YeDM3uyoHvnoBcp#2P
zWu}=C1?EynS;3#E5j$=GRL&E<X^yK(fz$%gZm~S`K81XXM5_dssE0)gm6iTL^eP{i
zL1pEzt^KgW8Xv?&xl@5hZ>9&7-qMl+L4ZvnvxLC60Ffnplv<{lhyq{zM0B6VN7Mk5
z0J``U&G6QFS!DlM(g_SlZK*N6CH*j*-R5j&ku7c!wcf3I6i5&MMwFY$AC}}a^Iy+w
zxeLx04Zb}q@8#M#S){KeL7(!@NwhRFhYJ(1hjiYh*5mjNfUN@muFSrw6qo?mj1Of2
z5q%2iQc$k>Ra{{)j~ZM+Zcf0<htP=rFl;Y(B+%1!iBBlg)0uQlmI^7@HI0InRB9bU
zkMQ%;C@8Ri+s9y+njK!@h(cL5arZMU<0O#qbJq8ediE>1z!gdcxJilRb4uEIG$X$&
T`HVe_kRE<qNt|mI<=Q_1w}{r1
diff --git a/fw_hal/Debug/Core/Src/i2c.su b/fw_hal/Debug/Core/Src/i2c.su
index 22387a9..2a78ef9 100644
--- a/fw_hal/Debug/Core/Src/i2c.su
+++ b/fw_hal/Debug/Core/Src/i2c.su
@@ -1,4 +1,4 @@
i2c.c:14:8:i2c_init 16 static
-i2c.c:24:8:i2c_transmit 40 static
-i2c.c:34:8:i2c_receive 40 static
+i2c.c:24:8:i2c_transmit 32 static
+i2c.c:34:8:i2c_receive 32 static
i2c.c:45:8:i2c_transmit_receive 56 static
diff --git a/fw_hal/Debug/iaq_wired_sensor_hal.bin b/fw_hal/Debug/iaq_wired_sensor_hal.bin
index 3974b0f6e774cccf9808acf8f21d16173355f6a3..df4f520d9ed34ed633401cf77b2eaee520205653 100755
GIT binary patch
delta 780
zcmb7?UuaTs6vxl;PPy|BUKgcTy>;{UhuCz1^-x#0l}jieBu236p~8*adT5V<g+YYA
z1e0Gq>}~YYOEl{;2+Z}5pofBOG%8{sgV6>-7KEG2>|ApZ6+u7vaK7gcUk;q#bOuWq
z6hH>KRRDg*4*Y8(=kTOqo&+@Cd(xkX<23Xy^zpy-*XvEYpFy8p@BOL)EI(!%X1U2u
z?8z-|!5+<sb6omr-Y~K6v;)>8gV#NxN@lP7vNh&Pu1TH?WB1H4Pu2^n<jL+&!gVZv
zS>ZP03@BJa<>WyZ6r)^zwD>5x8$jMej86Wa-(1`3ABHSp48|O^LQ2$Eu+s_>sG>Jp
z5ZzhB4O!v0-;O@$P4s%Q$WlpQ3SjwW^>-g*zFcgq#oih_@qpH9x@5$0ma!beXKdaQ
zcMeuLc&gS_HIX_u;OmRD9d<#za)L#ygHHQb4hjjg4CPQ&6-_=7vU0uB!5&(}hT1Co
zW_9C7O|&T-zG7kFtYy~<2O?d*UfHHi2+JF>UmM#IG+{q`*>MHa?5N*~eQe0T6Hl?6
z-x&;64Rn<akV-g9g<%(fBEqI4pwueSMn@pG)UcQ868NAUY85wo=RbraY-^w!lk7~O
z9h2I%z+D?IvF=b2FS1%_FD|fPcoEMtu`7<_+ECZ67Tb#m@as%7DH0#J69WD|@q`e<
tz`tomUF$4RK1K04F-ug5rDoK%&S&DoR6ULKvz7t)#{``pS}50R-vNd9$_D@d
delta 746
zcma))PiPZC6vp4nc0<e`yDGZ7Nz^rqN@+HxMo*hmFf}w5&7lZ|UZSZqv<iCCx=0Ql
zl4HUgL{QO_6+~;6f|^FF7Sw~(3ZfSw3O%$c=C*BUiL-U19z-1Y@xJ%w@x5VYYI%H<
zM-C*AmfOMcl=6a7+ThE<YbwB6@2UPoNpk<jZ2wzNt8Ur-3TAI>?@tZj`q{H)R+`*{
z;nMte4C^euV{-Wk+r5YB3+eV9nqc#L&$#=9tS0!*Uny(ZtL1flzQUs{5E-!keTmtI
zb0A|4<-vmjR1@q(u{xay14#QQ#mWEonp?KKoWIS;C>v2YbG&GdS4DrJB6<r>*+wMU
zvGY!1swdOqD<ILV1Kl9AtVq7HK}_nR{UVFw<g)7+z9QdTDgJbWf#+&dRWsV?P@q4)
zF)2XPI6?Z|CwYE_fl9_HK|R_~MSDPmg48tjl391m#x}@$j~5NS!y_{|LymC6uC65p
zMEb5xBd9;&7B*wAetTEMj=kh#@Dk?9afQc0GN$atVRBR9BWlA&?|c(z8NOB-5ddTn
zwj2g|)i}Dg!%;VF#82y6Apo7QY6Qp^<q)PxSLgr^kh7sq9MG?Y?t8FKQqd}&BA(cO
zTqN<>Jf0&R-6<^UW8JsfJX3LSw3sGJJT-JZ3XX9~nF29zytJaJP2SS{E{zW;&nSzO
d4^}j_$!E&S<7N)&zgYnKl_~Urp^fHd?FZTk!GZt)
diff --git a/fw_hal/Debug/iaq_wired_sensor_hal.elf b/fw_hal/Debug/iaq_wired_sensor_hal.elf
index bb75f26d0b50cdd1b89faa015b9bb6a4da4726bb..533008fdadca63900d9733c31f7a8fb7bec752de 100755
GIT binary patch
delta 9420
zcmb7K3v?Dmmaa#4(n%+fAAvkbNJ1P42zeNu5+FYy1Or0kVWM$J1R*$}Aj}#UFhPPw
zjF`*_7bPIsGdk>9K|q+EUBwY6x?wlY2@n-$1cHMjuF-*A=77j!zuW)cre*i+Ioq5|
z)pzf$>guX{tM08oyUu3qI-AvyprYa$lZK>pOcH`AQt%`3j~~VVrFAq`q{_~H>(<|h
ziHZ}}(VoKk1k~7^TzwKH>+tg>>K8zz(D}cJb^kZH$LG@jur6b-jaNq*&GnFA^Ff&{
z3pRftQ)Pi;O8Jql-mq7_F{V5qzE4rfNz2EkL?<WJ#1th|exK5>>ZSeBMg8iM#n_a7
zb$3*X7v=fCUDo~OQIR1#Wybvz6U3n@dT+y_cc<iF28M$g4*vi8`>5A<|D!`%V9LCr
z0LHL7k;l*zV@MHW6O-%SN=&L#o6|C^pS(Wh?a2!!_p6h?TwN)CnIYu)f4FjUN9Nx1
zhum?|rzSo-=tM=xwWi!j&)9OVe4kF*a%TKPSG4&3*c)TVE?E7ug#%_!>NPDv+_-cf
zO^T5Z#rM3b#aj!a)5Q7wD`OKQ1|*8Qv>TU(((hvAICbqix*j8w<X@e{Sec<^2aSu9
zi|xUewMZ0c=;T)CjX3#LA6eqOG*IS6$P)T+s9Z0rsd$)-m$PZfFgZxhr$(T>yemrB
z;uf)bL44<14<`tbktq7!B{HsEn&L|0(C6xhlfh3B1H^6O+NC7=(=d6bTu$j(a)PX+
ziY$4XtaP5wlKW!iIhv3!56LxjEnkk1pHtpA`GtIx635G#a;LLoy!^Eh+crs99<@`-
zBsp{1o_t~b7W5t{Zk(`AgiEe7eGdE%%2v=Z&=t_RaLIM1{{(e82PesKZy!|Zi%7G|
z6xJ&0ic}S5CaSaO9!q5<O?VqNsT!Ax<ojo6Arq`ufKM1Ke;IPCAS`#<Ep@5)m@->f
zY{#;xvp3A_fxbeNgJm!)ptMN;-P#BtugTaPaEH2zz4{0-VC0tmYC!MSXkk^l%%3dT
z0KJ!G>{c4tUrm)~>B;_TlsrMd0lK9mQdl*v-oQB4I~K8=;!@RJvdg(YRqa)>jba9<
ztMULvWvIL5BBvxnT~xBknK4ie3CKdK8l|#i75#dYnt{px+bA`(|IQx5!g`9Y<FI(?
zPovi(=3!vfSRzvYlO~K-X)=MzN2_AlK>J6lp>jW+W@hDY#;9yH?L0P%9`2ZWUa3dx
z6%l^{Co~s5zh%zCh|jt??aY}Q@i90Np;n(WXG%o7Q#DqdP$?x?_Q2OHdMaS*N=7l*
z$K-mT<+N<PS|+bMe;ThIjg<LRG)28XBr_l^OgiSiZ&f4u8Yp88ux@o(DepIc^=;B|
zEJYLDF;y*)WzLSNYPu<p(bv<}dbx`pouLY4IsJBqdS2E#Q|?yxTA0xt^VA?qw$KMZ
zRX>yMbo+c&BrnsGT-4CNp-?K7;>$7nwa$a(>Jy1A>y8K2b4sppK3J&6#>(D~dQ4@T
z%1ETV$JO7<i?ru)bxF25uT`msqhu=up28C6IHgai$Vj=0DxOt+6AH6D1L^nXuP}6N
zM*j+5GMrw3RGxEQdsgL3`0AfGs{1kM3D2oV(9@phREm7fX?sr9V+V0c8`Trh@c84~
z)MCJ~O|T(M*UIhcwCr?d?*LcMp|@VaWOmTtoq)5bk&6@b9Tz!HMYGx*A?ut=zgF3X
zyy^^kU40)dyC}m^_sXTtYDc|dV3PX1t(qh8p@)92W+Y->?33z2xtAU}2?N<nFPy}v
z-l5$n?)_tdu=oU!39(V>Yw|+|Ci;I4_U&L#NfIKZ<1Kt}Vr*2%{wh;9LX8#NcHqZC
zDQ&CUwoIfxg35VHKc!MsOppprsXlTZ%{zrR&!fjrss3^yZ9$Px6Abq-G}aEkxd66a
zM{TE6vaF-8(1YAUk*87Yr=Ofw8S*?$JB=x;qjjg%ZL-DLeOgV-Qr1N0LacuC)@8FW
zV0W)T>24n=y{8NnC5~gr?EFG>VNa<=xjX`U5lYX8Pr#Siu+Lh;IspFGC}HIQdwYSm
zQIt_2Pp1YJVc(bzHGbIG4^S{q$HU=E^K`asqGzF$TNx{?Ob8oL*0Cm@IiLji_(GIx
zP_{7>5931mG*1soZx1`8=ainidX9`q9<Ed6bqWsGgQ6^)<U9c-w1T;1)QBR`1a2j`
zp66xKVV368nc@1&^ji4iXOQx<CRB)9QI_`-Rw2q=^wkJxAET&|`d(OB1sARK&m(ne
z^u@l|+!4dTi#{Kze+pv@j?#l9_OB(Q^;B6v`$p?ggKPT>>q+#aQbT18$|~T?C{Lhl
zPZQQflr0n(qen&M3=q~<z*Z_Aqo+odX9(*u_M;MN9;4$E&ke<7V=acm7kRQhpIk*p
z$LI+-p#yig!(4KQekHIpH?%23&;7P8CvmKXyIrN?d_5B`)SRy)<+Pj;!rBFu6DWCL
zvqpyOq61|O@SIV?sz=Gst#~&-uY)?lXPe@O?I@ovjMMQ^J4c87rh@|GF&n*|G2?Z$
zOl%n=tQJFvy75>J^m2ZJuo}>+hK^3q4lI~97U;*S*?5`Qc$wHp`33xNosE@=jg^Uw
zm5Gg&iH((sjg^Uwm5Gl*Cbrg4Z$fZ=KZw7H>3}U#tTrFR6ELqSMp*Q2kxr=Q8r!qi
z4cFPOnb@AaR$OPhW-5dsdwj05VSCu?hk0!1Ol;^(Z0JmUmN8xLDSH0!VgSpEqwy1U
zQX1QSNto_K>2+F$I(q=MPt*wsTw_0A;=_q4ALL5i8vDbRJM~WYQ>hb;GMUBh;EmTS
znYSxU$56VRm|W|klautMh%QuH`_QRLdLl|#IsC;{isPD*7^2?&Lfn!FuB}ONHWlgt
z5*1+;z;(Dmfm>roVw97^HFhT^b|)rwCnk0$rk3;&u|I8@s?*}Q(i$fAD()(cKQpd?
zVabpXv4?qI=#|W4k7HtwV_FraohU<Hl~2}I1jDYJ&^LGG2#bA?#asJutqbIJ%Jr+x
z^MyK3T31o8%L{21x;1vn*Y4D^nk(#?OzfFV?3qmLnM~}7UbkM!ynMK#hq=zK>0z&A
z-Z4-Is5gAn<A)6>LNK$%*<Pf#$uxFic3>uUV5S-zgG|=M(D-+nTs!Ano1r%iE81<E
zXU*sVIi}1}Q9?>n3RAIzV~x#-ur&8aQg(YiOq!;ZZ5mbsTDx+~`FOQ9Be4g6_LLrh
z@V(c1U5;>L<$66G(ZRdx^<xN1^J?`hxs_^b^^@49^#(mo=1_104x}=tbb}rkDHl;q
zy$(je*)6R9se0X)PS)$evdxKnUhj%TOuF|){d8m!yS08#NK@x6Hsxw%dZTZkSxtHd
zLeCvddMq~kKQ`%&ve0>GyIv4k%1*35K&vRB44J2p>W03Vy;^_d32yHeu$$|%LXJQ%
z9@b@#*B5@oI`5>vst-jV!aV&?I#DY4{gu~ozLq#ccI&nX9Cnx9!~`_a!w2;3$_UVo
z1G=xwq=N_a<1*hFc2FORlC|{pJNmDP&HnT|eFwtJzVGUV@|d&wUEPRzbz)mJMI#7&
z^%zb(#Dwo3*MC8X=<M#$E2FWIr=QjheGo(Lzo`3~h$)YJr~e?)>DKS{G!8lc{5@8p
zhH|dzyAY4AzKS=u(|=vnD-owGzNR}Ou@w2HQIA&~F^w-RS?=uXVa(9@h#LXpMTz9=
z#aoQ#M0PX1K3ba5*+@SXBCpUC7Si3ljSRWUd91e)Yax29NjAnH^mG1YpfNI1E~N{@
zjOBn2W*J#=hzuLY8+9BhCf#Z5frZhLyNsX0QZkE-@rWuH7a5ZgW4>Nw1mzs(+ae=Z
z%1%m~VXQ!G@QWG7Z*ZDUyW2>X9nPY=jd+eFpPXxak%o_1_;<#K(q<>nn-ZlNIg`q(
zjCgva%82^$e}fROZK*P5%NplDs*D8z9COdi+-QJIPy{FvWPzfbnH!_O`5?&gORz^w
zt$s#rlEEHn!I;Q|<ghP#f!)pWw6NR__-Jjhoed}1U2OM*lN>3wQ%yc7YiM7w9goj9
z?*Ye+?MPPH@l<e+ZNOvhWVRdPg%opW9XPP7=6meh;4~lJV^2W(7CYOXjo7YYw!IR@
z_R(xR+jL_)Zgh*;g=naO(&s=mfhy*p{Tf=wsE`iNv1h^@0&_8}kKMv_qdCf*YsZ^z
zK<8F5W9#PPjn`@ST)W8R^Q(Z0@8f}%+7>0xvuEMO%jVgsY~`Eg*+~YUV$^=GJ(Suj
zZG%3WXHSO7r{8Pa8rC`NKKp*t4d<w_)b3~Uku`)?l%dC#`|NV}z)E6KDiz*upN0Jl
zE3<n_>>lGDu&Yfs$fM%<cCt)#PCa06k}!m2^X<0`c*5X?HsU>u?;-m%UX{BDbLhr-
zq5f+sFts(b0&F-$BNy$okBb&My2yS3Hd(P4sFl_&wvWRv=T_Po*wUV;wCBSaK4mnV
zu2o{xZlFhU3FeAVo}uo1)AS{Fy~#(;bjsxqy12ydH2K)6A-T#<buK?_mnoA^o)Ck;
zNH+N7q4J;GLFdzD_BO-h)2E)+RoQ9IOON4|aG66Z?Nq~bBSWfKi6uKh*B-~mxv?SJ
zO+V8O58Wyfwg;;0`KB8XQbiSJva<^Fl~320?FNLQUOH&)6ZTA#kCeUc6glUfuwOJW
z9c!!c;yP-s#&n#g!(7xjXR7TNlzW_Xy0+@nKV`4sZ6c}`7Lr3FYVCh7=Cqt0K;s`j
zEk9sHn?J&)i}~h;D_U@xFGM#ET~4-B@do>^)f`Z{a^y_6p_1&w*}#2$I3GC6hYNs*
z`0#Y#@jhGv%)uH8JW6EZe?MNt%mO<6G-jcI&OB|;477(wEzpXC?{*441GYDKzFFm~
zi8g9}#=e31Y_79k38wuJJcr)F8wix}D1mo~<vz?~;0=VOp8PDWd)A&=-5rA~u^jP1
zE{@Kju96aKflGON3FD2xp8|6Nsql|bei2S28NUkrQaGVx{3h^`@Ff#t9@ZSh_bBkV
z!>)ESRFA<5v+x2B^SF6`^DxWXe3<2&Ao%4cFdz@JoOeSHbNf0B(8HNxK_~_G7_4vr
zBla+N!270$S)Pd*@-WLe1Mx7+OMIB+Wt97zof_;;PD1O&F^a!gs}FNC&P)9A25Lk%
z0Zvf->~cB`c6E2o5}M|E1UQ}=_s02)hk1~3J-RW=IiK;%m-{fwInVLS3lPP481i0%
z6CaPkFKDF|^{{Yki73+fH1MQQ7kni6@p(F0Z)fLv?#>R(o$x(eNG*hy`!IKNopPVI
zv#a?W@p|KCTYZ?-I5YCgFZ(dd4V*E4d72NioX;S?e6$Zk-b-+r<yWYo3(sRwIJxrJ
z!*P0U0R9XN&lgH?T6uEx<K9bncq;TOATRXk|LP`vKJ7exZqMnNhv&gPU)W>^0-UIM
zOrD&*v~Lr}#yOjxeXege=Dzr7^yJk%_Wt3U4vhX~;P;V&ErkMq%Whze^vt~p0d50c
z2h0}^-nU*&=<W~wSL0%(oAEUoe1`@nd<|ldFnR;v0dWH9;b@!&Ymq~?`1Dr+d-62M
zgBbASu$<d-&gsb);r${X3Lb+MI3e|8PDK5f&wdYQ;{`{Ni1OVIe<8Q$MAefs=7iP5
zJn?PN_i*NL)Hsv%7_9IvrqsiksBo6+VU`c2bq#iEF6X*_c8d>lGtPtk@-jM#X4RYr
z``KFuc4Kb#TOa1Pbq@Zq+&~WPZ$HO}xjpCDet9eMY7awREjZEk82o~?tZobi_u9)Z
zpL~;?qa?q4sSk5|4xRk+tv>virf(bVUI7lL{5rUo`vvBPqbiTR9ZQ>we0&!e-qLcA
z<;gQq;ULSyd!hd+^gUyL54afldu_OV2k=M0HDUZ0;JL`(>%$oRRSS;NfL#{PO)c&V
zT!<mymoxDZ68HjF8nQLMPw?c?2!+m|L%y!#0cQX=L!a-r8IJ@W2fQ$hT~oq<z4n>x
z3>*!53|46K;Y?t@q44C4Iac(rtM9`s=K#_#pN;`~nB{!4;o(I*vUVSX6*%7X6d3ar
zhllxvO+L(W4n#dUW4`k6Fzd%r;6)st9G&{vZ&MKLYQFpMv)A|z8gAW%pZGj^CMx{1
zpNCmqHNG3OoYP0Yylp}^W;x%j_~iG9H3i)aR;ck|eu05&7q7u;EU5Pw;=&Eq=WCe|
zFLeHQQtoDa?zx-TX;c9=?c8j~Q2l1Rcc9>h4-FaCblS)5Cf~%KMQ6ay?G98UMPUT2
z<Oj6~QT8JoDIR4^xm)b)3O>epbO9XezXbalti2wwVJ}$cZs2L~%At@meh>H`abyh%
z<4=Hp?vr-`^Is64aP_aFQc8!n*r^r#2L$|^Aa|38cz-)WrM55*0`ngM;Gn@T#fqa$
z{+k7N&f+kKh%&_pyoT@Hx&2aL{-Xr`MUnAp;G+~IgfvKyQ3SujcE-2$Ed4#C{@#xR
zAL)aS3d=izmmmV;m16xa;1W8_y?sMx2s!;Y3Ty@XkaD*oJuIb0M(@);6zMAvGM@{#
z{1_uXj_JWqQf^OQ0k_ZvR{IKTT^MHfjS^xo0)D=6;1>=6E~VU;&}op0xhSO-T>On1
zx#&atP^9ypXpBY^o}mxWgySs~?!p~I<p^DXTJ8f-D+u>&V20MgSnI-{ng;BjiV48a
zQt)MaLcq`7z-rX^GM3HHejDs4d`D-v_YZ+NdE#Y@!=O$w#-QSW*_yrvz5rip2<zVf
zK8V0MA&k>(eobH-^3Pc`Vw-(iy8mspkbaXB+M0Qmwz%5swqbQmL?`_753~OO_TWIs
zHh5<K2>dKI;9cQQz6hKf9u(_;4~%8qW@iVM!P0BOV;L4B#7RnTawk8CqWXr<z*ayy
zBW#e|$>YG&Ag>Fzt^>{;5c>Iu<*x#7$IMhh&V$+yY+{hNhVeTr#~%)G`pWwM3he*(
zPh!MG(FmLLUhw5j3RiBz(Xm4G!8W-!++hxIDWz}6=d7jRc6)w$Vvo=v!>?;*X?Wpy
zcy9t%&|%hYrZd}N@mQ7}*l8AHwWf!=90c$EhJs-C@wc4^_7gDXRrK>6xEgrCY2IP$
zI9zMJx(BxwYz`%KWDl0Og}&Ki4>I|ZpoJ3O0H=+{y#WsIQ*G4v25wPm-mqg#-pAS<
HU{e1L<ZHT$
delta 9368
zcma)C3wTw<wVub`$w_tsIVj{oASVQQnWy0q<dp*mi6lZqUV=4|DA9rqLNB3F69hG4
zKu%Q_%0tpmTkdxSK|^<}p$0?>z1V_}ifw>kv7#Uriyw$^x&PYdY_sv}cfY&&7Bl}^
zYi7@$S!-skIoWbDd&|k}HA(8buA!7cz4ne1f+<??Bk_+P#s3BNhAPtJp&iSXUyb{&
ztMKgx{Q(qeO09bjCF}6>G3qBk#R>m6vF^Xqars<&AJ%2;wsGqyW4Rs{Jik-s$lT{Y
zlW8*7Hl_SX*FCviz4m7LFUq^7*Cwgdl<K%iNmaE;J!@Wgy|!w@>oJphHvFziJewip
zKfk`Hd&|QjLw3lF*<+K$t_kM$HM`m-<l^fGgVyZ)|MzwHyGUQLot@E7O_`sS!0%7y
z_m4<UZFnm=r6D#$JsZgI-SFy!*70-4_iT{Q)<#COnf`3bWIAKYOj&FvN6AM_xrNA*
z)8qmA%94{47hKZfoe@_@jF?;d)5<<m$8{@C5?3$WLsR4Ay@`pJwRmf8Y(V^T<fReG
zQGJp{L*VL#o9NGRa+ESJQI~j`A}`nj<7I}Hd#N-*&a?6^YLP4g=p@sAJ3)TYT^8B@
z*-z$2$s#(MDVNJ9sUk}z%GtCuOZJ!Zs0k>4#3dyxah<50o7nNz14%+;B#R!mii|54
zZgV6F=(F~LRPcL=KH^4k<w74ioh5IP<&>8#$H<wqFk9XzXWARH<&JpyPntYZ?vnE<
zev}*{zoc=a<Y#gT4IC{e%Qg1W(egJ&eCs&jbE%E8#>vUWn??%X7SQV;F-rLMM@p_U
zy$`$%WeaEz=u6O%NXd1kPeGUMcgM+5t)cA+JC*t@+N?H(Z$6!gRuyJnR7>b~pUO_T
zIRvXyp-PcDyHpFA<a-JDh{5s~A@_}l$n8Tub>aHqC6@59rOFK**Tb0Z>LJ7wuncDT
zl@{r5KN2P66&W7@H`7t<)?J7`{nqwYeXehb6}~EmdBgpWL+?cy-#|lqtBLYMdbGD1
zCil~Cfvzix7QT8%uU`V|y&qLh32Ew9*>2BHQ`?nnrMN!ovV56hGSqEyx;-;PomaBa
zF72lV`DFps3{%;%iheUpm16$C9i}pSujwLuSW<C10qd9k1bRJS?gmz&nIi2|8dIPG
z(nsY5s!Z0?>jf%P{)&z>bLMY{s~lC_f$gA+Gp4SW8qs=T)L*~}&qdd>%&Ckz*vUD>
zoM}<}z=;aC`jj~nqT1}55$cHQRfLuIpJvfxepAn66o;KkE(a>71*6phdDi~hX!Wyb
znMso-sCNe?`GpUYj=Aqq6GC78Wc+#TCw(1OuXopgbvES#EJY*TJW<V+CHAI?s>GCg
z=yZu%F4xh|N>!1ZLM^3gm0WC3xJ}LQVMaGiSN(mmnfCoe{ZzKmO?RtF@)SMFMK%2q
zh5Dv9C6;6M7u)xgtB)l%rJL_jPb)d!-dCwc#7o0g52+keolm0tCF&RQByC%wF31-9
z*EQ;a7}-Mp$FRf!d)8wrI$Bmz#Z#(BQbD$BAU)rB8AI1*?92F)zVr;F@`(NGr_@LZ
zcm4ZHH5-E-^R#*pJ#Bkh^^$AtgHNkQ6HYWMq?X3Q=|5Pn<^hh_02{(|E!wD#%R~0m
zP2kG$^wvw5%)K;lGhiWwxY$qMaS^a9n$+`Avc|sf8<k_oGj{)1)%UTooic1SL(Z{l
zZS|6YN$T0EnxgTcyWUZy$(R@GsJcgPrU#G0KsM7eM=`2xv=zmSKNbof@9{DzJ|_L)
zkzoT9z267>Ca@=@2+`}qxA4Kq@iAfht4do5HCAxifgca0z&fYx9Fg`QDjk%5O!ZQi
z3#ss!>MkeH^kaDQ1X^-T^_F+gS`<mu!AK98@mA!`g|PJ+I(ST_${P9tJ;*00`Z$VT
z(GABH&Il?#jw!35WyjTxvf18xT#e0E7lZb>c>PA-1tq*7yjP%fwhxr<GY1tVKEROK
z`GshQ-U^iEQNni$rR&4{;md5;ANqu^8T^JA;mZYf_X2mLC?S8oPV-O4zQM2KhmHMZ
z3g+uXIQ*=9og*9RDJbR5j2FHE5Z0q?U`;%CfZ(9MN|f_a9%LpS#s&0AzV4si7I8+`
zDP4DU9T}56Sf|Oe6dbJk$6SQ=6f`cPh0HCX5DI@IJgy2{*YlESH%l|=#9;k-`eL|f
zJEZ(P94<s(lvBD1UlGc6^u-Wp@1dBXdIqelf{PY<bEr;>J=sI}5)h@pi#{Eye*$9*
z4%7W5_OJU3^hB9UI|}r$fs1<!-=pa1n@CxmCVVx(r%)b2*%lDK^C+9iKU@!s3G@-Z
zb$~5YHe64PnUW!V7qK4|QPXgpn0zD?la00L3t!~Pc73vv4iDF3<Qnqd><sh%oApcn
zIeFnt8G6pQwcE)fG~DeBm5tPs;X+L#b+jxF48idQmHjArV1+}&cCi;_J@EKp!q<qB
zpT2lEKd*ugfzLL@58F{Dog1YSW7ZUe{bn!uM`Jb&d-!NwCzG3p3*TNth?>z@4)oG7
zM)=mCRW%(Rqit9)tt`|J)v@t1vGFpok@5@p;W`^D6B{cN8!HnVD-#<l6B{cN8!HnZ
zgG_9#;ogMc`maFzO-wIaqL;7L!*B)6Ym5^<YMZ2!>bS=C>~_O-wreJ~XSWsC*{+!i
zV45zU>ulIAcKcx-8#)skIujc@Q%8i(b`@QJcrk$QVpkeHR;L8m_KRTYOt*sEPD@Z{
z51>P1by5=7*bkWaaAL{?IZ~&_{;>8Iz1jIx>Oi9b%wl(N$Lp5NTNj}{D4kABuC>$A
zae7=-JE|?+>DV|u7Nzj9zc@+>Tsxl>CZlJVJ2Q%F^LyE=i*z4}3U(d13^yorYV1gi
za&x)H?!?6I#Ki8z)CPBAYEBOm`_tNqI*`DXmI$#|aaRHU%!ERQMT5e`9_D_bTQZM5
zj)^^vsWL)qP=>oIAFq8;4BK<V-`t)H2gwVI*LCMwJIL*n>u2m$MLJ*l&Y)hCAJ!~#
zYV4H1zD3JAuCQk^v1c-|XEL#8GO;JR-MS_7GU19Y<~qBki`|lWdq8_Z27J`zM+_)R
zFtgd-I7zRU0d`_`U?z58rs~2lUBqF=6S3Lk+7bIosa~BmDP)=_&DcJ<rp#3_LP}E#
zQ?Y|%jm@ZtH18TIyS>hmrs>Nu4c}t4cH~j^Uuv}(jXk*iF+Btke7EJg9O1^I<+=pX
zLECcu5Q5VD6?%$npcO0hqu8eP<9d_~Q1EdaNG0~H$92DGIi2bobubFf?!)>YYt%jH
zXrmq|TkYsodP_87((TXbC!$l>t@R!uO`Si_l(ouqM_*4<Ht14>o|`u45!meix<Rj$
z1@^rg_1x%LZSX_A53OQ^GGx9&G8_J8_G<l+E4Zmsz;3Qj3ONM9ctn>yUZ1;$)nTW<
zqIX3h!aV+8I$0|C{iRoNz82Yow(5gXIP5OGfeC1&2b%Rw>U;uiYSuku676i(OJt^<
zwNvkkk&Ef{@AcP+&Hnbbz8T?Vk2YN?_t>><I)r((<M(TdMG*MP`#A9s6TbU_{s%%t
zd+UdKQ7ks{^y7L>cf^pdpVvLGV)lXW^q(X;UH82%=8*I6-(w}JDfhCz74c~8WxTnK
z{&iU|LYy-1ivBPfOEJ<k8u5w)rt!H?PO*1%F-kQ);;P?xPRb+n+;v7%GP{{x9xKh*
z98=~fL|)-3ETG%2H!@_U{m}JBybsZ1eX21Wp`ZP`e#X#fIfu?=8P$OIWE<HDhzvuc
zjRuYsQ*JS~nRxesTaBN<QU**iMkA`6H^~@}81vOhMo^Bo&rUM(q&!4{Qez=vgI|^!
zzr|@<e4CLf_uBW}W+ZYf`RFv`vj9G(@;{9Cq{U94S0_s|dNP&Q7>V>?jS+M0fBg}!
zt*tSp%4++|8e^^>$J~>XR~jG_6a|U~`9LxD<dv~s?F*K`?}A<8R_G_yY8mV@AQ%@N
zNR9ZS8`%9=9*D@DfR7$2vvS}hTg$ATaFPRMR+`BNWj*aEvl8+7=I!7(u^q`8E0GFs
zw+wj9EzEX8ys%<`mVpDiYP#LJ5l-{o?baBiZ}C&Dsfg_=rdo?&Y#&Xva!e<-<3`t+
zXAlk5Q~DiH^-;wgXg{BpF)E<lcUY5Q4*qEv);^~&ooJ5ordf%m6VN$T%-FJNc;i{x
zI?bA7^7&OrWq0yGXIVZ<oo-FRix*6{(%8yZPq$JGKE>$J3@eikRapkLPq)Uy<kM$Z
zmWFj^-D%A>op6pqv#g#bA6bKF;T-h1_fD(aIj~Y#ltx9ft&^~ytT|R!iQQw=T~;03
zVAoyzt|a@|UDj#|D_C&1^_BrQ7+7f`*vqA|d#&SmPu_j_+;74~H7#Uxib7np(GD(}
z>F|BlGqA&oc|a|+Y@YQ2d~sTpm4R(+X_a+19N-g1ed$USM(PB2B=5)k@M)9j%rTYR
zZ#9~H%#=_bf5iFwtqzlqntGCptu*`M1J)d6@@W%h5E!WjpEgwfb1P_nvcOtzn0(?i
z(y|&WV88GXUI{nZwa7{{OeY$oibYta{d8psjKYZr*;aa*PDtofk)+*KW8G~!K_FGs
zVD>s{tW>zp6=pj@V7QmP^vF_cvdPEDc4yk{Q%kMqOiafkb$D?NHPvA{I%qc+)%J-x
z>lx)7Asvo=+KrD{5A)U#vjSETpdl-)|1RTHoQ+=NA3x1MU__YLVAH{TVZ#+IIJFm|
z6Nj%H+o<eu>+3oWq8vH$q#IF*gYmgI2bCxf9tqsrgA0LEJeVCh+k<BUb8v<Nj}im$
zzZc)f%v{?21ZE+ZPCQ{v_P0ewEzpVs?luZO3AQ_UzAxqLh*oNP(z=TIY-+Gx3a0)L
zFo)m4n+BBdD1mo~Di7u{@TS31SAK++J!MU<>x{dVs76eXj^i@ZQBvX&;9}lVB6ub6
z0bouV75)**k0Qw<<5z&6iX@SY-vE9ya<RmihczBCJqkR|u<M+x)Mc<jAzt8O9yjl4
zE@pYF2eX`$0<U~O2IOLv^A6}@ZeN1|x_E$?8%}#&1}nUb5xbZ>;JwntEKkA=xtQgg
zb-0-2MIOv@xbM?eTCg)A39lE&CEjK&9?Z=+7xBvLDTHqPoRoOkQ)oBXb)9)ic$yzZ
zP~)m`Z=AEZm<K7kbYhls4&#-Vdoas6xADqzJst#kH^Iq{SD}R#Hd<*;V(+rKAC8W^
z_#lO#hF#%sqm`5Ax;r~CkCN}+!rEb6?!nyKS;|{w<<#-n;daW+8a$ZQI2-cHPkAuQ
zIZN`&6L8MBnB{!#xS0DN;K7i06P#Lk6{_jnDl7^oR4#ikPRySJw}avOLJ>|VSB`$1
zy9gIggnk+1MIQa<ex%PQoU706IVE%Pbhzg;t1Z8ulQWmegWpU$R%2|Or+L{&dURs$
zi!(P@UdLna9lqV*vA+ns6KU6cC@|g%{4bCEAn-z@Xne`we(RZ}&i>GU9WGNk8K=?U
z3p6<5X>d8EQ_ch8q!9%kC1P<JEI{74*Fj;6uLO3)kOv^o!+^#|<lLU~Ojmv%-Y+tt
z;4)Z&lTa__<kO2e33YJ}Ua%X<C*SAr7jk<}PF*=;PEuXW6W<Db7Y`VWTAPQ#3fnQI
zKPaHWnXQXio=VHsSZR5j-+I~29y|a7&V9Y|5;}}#b)5Tp*$w?VF*n=d!Th#E1Fw~z
z_h6QfM;`6=$L%?<b}`FakW0H5@;brEwaZ|IgzQcX1?Q^ED<AwLIY&ue`5X`C_8dBS
z<qaPEkfyUCtDB$0DX$Lh;(m#_;i$@GZ^Y83BM09ChP$*JWV!MIsBn<w;_c8s0Dafk
z_W%cxv#*G>{}A|H;Q9#u2k<S(*&8Dm{nZJM(tsTn&&^`o5jYS-zz=5PT_o*=jx=m*
ze23u5V-X4+Mu&Vw#{<p)4nd#qv>6Wt&H}ECVD3K^14e;|`-3xZH0Ux|q1A&20Q0Sc
zD`(8HqKh4U4`w+BkY4#n4A8|a=i3Yy-^U|s^DtO}<4sqAF<)!Am|xiF!7S%M)Ri;l
zYYrE)z99c|I6gT#^|D{3AlP+$-{ED?_Z&3bx}AUNbDr@0JHPlvFw3h(Un}R7(bZ>p
z>zGbF0GRJnJo4Mc{K8HKEAVBDM?sv&Rf~&jv7qi_h;vt2pRZ!Vyzp*#i1MDt=N=h*
zEjxiKz(#bv3<cFcZ^fD1dL->&?ZH2Mb@(d_=>*t$o#AP;D2l?z{Gb*k=3IlL#m^X1
z-dZcCf)8&VlOKoqvtWM(8*fBJ*bO$f6?iy&F%xpedw^fSK{Y6XKL)<nBR>Poe+_`b
z(f=P*ifQ*+E3Jb67=VBM<8Ja1<*!13bTER0!2E+gju+7f@+rXh`vYgD5-@W!fp5TT
z_=cU^&j;o|FyP+~8P@{urXXR;kP4#+eu7Pm@8wzg4y4}RKLCESJ3cBR?*N{KxQl0)
z_0Iqo(QfYTD4if=?^)zu2egaw)*&e@rVyi@v;#$Y1p?($k(PhKh~L5V;KwJYr!Rn;
z=^U$lf)y@`uzSSda}eg2L~tMAV#<2~o#s&)7sa%Yi_a*;g-JV5r1PI!6rc&u&^|Qb
zC<}$NaPOn?CY^&?UMVKBFw(Pu8CnPvZHRno0N6VfV}O@Z@I`Bk-^+fS)hP5Lmd(p<
z1^YV~a7U!~_kcNN;$=&~ppG)epb~)Dnoa|sfCur<3Oun_fnPzmoD{)`$nhHgdSsm?
zG-SPXW4iZkD<D0J4Zl93z1GoQwjQhdZBqD$9`5u{U?=;-w!t&=SKy`CcDF=6`8;rX
zWKgXCJusGay_Ms?3zqKoo)ss=dz8MxnfxG%y01M3wh+=$5rgDTmH-cjydg5S2H<p@
z=j$T)72s8vnJQo&)a$_C0{4yJ-ve*Np9pZ$%KiNT*!%4t$BD6G8En#h!RJ3xxb!0&
z8!v>(8GWR~T;O6#--ypyK*5dH-RUu1!bc0gu8F0Qh2!D90bEAASvy20Hp1euESs>?
z%)n}uM7rz`?>$OEu)BNPP6vA-jCnr&d=oANO6{gimQKJ0)+^iirVEo+L<hEEiJR%G
oZB~DiuLhba`89A_Y1C`r@IKW_q1SMCQvVuuI^M_HY+zFV3nX)?EdT%j
diff --git a/fw_hal/Debug/iaq_wired_sensor_hal.list b/fw_hal/Debug/iaq_wired_sensor_hal.list
index d6719ea..1960ff6 100644
--- a/fw_hal/Debug/iaq_wired_sensor_hal.list
+++ b/fw_hal/Debug/iaq_wired_sensor_hal.list
@@ -5,25 +5,25 @@ Sections:
Idx Name Size VMA LMA File off Algn
0 .isr_vector 000000c0 08000000 08000000 00010000 2**0
CONTENTS, ALLOC, LOAD, READONLY, DATA
- 1 .text 00004288 080000c0 080000c0 000100c0 2**2
+ 1 .text 00004298 080000c0 080000c0 000100c0 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
- 2 .rodata 0000006c 08004348 08004348 00014348 2**2
+ 2 .rodata 0000006c 08004358 08004358 00014358 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
- 3 .ARM.extab 00000000 080043b4 080043b4 0002000c 2**0
+ 3 .ARM.extab 00000000 080043c4 080043c4 0002000c 2**0
CONTENTS
- 4 .ARM 00000008 080043b4 080043b4 000143b4 2**2
+ 4 .ARM 00000008 080043c4 080043c4 000143c4 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
- 5 .preinit_array 00000000 080043bc 080043bc 0002000c 2**0
+ 5 .preinit_array 00000000 080043cc 080043cc 0002000c 2**0
CONTENTS, ALLOC, LOAD, DATA
- 6 .init_array 00000004 080043bc 080043bc 000143bc 2**2
+ 6 .init_array 00000004 080043cc 080043cc 000143cc 2**2
CONTENTS, ALLOC, LOAD, DATA
- 7 .fini_array 00000004 080043c0 080043c0 000143c0 2**2
+ 7 .fini_array 00000004 080043d0 080043d0 000143d0 2**2
CONTENTS, ALLOC, LOAD, DATA
- 8 .data 0000000c 20000000 080043c4 00020000 2**2
+ 8 .data 0000000c 20000000 080043d4 00020000 2**2
CONTENTS, ALLOC, LOAD, DATA
- 9 .bss 00000204 2000000c 080043d0 0002000c 2**2
+ 9 .bss 00000204 2000000c 080043e0 0002000c 2**2
ALLOC
- 10 ._user_heap_stack 00000600 20000210 080043d0 00020210 2**0
+ 10 ._user_heap_stack 00000600 20000210 080043e0 00020210 2**0
ALLOC
11 .ARM.attributes 00000028 00000000 00000000 0002000c 2**0
CONTENTS, READONLY
@@ -65,7 +65,7 @@ Disassembly of section .text:
80000da: bd10 pop {r4, pc}
80000dc: 2000000c .word 0x2000000c
80000e0: 00000000 .word 0x00000000
- 80000e4: 08004330 .word 0x08004330
+ 80000e4: 08004340 .word 0x08004340
080000e8 <frame_dummy>:
80000e8: 4b04 ldr r3, [pc, #16] ; (80000fc <frame_dummy+0x14>)
@@ -80,7 +80,7 @@ Disassembly of section .text:
80000fa: 46c0 nop ; (mov r8, r8)
80000fc: 00000000 .word 0x00000000
8000100: 20000010 .word 0x20000010
- 8000104: 08004330 .word 0x08004330
+ 8000104: 08004340 .word 0x08004340
08000108 <__udivsi3>:
8000108: 2200 movs r2, #0
@@ -589,10151 +589,10150 @@ int8_t i2c_init(I2C_HandleTypeDef *context, uint16_t i2c_timeout)
080004d8 <i2c_transmit>:
-int8_t i2c_transmit(uint8_t address, uint8_t *buffer, int len)
+int8_t i2c_transmit(uint8_t address, uint8_t *buffer, uint16_t len)
{
80004d8: b590 push {r4, r7, lr}
- 80004da: b087 sub sp, #28
+ 80004da: b085 sub sp, #20
80004dc: af02 add r7, sp, #8
- 80004de: 60b9 str r1, [r7, #8]
- 80004e0: 607a str r2, [r7, #4]
- 80004e2: 210f movs r1, #15
- 80004e4: 187b adds r3, r7, r1
- 80004e6: 1c02 adds r2, r0, #0
- 80004e8: 701a strb r2, [r3, #0]
+ 80004de: 6039 str r1, [r7, #0]
+ 80004e0: 0011 movs r1, r2
+ 80004e2: 1dfb adds r3, r7, #7
+ 80004e4: 1c02 adds r2, r0, #0
+ 80004e6: 701a strb r2, [r3, #0]
+ 80004e8: 1d3b adds r3, r7, #4
+ 80004ea: 1c0a adds r2, r1, #0
+ 80004ec: 801a strh r2, [r3, #0]
if (HAL_I2C_Master_Transmit(i2c_context, address, buffer, len, timeout) == HAL_OK)
- 80004ea: 4b0c ldr r3, [pc, #48] ; (800051c <i2c_transmit+0x44>)
- 80004ec: 6818 ldr r0, [r3, #0]
- 80004ee: 187b adds r3, r7, r1
- 80004f0: 781b ldrb r3, [r3, #0]
- 80004f2: b299 uxth r1, r3
- 80004f4: 687b ldr r3, [r7, #4]
- 80004f6: b29c uxth r4, r3
- 80004f8: 4b09 ldr r3, [pc, #36] ; (8000520 <i2c_transmit+0x48>)
+ 80004ee: 4b0c ldr r3, [pc, #48] ; (8000520 <i2c_transmit+0x48>)
+ 80004f0: 6818 ldr r0, [r3, #0]
+ 80004f2: 1dfb adds r3, r7, #7
+ 80004f4: 781b ldrb r3, [r3, #0]
+ 80004f6: b299 uxth r1, r3
+ 80004f8: 4b0a ldr r3, [pc, #40] ; (8000524 <i2c_transmit+0x4c>)
80004fa: 881b ldrh r3, [r3, #0]
- 80004fc: 68ba ldr r2, [r7, #8]
- 80004fe: 9300 str r3, [sp, #0]
- 8000500: 0023 movs r3, r4
- 8000502: f001 f8ef bl 80016e4 <HAL_I2C_Master_Transmit>
- 8000506: 1e03 subs r3, r0, #0
- 8000508: d101 bne.n 800050e <i2c_transmit+0x36>
+ 80004fc: 001c movs r4, r3
+ 80004fe: 1d3b adds r3, r7, #4
+ 8000500: 881b ldrh r3, [r3, #0]
+ 8000502: 683a ldr r2, [r7, #0]
+ 8000504: 9400 str r4, [sp, #0]
+ 8000506: f001 f8f5 bl 80016f4 <HAL_I2C_Master_Transmit>
+ 800050a: 1e03 subs r3, r0, #0
+ 800050c: d101 bne.n 8000512 <i2c_transmit+0x3a>
{
return I2C_OK;
- 800050a: 2300 movs r3, #0
- 800050c: e001 b.n 8000512 <i2c_transmit+0x3a>
+ 800050e: 2300 movs r3, #0
+ 8000510: e001 b.n 8000516 <i2c_transmit+0x3e>
} else {
return I2C_ERROR;
- 800050e: 2301 movs r3, #1
- 8000510: 425b negs r3, r3
+ 8000512: 2301 movs r3, #1
+ 8000514: 425b negs r3, r3
}
}
- 8000512: 0018 movs r0, r3
- 8000514: 46bd mov sp, r7
- 8000516: b005 add sp, #20
- 8000518: bd90 pop {r4, r7, pc}
- 800051a: 46c0 nop ; (mov r8, r8)
- 800051c: 20000030 .word 0x20000030
- 8000520: 20000034 .word 0x20000034
+ 8000516: 0018 movs r0, r3
+ 8000518: 46bd mov sp, r7
+ 800051a: b003 add sp, #12
+ 800051c: bd90 pop {r4, r7, pc}
+ 800051e: 46c0 nop ; (mov r8, r8)
+ 8000520: 20000030 .word 0x20000030
+ 8000524: 20000034 .word 0x20000034
-08000524 <i2c_receive>:
+08000528 <i2c_receive>:
-int8_t i2c_receive(uint8_t address, uint8_t *buffer, int len)
+int8_t i2c_receive(uint8_t address, uint8_t *buffer, uint16_t len)
{
- 8000524: b590 push {r4, r7, lr}
- 8000526: b087 sub sp, #28
- 8000528: af02 add r7, sp, #8
- 800052a: 60b9 str r1, [r7, #8]
- 800052c: 607a str r2, [r7, #4]
- 800052e: 210f movs r1, #15
- 8000530: 187b adds r3, r7, r1
- 8000532: 1c02 adds r2, r0, #0
- 8000534: 701a strb r2, [r3, #0]
+ 8000528: b590 push {r4, r7, lr}
+ 800052a: b085 sub sp, #20
+ 800052c: af02 add r7, sp, #8
+ 800052e: 6039 str r1, [r7, #0]
+ 8000530: 0011 movs r1, r2
+ 8000532: 1dfb adds r3, r7, #7
+ 8000534: 1c02 adds r2, r0, #0
+ 8000536: 701a strb r2, [r3, #0]
+ 8000538: 1d3b adds r3, r7, #4
+ 800053a: 1c0a adds r2, r1, #0
+ 800053c: 801a strh r2, [r3, #0]
if (HAL_I2C_Master_Receive(i2c_context, address, buffer, len, timeout) == HAL_OK)
- 8000536: 4b0c ldr r3, [pc, #48] ; (8000568 <i2c_receive+0x44>)
- 8000538: 6818 ldr r0, [r3, #0]
- 800053a: 187b adds r3, r7, r1
- 800053c: 781b ldrb r3, [r3, #0]
- 800053e: b299 uxth r1, r3
- 8000540: 687b ldr r3, [r7, #4]
- 8000542: b29c uxth r4, r3
- 8000544: 4b09 ldr r3, [pc, #36] ; (800056c <i2c_receive+0x48>)
- 8000546: 881b ldrh r3, [r3, #0]
- 8000548: 68ba ldr r2, [r7, #8]
- 800054a: 9300 str r3, [sp, #0]
- 800054c: 0023 movs r3, r4
- 800054e: f001 f9d1 bl 80018f4 <HAL_I2C_Master_Receive>
- 8000552: 1e03 subs r3, r0, #0
- 8000554: d101 bne.n 800055a <i2c_receive+0x36>
+ 800053e: 4b0c ldr r3, [pc, #48] ; (8000570 <i2c_receive+0x48>)
+ 8000540: 6818 ldr r0, [r3, #0]
+ 8000542: 1dfb adds r3, r7, #7
+ 8000544: 781b ldrb r3, [r3, #0]
+ 8000546: b299 uxth r1, r3
+ 8000548: 4b0a ldr r3, [pc, #40] ; (8000574 <i2c_receive+0x4c>)
+ 800054a: 881b ldrh r3, [r3, #0]
+ 800054c: 001c movs r4, r3
+ 800054e: 1d3b adds r3, r7, #4
+ 8000550: 881b ldrh r3, [r3, #0]
+ 8000552: 683a ldr r2, [r7, #0]
+ 8000554: 9400 str r4, [sp, #0]
+ 8000556: f001 f9d5 bl 8001904 <HAL_I2C_Master_Receive>
+ 800055a: 1e03 subs r3, r0, #0
+ 800055c: d101 bne.n 8000562 <i2c_receive+0x3a>
{
return I2C_OK;
- 8000556: 2300 movs r3, #0
- 8000558: e001 b.n 800055e <i2c_receive+0x3a>
+ 800055e: 2300 movs r3, #0
+ 8000560: e001 b.n 8000566 <i2c_receive+0x3e>
} else
{
return I2C_ERROR;
- 800055a: 2301 movs r3, #1
- 800055c: 425b negs r3, r3
+ 8000562: 2301 movs r3, #1
+ 8000564: 425b negs r3, r3
}
}
- 800055e: 0018 movs r0, r3
- 8000560: 46bd mov sp, r7
- 8000562: b005 add sp, #20
- 8000564: bd90 pop {r4, r7, pc}
- 8000566: 46c0 nop ; (mov r8, r8)
- 8000568: 20000030 .word 0x20000030
- 800056c: 20000034 .word 0x20000034
+ 8000566: 0018 movs r0, r3
+ 8000568: 46bd mov sp, r7
+ 800056a: b003 add sp, #12
+ 800056c: bd90 pop {r4, r7, pc}
+ 800056e: 46c0 nop ; (mov r8, r8)
+ 8000570: 20000030 .word 0x20000030
+ 8000574: 20000034 .word 0x20000034
-08000570 <i2c_transmit_receive>:
+08000578 <i2c_transmit_receive>:
int8_t i2c_transmit_receive(uint8_t address, uint16_t tx_buffer, uint16_t tx_len, uint8_t *rx_buffer, uint16_t rx_len)
{
- 8000570: b5f0 push {r4, r5, r6, r7, lr}
- 8000572: b089 sub sp, #36 ; 0x24
- 8000574: af04 add r7, sp, #16
- 8000576: 0004 movs r4, r0
- 8000578: 0008 movs r0, r1
- 800057a: 0011 movs r1, r2
- 800057c: 607b str r3, [r7, #4]
- 800057e: 250f movs r5, #15
- 8000580: 197b adds r3, r7, r5
- 8000582: 1c22 adds r2, r4, #0
- 8000584: 701a strb r2, [r3, #0]
- 8000586: 260c movs r6, #12
- 8000588: 19bb adds r3, r7, r6
- 800058a: 1c02 adds r2, r0, #0
- 800058c: 801a strh r2, [r3, #0]
- 800058e: 240a movs r4, #10
- 8000590: 193b adds r3, r7, r4
- 8000592: 1c0a adds r2, r1, #0
+ 8000578: b5f0 push {r4, r5, r6, r7, lr}
+ 800057a: b089 sub sp, #36 ; 0x24
+ 800057c: af04 add r7, sp, #16
+ 800057e: 0004 movs r4, r0
+ 8000580: 0008 movs r0, r1
+ 8000582: 0011 movs r1, r2
+ 8000584: 607b str r3, [r7, #4]
+ 8000586: 250f movs r5, #15
+ 8000588: 197b adds r3, r7, r5
+ 800058a: 1c22 adds r2, r4, #0
+ 800058c: 701a strb r2, [r3, #0]
+ 800058e: 260c movs r6, #12
+ 8000590: 19bb adds r3, r7, r6
+ 8000592: 1c02 adds r2, r0, #0
8000594: 801a strh r2, [r3, #0]
- if(HAL_I2C_Mem_Read(i2c_context, address, tx_buffer, tx_len, rx_buffer, rx_len, 10) == HAL_OK)
- 8000596: 4b10 ldr r3, [pc, #64] ; (80005d8 <i2c_transmit_receive+0x68>)
- 8000598: 6818 ldr r0, [r3, #0]
- 800059a: 197b adds r3, r7, r5
- 800059c: 781b ldrb r3, [r3, #0]
- 800059e: b299 uxth r1, r3
- 80005a0: 193b adds r3, r7, r4
- 80005a2: 881c ldrh r4, [r3, #0]
- 80005a4: 19bb adds r3, r7, r6
- 80005a6: 881a ldrh r2, [r3, #0]
- 80005a8: 230a movs r3, #10
- 80005aa: 9302 str r3, [sp, #8]
- 80005ac: 2320 movs r3, #32
- 80005ae: 2508 movs r5, #8
- 80005b0: 46ac mov ip, r5
- 80005b2: 44bc add ip, r7
- 80005b4: 4463 add r3, ip
- 80005b6: 881b ldrh r3, [r3, #0]
- 80005b8: 9301 str r3, [sp, #4]
- 80005ba: 687b ldr r3, [r7, #4]
- 80005bc: 9300 str r3, [sp, #0]
- 80005be: 0023 movs r3, r4
- 80005c0: f001 faa0 bl 8001b04 <HAL_I2C_Mem_Read>
- 80005c4: 1e03 subs r3, r0, #0
- 80005c6: d101 bne.n 80005cc <i2c_transmit_receive+0x5c>
+ 8000596: 240a movs r4, #10
+ 8000598: 193b adds r3, r7, r4
+ 800059a: 1c0a adds r2, r1, #0
+ 800059c: 801a strh r2, [r3, #0]
+ if(HAL_I2C_Mem_Read(i2c_context, address, tx_buffer, tx_len, rx_buffer, rx_len, timeout) == HAL_OK)
+ 800059e: 4b11 ldr r3, [pc, #68] ; (80005e4 <i2c_transmit_receive+0x6c>)
+ 80005a0: 6818 ldr r0, [r3, #0]
+ 80005a2: 197b adds r3, r7, r5
+ 80005a4: 781b ldrb r3, [r3, #0]
+ 80005a6: b299 uxth r1, r3
+ 80005a8: 4b0f ldr r3, [pc, #60] ; (80005e8 <i2c_transmit_receive+0x70>)
+ 80005aa: 881b ldrh r3, [r3, #0]
+ 80005ac: 001d movs r5, r3
+ 80005ae: 193b adds r3, r7, r4
+ 80005b0: 881c ldrh r4, [r3, #0]
+ 80005b2: 19bb adds r3, r7, r6
+ 80005b4: 881a ldrh r2, [r3, #0]
+ 80005b6: 9502 str r5, [sp, #8]
+ 80005b8: 2320 movs r3, #32
+ 80005ba: 2508 movs r5, #8
+ 80005bc: 46ac mov ip, r5
+ 80005be: 44bc add ip, r7
+ 80005c0: 4463 add r3, ip
+ 80005c2: 881b ldrh r3, [r3, #0]
+ 80005c4: 9301 str r3, [sp, #4]
+ 80005c6: 687b ldr r3, [r7, #4]
+ 80005c8: 9300 str r3, [sp, #0]
+ 80005ca: 0023 movs r3, r4
+ 80005cc: f001 faa2 bl 8001b14 <HAL_I2C_Mem_Read>
+ 80005d0: 1e03 subs r3, r0, #0
+ 80005d2: d101 bne.n 80005d8 <i2c_transmit_receive+0x60>
{
return I2C_OK;
- 80005c8: 2300 movs r3, #0
- 80005ca: e001 b.n 80005d0 <i2c_transmit_receive+0x60>
+ 80005d4: 2300 movs r3, #0
+ 80005d6: e001 b.n 80005dc <i2c_transmit_receive+0x64>
} else
{
return I2C_ERROR;
- 80005cc: 2301 movs r3, #1
- 80005ce: 425b negs r3, r3
+ 80005d8: 2301 movs r3, #1
+ 80005da: 425b negs r3, r3
}
}
- 80005d0: 0018 movs r0, r3
- 80005d2: 46bd mov sp, r7
- 80005d4: b005 add sp, #20
- 80005d6: bdf0 pop {r4, r5, r6, r7, pc}
- 80005d8: 20000030 .word 0x20000030
+ 80005dc: 0018 movs r0, r3
+ 80005de: 46bd mov sp, r7
+ 80005e0: b005 add sp, #20
+ 80005e2: bdf0 pop {r4, r5, r6, r7, pc}
+ 80005e4: 20000030 .word 0x20000030
+ 80005e8: 20000034 .word 0x20000034
-080005dc <main>:
+080005ec <main>:
/**
* @brief The application entry point.
* @retval int
*/
int main(void)
{
- 80005dc: b580 push {r7, lr}
- 80005de: af00 add r7, sp, #0
+ 80005ec: b580 push {r7, lr}
+ 80005ee: af00 add r7, sp, #0
/* USER CODE END 1 */
/* MCU Configuration--------------------------------------------------------*/
/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
HAL_Init();
- 80005e0: f000 fd34 bl 800104c <HAL_Init>
+ 80005f0: f000 fd34 bl 800105c <HAL_Init>
/* USER CODE BEGIN Init */
/* USER CODE END Init */
/* Configure the system clock */
SystemClock_Config();
- 80005e4: f000 f83c bl 8000660 <SystemClock_Config>
+ 80005f4: f000 f83c bl 8000670 <SystemClock_Config>
/* USER CODE BEGIN SysInit */
/* USER CODE END SysInit */
/* Initialize all configured peripherals */
MX_GPIO_Init();
- 80005e8: f000 fa9a bl 8000b20 <MX_GPIO_Init>
+ 80005f8: f000 fa9a bl 8000b30 <MX_GPIO_Init>
MX_I2C1_Init();
- 80005ec: f000 f8ac bl 8000748 <MX_I2C1_Init>
+ 80005fc: f000 f8ac bl 8000758 <MX_I2C1_Init>
MX_TIM2_Init();
- 80005f0: f000 f8ea bl 80007c8 <MX_TIM2_Init>
+ 8000600: f000 f8ea bl 80007d8 <MX_TIM2_Init>
MX_TIM21_Init();
- 80005f4: f000 f96e bl 80008d4 <MX_TIM21_Init>
+ 8000604: f000 f96e bl 80008e4 <MX_TIM21_Init>
MX_TIM22_Init();
- 80005f8: f000 f9c6 bl 8000988 <MX_TIM22_Init>
+ 8000608: f000 f9c6 bl 8000998 <MX_TIM22_Init>
MX_USART2_UART_Init();
- 80005fc: f000 fa5c bl 8000ab8 <MX_USART2_UART_Init>
+ 800060c: f000 fa5c bl 8000ac8 <MX_USART2_UART_Init>
/* USER CODE BEGIN 2 */
i2c_init(&hi2c1,100);
- 8000600: 4b10 ldr r3, [pc, #64] ; (8000644 <main+0x68>)
- 8000602: 2164 movs r1, #100 ; 0x64
- 8000604: 0018 movs r0, r3
- 8000606: f7ff ff49 bl 800049c <i2c_init>
+ 8000610: 4b10 ldr r3, [pc, #64] ; (8000654 <main+0x68>)
+ 8000612: 2164 movs r1, #100 ; 0x64
+ 8000614: 0018 movs r0, r3
+ 8000616: f7ff ff41 bl 800049c <i2c_init>
HAL_Delay(3000);
- 800060a: 4b0f ldr r3, [pc, #60] ; (8000648 <main+0x6c>)
- 800060c: 0018 movs r0, r3
- 800060e: f000 fd8d bl 800112c <HAL_Delay>
+ 800061a: 4b0f ldr r3, [pc, #60] ; (8000658 <main+0x6c>)
+ 800061c: 0018 movs r0, r3
+ 800061e: f000 fd8d bl 800113c <HAL_Delay>
scd4x_start_periodic_measurement();
- 8000612: f000 fac7 bl 8000ba4 <scd4x_start_periodic_measurement>
+ 8000622: f000 fac7 bl 8000bb4 <scd4x_start_periodic_measurement>
HAL_Delay(3000);
- 8000616: 4b0c ldr r3, [pc, #48] ; (8000648 <main+0x6c>)
- 8000618: 0018 movs r0, r3
- 800061a: f000 fd87 bl 800112c <HAL_Delay>
+ 8000626: 4b0c ldr r3, [pc, #48] ; (8000658 <main+0x6c>)
+ 8000628: 0018 movs r0, r3
+ 800062a: f000 fd87 bl 800113c <HAL_Delay>
/* Infinite loop */
/* USER CODE BEGIN WHILE */
while (1)
{
sht4x_measure(&T_SHT4x, &RH_SHT4x);
- 800061e: 4a0b ldr r2, [pc, #44] ; (800064c <main+0x70>)
- 8000620: 4b0b ldr r3, [pc, #44] ; (8000650 <main+0x74>)
- 8000622: 0011 movs r1, r2
- 8000624: 0018 movs r0, r3
- 8000626: f000 fb31 bl 8000c8c <sht4x_measure>
+ 800062e: 4a0b ldr r2, [pc, #44] ; (800065c <main+0x70>)
+ 8000630: 4b0b ldr r3, [pc, #44] ; (8000660 <main+0x74>)
+ 8000632: 0011 movs r1, r2
+ 8000634: 0018 movs r0, r3
+ 8000636: f000 fb31 bl 8000c9c <sht4x_measure>
scd4x_read_measurement(&CO2,
- 800062a: 4a0a ldr r2, [pc, #40] ; (8000654 <main+0x78>)
- 800062c: 490a ldr r1, [pc, #40] ; (8000658 <main+0x7c>)
- 800062e: 4b0b ldr r3, [pc, #44] ; (800065c <main+0x80>)
- 8000630: 0018 movs r0, r3
- 8000632: f000 fac3 bl 8000bbc <scd4x_read_measurement>
+ 800063a: 4a0a ldr r2, [pc, #40] ; (8000664 <main+0x78>)
+ 800063c: 490a ldr r1, [pc, #40] ; (8000668 <main+0x7c>)
+ 800063e: 4b0b ldr r3, [pc, #44] ; (800066c <main+0x80>)
+ 8000640: 0018 movs r0, r3
+ 8000642: f000 fac3 bl 8000bcc <scd4x_read_measurement>
&T_SCD4x,
&RH_SCD4x);
HAL_Delay(2000);
- 8000636: 23fa movs r3, #250 ; 0xfa
- 8000638: 00db lsls r3, r3, #3
- 800063a: 0018 movs r0, r3
- 800063c: f000 fd76 bl 800112c <HAL_Delay>
+ 8000646: 23fa movs r3, #250 ; 0xfa
+ 8000648: 00db lsls r3, r3, #3
+ 800064a: 0018 movs r0, r3
+ 800064c: f000 fd76 bl 800113c <HAL_Delay>
sht4x_measure(&T_SHT4x, &RH_SHT4x);
- 8000640: e7ed b.n 800061e <main+0x42>
- 8000642: 46c0 nop ; (mov r8, r8)
- 8000644: 2000003c .word 0x2000003c
- 8000648: 00000bb8 .word 0x00000bb8
- 800064c: 200001c8 .word 0x200001c8
- 8000650: 20000038 .word 0x20000038
- 8000654: 200000d0 .word 0x200000d0
- 8000658: 2000008c .word 0x2000008c
- 800065c: 200001c4 .word 0x200001c4
+ 8000650: e7ed b.n 800062e <main+0x42>
+ 8000652: 46c0 nop ; (mov r8, r8)
+ 8000654: 2000003c .word 0x2000003c
+ 8000658: 00000bb8 .word 0x00000bb8
+ 800065c: 200001c8 .word 0x200001c8
+ 8000660: 20000038 .word 0x20000038
+ 8000664: 200000d0 .word 0x200000d0
+ 8000668: 2000008c .word 0x2000008c
+ 800066c: 200001c4 .word 0x200001c4
-08000660 <SystemClock_Config>:
+08000670 <SystemClock_Config>:
/**
* @brief System Clock Configuration
* @retval None
*/
void SystemClock_Config(void)
{
- 8000660: b590 push {r4, r7, lr}
- 8000662: b099 sub sp, #100 ; 0x64
- 8000664: af00 add r7, sp, #0
+ 8000670: b590 push {r4, r7, lr}
+ 8000672: b099 sub sp, #100 ; 0x64
+ 8000674: af00 add r7, sp, #0
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
- 8000666: 242c movs r4, #44 ; 0x2c
- 8000668: 193b adds r3, r7, r4
- 800066a: 0018 movs r0, r3
- 800066c: 2334 movs r3, #52 ; 0x34
- 800066e: 001a movs r2, r3
- 8000670: 2100 movs r1, #0
- 8000672: f003 fe55 bl 8004320 <memset>
- RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
- 8000676: 2318 movs r3, #24
- 8000678: 18fb adds r3, r7, r3
+ 8000676: 242c movs r4, #44 ; 0x2c
+ 8000678: 193b adds r3, r7, r4
800067a: 0018 movs r0, r3
- 800067c: 2314 movs r3, #20
+ 800067c: 2334 movs r3, #52 ; 0x34
800067e: 001a movs r2, r3
8000680: 2100 movs r1, #0
- 8000682: f003 fe4d bl 8004320 <memset>
+ 8000682: f003 fe55 bl 8004330 <memset>
+ RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+ 8000686: 2318 movs r3, #24
+ 8000688: 18fb adds r3, r7, r3
+ 800068a: 0018 movs r0, r3
+ 800068c: 2314 movs r3, #20
+ 800068e: 001a movs r2, r3
+ 8000690: 2100 movs r1, #0
+ 8000692: f003 fe4d bl 8004330 <memset>
RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
- 8000686: 003b movs r3, r7
- 8000688: 0018 movs r0, r3
- 800068a: 2318 movs r3, #24
- 800068c: 001a movs r2, r3
- 800068e: 2100 movs r1, #0
- 8000690: f003 fe46 bl 8004320 <memset>
+ 8000696: 003b movs r3, r7
+ 8000698: 0018 movs r0, r3
+ 800069a: 2318 movs r3, #24
+ 800069c: 001a movs r2, r3
+ 800069e: 2100 movs r1, #0
+ 80006a0: f003 fe46 bl 8004330 <memset>
/** Configure the main internal regulator output voltage
*/
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
- 8000694: 4b2a ldr r3, [pc, #168] ; (8000740 <SystemClock_Config+0xe0>)
- 8000696: 681b ldr r3, [r3, #0]
- 8000698: 4a2a ldr r2, [pc, #168] ; (8000744 <SystemClock_Config+0xe4>)
- 800069a: 401a ands r2, r3
- 800069c: 4b28 ldr r3, [pc, #160] ; (8000740 <SystemClock_Config+0xe0>)
- 800069e: 2180 movs r1, #128 ; 0x80
- 80006a0: 0109 lsls r1, r1, #4
- 80006a2: 430a orrs r2, r1
- 80006a4: 601a str r2, [r3, #0]
+ 80006a4: 4b2a ldr r3, [pc, #168] ; (8000750 <SystemClock_Config+0xe0>)
+ 80006a6: 681b ldr r3, [r3, #0]
+ 80006a8: 4a2a ldr r2, [pc, #168] ; (8000754 <SystemClock_Config+0xe4>)
+ 80006aa: 401a ands r2, r3
+ 80006ac: 4b28 ldr r3, [pc, #160] ; (8000750 <SystemClock_Config+0xe0>)
+ 80006ae: 2180 movs r1, #128 ; 0x80
+ 80006b0: 0109 lsls r1, r1, #4
+ 80006b2: 430a orrs r2, r1
+ 80006b4: 601a str r2, [r3, #0]
/** Initializes the RCC Oscillators according to the specified parameters
* in the RCC_OscInitTypeDef structure.
*/
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
- 80006a6: 0021 movs r1, r4
- 80006a8: 187b adds r3, r7, r1
- 80006aa: 2202 movs r2, #2
- 80006ac: 601a str r2, [r3, #0]
+ 80006b6: 0021 movs r1, r4
+ 80006b8: 187b adds r3, r7, r1
+ 80006ba: 2202 movs r2, #2
+ 80006bc: 601a str r2, [r3, #0]
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
- 80006ae: 187b adds r3, r7, r1
- 80006b0: 2201 movs r2, #1
- 80006b2: 60da str r2, [r3, #12]
+ 80006be: 187b adds r3, r7, r1
+ 80006c0: 2201 movs r2, #1
+ 80006c2: 60da str r2, [r3, #12]
RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
- 80006b4: 187b adds r3, r7, r1
- 80006b6: 2210 movs r2, #16
- 80006b8: 611a str r2, [r3, #16]
+ 80006c4: 187b adds r3, r7, r1
+ 80006c6: 2210 movs r2, #16
+ 80006c8: 611a str r2, [r3, #16]
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
- 80006ba: 187b adds r3, r7, r1
- 80006bc: 2202 movs r2, #2
- 80006be: 625a str r2, [r3, #36] ; 0x24
+ 80006ca: 187b adds r3, r7, r1
+ 80006cc: 2202 movs r2, #2
+ 80006ce: 625a str r2, [r3, #36] ; 0x24
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
- 80006c0: 187b adds r3, r7, r1
- 80006c2: 2200 movs r2, #0
- 80006c4: 629a str r2, [r3, #40] ; 0x28
+ 80006d0: 187b adds r3, r7, r1
+ 80006d2: 2200 movs r2, #0
+ 80006d4: 629a str r2, [r3, #40] ; 0x28
RCC_OscInitStruct.PLL.PLLMUL = RCC_PLLMUL_3;
- 80006c6: 187b adds r3, r7, r1
- 80006c8: 2200 movs r2, #0
- 80006ca: 62da str r2, [r3, #44] ; 0x2c
+ 80006d6: 187b adds r3, r7, r1
+ 80006d8: 2200 movs r2, #0
+ 80006da: 62da str r2, [r3, #44] ; 0x2c
RCC_OscInitStruct.PLL.PLLDIV = RCC_PLLDIV_2;
- 80006cc: 187b adds r3, r7, r1
- 80006ce: 2280 movs r2, #128 ; 0x80
- 80006d0: 03d2 lsls r2, r2, #15
- 80006d2: 631a str r2, [r3, #48] ; 0x30
+ 80006dc: 187b adds r3, r7, r1
+ 80006de: 2280 movs r2, #128 ; 0x80
+ 80006e0: 03d2 lsls r2, r2, #15
+ 80006e2: 631a str r2, [r3, #48] ; 0x30
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
- 80006d4: 187b adds r3, r7, r1
- 80006d6: 0018 movs r0, r3
- 80006d8: f001 fe3a bl 8002350 <HAL_RCC_OscConfig>
- 80006dc: 1e03 subs r3, r0, #0
- 80006de: d001 beq.n 80006e4 <SystemClock_Config+0x84>
+ 80006e4: 187b adds r3, r7, r1
+ 80006e6: 0018 movs r0, r3
+ 80006e8: f001 fe3a bl 8002360 <HAL_RCC_OscConfig>
+ 80006ec: 1e03 subs r3, r0, #0
+ 80006ee: d001 beq.n 80006f4 <SystemClock_Config+0x84>
{
Error_Handler();
- 80006e0: f000 fa34 bl 8000b4c <Error_Handler>
+ 80006f0: f000 fa34 bl 8000b5c <Error_Handler>
}
/** Initializes the CPU, AHB and APB buses clocks
*/
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
- 80006e4: 2118 movs r1, #24
- 80006e6: 187b adds r3, r7, r1
- 80006e8: 220f movs r2, #15
- 80006ea: 601a str r2, [r3, #0]
+ 80006f4: 2118 movs r1, #24
+ 80006f6: 187b adds r3, r7, r1
+ 80006f8: 220f movs r2, #15
+ 80006fa: 601a str r2, [r3, #0]
|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
- 80006ec: 187b adds r3, r7, r1
- 80006ee: 2203 movs r2, #3
- 80006f0: 605a str r2, [r3, #4]
+ 80006fc: 187b adds r3, r7, r1
+ 80006fe: 2203 movs r2, #3
+ 8000700: 605a str r2, [r3, #4]
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV2;
- 80006f2: 187b adds r3, r7, r1
- 80006f4: 2280 movs r2, #128 ; 0x80
- 80006f6: 609a str r2, [r3, #8]
+ 8000702: 187b adds r3, r7, r1
+ 8000704: 2280 movs r2, #128 ; 0x80
+ 8000706: 609a str r2, [r3, #8]
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
- 80006f8: 187b adds r3, r7, r1
- 80006fa: 2200 movs r2, #0
- 80006fc: 60da str r2, [r3, #12]
+ 8000708: 187b adds r3, r7, r1
+ 800070a: 2200 movs r2, #0
+ 800070c: 60da str r2, [r3, #12]
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
- 80006fe: 187b adds r3, r7, r1
- 8000700: 2200 movs r2, #0
- 8000702: 611a str r2, [r3, #16]
+ 800070e: 187b adds r3, r7, r1
+ 8000710: 2200 movs r2, #0
+ 8000712: 611a str r2, [r3, #16]
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK)
- 8000704: 187b adds r3, r7, r1
- 8000706: 2100 movs r1, #0
- 8000708: 0018 movs r0, r3
- 800070a: f002 f99d bl 8002a48 <HAL_RCC_ClockConfig>
- 800070e: 1e03 subs r3, r0, #0
- 8000710: d001 beq.n 8000716 <SystemClock_Config+0xb6>
+ 8000714: 187b adds r3, r7, r1
+ 8000716: 2100 movs r1, #0
+ 8000718: 0018 movs r0, r3
+ 800071a: f002 f99d bl 8002a58 <HAL_RCC_ClockConfig>
+ 800071e: 1e03 subs r3, r0, #0
+ 8000720: d001 beq.n 8000726 <SystemClock_Config+0xb6>
{
Error_Handler();
- 8000712: f000 fa1b bl 8000b4c <Error_Handler>
+ 8000722: f000 fa1b bl 8000b5c <Error_Handler>
}
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART2|RCC_PERIPHCLK_I2C1;
- 8000716: 003b movs r3, r7
- 8000718: 220a movs r2, #10
- 800071a: 601a str r2, [r3, #0]
+ 8000726: 003b movs r3, r7
+ 8000728: 220a movs r2, #10
+ 800072a: 601a str r2, [r3, #0]
PeriphClkInit.Usart2ClockSelection = RCC_USART2CLKSOURCE_PCLK1;
- 800071c: 003b movs r3, r7
- 800071e: 2200 movs r2, #0
- 8000720: 609a str r2, [r3, #8]
+ 800072c: 003b movs r3, r7
+ 800072e: 2200 movs r2, #0
+ 8000730: 609a str r2, [r3, #8]
PeriphClkInit.I2c1ClockSelection = RCC_I2C1CLKSOURCE_PCLK1;
- 8000722: 003b movs r3, r7
- 8000724: 2200 movs r2, #0
- 8000726: 611a str r2, [r3, #16]
+ 8000732: 003b movs r3, r7
+ 8000734: 2200 movs r2, #0
+ 8000736: 611a str r2, [r3, #16]
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
- 8000728: 003b movs r3, r7
- 800072a: 0018 movs r0, r3
- 800072c: f002 fbb0 bl 8002e90 <HAL_RCCEx_PeriphCLKConfig>
- 8000730: 1e03 subs r3, r0, #0
- 8000732: d001 beq.n 8000738 <SystemClock_Config+0xd8>
+ 8000738: 003b movs r3, r7
+ 800073a: 0018 movs r0, r3
+ 800073c: f002 fbb0 bl 8002ea0 <HAL_RCCEx_PeriphCLKConfig>
+ 8000740: 1e03 subs r3, r0, #0
+ 8000742: d001 beq.n 8000748 <SystemClock_Config+0xd8>
{
Error_Handler();
- 8000734: f000 fa0a bl 8000b4c <Error_Handler>
+ 8000744: f000 fa0a bl 8000b5c <Error_Handler>
}
}
- 8000738: 46c0 nop ; (mov r8, r8)
- 800073a: 46bd mov sp, r7
- 800073c: b019 add sp, #100 ; 0x64
- 800073e: bd90 pop {r4, r7, pc}
- 8000740: 40007000 .word 0x40007000
- 8000744: ffffe7ff .word 0xffffe7ff
+ 8000748: 46c0 nop ; (mov r8, r8)
+ 800074a: 46bd mov sp, r7
+ 800074c: b019 add sp, #100 ; 0x64
+ 800074e: bd90 pop {r4, r7, pc}
+ 8000750: 40007000 .word 0x40007000
+ 8000754: ffffe7ff .word 0xffffe7ff
-08000748 <MX_I2C1_Init>:
+08000758 <MX_I2C1_Init>:
* @brief I2C1 Initialization Function
* @param None
* @retval None
*/
static void MX_I2C1_Init(void)
{
- 8000748: b580 push {r7, lr}
- 800074a: af00 add r7, sp, #0
+ 8000758: b580 push {r7, lr}
+ 800075a: af00 add r7, sp, #0
/* USER CODE END I2C1_Init 0 */
/* USER CODE BEGIN I2C1_Init 1 */
/* USER CODE END I2C1_Init 1 */
hi2c1.Instance = I2C1;
- 800074c: 4b1b ldr r3, [pc, #108] ; (80007bc <MX_I2C1_Init+0x74>)
- 800074e: 4a1c ldr r2, [pc, #112] ; (80007c0 <MX_I2C1_Init+0x78>)
- 8000750: 601a str r2, [r3, #0]
+ 800075c: 4b1b ldr r3, [pc, #108] ; (80007cc <MX_I2C1_Init+0x74>)
+ 800075e: 4a1c ldr r2, [pc, #112] ; (80007d0 <MX_I2C1_Init+0x78>)
+ 8000760: 601a str r2, [r3, #0]
hi2c1.Init.Timing = 0x40000A0B;
- 8000752: 4b1a ldr r3, [pc, #104] ; (80007bc <MX_I2C1_Init+0x74>)
- 8000754: 4a1b ldr r2, [pc, #108] ; (80007c4 <MX_I2C1_Init+0x7c>)
- 8000756: 605a str r2, [r3, #4]
+ 8000762: 4b1a ldr r3, [pc, #104] ; (80007cc <MX_I2C1_Init+0x74>)
+ 8000764: 4a1b ldr r2, [pc, #108] ; (80007d4 <MX_I2C1_Init+0x7c>)
+ 8000766: 605a str r2, [r3, #4]
hi2c1.Init.OwnAddress1 = 0;
- 8000758: 4b18 ldr r3, [pc, #96] ; (80007bc <MX_I2C1_Init+0x74>)
- 800075a: 2200 movs r2, #0
- 800075c: 609a str r2, [r3, #8]
+ 8000768: 4b18 ldr r3, [pc, #96] ; (80007cc <MX_I2C1_Init+0x74>)
+ 800076a: 2200 movs r2, #0
+ 800076c: 609a str r2, [r3, #8]
hi2c1.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT;
- 800075e: 4b17 ldr r3, [pc, #92] ; (80007bc <MX_I2C1_Init+0x74>)
- 8000760: 2201 movs r2, #1
- 8000762: 60da str r2, [r3, #12]
+ 800076e: 4b17 ldr r3, [pc, #92] ; (80007cc <MX_I2C1_Init+0x74>)
+ 8000770: 2201 movs r2, #1
+ 8000772: 60da str r2, [r3, #12]
hi2c1.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE;
- 8000764: 4b15 ldr r3, [pc, #84] ; (80007bc <MX_I2C1_Init+0x74>)
- 8000766: 2200 movs r2, #0
- 8000768: 611a str r2, [r3, #16]
+ 8000774: 4b15 ldr r3, [pc, #84] ; (80007cc <MX_I2C1_Init+0x74>)
+ 8000776: 2200 movs r2, #0
+ 8000778: 611a str r2, [r3, #16]
hi2c1.Init.OwnAddress2 = 0;
- 800076a: 4b14 ldr r3, [pc, #80] ; (80007bc <MX_I2C1_Init+0x74>)
- 800076c: 2200 movs r2, #0
- 800076e: 615a str r2, [r3, #20]
+ 800077a: 4b14 ldr r3, [pc, #80] ; (80007cc <MX_I2C1_Init+0x74>)
+ 800077c: 2200 movs r2, #0
+ 800077e: 615a str r2, [r3, #20]
hi2c1.Init.OwnAddress2Masks = I2C_OA2_NOMASK;
- 8000770: 4b12 ldr r3, [pc, #72] ; (80007bc <MX_I2C1_Init+0x74>)
- 8000772: 2200 movs r2, #0
- 8000774: 619a str r2, [r3, #24]
+ 8000780: 4b12 ldr r3, [pc, #72] ; (80007cc <MX_I2C1_Init+0x74>)
+ 8000782: 2200 movs r2, #0
+ 8000784: 619a str r2, [r3, #24]
hi2c1.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE;
- 8000776: 4b11 ldr r3, [pc, #68] ; (80007bc <MX_I2C1_Init+0x74>)
- 8000778: 2200 movs r2, #0
- 800077a: 61da str r2, [r3, #28]
+ 8000786: 4b11 ldr r3, [pc, #68] ; (80007cc <MX_I2C1_Init+0x74>)
+ 8000788: 2200 movs r2, #0
+ 800078a: 61da str r2, [r3, #28]
hi2c1.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE;
- 800077c: 4b0f ldr r3, [pc, #60] ; (80007bc <MX_I2C1_Init+0x74>)
- 800077e: 2200 movs r2, #0
- 8000780: 621a str r2, [r3, #32]
+ 800078c: 4b0f ldr r3, [pc, #60] ; (80007cc <MX_I2C1_Init+0x74>)
+ 800078e: 2200 movs r2, #0
+ 8000790: 621a str r2, [r3, #32]
if (HAL_I2C_Init(&hi2c1) != HAL_OK)
- 8000782: 4b0e ldr r3, [pc, #56] ; (80007bc <MX_I2C1_Init+0x74>)
- 8000784: 0018 movs r0, r3
- 8000786: f000 ff17 bl 80015b8 <HAL_I2C_Init>
- 800078a: 1e03 subs r3, r0, #0
- 800078c: d001 beq.n 8000792 <MX_I2C1_Init+0x4a>
+ 8000792: 4b0e ldr r3, [pc, #56] ; (80007cc <MX_I2C1_Init+0x74>)
+ 8000794: 0018 movs r0, r3
+ 8000796: f000 ff17 bl 80015c8 <HAL_I2C_Init>
+ 800079a: 1e03 subs r3, r0, #0
+ 800079c: d001 beq.n 80007a2 <MX_I2C1_Init+0x4a>
{
Error_Handler();
- 800078e: f000 f9dd bl 8000b4c <Error_Handler>
+ 800079e: f000 f9dd bl 8000b5c <Error_Handler>
}
/** Configure Analogue filter
*/
if (HAL_I2CEx_ConfigAnalogFilter(&hi2c1, I2C_ANALOGFILTER_ENABLE) != HAL_OK)
- 8000792: 4b0a ldr r3, [pc, #40] ; (80007bc <MX_I2C1_Init+0x74>)
- 8000794: 2100 movs r1, #0
- 8000796: 0018 movs r0, r3
- 8000798: f001 fd42 bl 8002220 <HAL_I2CEx_ConfigAnalogFilter>
- 800079c: 1e03 subs r3, r0, #0
- 800079e: d001 beq.n 80007a4 <MX_I2C1_Init+0x5c>
+ 80007a2: 4b0a ldr r3, [pc, #40] ; (80007cc <MX_I2C1_Init+0x74>)
+ 80007a4: 2100 movs r1, #0
+ 80007a6: 0018 movs r0, r3
+ 80007a8: f001 fd42 bl 8002230 <HAL_I2CEx_ConfigAnalogFilter>
+ 80007ac: 1e03 subs r3, r0, #0
+ 80007ae: d001 beq.n 80007b4 <MX_I2C1_Init+0x5c>
{
Error_Handler();
- 80007a0: f000 f9d4 bl 8000b4c <Error_Handler>
+ 80007b0: f000 f9d4 bl 8000b5c <Error_Handler>
}
/** Configure Digital filter
*/
if (HAL_I2CEx_ConfigDigitalFilter(&hi2c1, 0) != HAL_OK)
- 80007a4: 4b05 ldr r3, [pc, #20] ; (80007bc <MX_I2C1_Init+0x74>)
- 80007a6: 2100 movs r1, #0
- 80007a8: 0018 movs r0, r3
- 80007aa: f001 fd85 bl 80022b8 <HAL_I2CEx_ConfigDigitalFilter>
- 80007ae: 1e03 subs r3, r0, #0
- 80007b0: d001 beq.n 80007b6 <MX_I2C1_Init+0x6e>
+ 80007b4: 4b05 ldr r3, [pc, #20] ; (80007cc <MX_I2C1_Init+0x74>)
+ 80007b6: 2100 movs r1, #0
+ 80007b8: 0018 movs r0, r3
+ 80007ba: f001 fd85 bl 80022c8 <HAL_I2CEx_ConfigDigitalFilter>
+ 80007be: 1e03 subs r3, r0, #0
+ 80007c0: d001 beq.n 80007c6 <MX_I2C1_Init+0x6e>
{
Error_Handler();
- 80007b2: f000 f9cb bl 8000b4c <Error_Handler>
+ 80007c2: f000 f9cb bl 8000b5c <Error_Handler>
}
/* USER CODE BEGIN I2C1_Init 2 */
/* USER CODE END I2C1_Init 2 */
}
- 80007b6: 46c0 nop ; (mov r8, r8)
- 80007b8: 46bd mov sp, r7
- 80007ba: bd80 pop {r7, pc}
- 80007bc: 2000003c .word 0x2000003c
- 80007c0: 40005400 .word 0x40005400
- 80007c4: 40000a0b .word 0x40000a0b
+ 80007c6: 46c0 nop ; (mov r8, r8)
+ 80007c8: 46bd mov sp, r7
+ 80007ca: bd80 pop {r7, pc}
+ 80007cc: 2000003c .word 0x2000003c
+ 80007d0: 40005400 .word 0x40005400
+ 80007d4: 40000a0b .word 0x40000a0b
-080007c8 <MX_TIM2_Init>:
+080007d8 <MX_TIM2_Init>:
* @brief TIM2 Initialization Function
* @param None
* @retval None
*/
static void MX_TIM2_Init(void)
{
- 80007c8: b580 push {r7, lr}
- 80007ca: b08a sub sp, #40 ; 0x28
- 80007cc: af00 add r7, sp, #0
+ 80007d8: b580 push {r7, lr}
+ 80007da: b08a sub sp, #40 ; 0x28
+ 80007dc: af00 add r7, sp, #0
/* USER CODE BEGIN TIM2_Init 0 */
/* USER CODE END TIM2_Init 0 */
TIM_ClockConfigTypeDef sClockSourceConfig = {0};
- 80007ce: 2318 movs r3, #24
- 80007d0: 18fb adds r3, r7, r3
- 80007d2: 0018 movs r0, r3
- 80007d4: 2310 movs r3, #16
- 80007d6: 001a movs r2, r3
- 80007d8: 2100 movs r1, #0
- 80007da: f003 fda1 bl 8004320 <memset>
- TIM_MasterConfigTypeDef sMasterConfig = {0};
- 80007de: 2310 movs r3, #16
+ 80007de: 2318 movs r3, #24
80007e0: 18fb adds r3, r7, r3
80007e2: 0018 movs r0, r3
- 80007e4: 2308 movs r3, #8
+ 80007e4: 2310 movs r3, #16
80007e6: 001a movs r2, r3
80007e8: 2100 movs r1, #0
- 80007ea: f003 fd99 bl 8004320 <memset>
+ 80007ea: f003 fda1 bl 8004330 <memset>
+ TIM_MasterConfigTypeDef sMasterConfig = {0};
+ 80007ee: 2310 movs r3, #16
+ 80007f0: 18fb adds r3, r7, r3
+ 80007f2: 0018 movs r0, r3
+ 80007f4: 2308 movs r3, #8
+ 80007f6: 001a movs r2, r3
+ 80007f8: 2100 movs r1, #0
+ 80007fa: f003 fd99 bl 8004330 <memset>
TIM_OC_InitTypeDef sConfigOC = {0};
- 80007ee: 003b movs r3, r7
- 80007f0: 0018 movs r0, r3
- 80007f2: 2310 movs r3, #16
- 80007f4: 001a movs r2, r3
- 80007f6: 2100 movs r1, #0
- 80007f8: f003 fd92 bl 8004320 <memset>
+ 80007fe: 003b movs r3, r7
+ 8000800: 0018 movs r0, r3
+ 8000802: 2310 movs r3, #16
+ 8000804: 001a movs r2, r3
+ 8000806: 2100 movs r1, #0
+ 8000808: f003 fd92 bl 8004330 <memset>
/* USER CODE BEGIN TIM2_Init 1 */
/* USER CODE END TIM2_Init 1 */
htim2.Instance = TIM2;
- 80007fc: 4b32 ldr r3, [pc, #200] ; (80008c8 <MX_TIM2_Init+0x100>)
- 80007fe: 2280 movs r2, #128 ; 0x80
- 8000800: 05d2 lsls r2, r2, #23
- 8000802: 601a str r2, [r3, #0]
+ 800080c: 4b32 ldr r3, [pc, #200] ; (80008d8 <MX_TIM2_Init+0x100>)
+ 800080e: 2280 movs r2, #128 ; 0x80
+ 8000810: 05d2 lsls r2, r2, #23
+ 8000812: 601a str r2, [r3, #0]
htim2.Init.Prescaler = led_pwm_prescaler;
- 8000804: 4b31 ldr r3, [pc, #196] ; (80008cc <MX_TIM2_Init+0x104>)
- 8000806: 001a movs r2, r3
- 8000808: 4b2f ldr r3, [pc, #188] ; (80008c8 <MX_TIM2_Init+0x100>)
- 800080a: 605a str r2, [r3, #4]
+ 8000814: 4b31 ldr r3, [pc, #196] ; (80008dc <MX_TIM2_Init+0x104>)
+ 8000816: 001a movs r2, r3
+ 8000818: 4b2f ldr r3, [pc, #188] ; (80008d8 <MX_TIM2_Init+0x100>)
+ 800081a: 605a str r2, [r3, #4]
htim2.Init.CounterMode = TIM_COUNTERMODE_UP;
- 800080c: 4b2e ldr r3, [pc, #184] ; (80008c8 <MX_TIM2_Init+0x100>)
- 800080e: 2200 movs r2, #0
- 8000810: 609a str r2, [r3, #8]
+ 800081c: 4b2e ldr r3, [pc, #184] ; (80008d8 <MX_TIM2_Init+0x100>)
+ 800081e: 2200 movs r2, #0
+ 8000820: 609a str r2, [r3, #8]
htim2.Init.Period = led_pwm_period;
- 8000812: 2363 movs r3, #99 ; 0x63
- 8000814: 001a movs r2, r3
- 8000816: 4b2c ldr r3, [pc, #176] ; (80008c8 <MX_TIM2_Init+0x100>)
- 8000818: 60da str r2, [r3, #12]
+ 8000822: 2363 movs r3, #99 ; 0x63
+ 8000824: 001a movs r2, r3
+ 8000826: 4b2c ldr r3, [pc, #176] ; (80008d8 <MX_TIM2_Init+0x100>)
+ 8000828: 60da str r2, [r3, #12]
htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
- 800081a: 4b2b ldr r3, [pc, #172] ; (80008c8 <MX_TIM2_Init+0x100>)
- 800081c: 2200 movs r2, #0
- 800081e: 611a str r2, [r3, #16]
+ 800082a: 4b2b ldr r3, [pc, #172] ; (80008d8 <MX_TIM2_Init+0x100>)
+ 800082c: 2200 movs r2, #0
+ 800082e: 611a str r2, [r3, #16]
htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_ENABLE;
- 8000820: 4b29 ldr r3, [pc, #164] ; (80008c8 <MX_TIM2_Init+0x100>)
- 8000822: 2280 movs r2, #128 ; 0x80
- 8000824: 615a str r2, [r3, #20]
+ 8000830: 4b29 ldr r3, [pc, #164] ; (80008d8 <MX_TIM2_Init+0x100>)
+ 8000832: 2280 movs r2, #128 ; 0x80
+ 8000834: 615a str r2, [r3, #20]
if (HAL_TIM_Base_Init(&htim2) != HAL_OK)
- 8000826: 4b28 ldr r3, [pc, #160] ; (80008c8 <MX_TIM2_Init+0x100>)
- 8000828: 0018 movs r0, r3
- 800082a: f002 fc57 bl 80030dc <HAL_TIM_Base_Init>
- 800082e: 1e03 subs r3, r0, #0
- 8000830: d001 beq.n 8000836 <MX_TIM2_Init+0x6e>
+ 8000836: 4b28 ldr r3, [pc, #160] ; (80008d8 <MX_TIM2_Init+0x100>)
+ 8000838: 0018 movs r0, r3
+ 800083a: f002 fc57 bl 80030ec <HAL_TIM_Base_Init>
+ 800083e: 1e03 subs r3, r0, #0
+ 8000840: d001 beq.n 8000846 <MX_TIM2_Init+0x6e>
{
Error_Handler();
- 8000832: f000 f98b bl 8000b4c <Error_Handler>
+ 8000842: f000 f98b bl 8000b5c <Error_Handler>
}
sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
- 8000836: 2118 movs r1, #24
- 8000838: 187b adds r3, r7, r1
- 800083a: 2280 movs r2, #128 ; 0x80
- 800083c: 0152 lsls r2, r2, #5
- 800083e: 601a str r2, [r3, #0]
+ 8000846: 2118 movs r1, #24
+ 8000848: 187b adds r3, r7, r1
+ 800084a: 2280 movs r2, #128 ; 0x80
+ 800084c: 0152 lsls r2, r2, #5
+ 800084e: 601a str r2, [r3, #0]
if (HAL_TIM_ConfigClockSource(&htim2, &sClockSourceConfig) != HAL_OK)
- 8000840: 187a adds r2, r7, r1
- 8000842: 4b21 ldr r3, [pc, #132] ; (80008c8 <MX_TIM2_Init+0x100>)
- 8000844: 0011 movs r1, r2
- 8000846: 0018 movs r0, r3
- 8000848: f002 fd96 bl 8003378 <HAL_TIM_ConfigClockSource>
- 800084c: 1e03 subs r3, r0, #0
- 800084e: d001 beq.n 8000854 <MX_TIM2_Init+0x8c>
+ 8000850: 187a adds r2, r7, r1
+ 8000852: 4b21 ldr r3, [pc, #132] ; (80008d8 <MX_TIM2_Init+0x100>)
+ 8000854: 0011 movs r1, r2
+ 8000856: 0018 movs r0, r3
+ 8000858: f002 fd96 bl 8003388 <HAL_TIM_ConfigClockSource>
+ 800085c: 1e03 subs r3, r0, #0
+ 800085e: d001 beq.n 8000864 <MX_TIM2_Init+0x8c>
{
Error_Handler();
- 8000850: f000 f97c bl 8000b4c <Error_Handler>
+ 8000860: f000 f97c bl 8000b5c <Error_Handler>
}
if (HAL_TIM_PWM_Init(&htim2) != HAL_OK)
- 8000854: 4b1c ldr r3, [pc, #112] ; (80008c8 <MX_TIM2_Init+0x100>)
- 8000856: 0018 movs r0, r3
- 8000858: f002 fc80 bl 800315c <HAL_TIM_PWM_Init>
- 800085c: 1e03 subs r3, r0, #0
- 800085e: d001 beq.n 8000864 <MX_TIM2_Init+0x9c>
+ 8000864: 4b1c ldr r3, [pc, #112] ; (80008d8 <MX_TIM2_Init+0x100>)
+ 8000866: 0018 movs r0, r3
+ 8000868: f002 fc80 bl 800316c <HAL_TIM_PWM_Init>
+ 800086c: 1e03 subs r3, r0, #0
+ 800086e: d001 beq.n 8000874 <MX_TIM2_Init+0x9c>
{
Error_Handler();
- 8000860: f000 f974 bl 8000b4c <Error_Handler>
+ 8000870: f000 f974 bl 8000b5c <Error_Handler>
}
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
- 8000864: 2110 movs r1, #16
- 8000866: 187b adds r3, r7, r1
- 8000868: 2200 movs r2, #0
- 800086a: 601a str r2, [r3, #0]
+ 8000874: 2110 movs r1, #16
+ 8000876: 187b adds r3, r7, r1
+ 8000878: 2200 movs r2, #0
+ 800087a: 601a str r2, [r3, #0]
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
- 800086c: 187b adds r3, r7, r1
- 800086e: 2200 movs r2, #0
- 8000870: 605a str r2, [r3, #4]
+ 800087c: 187b adds r3, r7, r1
+ 800087e: 2200 movs r2, #0
+ 8000880: 605a str r2, [r3, #4]
if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK)
- 8000872: 187a adds r2, r7, r1
- 8000874: 4b14 ldr r3, [pc, #80] ; (80008c8 <MX_TIM2_Init+0x100>)
- 8000876: 0011 movs r1, r2
- 8000878: 0018 movs r0, r3
- 800087a: f003 f843 bl 8003904 <HAL_TIMEx_MasterConfigSynchronization>
- 800087e: 1e03 subs r3, r0, #0
- 8000880: d001 beq.n 8000886 <MX_TIM2_Init+0xbe>
+ 8000882: 187a adds r2, r7, r1
+ 8000884: 4b14 ldr r3, [pc, #80] ; (80008d8 <MX_TIM2_Init+0x100>)
+ 8000886: 0011 movs r1, r2
+ 8000888: 0018 movs r0, r3
+ 800088a: f003 f843 bl 8003914 <HAL_TIMEx_MasterConfigSynchronization>
+ 800088e: 1e03 subs r3, r0, #0
+ 8000890: d001 beq.n 8000896 <MX_TIM2_Init+0xbe>
{
Error_Handler();
- 8000882: f000 f963 bl 8000b4c <Error_Handler>
+ 8000892: f000 f963 bl 8000b5c <Error_Handler>
}
sConfigOC.OCMode = TIM_OCMODE_PWM1;
- 8000886: 003b movs r3, r7
- 8000888: 2260 movs r2, #96 ; 0x60
- 800088a: 601a str r2, [r3, #0]
- sConfigOC.Pulse = led_pwm_pulse_b;
- 800088c: 4b10 ldr r3, [pc, #64] ; (80008d0 <MX_TIM2_Init+0x108>)
- 800088e: 881b ldrh r3, [r3, #0]
- 8000890: 001a movs r2, r3
- 8000892: 003b movs r3, r7
- 8000894: 605a str r2, [r3, #4]
- sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
8000896: 003b movs r3, r7
- 8000898: 2200 movs r2, #0
- 800089a: 609a str r2, [r3, #8]
+ 8000898: 2260 movs r2, #96 ; 0x60
+ 800089a: 601a str r2, [r3, #0]
+ sConfigOC.Pulse = led_pwm_pulse_b;
+ 800089c: 4b10 ldr r3, [pc, #64] ; (80008e0 <MX_TIM2_Init+0x108>)
+ 800089e: 881b ldrh r3, [r3, #0]
+ 80008a0: 001a movs r2, r3
+ 80008a2: 003b movs r3, r7
+ 80008a4: 605a str r2, [r3, #4]
+ sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
+ 80008a6: 003b movs r3, r7
+ 80008a8: 2200 movs r2, #0
+ 80008aa: 609a str r2, [r3, #8]
sConfigOC.OCFastMode = TIM_OCFAST_DISABLE;
- 800089c: 003b movs r3, r7
- 800089e: 2200 movs r2, #0
- 80008a0: 60da str r2, [r3, #12]
+ 80008ac: 003b movs r3, r7
+ 80008ae: 2200 movs r2, #0
+ 80008b0: 60da str r2, [r3, #12]
if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_1) != HAL_OK)
- 80008a2: 0039 movs r1, r7
- 80008a4: 4b08 ldr r3, [pc, #32] ; (80008c8 <MX_TIM2_Init+0x100>)
- 80008a6: 2200 movs r2, #0
- 80008a8: 0018 movs r0, r3
- 80008aa: f002 fc9f bl 80031ec <HAL_TIM_PWM_ConfigChannel>
- 80008ae: 1e03 subs r3, r0, #0
- 80008b0: d001 beq.n 80008b6 <MX_TIM2_Init+0xee>
+ 80008b2: 0039 movs r1, r7
+ 80008b4: 4b08 ldr r3, [pc, #32] ; (80008d8 <MX_TIM2_Init+0x100>)
+ 80008b6: 2200 movs r2, #0
+ 80008b8: 0018 movs r0, r3
+ 80008ba: f002 fc9f bl 80031fc <HAL_TIM_PWM_ConfigChannel>
+ 80008be: 1e03 subs r3, r0, #0
+ 80008c0: d001 beq.n 80008c6 <MX_TIM2_Init+0xee>
{
Error_Handler();
- 80008b2: f000 f94b bl 8000b4c <Error_Handler>
+ 80008c2: f000 f94b bl 8000b5c <Error_Handler>
}
/* USER CODE BEGIN TIM2_Init 2 */
/* USER CODE END TIM2_Init 2 */
HAL_TIM_MspPostInit(&htim2);
- 80008b6: 4b04 ldr r3, [pc, #16] ; (80008c8 <MX_TIM2_Init+0x100>)
- 80008b8: 0018 movs r0, r3
- 80008ba: f000 fad7 bl 8000e6c <HAL_TIM_MspPostInit>
+ 80008c6: 4b04 ldr r3, [pc, #16] ; (80008d8 <MX_TIM2_Init+0x100>)
+ 80008c8: 0018 movs r0, r3
+ 80008ca: f000 fad7 bl 8000e7c <HAL_TIM_MspPostInit>
}
- 80008be: 46c0 nop ; (mov r8, r8)
- 80008c0: 46bd mov sp, r7
- 80008c2: b00a add sp, #40 ; 0x28
- 80008c4: bd80 pop {r7, pc}
- 80008c6: 46c0 nop ; (mov r8, r8)
- 80008c8: 20000100 .word 0x20000100
- 80008cc: 000004af .word 0x000004af
- 80008d0: 2000002c .word 0x2000002c
+ 80008ce: 46c0 nop ; (mov r8, r8)
+ 80008d0: 46bd mov sp, r7
+ 80008d2: b00a add sp, #40 ; 0x28
+ 80008d4: bd80 pop {r7, pc}
+ 80008d6: 46c0 nop ; (mov r8, r8)
+ 80008d8: 20000100 .word 0x20000100
+ 80008dc: 000004af .word 0x000004af
+ 80008e0: 2000002c .word 0x2000002c
-080008d4 <MX_TIM21_Init>:
+080008e4 <MX_TIM21_Init>:
* @brief TIM21 Initialization Function
* @param None
* @retval None
*/
static void MX_TIM21_Init(void)
{
- 80008d4: b580 push {r7, lr}
- 80008d6: b086 sub sp, #24
- 80008d8: af00 add r7, sp, #0
+ 80008e4: b580 push {r7, lr}
+ 80008e6: b086 sub sp, #24
+ 80008e8: af00 add r7, sp, #0
/* USER CODE BEGIN TIM21_Init 0 */
/* USER CODE END TIM21_Init 0 */
TIM_ClockConfigTypeDef sClockSourceConfig = {0};
- 80008da: 2308 movs r3, #8
- 80008dc: 18fb adds r3, r7, r3
- 80008de: 0018 movs r0, r3
- 80008e0: 2310 movs r3, #16
- 80008e2: 001a movs r2, r3
- 80008e4: 2100 movs r1, #0
- 80008e6: f003 fd1b bl 8004320 <memset>
+ 80008ea: 2308 movs r3, #8
+ 80008ec: 18fb adds r3, r7, r3
+ 80008ee: 0018 movs r0, r3
+ 80008f0: 2310 movs r3, #16
+ 80008f2: 001a movs r2, r3
+ 80008f4: 2100 movs r1, #0
+ 80008f6: f003 fd1b bl 8004330 <memset>
TIM_MasterConfigTypeDef sMasterConfig = {0};
- 80008ea: 003b movs r3, r7
- 80008ec: 0018 movs r0, r3
- 80008ee: 2308 movs r3, #8
- 80008f0: 001a movs r2, r3
- 80008f2: 2100 movs r1, #0
- 80008f4: f003 fd14 bl 8004320 <memset>
+ 80008fa: 003b movs r3, r7
+ 80008fc: 0018 movs r0, r3
+ 80008fe: 2308 movs r3, #8
+ 8000900: 001a movs r2, r3
+ 8000902: 2100 movs r1, #0
+ 8000904: f003 fd14 bl 8004330 <memset>
/* USER CODE BEGIN TIM21_Init 1 */
/* USER CODE END TIM21_Init 1 */
htim21.Instance = TIM21;
- 80008f8: 4b1f ldr r3, [pc, #124] ; (8000978 <MX_TIM21_Init+0xa4>)
- 80008fa: 4a20 ldr r2, [pc, #128] ; (800097c <MX_TIM21_Init+0xa8>)
- 80008fc: 601a str r2, [r3, #0]
+ 8000908: 4b1f ldr r3, [pc, #124] ; (8000988 <MX_TIM21_Init+0xa4>)
+ 800090a: 4a20 ldr r2, [pc, #128] ; (800098c <MX_TIM21_Init+0xa8>)
+ 800090c: 601a str r2, [r3, #0]
htim21.Init.Prescaler = tim21_prescaler;
- 80008fe: 4b20 ldr r3, [pc, #128] ; (8000980 <MX_TIM21_Init+0xac>)
- 8000900: 001a movs r2, r3
- 8000902: 4b1d ldr r3, [pc, #116] ; (8000978 <MX_TIM21_Init+0xa4>)
- 8000904: 605a str r2, [r3, #4]
+ 800090e: 4b20 ldr r3, [pc, #128] ; (8000990 <MX_TIM21_Init+0xac>)
+ 8000910: 001a movs r2, r3
+ 8000912: 4b1d ldr r3, [pc, #116] ; (8000988 <MX_TIM21_Init+0xa4>)
+ 8000914: 605a str r2, [r3, #4]
htim21.Init.CounterMode = TIM_COUNTERMODE_UP;
- 8000906: 4b1c ldr r3, [pc, #112] ; (8000978 <MX_TIM21_Init+0xa4>)
- 8000908: 2200 movs r2, #0
- 800090a: 609a str r2, [r3, #8]
+ 8000916: 4b1c ldr r3, [pc, #112] ; (8000988 <MX_TIM21_Init+0xa4>)
+ 8000918: 2200 movs r2, #0
+ 800091a: 609a str r2, [r3, #8]
htim21.Init.Period = tim21_period;
- 800090c: 4b1d ldr r3, [pc, #116] ; (8000984 <MX_TIM21_Init+0xb0>)
- 800090e: 001a movs r2, r3
- 8000910: 4b19 ldr r3, [pc, #100] ; (8000978 <MX_TIM21_Init+0xa4>)
- 8000912: 60da str r2, [r3, #12]
+ 800091c: 4b1d ldr r3, [pc, #116] ; (8000994 <MX_TIM21_Init+0xb0>)
+ 800091e: 001a movs r2, r3
+ 8000920: 4b19 ldr r3, [pc, #100] ; (8000988 <MX_TIM21_Init+0xa4>)
+ 8000922: 60da str r2, [r3, #12]
htim21.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
- 8000914: 4b18 ldr r3, [pc, #96] ; (8000978 <MX_TIM21_Init+0xa4>)
- 8000916: 2200 movs r2, #0
- 8000918: 611a str r2, [r3, #16]
+ 8000924: 4b18 ldr r3, [pc, #96] ; (8000988 <MX_TIM21_Init+0xa4>)
+ 8000926: 2200 movs r2, #0
+ 8000928: 611a str r2, [r3, #16]
htim21.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_ENABLE;
- 800091a: 4b17 ldr r3, [pc, #92] ; (8000978 <MX_TIM21_Init+0xa4>)
- 800091c: 2280 movs r2, #128 ; 0x80
- 800091e: 615a str r2, [r3, #20]
+ 800092a: 4b17 ldr r3, [pc, #92] ; (8000988 <MX_TIM21_Init+0xa4>)
+ 800092c: 2280 movs r2, #128 ; 0x80
+ 800092e: 615a str r2, [r3, #20]
if (HAL_TIM_Base_Init(&htim21) != HAL_OK)
- 8000920: 4b15 ldr r3, [pc, #84] ; (8000978 <MX_TIM21_Init+0xa4>)
- 8000922: 0018 movs r0, r3
- 8000924: f002 fbda bl 80030dc <HAL_TIM_Base_Init>
- 8000928: 1e03 subs r3, r0, #0
- 800092a: d001 beq.n 8000930 <MX_TIM21_Init+0x5c>
+ 8000930: 4b15 ldr r3, [pc, #84] ; (8000988 <MX_TIM21_Init+0xa4>)
+ 8000932: 0018 movs r0, r3
+ 8000934: f002 fbda bl 80030ec <HAL_TIM_Base_Init>
+ 8000938: 1e03 subs r3, r0, #0
+ 800093a: d001 beq.n 8000940 <MX_TIM21_Init+0x5c>
{
Error_Handler();
- 800092c: f000 f90e bl 8000b4c <Error_Handler>
+ 800093c: f000 f90e bl 8000b5c <Error_Handler>
}
sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
- 8000930: 2108 movs r1, #8
- 8000932: 187b adds r3, r7, r1
- 8000934: 2280 movs r2, #128 ; 0x80
- 8000936: 0152 lsls r2, r2, #5
- 8000938: 601a str r2, [r3, #0]
+ 8000940: 2108 movs r1, #8
+ 8000942: 187b adds r3, r7, r1
+ 8000944: 2280 movs r2, #128 ; 0x80
+ 8000946: 0152 lsls r2, r2, #5
+ 8000948: 601a str r2, [r3, #0]
if (HAL_TIM_ConfigClockSource(&htim21, &sClockSourceConfig) != HAL_OK)
- 800093a: 187a adds r2, r7, r1
- 800093c: 4b0e ldr r3, [pc, #56] ; (8000978 <MX_TIM21_Init+0xa4>)
- 800093e: 0011 movs r1, r2
- 8000940: 0018 movs r0, r3
- 8000942: f002 fd19 bl 8003378 <HAL_TIM_ConfigClockSource>
- 8000946: 1e03 subs r3, r0, #0
- 8000948: d001 beq.n 800094e <MX_TIM21_Init+0x7a>
+ 800094a: 187a adds r2, r7, r1
+ 800094c: 4b0e ldr r3, [pc, #56] ; (8000988 <MX_TIM21_Init+0xa4>)
+ 800094e: 0011 movs r1, r2
+ 8000950: 0018 movs r0, r3
+ 8000952: f002 fd19 bl 8003388 <HAL_TIM_ConfigClockSource>
+ 8000956: 1e03 subs r3, r0, #0
+ 8000958: d001 beq.n 800095e <MX_TIM21_Init+0x7a>
{
Error_Handler();
- 800094a: f000 f8ff bl 8000b4c <Error_Handler>
+ 800095a: f000 f8ff bl 8000b5c <Error_Handler>
}
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
- 800094e: 003b movs r3, r7
- 8000950: 2200 movs r2, #0
- 8000952: 601a str r2, [r3, #0]
+ 800095e: 003b movs r3, r7
+ 8000960: 2200 movs r2, #0
+ 8000962: 601a str r2, [r3, #0]
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
- 8000954: 003b movs r3, r7
- 8000956: 2200 movs r2, #0
- 8000958: 605a str r2, [r3, #4]
+ 8000964: 003b movs r3, r7
+ 8000966: 2200 movs r2, #0
+ 8000968: 605a str r2, [r3, #4]
if (HAL_TIMEx_MasterConfigSynchronization(&htim21, &sMasterConfig) != HAL_OK)
- 800095a: 003a movs r2, r7
- 800095c: 4b06 ldr r3, [pc, #24] ; (8000978 <MX_TIM21_Init+0xa4>)
- 800095e: 0011 movs r1, r2
- 8000960: 0018 movs r0, r3
- 8000962: f002 ffcf bl 8003904 <HAL_TIMEx_MasterConfigSynchronization>
- 8000966: 1e03 subs r3, r0, #0
- 8000968: d001 beq.n 800096e <MX_TIM21_Init+0x9a>
+ 800096a: 003a movs r2, r7
+ 800096c: 4b06 ldr r3, [pc, #24] ; (8000988 <MX_TIM21_Init+0xa4>)
+ 800096e: 0011 movs r1, r2
+ 8000970: 0018 movs r0, r3
+ 8000972: f002 ffcf bl 8003914 <HAL_TIMEx_MasterConfigSynchronization>
+ 8000976: 1e03 subs r3, r0, #0
+ 8000978: d001 beq.n 800097e <MX_TIM21_Init+0x9a>
{
Error_Handler();
- 800096a: f000 f8ef bl 8000b4c <Error_Handler>
+ 800097a: f000 f8ef bl 8000b5c <Error_Handler>
}
/* USER CODE BEGIN TIM21_Init 2 */
/* USER CODE END TIM21_Init 2 */
}
- 800096e: 46c0 nop ; (mov r8, r8)
- 8000970: 46bd mov sp, r7
- 8000972: b006 add sp, #24
- 8000974: bd80 pop {r7, pc}
- 8000976: 46c0 nop ; (mov r8, r8)
- 8000978: 200001cc .word 0x200001cc
- 800097c: 40010800 .word 0x40010800
- 8000980: 0000ea5f .word 0x0000ea5f
- 8000984: 000004af .word 0x000004af
+ 800097e: 46c0 nop ; (mov r8, r8)
+ 8000980: 46bd mov sp, r7
+ 8000982: b006 add sp, #24
+ 8000984: bd80 pop {r7, pc}
+ 8000986: 46c0 nop ; (mov r8, r8)
+ 8000988: 200001cc .word 0x200001cc
+ 800098c: 40010800 .word 0x40010800
+ 8000990: 0000ea5f .word 0x0000ea5f
+ 8000994: 000004af .word 0x000004af
-08000988 <MX_TIM22_Init>:
+08000998 <MX_TIM22_Init>:
* @brief TIM22 Initialization Function
* @param None
* @retval None
*/
static void MX_TIM22_Init(void)
{
- 8000988: b580 push {r7, lr}
- 800098a: b08a sub sp, #40 ; 0x28
- 800098c: af00 add r7, sp, #0
+ 8000998: b580 push {r7, lr}
+ 800099a: b08a sub sp, #40 ; 0x28
+ 800099c: af00 add r7, sp, #0
/* USER CODE BEGIN TIM22_Init 0 */
/* USER CODE END TIM22_Init 0 */
TIM_ClockConfigTypeDef sClockSourceConfig = {0};
- 800098e: 2318 movs r3, #24
- 8000990: 18fb adds r3, r7, r3
- 8000992: 0018 movs r0, r3
- 8000994: 2310 movs r3, #16
- 8000996: 001a movs r2, r3
- 8000998: 2100 movs r1, #0
- 800099a: f003 fcc1 bl 8004320 <memset>
- TIM_MasterConfigTypeDef sMasterConfig = {0};
- 800099e: 2310 movs r3, #16
+ 800099e: 2318 movs r3, #24
80009a0: 18fb adds r3, r7, r3
80009a2: 0018 movs r0, r3
- 80009a4: 2308 movs r3, #8
+ 80009a4: 2310 movs r3, #16
80009a6: 001a movs r2, r3
80009a8: 2100 movs r1, #0
- 80009aa: f003 fcb9 bl 8004320 <memset>
+ 80009aa: f003 fcc1 bl 8004330 <memset>
+ TIM_MasterConfigTypeDef sMasterConfig = {0};
+ 80009ae: 2310 movs r3, #16
+ 80009b0: 18fb adds r3, r7, r3
+ 80009b2: 0018 movs r0, r3
+ 80009b4: 2308 movs r3, #8
+ 80009b6: 001a movs r2, r3
+ 80009b8: 2100 movs r1, #0
+ 80009ba: f003 fcb9 bl 8004330 <memset>
TIM_OC_InitTypeDef sConfigOC = {0};
- 80009ae: 003b movs r3, r7
- 80009b0: 0018 movs r0, r3
- 80009b2: 2310 movs r3, #16
- 80009b4: 001a movs r2, r3
- 80009b6: 2100 movs r1, #0
- 80009b8: f003 fcb2 bl 8004320 <memset>
+ 80009be: 003b movs r3, r7
+ 80009c0: 0018 movs r0, r3
+ 80009c2: 2310 movs r3, #16
+ 80009c4: 001a movs r2, r3
+ 80009c6: 2100 movs r1, #0
+ 80009c8: f003 fcb2 bl 8004330 <memset>
/* USER CODE BEGIN TIM22_Init 1 */
/* USER CODE END TIM22_Init 1 */
htim22.Instance = TIM22;
- 80009bc: 4b39 ldr r3, [pc, #228] ; (8000aa4 <MX_TIM22_Init+0x11c>)
- 80009be: 4a3a ldr r2, [pc, #232] ; (8000aa8 <MX_TIM22_Init+0x120>)
- 80009c0: 601a str r2, [r3, #0]
+ 80009cc: 4b39 ldr r3, [pc, #228] ; (8000ab4 <MX_TIM22_Init+0x11c>)
+ 80009ce: 4a3a ldr r2, [pc, #232] ; (8000ab8 <MX_TIM22_Init+0x120>)
+ 80009d0: 601a str r2, [r3, #0]
htim22.Init.Prescaler = led_pwm_prescaler;
- 80009c2: 4b3a ldr r3, [pc, #232] ; (8000aac <MX_TIM22_Init+0x124>)
- 80009c4: 001a movs r2, r3
- 80009c6: 4b37 ldr r3, [pc, #220] ; (8000aa4 <MX_TIM22_Init+0x11c>)
- 80009c8: 605a str r2, [r3, #4]
+ 80009d2: 4b3a ldr r3, [pc, #232] ; (8000abc <MX_TIM22_Init+0x124>)
+ 80009d4: 001a movs r2, r3
+ 80009d6: 4b37 ldr r3, [pc, #220] ; (8000ab4 <MX_TIM22_Init+0x11c>)
+ 80009d8: 605a str r2, [r3, #4]
htim22.Init.CounterMode = TIM_COUNTERMODE_UP;
- 80009ca: 4b36 ldr r3, [pc, #216] ; (8000aa4 <MX_TIM22_Init+0x11c>)
- 80009cc: 2200 movs r2, #0
- 80009ce: 609a str r2, [r3, #8]
+ 80009da: 4b36 ldr r3, [pc, #216] ; (8000ab4 <MX_TIM22_Init+0x11c>)
+ 80009dc: 2200 movs r2, #0
+ 80009de: 609a str r2, [r3, #8]
htim22.Init.Period = led_pwm_period;
- 80009d0: 2363 movs r3, #99 ; 0x63
- 80009d2: 001a movs r2, r3
- 80009d4: 4b33 ldr r3, [pc, #204] ; (8000aa4 <MX_TIM22_Init+0x11c>)
- 80009d6: 60da str r2, [r3, #12]
+ 80009e0: 2363 movs r3, #99 ; 0x63
+ 80009e2: 001a movs r2, r3
+ 80009e4: 4b33 ldr r3, [pc, #204] ; (8000ab4 <MX_TIM22_Init+0x11c>)
+ 80009e6: 60da str r2, [r3, #12]
htim22.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
- 80009d8: 4b32 ldr r3, [pc, #200] ; (8000aa4 <MX_TIM22_Init+0x11c>)
- 80009da: 2200 movs r2, #0
- 80009dc: 611a str r2, [r3, #16]
+ 80009e8: 4b32 ldr r3, [pc, #200] ; (8000ab4 <MX_TIM22_Init+0x11c>)
+ 80009ea: 2200 movs r2, #0
+ 80009ec: 611a str r2, [r3, #16]
htim22.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_ENABLE;
- 80009de: 4b31 ldr r3, [pc, #196] ; (8000aa4 <MX_TIM22_Init+0x11c>)
- 80009e0: 2280 movs r2, #128 ; 0x80
- 80009e2: 615a str r2, [r3, #20]
+ 80009ee: 4b31 ldr r3, [pc, #196] ; (8000ab4 <MX_TIM22_Init+0x11c>)
+ 80009f0: 2280 movs r2, #128 ; 0x80
+ 80009f2: 615a str r2, [r3, #20]
if (HAL_TIM_Base_Init(&htim22) != HAL_OK)
- 80009e4: 4b2f ldr r3, [pc, #188] ; (8000aa4 <MX_TIM22_Init+0x11c>)
- 80009e6: 0018 movs r0, r3
- 80009e8: f002 fb78 bl 80030dc <HAL_TIM_Base_Init>
- 80009ec: 1e03 subs r3, r0, #0
- 80009ee: d001 beq.n 80009f4 <MX_TIM22_Init+0x6c>
+ 80009f4: 4b2f ldr r3, [pc, #188] ; (8000ab4 <MX_TIM22_Init+0x11c>)
+ 80009f6: 0018 movs r0, r3
+ 80009f8: f002 fb78 bl 80030ec <HAL_TIM_Base_Init>
+ 80009fc: 1e03 subs r3, r0, #0
+ 80009fe: d001 beq.n 8000a04 <MX_TIM22_Init+0x6c>
{
Error_Handler();
- 80009f0: f000 f8ac bl 8000b4c <Error_Handler>
+ 8000a00: f000 f8ac bl 8000b5c <Error_Handler>
}
sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
- 80009f4: 2118 movs r1, #24
- 80009f6: 187b adds r3, r7, r1
- 80009f8: 2280 movs r2, #128 ; 0x80
- 80009fa: 0152 lsls r2, r2, #5
- 80009fc: 601a str r2, [r3, #0]
+ 8000a04: 2118 movs r1, #24
+ 8000a06: 187b adds r3, r7, r1
+ 8000a08: 2280 movs r2, #128 ; 0x80
+ 8000a0a: 0152 lsls r2, r2, #5
+ 8000a0c: 601a str r2, [r3, #0]
if (HAL_TIM_ConfigClockSource(&htim22, &sClockSourceConfig) != HAL_OK)
- 80009fe: 187a adds r2, r7, r1
- 8000a00: 4b28 ldr r3, [pc, #160] ; (8000aa4 <MX_TIM22_Init+0x11c>)
- 8000a02: 0011 movs r1, r2
- 8000a04: 0018 movs r0, r3
- 8000a06: f002 fcb7 bl 8003378 <HAL_TIM_ConfigClockSource>
- 8000a0a: 1e03 subs r3, r0, #0
- 8000a0c: d001 beq.n 8000a12 <MX_TIM22_Init+0x8a>
+ 8000a0e: 187a adds r2, r7, r1
+ 8000a10: 4b28 ldr r3, [pc, #160] ; (8000ab4 <MX_TIM22_Init+0x11c>)
+ 8000a12: 0011 movs r1, r2
+ 8000a14: 0018 movs r0, r3
+ 8000a16: f002 fcb7 bl 8003388 <HAL_TIM_ConfigClockSource>
+ 8000a1a: 1e03 subs r3, r0, #0
+ 8000a1c: d001 beq.n 8000a22 <MX_TIM22_Init+0x8a>
{
Error_Handler();
- 8000a0e: f000 f89d bl 8000b4c <Error_Handler>
+ 8000a1e: f000 f89d bl 8000b5c <Error_Handler>
}
if (HAL_TIM_PWM_Init(&htim22) != HAL_OK)
- 8000a12: 4b24 ldr r3, [pc, #144] ; (8000aa4 <MX_TIM22_Init+0x11c>)
- 8000a14: 0018 movs r0, r3
- 8000a16: f002 fba1 bl 800315c <HAL_TIM_PWM_Init>
- 8000a1a: 1e03 subs r3, r0, #0
- 8000a1c: d001 beq.n 8000a22 <MX_TIM22_Init+0x9a>
+ 8000a22: 4b24 ldr r3, [pc, #144] ; (8000ab4 <MX_TIM22_Init+0x11c>)
+ 8000a24: 0018 movs r0, r3
+ 8000a26: f002 fba1 bl 800316c <HAL_TIM_PWM_Init>
+ 8000a2a: 1e03 subs r3, r0, #0
+ 8000a2c: d001 beq.n 8000a32 <MX_TIM22_Init+0x9a>
{
Error_Handler();
- 8000a1e: f000 f895 bl 8000b4c <Error_Handler>
+ 8000a2e: f000 f895 bl 8000b5c <Error_Handler>
}
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
- 8000a22: 2110 movs r1, #16
- 8000a24: 187b adds r3, r7, r1
- 8000a26: 2200 movs r2, #0
- 8000a28: 601a str r2, [r3, #0]
+ 8000a32: 2110 movs r1, #16
+ 8000a34: 187b adds r3, r7, r1
+ 8000a36: 2200 movs r2, #0
+ 8000a38: 601a str r2, [r3, #0]
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
- 8000a2a: 187b adds r3, r7, r1
- 8000a2c: 2200 movs r2, #0
- 8000a2e: 605a str r2, [r3, #4]
+ 8000a3a: 187b adds r3, r7, r1
+ 8000a3c: 2200 movs r2, #0
+ 8000a3e: 605a str r2, [r3, #4]
if (HAL_TIMEx_MasterConfigSynchronization(&htim22, &sMasterConfig) != HAL_OK)
- 8000a30: 187a adds r2, r7, r1
- 8000a32: 4b1c ldr r3, [pc, #112] ; (8000aa4 <MX_TIM22_Init+0x11c>)
- 8000a34: 0011 movs r1, r2
- 8000a36: 0018 movs r0, r3
- 8000a38: f002 ff64 bl 8003904 <HAL_TIMEx_MasterConfigSynchronization>
- 8000a3c: 1e03 subs r3, r0, #0
- 8000a3e: d001 beq.n 8000a44 <MX_TIM22_Init+0xbc>
+ 8000a40: 187a adds r2, r7, r1
+ 8000a42: 4b1c ldr r3, [pc, #112] ; (8000ab4 <MX_TIM22_Init+0x11c>)
+ 8000a44: 0011 movs r1, r2
+ 8000a46: 0018 movs r0, r3
+ 8000a48: f002 ff64 bl 8003914 <HAL_TIMEx_MasterConfigSynchronization>
+ 8000a4c: 1e03 subs r3, r0, #0
+ 8000a4e: d001 beq.n 8000a54 <MX_TIM22_Init+0xbc>
{
Error_Handler();
- 8000a40: f000 f884 bl 8000b4c <Error_Handler>
+ 8000a50: f000 f884 bl 8000b5c <Error_Handler>
}
sConfigOC.OCMode = TIM_OCMODE_PWM1;
- 8000a44: 003b movs r3, r7
- 8000a46: 2260 movs r2, #96 ; 0x60
- 8000a48: 601a str r2, [r3, #0]
- sConfigOC.Pulse = led_pwm_pulse_g;
- 8000a4a: 4b19 ldr r3, [pc, #100] ; (8000ab0 <MX_TIM22_Init+0x128>)
- 8000a4c: 881b ldrh r3, [r3, #0]
- 8000a4e: 001a movs r2, r3
- 8000a50: 003b movs r3, r7
- 8000a52: 605a str r2, [r3, #4]
- sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
8000a54: 003b movs r3, r7
- 8000a56: 2200 movs r2, #0
- 8000a58: 609a str r2, [r3, #8]
+ 8000a56: 2260 movs r2, #96 ; 0x60
+ 8000a58: 601a str r2, [r3, #0]
+ sConfigOC.Pulse = led_pwm_pulse_g;
+ 8000a5a: 4b19 ldr r3, [pc, #100] ; (8000ac0 <MX_TIM22_Init+0x128>)
+ 8000a5c: 881b ldrh r3, [r3, #0]
+ 8000a5e: 001a movs r2, r3
+ 8000a60: 003b movs r3, r7
+ 8000a62: 605a str r2, [r3, #4]
+ sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
+ 8000a64: 003b movs r3, r7
+ 8000a66: 2200 movs r2, #0
+ 8000a68: 609a str r2, [r3, #8]
sConfigOC.OCFastMode = TIM_OCFAST_DISABLE;
- 8000a5a: 003b movs r3, r7
- 8000a5c: 2200 movs r2, #0
- 8000a5e: 60da str r2, [r3, #12]
+ 8000a6a: 003b movs r3, r7
+ 8000a6c: 2200 movs r2, #0
+ 8000a6e: 60da str r2, [r3, #12]
if (HAL_TIM_PWM_ConfigChannel(&htim22, &sConfigOC, TIM_CHANNEL_1) != HAL_OK)
- 8000a60: 0039 movs r1, r7
- 8000a62: 4b10 ldr r3, [pc, #64] ; (8000aa4 <MX_TIM22_Init+0x11c>)
- 8000a64: 2200 movs r2, #0
- 8000a66: 0018 movs r0, r3
- 8000a68: f002 fbc0 bl 80031ec <HAL_TIM_PWM_ConfigChannel>
- 8000a6c: 1e03 subs r3, r0, #0
- 8000a6e: d001 beq.n 8000a74 <MX_TIM22_Init+0xec>
+ 8000a70: 0039 movs r1, r7
+ 8000a72: 4b10 ldr r3, [pc, #64] ; (8000ab4 <MX_TIM22_Init+0x11c>)
+ 8000a74: 2200 movs r2, #0
+ 8000a76: 0018 movs r0, r3
+ 8000a78: f002 fbc0 bl 80031fc <HAL_TIM_PWM_ConfigChannel>
+ 8000a7c: 1e03 subs r3, r0, #0
+ 8000a7e: d001 beq.n 8000a84 <MX_TIM22_Init+0xec>
{
Error_Handler();
- 8000a70: f000 f86c bl 8000b4c <Error_Handler>
+ 8000a80: f000 f86c bl 8000b5c <Error_Handler>
}
sConfigOC.Pulse = led_pwm_pulse_r;
- 8000a74: 4b0f ldr r3, [pc, #60] ; (8000ab4 <MX_TIM22_Init+0x12c>)
- 8000a76: 881b ldrh r3, [r3, #0]
- 8000a78: 001a movs r2, r3
- 8000a7a: 003b movs r3, r7
- 8000a7c: 605a str r2, [r3, #4]
+ 8000a84: 4b0f ldr r3, [pc, #60] ; (8000ac4 <MX_TIM22_Init+0x12c>)
+ 8000a86: 881b ldrh r3, [r3, #0]
+ 8000a88: 001a movs r2, r3
+ 8000a8a: 003b movs r3, r7
+ 8000a8c: 605a str r2, [r3, #4]
if (HAL_TIM_PWM_ConfigChannel(&htim22, &sConfigOC, TIM_CHANNEL_2) != HAL_OK)
- 8000a7e: 0039 movs r1, r7
- 8000a80: 4b08 ldr r3, [pc, #32] ; (8000aa4 <MX_TIM22_Init+0x11c>)
- 8000a82: 2204 movs r2, #4
- 8000a84: 0018 movs r0, r3
- 8000a86: f002 fbb1 bl 80031ec <HAL_TIM_PWM_ConfigChannel>
- 8000a8a: 1e03 subs r3, r0, #0
- 8000a8c: d001 beq.n 8000a92 <MX_TIM22_Init+0x10a>
+ 8000a8e: 0039 movs r1, r7
+ 8000a90: 4b08 ldr r3, [pc, #32] ; (8000ab4 <MX_TIM22_Init+0x11c>)
+ 8000a92: 2204 movs r2, #4
+ 8000a94: 0018 movs r0, r3
+ 8000a96: f002 fbb1 bl 80031fc <HAL_TIM_PWM_ConfigChannel>
+ 8000a9a: 1e03 subs r3, r0, #0
+ 8000a9c: d001 beq.n 8000aa2 <MX_TIM22_Init+0x10a>
{
Error_Handler();
- 8000a8e: f000 f85d bl 8000b4c <Error_Handler>
+ 8000a9e: f000 f85d bl 8000b5c <Error_Handler>
}
/* USER CODE BEGIN TIM22_Init 2 */
/* USER CODE END TIM22_Init 2 */
HAL_TIM_MspPostInit(&htim22);
- 8000a92: 4b04 ldr r3, [pc, #16] ; (8000aa4 <MX_TIM22_Init+0x11c>)
- 8000a94: 0018 movs r0, r3
- 8000a96: f000 f9e9 bl 8000e6c <HAL_TIM_MspPostInit>
+ 8000aa2: 4b04 ldr r3, [pc, #16] ; (8000ab4 <MX_TIM22_Init+0x11c>)
+ 8000aa4: 0018 movs r0, r3
+ 8000aa6: f000 f9e9 bl 8000e7c <HAL_TIM_MspPostInit>
}
- 8000a9a: 46c0 nop ; (mov r8, r8)
- 8000a9c: 46bd mov sp, r7
- 8000a9e: b00a add sp, #40 ; 0x28
- 8000aa0: bd80 pop {r7, pc}
- 8000aa2: 46c0 nop ; (mov r8, r8)
- 8000aa4: 20000090 .word 0x20000090
- 8000aa8: 40011400 .word 0x40011400
- 8000aac: 000004af .word 0x000004af
- 8000ab0: 2000002a .word 0x2000002a
- 8000ab4: 20000028 .word 0x20000028
+ 8000aaa: 46c0 nop ; (mov r8, r8)
+ 8000aac: 46bd mov sp, r7
+ 8000aae: b00a add sp, #40 ; 0x28
+ 8000ab0: bd80 pop {r7, pc}
+ 8000ab2: 46c0 nop ; (mov r8, r8)
+ 8000ab4: 20000090 .word 0x20000090
+ 8000ab8: 40011400 .word 0x40011400
+ 8000abc: 000004af .word 0x000004af
+ 8000ac0: 2000002a .word 0x2000002a
+ 8000ac4: 20000028 .word 0x20000028
-08000ab8 <MX_USART2_UART_Init>:
+08000ac8 <MX_USART2_UART_Init>:
* @brief USART2 Initialization Function
* @param None
* @retval None
*/
static void MX_USART2_UART_Init(void)
{
- 8000ab8: b580 push {r7, lr}
- 8000aba: af00 add r7, sp, #0
+ 8000ac8: b580 push {r7, lr}
+ 8000aca: af00 add r7, sp, #0
/* USER CODE END USART2_Init 0 */
/* USER CODE BEGIN USART2_Init 1 */
/* USER CODE END USART2_Init 1 */
huart2.Instance = USART2;
- 8000abc: 4b16 ldr r3, [pc, #88] ; (8000b18 <MX_USART2_UART_Init+0x60>)
- 8000abe: 4a17 ldr r2, [pc, #92] ; (8000b1c <MX_USART2_UART_Init+0x64>)
- 8000ac0: 601a str r2, [r3, #0]
+ 8000acc: 4b16 ldr r3, [pc, #88] ; (8000b28 <MX_USART2_UART_Init+0x60>)
+ 8000ace: 4a17 ldr r2, [pc, #92] ; (8000b2c <MX_USART2_UART_Init+0x64>)
+ 8000ad0: 601a str r2, [r3, #0]
huart2.Init.BaudRate = 115200;
- 8000ac2: 4b15 ldr r3, [pc, #84] ; (8000b18 <MX_USART2_UART_Init+0x60>)
- 8000ac4: 22e1 movs r2, #225 ; 0xe1
- 8000ac6: 0252 lsls r2, r2, #9
- 8000ac8: 605a str r2, [r3, #4]
+ 8000ad2: 4b15 ldr r3, [pc, #84] ; (8000b28 <MX_USART2_UART_Init+0x60>)
+ 8000ad4: 22e1 movs r2, #225 ; 0xe1
+ 8000ad6: 0252 lsls r2, r2, #9
+ 8000ad8: 605a str r2, [r3, #4]
huart2.Init.WordLength = UART_WORDLENGTH_9B;
- 8000aca: 4b13 ldr r3, [pc, #76] ; (8000b18 <MX_USART2_UART_Init+0x60>)
- 8000acc: 2280 movs r2, #128 ; 0x80
- 8000ace: 0152 lsls r2, r2, #5
- 8000ad0: 609a str r2, [r3, #8]
+ 8000ada: 4b13 ldr r3, [pc, #76] ; (8000b28 <MX_USART2_UART_Init+0x60>)
+ 8000adc: 2280 movs r2, #128 ; 0x80
+ 8000ade: 0152 lsls r2, r2, #5
+ 8000ae0: 609a str r2, [r3, #8]
huart2.Init.StopBits = UART_STOPBITS_1;
- 8000ad2: 4b11 ldr r3, [pc, #68] ; (8000b18 <MX_USART2_UART_Init+0x60>)
- 8000ad4: 2200 movs r2, #0
- 8000ad6: 60da str r2, [r3, #12]
+ 8000ae2: 4b11 ldr r3, [pc, #68] ; (8000b28 <MX_USART2_UART_Init+0x60>)
+ 8000ae4: 2200 movs r2, #0
+ 8000ae6: 60da str r2, [r3, #12]
huart2.Init.Parity = UART_PARITY_EVEN;
- 8000ad8: 4b0f ldr r3, [pc, #60] ; (8000b18 <MX_USART2_UART_Init+0x60>)
- 8000ada: 2280 movs r2, #128 ; 0x80
- 8000adc: 00d2 lsls r2, r2, #3
- 8000ade: 611a str r2, [r3, #16]
+ 8000ae8: 4b0f ldr r3, [pc, #60] ; (8000b28 <MX_USART2_UART_Init+0x60>)
+ 8000aea: 2280 movs r2, #128 ; 0x80
+ 8000aec: 00d2 lsls r2, r2, #3
+ 8000aee: 611a str r2, [r3, #16]
huart2.Init.Mode = UART_MODE_TX_RX;
- 8000ae0: 4b0d ldr r3, [pc, #52] ; (8000b18 <MX_USART2_UART_Init+0x60>)
- 8000ae2: 220c movs r2, #12
- 8000ae4: 615a str r2, [r3, #20]
+ 8000af0: 4b0d ldr r3, [pc, #52] ; (8000b28 <MX_USART2_UART_Init+0x60>)
+ 8000af2: 220c movs r2, #12
+ 8000af4: 615a str r2, [r3, #20]
huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE;
- 8000ae6: 4b0c ldr r3, [pc, #48] ; (8000b18 <MX_USART2_UART_Init+0x60>)
- 8000ae8: 2200 movs r2, #0
- 8000aea: 619a str r2, [r3, #24]
+ 8000af6: 4b0c ldr r3, [pc, #48] ; (8000b28 <MX_USART2_UART_Init+0x60>)
+ 8000af8: 2200 movs r2, #0
+ 8000afa: 619a str r2, [r3, #24]
huart2.Init.OverSampling = UART_OVERSAMPLING_16;
- 8000aec: 4b0a ldr r3, [pc, #40] ; (8000b18 <MX_USART2_UART_Init+0x60>)
- 8000aee: 2200 movs r2, #0
- 8000af0: 61da str r2, [r3, #28]
+ 8000afc: 4b0a ldr r3, [pc, #40] ; (8000b28 <MX_USART2_UART_Init+0x60>)
+ 8000afe: 2200 movs r2, #0
+ 8000b00: 61da str r2, [r3, #28]
huart2.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
- 8000af2: 4b09 ldr r3, [pc, #36] ; (8000b18 <MX_USART2_UART_Init+0x60>)
- 8000af4: 2200 movs r2, #0
- 8000af6: 621a str r2, [r3, #32]
+ 8000b02: 4b09 ldr r3, [pc, #36] ; (8000b28 <MX_USART2_UART_Init+0x60>)
+ 8000b04: 2200 movs r2, #0
+ 8000b06: 621a str r2, [r3, #32]
huart2.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
- 8000af8: 4b07 ldr r3, [pc, #28] ; (8000b18 <MX_USART2_UART_Init+0x60>)
- 8000afa: 2200 movs r2, #0
- 8000afc: 625a str r2, [r3, #36] ; 0x24
+ 8000b08: 4b07 ldr r3, [pc, #28] ; (8000b28 <MX_USART2_UART_Init+0x60>)
+ 8000b0a: 2200 movs r2, #0
+ 8000b0c: 625a str r2, [r3, #36] ; 0x24
if (HAL_RS485Ex_Init(&huart2, UART_DE_POLARITY_HIGH, 0, 0) != HAL_OK)
- 8000afe: 4806 ldr r0, [pc, #24] ; (8000b18 <MX_USART2_UART_Init+0x60>)
- 8000b00: 2300 movs r3, #0
- 8000b02: 2200 movs r2, #0
- 8000b04: 2100 movs r1, #0
- 8000b06: f003 fb77 bl 80041f8 <HAL_RS485Ex_Init>
- 8000b0a: 1e03 subs r3, r0, #0
- 8000b0c: d001 beq.n 8000b12 <MX_USART2_UART_Init+0x5a>
+ 8000b0e: 4806 ldr r0, [pc, #24] ; (8000b28 <MX_USART2_UART_Init+0x60>)
+ 8000b10: 2300 movs r3, #0
+ 8000b12: 2200 movs r2, #0
+ 8000b14: 2100 movs r1, #0
+ 8000b16: f003 fb77 bl 8004208 <HAL_RS485Ex_Init>
+ 8000b1a: 1e03 subs r3, r0, #0
+ 8000b1c: d001 beq.n 8000b22 <MX_USART2_UART_Init+0x5a>
{
Error_Handler();
- 8000b0e: f000 f81d bl 8000b4c <Error_Handler>
+ 8000b1e: f000 f81d bl 8000b5c <Error_Handler>
}
/* USER CODE BEGIN USART2_Init 2 */
/* USER CODE END USART2_Init 2 */
}
- 8000b12: 46c0 nop ; (mov r8, r8)
- 8000b14: 46bd mov sp, r7
- 8000b16: bd80 pop {r7, pc}
- 8000b18: 20000140 .word 0x20000140
- 8000b1c: 40004400 .word 0x40004400
+ 8000b22: 46c0 nop ; (mov r8, r8)
+ 8000b24: 46bd mov sp, r7
+ 8000b26: bd80 pop {r7, pc}
+ 8000b28: 20000140 .word 0x20000140
+ 8000b2c: 40004400 .word 0x40004400
-08000b20 <MX_GPIO_Init>:
+08000b30 <MX_GPIO_Init>:
* @brief GPIO Initialization Function
* @param None
* @retval None
*/
static void MX_GPIO_Init(void)
{
- 8000b20: b580 push {r7, lr}
- 8000b22: b082 sub sp, #8
- 8000b24: af00 add r7, sp, #0
+ 8000b30: b580 push {r7, lr}
+ 8000b32: b082 sub sp, #8
+ 8000b34: af00 add r7, sp, #0
/* GPIO Ports Clock Enable */
__HAL_RCC_GPIOA_CLK_ENABLE();
- 8000b26: 4b08 ldr r3, [pc, #32] ; (8000b48 <MX_GPIO_Init+0x28>)
- 8000b28: 6ada ldr r2, [r3, #44] ; 0x2c
- 8000b2a: 4b07 ldr r3, [pc, #28] ; (8000b48 <MX_GPIO_Init+0x28>)
- 8000b2c: 2101 movs r1, #1
- 8000b2e: 430a orrs r2, r1
- 8000b30: 62da str r2, [r3, #44] ; 0x2c
- 8000b32: 4b05 ldr r3, [pc, #20] ; (8000b48 <MX_GPIO_Init+0x28>)
- 8000b34: 6adb ldr r3, [r3, #44] ; 0x2c
- 8000b36: 2201 movs r2, #1
- 8000b38: 4013 ands r3, r2
- 8000b3a: 607b str r3, [r7, #4]
- 8000b3c: 687b ldr r3, [r7, #4]
+ 8000b36: 4b08 ldr r3, [pc, #32] ; (8000b58 <MX_GPIO_Init+0x28>)
+ 8000b38: 6ada ldr r2, [r3, #44] ; 0x2c
+ 8000b3a: 4b07 ldr r3, [pc, #28] ; (8000b58 <MX_GPIO_Init+0x28>)
+ 8000b3c: 2101 movs r1, #1
+ 8000b3e: 430a orrs r2, r1
+ 8000b40: 62da str r2, [r3, #44] ; 0x2c
+ 8000b42: 4b05 ldr r3, [pc, #20] ; (8000b58 <MX_GPIO_Init+0x28>)
+ 8000b44: 6adb ldr r3, [r3, #44] ; 0x2c
+ 8000b46: 2201 movs r2, #1
+ 8000b48: 4013 ands r3, r2
+ 8000b4a: 607b str r3, [r7, #4]
+ 8000b4c: 687b ldr r3, [r7, #4]
}
- 8000b3e: 46c0 nop ; (mov r8, r8)
- 8000b40: 46bd mov sp, r7
- 8000b42: b002 add sp, #8
- 8000b44: bd80 pop {r7, pc}
- 8000b46: 46c0 nop ; (mov r8, r8)
- 8000b48: 40021000 .word 0x40021000
+ 8000b4e: 46c0 nop ; (mov r8, r8)
+ 8000b50: 46bd mov sp, r7
+ 8000b52: b002 add sp, #8
+ 8000b54: bd80 pop {r7, pc}
+ 8000b56: 46c0 nop ; (mov r8, r8)
+ 8000b58: 40021000 .word 0x40021000
-08000b4c <Error_Handler>:
+08000b5c <Error_Handler>:
/**
* @brief This function is executed in case of error occurrence.
* @retval None
*/
void Error_Handler(void)
{
- 8000b4c: b580 push {r7, lr}
- 8000b4e: af00 add r7, sp, #0
+ 8000b5c: b580 push {r7, lr}
+ 8000b5e: af00 add r7, sp, #0
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__STATIC_FORCEINLINE void __disable_irq(void)
{
__ASM volatile ("cpsid i" : : : "memory");
- 8000b50: b672 cpsid i
+ 8000b60: b672 cpsid i
}
- 8000b52: 46c0 nop ; (mov r8, r8)
+ 8000b62: 46c0 nop ; (mov r8, r8)
/* USER CODE BEGIN Error_Handler_Debug */
/* User can add his own implementation to report the HAL error return state */
__disable_irq();
while (1)
- 8000b54: e7fe b.n 8000b54 <Error_Handler+0x8>
+ 8000b64: e7fe b.n 8000b64 <Error_Handler+0x8>
-08000b56 <scd4x_send_cmd>:
+08000b66 <scd4x_send_cmd>:
#include "scd4x.h"
#include "main.h" /* for uart_disable_interrupts() */
int8_t scd4x_send_cmd(scd4x_cmd_t cmd)
{
- 8000b56: b580 push {r7, lr}
- 8000b58: b08c sub sp, #48 ; 0x30
- 8000b5a: af00 add r7, sp, #0
- 8000b5c: 0002 movs r2, r0
- 8000b5e: 1dbb adds r3, r7, #6
- 8000b60: 801a strh r2, [r3, #0]
+ 8000b66: b580 push {r7, lr}
+ 8000b68: b08c sub sp, #48 ; 0x30
+ 8000b6a: af00 add r7, sp, #0
+ 8000b6c: 0002 movs r2, r0
+ 8000b6e: 1dbb adds r3, r7, #6
+ 8000b70: 801a strh r2, [r3, #0]
uint8_t buffer[32];
int result;
// start measurement
buffer[0] = cmd >> 8;
- 8000b62: 1dbb adds r3, r7, #6
- 8000b64: 881b ldrh r3, [r3, #0]
- 8000b66: 0a1b lsrs r3, r3, #8
- 8000b68: b29b uxth r3, r3
- 8000b6a: b2da uxtb r2, r3
- 8000b6c: 210c movs r1, #12
- 8000b6e: 187b adds r3, r7, r1
- 8000b70: 701a strb r2, [r3, #0]
- buffer[1] = cmd & 0x00ff;
8000b72: 1dbb adds r3, r7, #6
8000b74: 881b ldrh r3, [r3, #0]
- 8000b76: b2da uxtb r2, r3
- 8000b78: 187b adds r3, r7, r1
- 8000b7a: 705a strb r2, [r3, #1]
+ 8000b76: 0a1b lsrs r3, r3, #8
+ 8000b78: b29b uxth r3, r3
+ 8000b7a: b2da uxtb r2, r3
+ 8000b7c: 210c movs r1, #12
+ 8000b7e: 187b adds r3, r7, r1
+ 8000b80: 701a strb r2, [r3, #0]
+ buffer[1] = cmd & 0x00ff;
+ 8000b82: 1dbb adds r3, r7, #6
+ 8000b84: 881b ldrh r3, [r3, #0]
+ 8000b86: b2da uxtb r2, r3
+ 8000b88: 187b adds r3, r7, r1
+ 8000b8a: 705a strb r2, [r3, #1]
result = i2c_transmit(SCD4X_I2C_ADDRESS<<1, buffer, 2);
- 8000b7c: 187b adds r3, r7, r1
- 8000b7e: 2202 movs r2, #2
- 8000b80: 0019 movs r1, r3
- 8000b82: 20c4 movs r0, #196 ; 0xc4
- 8000b84: f7ff fca8 bl 80004d8 <i2c_transmit>
- 8000b88: 0003 movs r3, r0
- 8000b8a: 62fb str r3, [r7, #44] ; 0x2c
+ 8000b8c: 187b adds r3, r7, r1
+ 8000b8e: 2202 movs r2, #2
+ 8000b90: 0019 movs r1, r3
+ 8000b92: 20c4 movs r0, #196 ; 0xc4
+ 8000b94: f7ff fca0 bl 80004d8 <i2c_transmit>
+ 8000b98: 0003 movs r3, r0
+ 8000b9a: 62fb str r3, [r7, #44] ; 0x2c
if (result != I2C_OK) {
- 8000b8c: 6afb ldr r3, [r7, #44] ; 0x2c
- 8000b8e: 2b00 cmp r3, #0
- 8000b90: d002 beq.n 8000b98 <scd4x_send_cmd+0x42>
+ 8000b9c: 6afb ldr r3, [r7, #44] ; 0x2c
+ 8000b9e: 2b00 cmp r3, #0
+ 8000ba0: d002 beq.n 8000ba8 <scd4x_send_cmd+0x42>
return SCD4X_ERROR;
- 8000b92: 2301 movs r3, #1
- 8000b94: 425b negs r3, r3
- 8000b96: e000 b.n 8000b9a <scd4x_send_cmd+0x44>
+ 8000ba2: 2301 movs r3, #1
+ 8000ba4: 425b negs r3, r3
+ 8000ba6: e000 b.n 8000baa <scd4x_send_cmd+0x44>
}
return SCD4X_OK;
- 8000b98: 2300 movs r3, #0
+ 8000ba8: 2300 movs r3, #0
}
- 8000b9a: 0018 movs r0, r3
- 8000b9c: 46bd mov sp, r7
- 8000b9e: b00c add sp, #48 ; 0x30
- 8000ba0: bd80 pop {r7, pc}
+ 8000baa: 0018 movs r0, r3
+ 8000bac: 46bd mov sp, r7
+ 8000bae: b00c add sp, #48 ; 0x30
+ 8000bb0: bd80 pop {r7, pc}
...
-08000ba4 <scd4x_start_periodic_measurement>:
+08000bb4 <scd4x_start_periodic_measurement>:
{
return SCD4X_OK;
}
int8_t scd4x_start_periodic_measurement( void )
{
- 8000ba4: b580 push {r7, lr}
- 8000ba6: af00 add r7, sp, #0
+ 8000bb4: b580 push {r7, lr}
+ 8000bb6: af00 add r7, sp, #0
return scd4x_send_cmd(SCD4X_START_PERIODIC_MEASUREMENT);
- 8000ba8: 4b03 ldr r3, [pc, #12] ; (8000bb8 <scd4x_start_periodic_measurement+0x14>)
- 8000baa: 0018 movs r0, r3
- 8000bac: f7ff ffd3 bl 8000b56 <scd4x_send_cmd>
- 8000bb0: 0003 movs r3, r0
+ 8000bb8: 4b03 ldr r3, [pc, #12] ; (8000bc8 <scd4x_start_periodic_measurement+0x14>)
+ 8000bba: 0018 movs r0, r3
+ 8000bbc: f7ff ffd3 bl 8000b66 <scd4x_send_cmd>
+ 8000bc0: 0003 movs r3, r0
}
- 8000bb2: 0018 movs r0, r3
- 8000bb4: 46bd mov sp, r7
- 8000bb6: bd80 pop {r7, pc}
- 8000bb8: 000021b1 .word 0x000021b1
+ 8000bc2: 0018 movs r0, r3
+ 8000bc4: 46bd mov sp, r7
+ 8000bc6: bd80 pop {r7, pc}
+ 8000bc8: 000021b1 .word 0x000021b1
-08000bbc <scd4x_read_measurement>:
+08000bcc <scd4x_read_measurement>:
{
return scd4x_send_cmd(SCD4X_PERFORM_FACTORY_RESET);
}
int8_t scd4x_read_measurement(uint16_t * co2, int16_t *temperature, uint16_t *relative_humidity)
{
- 8000bbc: b5b0 push {r4, r5, r7, lr}
- 8000bbe: b094 sub sp, #80 ; 0x50
- 8000bc0: af02 add r7, sp, #8
- 8000bc2: 60f8 str r0, [r7, #12]
- 8000bc4: 60b9 str r1, [r7, #8]
- 8000bc6: 607a str r2, [r7, #4]
+ 8000bcc: b5b0 push {r4, r5, r7, lr}
+ 8000bce: b094 sub sp, #80 ; 0x50
+ 8000bd0: af02 add r7, sp, #8
+ 8000bd2: 60f8 str r0, [r7, #12]
+ 8000bd4: 60b9 str r1, [r7, #8]
+ 8000bd6: 607a str r2, [r7, #4]
// result = i2c_receive(SCD4X_I2C_ADDRESS<<1, buffer, 9);
// if (result != I2C_OK)
// {
// return SCD4X_ERROR;
// }
- result = i2c_transmit_receive(SCD4X_I2C_ADDRESS<<1, SCD4X_READ_MEASUREMENT, 2, buffer, 9);
- 8000bc8: 2543 movs r5, #67 ; 0x43
- 8000bca: 197c adds r4, r7, r5
- 8000bcc: 2310 movs r3, #16
- 8000bce: 18fb adds r3, r7, r3
- 8000bd0: 492b ldr r1, [pc, #172] ; (8000c80 <scd4x_read_measurement+0xc4>)
- 8000bd2: 2209 movs r2, #9
- 8000bd4: 9200 str r2, [sp, #0]
- 8000bd6: 2202 movs r2, #2
- 8000bd8: 20c4 movs r0, #196 ; 0xc4
- 8000bda: f7ff fcc9 bl 8000570 <i2c_transmit_receive>
- 8000bde: 0003 movs r3, r0
- 8000be0: 7023 strb r3, [r4, #0]
+ result = i2c_transmit_receive(SCD4X_I2C_ADDRESS<<1, SCD4X_READ_MEASUREMENT, I2C_MEMADD_SIZE_16BIT, buffer, 9);
+ 8000bd8: 2543 movs r5, #67 ; 0x43
+ 8000bda: 197c adds r4, r7, r5
+ 8000bdc: 2310 movs r3, #16
+ 8000bde: 18fb adds r3, r7, r3
+ 8000be0: 492b ldr r1, [pc, #172] ; (8000c90 <scd4x_read_measurement+0xc4>)
+ 8000be2: 2209 movs r2, #9
+ 8000be4: 9200 str r2, [sp, #0]
+ 8000be6: 2202 movs r2, #2
+ 8000be8: 20c4 movs r0, #196 ; 0xc4
+ 8000bea: f7ff fcc5 bl 8000578 <i2c_transmit_receive>
+ 8000bee: 0003 movs r3, r0
+ 8000bf0: 7023 strb r3, [r4, #0]
if (result != I2C_OK)
- 8000be2: 197b adds r3, r7, r5
- 8000be4: 781b ldrb r3, [r3, #0]
- 8000be6: b25b sxtb r3, r3
- 8000be8: 2b00 cmp r3, #0
- 8000bea: d002 beq.n 8000bf2 <scd4x_read_measurement+0x36>
+ 8000bf2: 197b adds r3, r7, r5
+ 8000bf4: 781b ldrb r3, [r3, #0]
+ 8000bf6: b25b sxtb r3, r3
+ 8000bf8: 2b00 cmp r3, #0
+ 8000bfa: d002 beq.n 8000c02 <scd4x_read_measurement+0x36>
{
return SCD4X_ERROR;
- 8000bec: 2301 movs r3, #1
- 8000bee: 425b negs r3, r3
- 8000bf0: e041 b.n 8000c76 <scd4x_read_measurement+0xba>
+ 8000bfc: 2301 movs r3, #1
+ 8000bfe: 425b negs r3, r3
+ 8000c00: e041 b.n 8000c86 <scd4x_read_measurement+0xba>
}
// uart_enable_interrupts();
// TODO checksum
// Convert to T and RH; taken directly from pseudocode in SHT4x datasheet, page 3
uint32_t co2_ticks = (buffer[0] << 8) + buffer[1];
- 8000bf2: 2110 movs r1, #16
- 8000bf4: 187b adds r3, r7, r1
- 8000bf6: 781b ldrb r3, [r3, #0]
- 8000bf8: 021b lsls r3, r3, #8
- 8000bfa: 187a adds r2, r7, r1
- 8000bfc: 7852 ldrb r2, [r2, #1]
- 8000bfe: 189b adds r3, r3, r2
- 8000c00: 63fb str r3, [r7, #60] ; 0x3c
+ 8000c02: 2110 movs r1, #16
+ 8000c04: 187b adds r3, r7, r1
+ 8000c06: 781b ldrb r3, [r3, #0]
+ 8000c08: 021b lsls r3, r3, #8
+ 8000c0a: 187a adds r2, r7, r1
+ 8000c0c: 7852 ldrb r2, [r2, #1]
+ 8000c0e: 189b adds r3, r3, r2
+ 8000c10: 63fb str r3, [r7, #60] ; 0x3c
uint32_t t_ticks = (buffer[3] << 8) + buffer[4];
- 8000c02: 187b adds r3, r7, r1
- 8000c04: 78db ldrb r3, [r3, #3]
- 8000c06: 021b lsls r3, r3, #8
- 8000c08: 187a adds r2, r7, r1
- 8000c0a: 7912 ldrb r2, [r2, #4]
- 8000c0c: 189b adds r3, r3, r2
- 8000c0e: 63bb str r3, [r7, #56] ; 0x38
- uint32_t rh_ticks = (buffer[6] << 8) + buffer[7];
- 8000c10: 000a movs r2, r1
- 8000c12: 18bb adds r3, r7, r2
- 8000c14: 799b ldrb r3, [r3, #6]
+ 8000c12: 187b adds r3, r7, r1
+ 8000c14: 78db ldrb r3, [r3, #3]
8000c16: 021b lsls r3, r3, #8
- 8000c18: 18ba adds r2, r7, r2
- 8000c1a: 79d2 ldrb r2, [r2, #7]
+ 8000c18: 187a adds r2, r7, r1
+ 8000c1a: 7912 ldrb r2, [r2, #4]
8000c1c: 189b adds r3, r3, r2
- 8000c1e: 637b str r3, [r7, #52] ; 0x34
+ 8000c1e: 63bb str r3, [r7, #56] ; 0x38
+ uint32_t rh_ticks = (buffer[6] << 8) + buffer[7];
+ 8000c20: 000a movs r2, r1
+ 8000c22: 18bb adds r3, r7, r2
+ 8000c24: 799b ldrb r3, [r3, #6]
+ 8000c26: 021b lsls r3, r3, #8
+ 8000c28: 18ba adds r2, r7, r2
+ 8000c2a: 79d2 ldrb r2, [r2, #7]
+ 8000c2c: 189b adds r3, r3, r2
+ 8000c2e: 637b str r3, [r7, #52] ; 0x34
int t_degC = -450 + 10 * 175 * t_ticks / 65535;
- 8000c20: 6bbb ldr r3, [r7, #56] ; 0x38
- 8000c22: 4a18 ldr r2, [pc, #96] ; (8000c84 <scd4x_read_measurement+0xc8>)
- 8000c24: 4353 muls r3, r2
- 8000c26: 4918 ldr r1, [pc, #96] ; (8000c88 <scd4x_read_measurement+0xcc>)
- 8000c28: 0018 movs r0, r3
- 8000c2a: f7ff fa6d bl 8000108 <__udivsi3>
- 8000c2e: 0003 movs r3, r0
- 8000c30: 3bc3 subs r3, #195 ; 0xc3
- 8000c32: 3bff subs r3, #255 ; 0xff
- 8000c34: 633b str r3, [r7, #48] ; 0x30
+ 8000c30: 6bbb ldr r3, [r7, #56] ; 0x38
+ 8000c32: 4a18 ldr r2, [pc, #96] ; (8000c94 <scd4x_read_measurement+0xc8>)
+ 8000c34: 4353 muls r3, r2
+ 8000c36: 4918 ldr r1, [pc, #96] ; (8000c98 <scd4x_read_measurement+0xcc>)
+ 8000c38: 0018 movs r0, r3
+ 8000c3a: f7ff fa65 bl 8000108 <__udivsi3>
+ 8000c3e: 0003 movs r3, r0
+ 8000c40: 3bc3 subs r3, #195 ; 0xc3
+ 8000c42: 3bff subs r3, #255 ; 0xff
+ 8000c44: 633b str r3, [r7, #48] ; 0x30
int rh_pRH = 100 * rh_ticks / 65535;
- 8000c36: 6b7b ldr r3, [r7, #52] ; 0x34
- 8000c38: 2264 movs r2, #100 ; 0x64
- 8000c3a: 4353 muls r3, r2
- 8000c3c: 4912 ldr r1, [pc, #72] ; (8000c88 <scd4x_read_measurement+0xcc>)
- 8000c3e: 0018 movs r0, r3
- 8000c40: f7ff fa62 bl 8000108 <__udivsi3>
- 8000c44: 0003 movs r3, r0
- 8000c46: 647b str r3, [r7, #68] ; 0x44
+ 8000c46: 6b7b ldr r3, [r7, #52] ; 0x34
+ 8000c48: 2264 movs r2, #100 ; 0x64
+ 8000c4a: 4353 muls r3, r2
+ 8000c4c: 4912 ldr r1, [pc, #72] ; (8000c98 <scd4x_read_measurement+0xcc>)
+ 8000c4e: 0018 movs r0, r3
+ 8000c50: f7ff fa5a bl 8000108 <__udivsi3>
+ 8000c54: 0003 movs r3, r0
+ 8000c56: 647b str r3, [r7, #68] ; 0x44
if (rh_pRH > 100) {
- 8000c48: 6c7b ldr r3, [r7, #68] ; 0x44
- 8000c4a: 2b64 cmp r3, #100 ; 0x64
- 8000c4c: dd01 ble.n 8000c52 <scd4x_read_measurement+0x96>
+ 8000c58: 6c7b ldr r3, [r7, #68] ; 0x44
+ 8000c5a: 2b64 cmp r3, #100 ; 0x64
+ 8000c5c: dd01 ble.n 8000c62 <scd4x_read_measurement+0x96>
rh_pRH = 100;
- 8000c4e: 2364 movs r3, #100 ; 0x64
- 8000c50: 647b str r3, [r7, #68] ; 0x44
+ 8000c5e: 2364 movs r3, #100 ; 0x64
+ 8000c60: 647b str r3, [r7, #68] ; 0x44
}
if (rh_pRH < 0) {
- 8000c52: 6c7b ldr r3, [r7, #68] ; 0x44
- 8000c54: 2b00 cmp r3, #0
- 8000c56: da01 bge.n 8000c5c <scd4x_read_measurement+0xa0>
+ 8000c62: 6c7b ldr r3, [r7, #68] ; 0x44
+ 8000c64: 2b00 cmp r3, #0
+ 8000c66: da01 bge.n 8000c6c <scd4x_read_measurement+0xa0>
rh_pRH = 0;
- 8000c58: 2300 movs r3, #0
- 8000c5a: 647b str r3, [r7, #68] ; 0x44
+ 8000c68: 2300 movs r3, #0
+ 8000c6a: 647b str r3, [r7, #68] ; 0x44
}
*co2 = co2_ticks;
- 8000c5c: 6bfb ldr r3, [r7, #60] ; 0x3c
- 8000c5e: b29a uxth r2, r3
- 8000c60: 68fb ldr r3, [r7, #12]
- 8000c62: 801a strh r2, [r3, #0]
- *temperature = t_degC;
- 8000c64: 6b3b ldr r3, [r7, #48] ; 0x30
- 8000c66: b21a sxth r2, r3
- 8000c68: 68bb ldr r3, [r7, #8]
- 8000c6a: 801a strh r2, [r3, #0]
- *relative_humidity = rh_pRH;
- 8000c6c: 6c7b ldr r3, [r7, #68] ; 0x44
+ 8000c6c: 6bfb ldr r3, [r7, #60] ; 0x3c
8000c6e: b29a uxth r2, r3
- 8000c70: 687b ldr r3, [r7, #4]
+ 8000c70: 68fb ldr r3, [r7, #12]
8000c72: 801a strh r2, [r3, #0]
+ *temperature = t_degC;
+ 8000c74: 6b3b ldr r3, [r7, #48] ; 0x30
+ 8000c76: b21a sxth r2, r3
+ 8000c78: 68bb ldr r3, [r7, #8]
+ 8000c7a: 801a strh r2, [r3, #0]
+ *relative_humidity = rh_pRH;
+ 8000c7c: 6c7b ldr r3, [r7, #68] ; 0x44
+ 8000c7e: b29a uxth r2, r3
+ 8000c80: 687b ldr r3, [r7, #4]
+ 8000c82: 801a strh r2, [r3, #0]
return SCD4X_OK;
- 8000c74: 2300 movs r3, #0
+ 8000c84: 2300 movs r3, #0
}
- 8000c76: 0018 movs r0, r3
- 8000c78: 46bd mov sp, r7
- 8000c7a: b012 add sp, #72 ; 0x48
- 8000c7c: bdb0 pop {r4, r5, r7, pc}
- 8000c7e: 46c0 nop ; (mov r8, r8)
- 8000c80: 0000ec05 .word 0x0000ec05
- 8000c84: 000006d6 .word 0x000006d6
- 8000c88: 0000ffff .word 0x0000ffff
+ 8000c86: 0018 movs r0, r3
+ 8000c88: 46bd mov sp, r7
+ 8000c8a: b012 add sp, #72 ; 0x48
+ 8000c8c: bdb0 pop {r4, r5, r7, pc}
+ 8000c8e: 46c0 nop ; (mov r8, r8)
+ 8000c90: 0000ec05 .word 0x0000ec05
+ 8000c94: 000006d6 .word 0x000006d6
+ 8000c98: 0000ffff .word 0x0000ffff
-08000c8c <sht4x_measure>:
+08000c9c <sht4x_measure>:
{
return SHT4X_OK;
}
int8_t sht4x_measure(int16_t *temperature, uint16_t *relative_humidity)
{
- 8000c8c: b590 push {r4, r7, lr}
- 8000c8e: b091 sub sp, #68 ; 0x44
- 8000c90: af00 add r7, sp, #0
- 8000c92: 6078 str r0, [r7, #4]
- 8000c94: 6039 str r1, [r7, #0]
+ 8000c9c: b590 push {r4, r7, lr}
+ 8000c9e: b091 sub sp, #68 ; 0x44
+ 8000ca0: af00 add r7, sp, #0
+ 8000ca2: 6078 str r0, [r7, #4]
+ 8000ca4: 6039 str r1, [r7, #0]
uint8_t buffer[32];
int result;
// start measurement
buffer[0] = SHT4X_START_MEAS_HIGH_PRECISION;
- 8000c96: 240c movs r4, #12
- 8000c98: 193b adds r3, r7, r4
- 8000c9a: 22fd movs r2, #253 ; 0xfd
- 8000c9c: 701a strb r2, [r3, #0]
+ 8000ca6: 240c movs r4, #12
+ 8000ca8: 193b adds r3, r7, r4
+ 8000caa: 22fd movs r2, #253 ; 0xfd
+ 8000cac: 701a strb r2, [r3, #0]
result = i2c_transmit(SHT4X_I2C_ADDRESS<<1, buffer, 1);
- 8000c9e: 193b adds r3, r7, r4
- 8000ca0: 2201 movs r2, #1
- 8000ca2: 0019 movs r1, r3
- 8000ca4: 2088 movs r0, #136 ; 0x88
- 8000ca6: f7ff fc17 bl 80004d8 <i2c_transmit>
- 8000caa: 0003 movs r3, r0
- 8000cac: 63bb str r3, [r7, #56] ; 0x38
+ 8000cae: 193b adds r3, r7, r4
+ 8000cb0: 2201 movs r2, #1
+ 8000cb2: 0019 movs r1, r3
+ 8000cb4: 2088 movs r0, #136 ; 0x88
+ 8000cb6: f7ff fc0f bl 80004d8 <i2c_transmit>
+ 8000cba: 0003 movs r3, r0
+ 8000cbc: 63bb str r3, [r7, #56] ; 0x38
}*/
/*uart_disable_interrupts();
LL_mDelay(10); // 10 ms should be enough
uart_enable_interrupts();
*/
HAL_Delay(10);
- 8000cae: 200a movs r0, #10
- 8000cb0: f000 fa3c bl 800112c <HAL_Delay>
+ 8000cbe: 200a movs r0, #10
+ 8000cc0: f000 fa3c bl 800113c <HAL_Delay>
// read out
result = i2c_receive(SHT4X_I2C_ADDRESS<<1, buffer, 6);
- 8000cb4: 193b adds r3, r7, r4
- 8000cb6: 2206 movs r2, #6
- 8000cb8: 0019 movs r1, r3
- 8000cba: 2088 movs r0, #136 ; 0x88
- 8000cbc: f7ff fc32 bl 8000524 <i2c_receive>
- 8000cc0: 0003 movs r3, r0
- 8000cc2: 63bb str r3, [r7, #56] ; 0x38
+ 8000cc4: 193b adds r3, r7, r4
+ 8000cc6: 2206 movs r2, #6
+ 8000cc8: 0019 movs r1, r3
+ 8000cca: 2088 movs r0, #136 ; 0x88
+ 8000ccc: f7ff fc2c bl 8000528 <i2c_receive>
+ 8000cd0: 0003 movs r3, r0
+ 8000cd2: 63bb str r3, [r7, #56] ; 0x38
if (result != I2C_OK) {
- 8000cc4: 6bbb ldr r3, [r7, #56] ; 0x38
- 8000cc6: 2b00 cmp r3, #0
- 8000cc8: d002 beq.n 8000cd0 <sht4x_measure+0x44>
+ 8000cd4: 6bbb ldr r3, [r7, #56] ; 0x38
+ 8000cd6: 2b00 cmp r3, #0
+ 8000cd8: d002 beq.n 8000ce0 <sht4x_measure+0x44>
return SHT4X_ERROR;
- 8000cca: 2301 movs r3, #1
- 8000ccc: 425b negs r3, r3
- 8000cce: e03a b.n 8000d46 <sht4x_measure+0xba>
+ 8000cda: 2301 movs r3, #1
+ 8000cdc: 425b negs r3, r3
+ 8000cde: e03a b.n 8000d56 <sht4x_measure+0xba>
}
// TODO checksum
// Convert to T and RH; taken directly from pseudocode in SHT4x datasheet, page 3
uint32_t t_ticks = (buffer[0] << 8) + buffer[1];
- 8000cd0: 210c movs r1, #12
- 8000cd2: 187b adds r3, r7, r1
- 8000cd4: 781b ldrb r3, [r3, #0]
- 8000cd6: 021b lsls r3, r3, #8
- 8000cd8: 187a adds r2, r7, r1
- 8000cda: 7852 ldrb r2, [r2, #1]
- 8000cdc: 189b adds r3, r3, r2
- 8000cde: 637b str r3, [r7, #52] ; 0x34
- uint32_t rh_ticks = (buffer[3] << 8) + buffer[4];
- 8000ce0: 000a movs r2, r1
- 8000ce2: 18bb adds r3, r7, r2
- 8000ce4: 78db ldrb r3, [r3, #3]
+ 8000ce0: 210c movs r1, #12
+ 8000ce2: 187b adds r3, r7, r1
+ 8000ce4: 781b ldrb r3, [r3, #0]
8000ce6: 021b lsls r3, r3, #8
- 8000ce8: 18ba adds r2, r7, r2
- 8000cea: 7912 ldrb r2, [r2, #4]
+ 8000ce8: 187a adds r2, r7, r1
+ 8000cea: 7852 ldrb r2, [r2, #1]
8000cec: 189b adds r3, r3, r2
- 8000cee: 633b str r3, [r7, #48] ; 0x30
+ 8000cee: 637b str r3, [r7, #52] ; 0x34
+ uint32_t rh_ticks = (buffer[3] << 8) + buffer[4];
+ 8000cf0: 000a movs r2, r1
+ 8000cf2: 18bb adds r3, r7, r2
+ 8000cf4: 78db ldrb r3, [r3, #3]
+ 8000cf6: 021b lsls r3, r3, #8
+ 8000cf8: 18ba adds r2, r7, r2
+ 8000cfa: 7912 ldrb r2, [r2, #4]
+ 8000cfc: 189b adds r3, r3, r2
+ 8000cfe: 633b str r3, [r7, #48] ; 0x30
int t_degC = -450 + 10 * 175 * t_ticks / 65535; /* temperature * 10 */
- 8000cf0: 6b7b ldr r3, [r7, #52] ; 0x34
- 8000cf2: 4a17 ldr r2, [pc, #92] ; (8000d50 <sht4x_measure+0xc4>)
- 8000cf4: 4353 muls r3, r2
- 8000cf6: 4917 ldr r1, [pc, #92] ; (8000d54 <sht4x_measure+0xc8>)
- 8000cf8: 0018 movs r0, r3
- 8000cfa: f7ff fa05 bl 8000108 <__udivsi3>
- 8000cfe: 0003 movs r3, r0
- 8000d00: 3bc3 subs r3, #195 ; 0xc3
- 8000d02: 3bff subs r3, #255 ; 0xff
- 8000d04: 62fb str r3, [r7, #44] ; 0x2c
+ 8000d00: 6b7b ldr r3, [r7, #52] ; 0x34
+ 8000d02: 4a17 ldr r2, [pc, #92] ; (8000d60 <sht4x_measure+0xc4>)
+ 8000d04: 4353 muls r3, r2
+ 8000d06: 4917 ldr r1, [pc, #92] ; (8000d64 <sht4x_measure+0xc8>)
+ 8000d08: 0018 movs r0, r3
+ 8000d0a: f7ff f9fd bl 8000108 <__udivsi3>
+ 8000d0e: 0003 movs r3, r0
+ 8000d10: 3bc3 subs r3, #195 ; 0xc3
+ 8000d12: 3bff subs r3, #255 ; 0xff
+ 8000d14: 62fb str r3, [r7, #44] ; 0x2c
int rh_pRH = -6 + 125 * rh_ticks / 65535;
- 8000d06: 6b3a ldr r2, [r7, #48] ; 0x30
- 8000d08: 0013 movs r3, r2
- 8000d0a: 015b lsls r3, r3, #5
- 8000d0c: 1a9b subs r3, r3, r2
- 8000d0e: 009b lsls r3, r3, #2
- 8000d10: 189b adds r3, r3, r2
- 8000d12: 4910 ldr r1, [pc, #64] ; (8000d54 <sht4x_measure+0xc8>)
- 8000d14: 0018 movs r0, r3
- 8000d16: f7ff f9f7 bl 8000108 <__udivsi3>
- 8000d1a: 0003 movs r3, r0
- 8000d1c: 3b06 subs r3, #6
- 8000d1e: 63fb str r3, [r7, #60] ; 0x3c
+ 8000d16: 6b3a ldr r2, [r7, #48] ; 0x30
+ 8000d18: 0013 movs r3, r2
+ 8000d1a: 015b lsls r3, r3, #5
+ 8000d1c: 1a9b subs r3, r3, r2
+ 8000d1e: 009b lsls r3, r3, #2
+ 8000d20: 189b adds r3, r3, r2
+ 8000d22: 4910 ldr r1, [pc, #64] ; (8000d64 <sht4x_measure+0xc8>)
+ 8000d24: 0018 movs r0, r3
+ 8000d26: f7ff f9ef bl 8000108 <__udivsi3>
+ 8000d2a: 0003 movs r3, r0
+ 8000d2c: 3b06 subs r3, #6
+ 8000d2e: 63fb str r3, [r7, #60] ; 0x3c
if (rh_pRH > 100) {
- 8000d20: 6bfb ldr r3, [r7, #60] ; 0x3c
- 8000d22: 2b64 cmp r3, #100 ; 0x64
- 8000d24: dd01 ble.n 8000d2a <sht4x_measure+0x9e>
+ 8000d30: 6bfb ldr r3, [r7, #60] ; 0x3c
+ 8000d32: 2b64 cmp r3, #100 ; 0x64
+ 8000d34: dd01 ble.n 8000d3a <sht4x_measure+0x9e>
rh_pRH = 100;
- 8000d26: 2364 movs r3, #100 ; 0x64
- 8000d28: 63fb str r3, [r7, #60] ; 0x3c
+ 8000d36: 2364 movs r3, #100 ; 0x64
+ 8000d38: 63fb str r3, [r7, #60] ; 0x3c
}
if (rh_pRH < 0) {
- 8000d2a: 6bfb ldr r3, [r7, #60] ; 0x3c
- 8000d2c: 2b00 cmp r3, #0
- 8000d2e: da01 bge.n 8000d34 <sht4x_measure+0xa8>
+ 8000d3a: 6bfb ldr r3, [r7, #60] ; 0x3c
+ 8000d3c: 2b00 cmp r3, #0
+ 8000d3e: da01 bge.n 8000d44 <sht4x_measure+0xa8>
rh_pRH = 0;
- 8000d30: 2300 movs r3, #0
- 8000d32: 63fb str r3, [r7, #60] ; 0x3c
+ 8000d40: 2300 movs r3, #0
+ 8000d42: 63fb str r3, [r7, #60] ; 0x3c
}
*temperature = t_degC;
- 8000d34: 6afb ldr r3, [r7, #44] ; 0x2c
- 8000d36: b21a sxth r2, r3
- 8000d38: 687b ldr r3, [r7, #4]
- 8000d3a: 801a strh r2, [r3, #0]
+ 8000d44: 6afb ldr r3, [r7, #44] ; 0x2c
+ 8000d46: b21a sxth r2, r3
+ 8000d48: 687b ldr r3, [r7, #4]
+ 8000d4a: 801a strh r2, [r3, #0]
*relative_humidity = rh_pRH;
- 8000d3c: 6bfb ldr r3, [r7, #60] ; 0x3c
- 8000d3e: b29a uxth r2, r3
- 8000d40: 683b ldr r3, [r7, #0]
- 8000d42: 801a strh r2, [r3, #0]
+ 8000d4c: 6bfb ldr r3, [r7, #60] ; 0x3c
+ 8000d4e: b29a uxth r2, r3
+ 8000d50: 683b ldr r3, [r7, #0]
+ 8000d52: 801a strh r2, [r3, #0]
return SHT4X_OK;
- 8000d44: 2300 movs r3, #0
+ 8000d54: 2300 movs r3, #0
}
- 8000d46: 0018 movs r0, r3
- 8000d48: 46bd mov sp, r7
- 8000d4a: b011 add sp, #68 ; 0x44
- 8000d4c: bd90 pop {r4, r7, pc}
- 8000d4e: 46c0 nop ; (mov r8, r8)
- 8000d50: 000006d6 .word 0x000006d6
- 8000d54: 0000ffff .word 0x0000ffff
+ 8000d56: 0018 movs r0, r3
+ 8000d58: 46bd mov sp, r7
+ 8000d5a: b011 add sp, #68 ; 0x44
+ 8000d5c: bd90 pop {r4, r7, pc}
+ 8000d5e: 46c0 nop ; (mov r8, r8)
+ 8000d60: 000006d6 .word 0x000006d6
+ 8000d64: 0000ffff .word 0x0000ffff
-08000d58 <HAL_MspInit>:
+08000d68 <HAL_MspInit>:
void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim);
/**
* Initializes the Global MSP.
*/
void HAL_MspInit(void)
{
- 8000d58: b580 push {r7, lr}
- 8000d5a: af00 add r7, sp, #0
+ 8000d68: b580 push {r7, lr}
+ 8000d6a: af00 add r7, sp, #0
/* USER CODE BEGIN MspInit 0 */
/* USER CODE END MspInit 0 */
__HAL_RCC_SYSCFG_CLK_ENABLE();
- 8000d5c: 4b07 ldr r3, [pc, #28] ; (8000d7c <HAL_MspInit+0x24>)
- 8000d5e: 6b5a ldr r2, [r3, #52] ; 0x34
- 8000d60: 4b06 ldr r3, [pc, #24] ; (8000d7c <HAL_MspInit+0x24>)
- 8000d62: 2101 movs r1, #1
- 8000d64: 430a orrs r2, r1
- 8000d66: 635a str r2, [r3, #52] ; 0x34
+ 8000d6c: 4b07 ldr r3, [pc, #28] ; (8000d8c <HAL_MspInit+0x24>)
+ 8000d6e: 6b5a ldr r2, [r3, #52] ; 0x34
+ 8000d70: 4b06 ldr r3, [pc, #24] ; (8000d8c <HAL_MspInit+0x24>)
+ 8000d72: 2101 movs r1, #1
+ 8000d74: 430a orrs r2, r1
+ 8000d76: 635a str r2, [r3, #52] ; 0x34
__HAL_RCC_PWR_CLK_ENABLE();
- 8000d68: 4b04 ldr r3, [pc, #16] ; (8000d7c <HAL_MspInit+0x24>)
- 8000d6a: 6b9a ldr r2, [r3, #56] ; 0x38
- 8000d6c: 4b03 ldr r3, [pc, #12] ; (8000d7c <HAL_MspInit+0x24>)
- 8000d6e: 2180 movs r1, #128 ; 0x80
- 8000d70: 0549 lsls r1, r1, #21
- 8000d72: 430a orrs r2, r1
- 8000d74: 639a str r2, [r3, #56] ; 0x38
+ 8000d78: 4b04 ldr r3, [pc, #16] ; (8000d8c <HAL_MspInit+0x24>)
+ 8000d7a: 6b9a ldr r2, [r3, #56] ; 0x38
+ 8000d7c: 4b03 ldr r3, [pc, #12] ; (8000d8c <HAL_MspInit+0x24>)
+ 8000d7e: 2180 movs r1, #128 ; 0x80
+ 8000d80: 0549 lsls r1, r1, #21
+ 8000d82: 430a orrs r2, r1
+ 8000d84: 639a str r2, [r3, #56] ; 0x38
/* System interrupt init*/
/* USER CODE BEGIN MspInit 1 */
/* USER CODE END MspInit 1 */
}
- 8000d76: 46c0 nop ; (mov r8, r8)
- 8000d78: 46bd mov sp, r7
- 8000d7a: bd80 pop {r7, pc}
- 8000d7c: 40021000 .word 0x40021000
+ 8000d86: 46c0 nop ; (mov r8, r8)
+ 8000d88: 46bd mov sp, r7
+ 8000d8a: bd80 pop {r7, pc}
+ 8000d8c: 40021000 .word 0x40021000
-08000d80 <HAL_I2C_MspInit>:
+08000d90 <HAL_I2C_MspInit>:
* This function configures the hardware resources used in this example
* @param hi2c: I2C handle pointer
* @retval None
*/
void HAL_I2C_MspInit(I2C_HandleTypeDef* hi2c)
{
- 8000d80: b590 push {r4, r7, lr}
- 8000d82: b089 sub sp, #36 ; 0x24
- 8000d84: af00 add r7, sp, #0
- 8000d86: 6078 str r0, [r7, #4]
+ 8000d90: b590 push {r4, r7, lr}
+ 8000d92: b089 sub sp, #36 ; 0x24
+ 8000d94: af00 add r7, sp, #0
+ 8000d96: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
- 8000d88: 240c movs r4, #12
- 8000d8a: 193b adds r3, r7, r4
- 8000d8c: 0018 movs r0, r3
- 8000d8e: 2314 movs r3, #20
- 8000d90: 001a movs r2, r3
- 8000d92: 2100 movs r1, #0
- 8000d94: f003 fac4 bl 8004320 <memset>
+ 8000d98: 240c movs r4, #12
+ 8000d9a: 193b adds r3, r7, r4
+ 8000d9c: 0018 movs r0, r3
+ 8000d9e: 2314 movs r3, #20
+ 8000da0: 001a movs r2, r3
+ 8000da2: 2100 movs r1, #0
+ 8000da4: f003 fac4 bl 8004330 <memset>
if(hi2c->Instance==I2C1)
- 8000d98: 687b ldr r3, [r7, #4]
- 8000d9a: 681b ldr r3, [r3, #0]
- 8000d9c: 4a18 ldr r2, [pc, #96] ; (8000e00 <HAL_I2C_MspInit+0x80>)
- 8000d9e: 4293 cmp r3, r2
- 8000da0: d12a bne.n 8000df8 <HAL_I2C_MspInit+0x78>
+ 8000da8: 687b ldr r3, [r7, #4]
+ 8000daa: 681b ldr r3, [r3, #0]
+ 8000dac: 4a18 ldr r2, [pc, #96] ; (8000e10 <HAL_I2C_MspInit+0x80>)
+ 8000dae: 4293 cmp r3, r2
+ 8000db0: d12a bne.n 8000e08 <HAL_I2C_MspInit+0x78>
{
/* USER CODE BEGIN I2C1_MspInit 0 */
/* USER CODE END I2C1_MspInit 0 */
__HAL_RCC_GPIOA_CLK_ENABLE();
- 8000da2: 4b18 ldr r3, [pc, #96] ; (8000e04 <HAL_I2C_MspInit+0x84>)
- 8000da4: 6ada ldr r2, [r3, #44] ; 0x2c
- 8000da6: 4b17 ldr r3, [pc, #92] ; (8000e04 <HAL_I2C_MspInit+0x84>)
- 8000da8: 2101 movs r1, #1
- 8000daa: 430a orrs r2, r1
- 8000dac: 62da str r2, [r3, #44] ; 0x2c
- 8000dae: 4b15 ldr r3, [pc, #84] ; (8000e04 <HAL_I2C_MspInit+0x84>)
- 8000db0: 6adb ldr r3, [r3, #44] ; 0x2c
- 8000db2: 2201 movs r2, #1
- 8000db4: 4013 ands r3, r2
- 8000db6: 60bb str r3, [r7, #8]
- 8000db8: 68bb ldr r3, [r7, #8]
+ 8000db2: 4b18 ldr r3, [pc, #96] ; (8000e14 <HAL_I2C_MspInit+0x84>)
+ 8000db4: 6ada ldr r2, [r3, #44] ; 0x2c
+ 8000db6: 4b17 ldr r3, [pc, #92] ; (8000e14 <HAL_I2C_MspInit+0x84>)
+ 8000db8: 2101 movs r1, #1
+ 8000dba: 430a orrs r2, r1
+ 8000dbc: 62da str r2, [r3, #44] ; 0x2c
+ 8000dbe: 4b15 ldr r3, [pc, #84] ; (8000e14 <HAL_I2C_MspInit+0x84>)
+ 8000dc0: 6adb ldr r3, [r3, #44] ; 0x2c
+ 8000dc2: 2201 movs r2, #1
+ 8000dc4: 4013 ands r3, r2
+ 8000dc6: 60bb str r3, [r7, #8]
+ 8000dc8: 68bb ldr r3, [r7, #8]
/**I2C1 GPIO Configuration
PA9 ------> I2C1_SCL
PA10 ------> I2C1_SDA
*/
GPIO_InitStruct.Pin = GPIO_PIN_9|GPIO_PIN_10;
- 8000dba: 193b adds r3, r7, r4
- 8000dbc: 22c0 movs r2, #192 ; 0xc0
- 8000dbe: 00d2 lsls r2, r2, #3
- 8000dc0: 601a str r2, [r3, #0]
+ 8000dca: 193b adds r3, r7, r4
+ 8000dcc: 22c0 movs r2, #192 ; 0xc0
+ 8000dce: 00d2 lsls r2, r2, #3
+ 8000dd0: 601a str r2, [r3, #0]
GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
- 8000dc2: 0021 movs r1, r4
- 8000dc4: 187b adds r3, r7, r1
- 8000dc6: 2212 movs r2, #18
- 8000dc8: 605a str r2, [r3, #4]
+ 8000dd2: 0021 movs r1, r4
+ 8000dd4: 187b adds r3, r7, r1
+ 8000dd6: 2212 movs r2, #18
+ 8000dd8: 605a str r2, [r3, #4]
GPIO_InitStruct.Pull = GPIO_PULLUP;
- 8000dca: 187b adds r3, r7, r1
- 8000dcc: 2201 movs r2, #1
- 8000dce: 609a str r2, [r3, #8]
+ 8000dda: 187b adds r3, r7, r1
+ 8000ddc: 2201 movs r2, #1
+ 8000dde: 609a str r2, [r3, #8]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
- 8000dd0: 187b adds r3, r7, r1
- 8000dd2: 2203 movs r2, #3
- 8000dd4: 60da str r2, [r3, #12]
+ 8000de0: 187b adds r3, r7, r1
+ 8000de2: 2203 movs r2, #3
+ 8000de4: 60da str r2, [r3, #12]
GPIO_InitStruct.Alternate = GPIO_AF1_I2C1;
- 8000dd6: 187b adds r3, r7, r1
- 8000dd8: 2201 movs r2, #1
- 8000dda: 611a str r2, [r3, #16]
+ 8000de6: 187b adds r3, r7, r1
+ 8000de8: 2201 movs r2, #1
+ 8000dea: 611a str r2, [r3, #16]
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
- 8000ddc: 187a adds r2, r7, r1
- 8000dde: 23a0 movs r3, #160 ; 0xa0
- 8000de0: 05db lsls r3, r3, #23
- 8000de2: 0011 movs r1, r2
- 8000de4: 0018 movs r0, r3
- 8000de6: f000 fa79 bl 80012dc <HAL_GPIO_Init>
+ 8000dec: 187a adds r2, r7, r1
+ 8000dee: 23a0 movs r3, #160 ; 0xa0
+ 8000df0: 05db lsls r3, r3, #23
+ 8000df2: 0011 movs r1, r2
+ 8000df4: 0018 movs r0, r3
+ 8000df6: f000 fa79 bl 80012ec <HAL_GPIO_Init>
/* Peripheral clock enable */
__HAL_RCC_I2C1_CLK_ENABLE();
- 8000dea: 4b06 ldr r3, [pc, #24] ; (8000e04 <HAL_I2C_MspInit+0x84>)
- 8000dec: 6b9a ldr r2, [r3, #56] ; 0x38
- 8000dee: 4b05 ldr r3, [pc, #20] ; (8000e04 <HAL_I2C_MspInit+0x84>)
- 8000df0: 2180 movs r1, #128 ; 0x80
- 8000df2: 0389 lsls r1, r1, #14
- 8000df4: 430a orrs r2, r1
- 8000df6: 639a str r2, [r3, #56] ; 0x38
+ 8000dfa: 4b06 ldr r3, [pc, #24] ; (8000e14 <HAL_I2C_MspInit+0x84>)
+ 8000dfc: 6b9a ldr r2, [r3, #56] ; 0x38
+ 8000dfe: 4b05 ldr r3, [pc, #20] ; (8000e14 <HAL_I2C_MspInit+0x84>)
+ 8000e00: 2180 movs r1, #128 ; 0x80
+ 8000e02: 0389 lsls r1, r1, #14
+ 8000e04: 430a orrs r2, r1
+ 8000e06: 639a str r2, [r3, #56] ; 0x38
/* USER CODE BEGIN I2C1_MspInit 1 */
/* USER CODE END I2C1_MspInit 1 */
}
}
- 8000df8: 46c0 nop ; (mov r8, r8)
- 8000dfa: 46bd mov sp, r7
- 8000dfc: b009 add sp, #36 ; 0x24
- 8000dfe: bd90 pop {r4, r7, pc}
- 8000e00: 40005400 .word 0x40005400
- 8000e04: 40021000 .word 0x40021000
+ 8000e08: 46c0 nop ; (mov r8, r8)
+ 8000e0a: 46bd mov sp, r7
+ 8000e0c: b009 add sp, #36 ; 0x24
+ 8000e0e: bd90 pop {r4, r7, pc}
+ 8000e10: 40005400 .word 0x40005400
+ 8000e14: 40021000 .word 0x40021000
-08000e08 <HAL_TIM_Base_MspInit>:
+08000e18 <HAL_TIM_Base_MspInit>:
* This function configures the hardware resources used in this example
* @param htim_base: TIM_Base handle pointer
* @retval None
*/
void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base)
{
- 8000e08: b580 push {r7, lr}
- 8000e0a: b082 sub sp, #8
- 8000e0c: af00 add r7, sp, #0
- 8000e0e: 6078 str r0, [r7, #4]
+ 8000e18: b580 push {r7, lr}
+ 8000e1a: b082 sub sp, #8
+ 8000e1c: af00 add r7, sp, #0
+ 8000e1e: 6078 str r0, [r7, #4]
if(htim_base->Instance==TIM2)
- 8000e10: 687b ldr r3, [r7, #4]
- 8000e12: 681a ldr r2, [r3, #0]
- 8000e14: 2380 movs r3, #128 ; 0x80
- 8000e16: 05db lsls r3, r3, #23
- 8000e18: 429a cmp r2, r3
- 8000e1a: d106 bne.n 8000e2a <HAL_TIM_Base_MspInit+0x22>
+ 8000e20: 687b ldr r3, [r7, #4]
+ 8000e22: 681a ldr r2, [r3, #0]
+ 8000e24: 2380 movs r3, #128 ; 0x80
+ 8000e26: 05db lsls r3, r3, #23
+ 8000e28: 429a cmp r2, r3
+ 8000e2a: d106 bne.n 8000e3a <HAL_TIM_Base_MspInit+0x22>
{
/* USER CODE BEGIN TIM2_MspInit 0 */
/* USER CODE END TIM2_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_TIM2_CLK_ENABLE();
- 8000e1c: 4b10 ldr r3, [pc, #64] ; (8000e60 <HAL_TIM_Base_MspInit+0x58>)
- 8000e1e: 6b9a ldr r2, [r3, #56] ; 0x38
- 8000e20: 4b0f ldr r3, [pc, #60] ; (8000e60 <HAL_TIM_Base_MspInit+0x58>)
- 8000e22: 2101 movs r1, #1
- 8000e24: 430a orrs r2, r1
- 8000e26: 639a str r2, [r3, #56] ; 0x38
+ 8000e2c: 4b10 ldr r3, [pc, #64] ; (8000e70 <HAL_TIM_Base_MspInit+0x58>)
+ 8000e2e: 6b9a ldr r2, [r3, #56] ; 0x38
+ 8000e30: 4b0f ldr r3, [pc, #60] ; (8000e70 <HAL_TIM_Base_MspInit+0x58>)
+ 8000e32: 2101 movs r1, #1
+ 8000e34: 430a orrs r2, r1
+ 8000e36: 639a str r2, [r3, #56] ; 0x38
/* USER CODE BEGIN TIM22_MspInit 1 */
/* USER CODE END TIM22_MspInit 1 */
}
}
- 8000e28: e016 b.n 8000e58 <HAL_TIM_Base_MspInit+0x50>
+ 8000e38: e016 b.n 8000e68 <HAL_TIM_Base_MspInit+0x50>
else if(htim_base->Instance==TIM21)
- 8000e2a: 687b ldr r3, [r7, #4]
- 8000e2c: 681b ldr r3, [r3, #0]
- 8000e2e: 4a0d ldr r2, [pc, #52] ; (8000e64 <HAL_TIM_Base_MspInit+0x5c>)
- 8000e30: 4293 cmp r3, r2
- 8000e32: d106 bne.n 8000e42 <HAL_TIM_Base_MspInit+0x3a>
+ 8000e3a: 687b ldr r3, [r7, #4]
+ 8000e3c: 681b ldr r3, [r3, #0]
+ 8000e3e: 4a0d ldr r2, [pc, #52] ; (8000e74 <HAL_TIM_Base_MspInit+0x5c>)
+ 8000e40: 4293 cmp r3, r2
+ 8000e42: d106 bne.n 8000e52 <HAL_TIM_Base_MspInit+0x3a>
__HAL_RCC_TIM21_CLK_ENABLE();
- 8000e34: 4b0a ldr r3, [pc, #40] ; (8000e60 <HAL_TIM_Base_MspInit+0x58>)
- 8000e36: 6b5a ldr r2, [r3, #52] ; 0x34
- 8000e38: 4b09 ldr r3, [pc, #36] ; (8000e60 <HAL_TIM_Base_MspInit+0x58>)
- 8000e3a: 2104 movs r1, #4
- 8000e3c: 430a orrs r2, r1
- 8000e3e: 635a str r2, [r3, #52] ; 0x34
+ 8000e44: 4b0a ldr r3, [pc, #40] ; (8000e70 <HAL_TIM_Base_MspInit+0x58>)
+ 8000e46: 6b5a ldr r2, [r3, #52] ; 0x34
+ 8000e48: 4b09 ldr r3, [pc, #36] ; (8000e70 <HAL_TIM_Base_MspInit+0x58>)
+ 8000e4a: 2104 movs r1, #4
+ 8000e4c: 430a orrs r2, r1
+ 8000e4e: 635a str r2, [r3, #52] ; 0x34
}
- 8000e40: e00a b.n 8000e58 <HAL_TIM_Base_MspInit+0x50>
+ 8000e50: e00a b.n 8000e68 <HAL_TIM_Base_MspInit+0x50>
else if(htim_base->Instance==TIM22)
- 8000e42: 687b ldr r3, [r7, #4]
- 8000e44: 681b ldr r3, [r3, #0]
- 8000e46: 4a08 ldr r2, [pc, #32] ; (8000e68 <HAL_TIM_Base_MspInit+0x60>)
- 8000e48: 4293 cmp r3, r2
- 8000e4a: d105 bne.n 8000e58 <HAL_TIM_Base_MspInit+0x50>
+ 8000e52: 687b ldr r3, [r7, #4]
+ 8000e54: 681b ldr r3, [r3, #0]
+ 8000e56: 4a08 ldr r2, [pc, #32] ; (8000e78 <HAL_TIM_Base_MspInit+0x60>)
+ 8000e58: 4293 cmp r3, r2
+ 8000e5a: d105 bne.n 8000e68 <HAL_TIM_Base_MspInit+0x50>
__HAL_RCC_TIM22_CLK_ENABLE();
- 8000e4c: 4b04 ldr r3, [pc, #16] ; (8000e60 <HAL_TIM_Base_MspInit+0x58>)
- 8000e4e: 6b5a ldr r2, [r3, #52] ; 0x34
- 8000e50: 4b03 ldr r3, [pc, #12] ; (8000e60 <HAL_TIM_Base_MspInit+0x58>)
- 8000e52: 2120 movs r1, #32
- 8000e54: 430a orrs r2, r1
- 8000e56: 635a str r2, [r3, #52] ; 0x34
+ 8000e5c: 4b04 ldr r3, [pc, #16] ; (8000e70 <HAL_TIM_Base_MspInit+0x58>)
+ 8000e5e: 6b5a ldr r2, [r3, #52] ; 0x34
+ 8000e60: 4b03 ldr r3, [pc, #12] ; (8000e70 <HAL_TIM_Base_MspInit+0x58>)
+ 8000e62: 2120 movs r1, #32
+ 8000e64: 430a orrs r2, r1
+ 8000e66: 635a str r2, [r3, #52] ; 0x34
}
- 8000e58: 46c0 nop ; (mov r8, r8)
- 8000e5a: 46bd mov sp, r7
- 8000e5c: b002 add sp, #8
- 8000e5e: bd80 pop {r7, pc}
- 8000e60: 40021000 .word 0x40021000
- 8000e64: 40010800 .word 0x40010800
- 8000e68: 40011400 .word 0x40011400
+ 8000e68: 46c0 nop ; (mov r8, r8)
+ 8000e6a: 46bd mov sp, r7
+ 8000e6c: b002 add sp, #8
+ 8000e6e: bd80 pop {r7, pc}
+ 8000e70: 40021000 .word 0x40021000
+ 8000e74: 40010800 .word 0x40010800
+ 8000e78: 40011400 .word 0x40011400
-08000e6c <HAL_TIM_MspPostInit>:
+08000e7c <HAL_TIM_MspPostInit>:
void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim)
{
- 8000e6c: b590 push {r4, r7, lr}
- 8000e6e: b08b sub sp, #44 ; 0x2c
- 8000e70: af00 add r7, sp, #0
- 8000e72: 6078 str r0, [r7, #4]
+ 8000e7c: b590 push {r4, r7, lr}
+ 8000e7e: b08b sub sp, #44 ; 0x2c
+ 8000e80: af00 add r7, sp, #0
+ 8000e82: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
- 8000e74: 2414 movs r4, #20
- 8000e76: 193b adds r3, r7, r4
- 8000e78: 0018 movs r0, r3
- 8000e7a: 2314 movs r3, #20
- 8000e7c: 001a movs r2, r3
- 8000e7e: 2100 movs r1, #0
- 8000e80: f003 fa4e bl 8004320 <memset>
+ 8000e84: 2414 movs r4, #20
+ 8000e86: 193b adds r3, r7, r4
+ 8000e88: 0018 movs r0, r3
+ 8000e8a: 2314 movs r3, #20
+ 8000e8c: 001a movs r2, r3
+ 8000e8e: 2100 movs r1, #0
+ 8000e90: f003 fa4e bl 8004330 <memset>
if(htim->Instance==TIM2)
- 8000e84: 687b ldr r3, [r7, #4]
- 8000e86: 681a ldr r2, [r3, #0]
- 8000e88: 2380 movs r3, #128 ; 0x80
- 8000e8a: 05db lsls r3, r3, #23
- 8000e8c: 429a cmp r2, r3
- 8000e8e: d123 bne.n 8000ed8 <HAL_TIM_MspPostInit+0x6c>
+ 8000e94: 687b ldr r3, [r7, #4]
+ 8000e96: 681a ldr r2, [r3, #0]
+ 8000e98: 2380 movs r3, #128 ; 0x80
+ 8000e9a: 05db lsls r3, r3, #23
+ 8000e9c: 429a cmp r2, r3
+ 8000e9e: d123 bne.n 8000ee8 <HAL_TIM_MspPostInit+0x6c>
{
/* USER CODE BEGIN TIM2_MspPostInit 0 */
/* USER CODE END TIM2_MspPostInit 0 */
__HAL_RCC_GPIOA_CLK_ENABLE();
- 8000e90: 4b27 ldr r3, [pc, #156] ; (8000f30 <HAL_TIM_MspPostInit+0xc4>)
- 8000e92: 6ada ldr r2, [r3, #44] ; 0x2c
- 8000e94: 4b26 ldr r3, [pc, #152] ; (8000f30 <HAL_TIM_MspPostInit+0xc4>)
- 8000e96: 2101 movs r1, #1
- 8000e98: 430a orrs r2, r1
- 8000e9a: 62da str r2, [r3, #44] ; 0x2c
- 8000e9c: 4b24 ldr r3, [pc, #144] ; (8000f30 <HAL_TIM_MspPostInit+0xc4>)
- 8000e9e: 6adb ldr r3, [r3, #44] ; 0x2c
- 8000ea0: 2201 movs r2, #1
- 8000ea2: 4013 ands r3, r2
- 8000ea4: 613b str r3, [r7, #16]
- 8000ea6: 693b ldr r3, [r7, #16]
+ 8000ea0: 4b27 ldr r3, [pc, #156] ; (8000f40 <HAL_TIM_MspPostInit+0xc4>)
+ 8000ea2: 6ada ldr r2, [r3, #44] ; 0x2c
+ 8000ea4: 4b26 ldr r3, [pc, #152] ; (8000f40 <HAL_TIM_MspPostInit+0xc4>)
+ 8000ea6: 2101 movs r1, #1
+ 8000ea8: 430a orrs r2, r1
+ 8000eaa: 62da str r2, [r3, #44] ; 0x2c
+ 8000eac: 4b24 ldr r3, [pc, #144] ; (8000f40 <HAL_TIM_MspPostInit+0xc4>)
+ 8000eae: 6adb ldr r3, [r3, #44] ; 0x2c
+ 8000eb0: 2201 movs r2, #1
+ 8000eb2: 4013 ands r3, r2
+ 8000eb4: 613b str r3, [r7, #16]
+ 8000eb6: 693b ldr r3, [r7, #16]
/**TIM2 GPIO Configuration
PA5 ------> TIM2_CH1
*/
GPIO_InitStruct.Pin = GPIO_PIN_5;
- 8000ea8: 0021 movs r1, r4
- 8000eaa: 187b adds r3, r7, r1
- 8000eac: 2220 movs r2, #32
- 8000eae: 601a str r2, [r3, #0]
+ 8000eb8: 0021 movs r1, r4
+ 8000eba: 187b adds r3, r7, r1
+ 8000ebc: 2220 movs r2, #32
+ 8000ebe: 601a str r2, [r3, #0]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
- 8000eb0: 187b adds r3, r7, r1
- 8000eb2: 2202 movs r2, #2
- 8000eb4: 605a str r2, [r3, #4]
+ 8000ec0: 187b adds r3, r7, r1
+ 8000ec2: 2202 movs r2, #2
+ 8000ec4: 605a str r2, [r3, #4]
GPIO_InitStruct.Pull = GPIO_NOPULL;
- 8000eb6: 187b adds r3, r7, r1
- 8000eb8: 2200 movs r2, #0
- 8000eba: 609a str r2, [r3, #8]
+ 8000ec6: 187b adds r3, r7, r1
+ 8000ec8: 2200 movs r2, #0
+ 8000eca: 609a str r2, [r3, #8]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
- 8000ebc: 187b adds r3, r7, r1
- 8000ebe: 2200 movs r2, #0
- 8000ec0: 60da str r2, [r3, #12]
+ 8000ecc: 187b adds r3, r7, r1
+ 8000ece: 2200 movs r2, #0
+ 8000ed0: 60da str r2, [r3, #12]
GPIO_InitStruct.Alternate = GPIO_AF5_TIM2;
- 8000ec2: 187b adds r3, r7, r1
- 8000ec4: 2205 movs r2, #5
- 8000ec6: 611a str r2, [r3, #16]
+ 8000ed2: 187b adds r3, r7, r1
+ 8000ed4: 2205 movs r2, #5
+ 8000ed6: 611a str r2, [r3, #16]
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
- 8000ec8: 187a adds r2, r7, r1
- 8000eca: 23a0 movs r3, #160 ; 0xa0
- 8000ecc: 05db lsls r3, r3, #23
- 8000ece: 0011 movs r1, r2
- 8000ed0: 0018 movs r0, r3
- 8000ed2: f000 fa03 bl 80012dc <HAL_GPIO_Init>
+ 8000ed8: 187a adds r2, r7, r1
+ 8000eda: 23a0 movs r3, #160 ; 0xa0
+ 8000edc: 05db lsls r3, r3, #23
+ 8000ede: 0011 movs r1, r2
+ 8000ee0: 0018 movs r0, r3
+ 8000ee2: f000 fa03 bl 80012ec <HAL_GPIO_Init>
/* USER CODE BEGIN TIM22_MspPostInit 1 */
/* USER CODE END TIM22_MspPostInit 1 */
}
}
- 8000ed6: e027 b.n 8000f28 <HAL_TIM_MspPostInit+0xbc>
+ 8000ee6: e027 b.n 8000f38 <HAL_TIM_MspPostInit+0xbc>
else if(htim->Instance==TIM22)
- 8000ed8: 687b ldr r3, [r7, #4]
- 8000eda: 681b ldr r3, [r3, #0]
- 8000edc: 4a15 ldr r2, [pc, #84] ; (8000f34 <HAL_TIM_MspPostInit+0xc8>)
- 8000ede: 4293 cmp r3, r2
- 8000ee0: d122 bne.n 8000f28 <HAL_TIM_MspPostInit+0xbc>
+ 8000ee8: 687b ldr r3, [r7, #4]
+ 8000eea: 681b ldr r3, [r3, #0]
+ 8000eec: 4a15 ldr r2, [pc, #84] ; (8000f44 <HAL_TIM_MspPostInit+0xc8>)
+ 8000eee: 4293 cmp r3, r2
+ 8000ef0: d122 bne.n 8000f38 <HAL_TIM_MspPostInit+0xbc>
__HAL_RCC_GPIOA_CLK_ENABLE();
- 8000ee2: 4b13 ldr r3, [pc, #76] ; (8000f30 <HAL_TIM_MspPostInit+0xc4>)
- 8000ee4: 6ada ldr r2, [r3, #44] ; 0x2c
- 8000ee6: 4b12 ldr r3, [pc, #72] ; (8000f30 <HAL_TIM_MspPostInit+0xc4>)
- 8000ee8: 2101 movs r1, #1
- 8000eea: 430a orrs r2, r1
- 8000eec: 62da str r2, [r3, #44] ; 0x2c
- 8000eee: 4b10 ldr r3, [pc, #64] ; (8000f30 <HAL_TIM_MspPostInit+0xc4>)
- 8000ef0: 6adb ldr r3, [r3, #44] ; 0x2c
- 8000ef2: 2201 movs r2, #1
- 8000ef4: 4013 ands r3, r2
- 8000ef6: 60fb str r3, [r7, #12]
- 8000ef8: 68fb ldr r3, [r7, #12]
+ 8000ef2: 4b13 ldr r3, [pc, #76] ; (8000f40 <HAL_TIM_MspPostInit+0xc4>)
+ 8000ef4: 6ada ldr r2, [r3, #44] ; 0x2c
+ 8000ef6: 4b12 ldr r3, [pc, #72] ; (8000f40 <HAL_TIM_MspPostInit+0xc4>)
+ 8000ef8: 2101 movs r1, #1
+ 8000efa: 430a orrs r2, r1
+ 8000efc: 62da str r2, [r3, #44] ; 0x2c
+ 8000efe: 4b10 ldr r3, [pc, #64] ; (8000f40 <HAL_TIM_MspPostInit+0xc4>)
+ 8000f00: 6adb ldr r3, [r3, #44] ; 0x2c
+ 8000f02: 2201 movs r2, #1
+ 8000f04: 4013 ands r3, r2
+ 8000f06: 60fb str r3, [r7, #12]
+ 8000f08: 68fb ldr r3, [r7, #12]
GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7;
- 8000efa: 2114 movs r1, #20
- 8000efc: 187b adds r3, r7, r1
- 8000efe: 22c0 movs r2, #192 ; 0xc0
- 8000f00: 601a str r2, [r3, #0]
+ 8000f0a: 2114 movs r1, #20
+ 8000f0c: 187b adds r3, r7, r1
+ 8000f0e: 22c0 movs r2, #192 ; 0xc0
+ 8000f10: 601a str r2, [r3, #0]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
- 8000f02: 187b adds r3, r7, r1
- 8000f04: 2202 movs r2, #2
- 8000f06: 605a str r2, [r3, #4]
+ 8000f12: 187b adds r3, r7, r1
+ 8000f14: 2202 movs r2, #2
+ 8000f16: 605a str r2, [r3, #4]
GPIO_InitStruct.Pull = GPIO_NOPULL;
- 8000f08: 187b adds r3, r7, r1
- 8000f0a: 2200 movs r2, #0
- 8000f0c: 609a str r2, [r3, #8]
+ 8000f18: 187b adds r3, r7, r1
+ 8000f1a: 2200 movs r2, #0
+ 8000f1c: 609a str r2, [r3, #8]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
- 8000f0e: 187b adds r3, r7, r1
- 8000f10: 2200 movs r2, #0
- 8000f12: 60da str r2, [r3, #12]
+ 8000f1e: 187b adds r3, r7, r1
+ 8000f20: 2200 movs r2, #0
+ 8000f22: 60da str r2, [r3, #12]
GPIO_InitStruct.Alternate = GPIO_AF5_TIM22;
- 8000f14: 187b adds r3, r7, r1
- 8000f16: 2205 movs r2, #5
- 8000f18: 611a str r2, [r3, #16]
+ 8000f24: 187b adds r3, r7, r1
+ 8000f26: 2205 movs r2, #5
+ 8000f28: 611a str r2, [r3, #16]
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
- 8000f1a: 187a adds r2, r7, r1
- 8000f1c: 23a0 movs r3, #160 ; 0xa0
- 8000f1e: 05db lsls r3, r3, #23
- 8000f20: 0011 movs r1, r2
- 8000f22: 0018 movs r0, r3
- 8000f24: f000 f9da bl 80012dc <HAL_GPIO_Init>
+ 8000f2a: 187a adds r2, r7, r1
+ 8000f2c: 23a0 movs r3, #160 ; 0xa0
+ 8000f2e: 05db lsls r3, r3, #23
+ 8000f30: 0011 movs r1, r2
+ 8000f32: 0018 movs r0, r3
+ 8000f34: f000 f9da bl 80012ec <HAL_GPIO_Init>
}
- 8000f28: 46c0 nop ; (mov r8, r8)
- 8000f2a: 46bd mov sp, r7
- 8000f2c: b00b add sp, #44 ; 0x2c
- 8000f2e: bd90 pop {r4, r7, pc}
- 8000f30: 40021000 .word 0x40021000
- 8000f34: 40011400 .word 0x40011400
+ 8000f38: 46c0 nop ; (mov r8, r8)
+ 8000f3a: 46bd mov sp, r7
+ 8000f3c: b00b add sp, #44 ; 0x2c
+ 8000f3e: bd90 pop {r4, r7, pc}
+ 8000f40: 40021000 .word 0x40021000
+ 8000f44: 40011400 .word 0x40011400
-08000f38 <HAL_UART_MspInit>:
+08000f48 <HAL_UART_MspInit>:
* This function configures the hardware resources used in this example
* @param huart: UART handle pointer
* @retval None
*/
void HAL_UART_MspInit(UART_HandleTypeDef* huart)
{
- 8000f38: b590 push {r4, r7, lr}
- 8000f3a: b089 sub sp, #36 ; 0x24
- 8000f3c: af00 add r7, sp, #0
- 8000f3e: 6078 str r0, [r7, #4]
+ 8000f48: b590 push {r4, r7, lr}
+ 8000f4a: b089 sub sp, #36 ; 0x24
+ 8000f4c: af00 add r7, sp, #0
+ 8000f4e: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
- 8000f40: 240c movs r4, #12
- 8000f42: 193b adds r3, r7, r4
- 8000f44: 0018 movs r0, r3
- 8000f46: 2314 movs r3, #20
- 8000f48: 001a movs r2, r3
- 8000f4a: 2100 movs r1, #0
- 8000f4c: f003 f9e8 bl 8004320 <memset>
+ 8000f50: 240c movs r4, #12
+ 8000f52: 193b adds r3, r7, r4
+ 8000f54: 0018 movs r0, r3
+ 8000f56: 2314 movs r3, #20
+ 8000f58: 001a movs r2, r3
+ 8000f5a: 2100 movs r1, #0
+ 8000f5c: f003 f9e8 bl 8004330 <memset>
if(huart->Instance==USART2)
- 8000f50: 687b ldr r3, [r7, #4]
- 8000f52: 681b ldr r3, [r3, #0]
- 8000f54: 4a18 ldr r2, [pc, #96] ; (8000fb8 <HAL_UART_MspInit+0x80>)
- 8000f56: 4293 cmp r3, r2
- 8000f58: d129 bne.n 8000fae <HAL_UART_MspInit+0x76>
+ 8000f60: 687b ldr r3, [r7, #4]
+ 8000f62: 681b ldr r3, [r3, #0]
+ 8000f64: 4a18 ldr r2, [pc, #96] ; (8000fc8 <HAL_UART_MspInit+0x80>)
+ 8000f66: 4293 cmp r3, r2
+ 8000f68: d129 bne.n 8000fbe <HAL_UART_MspInit+0x76>
{
/* USER CODE BEGIN USART2_MspInit 0 */
/* USER CODE END USART2_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_USART2_CLK_ENABLE();
- 8000f5a: 4b18 ldr r3, [pc, #96] ; (8000fbc <HAL_UART_MspInit+0x84>)
- 8000f5c: 6b9a ldr r2, [r3, #56] ; 0x38
- 8000f5e: 4b17 ldr r3, [pc, #92] ; (8000fbc <HAL_UART_MspInit+0x84>)
- 8000f60: 2180 movs r1, #128 ; 0x80
- 8000f62: 0289 lsls r1, r1, #10
- 8000f64: 430a orrs r2, r1
- 8000f66: 639a str r2, [r3, #56] ; 0x38
+ 8000f6a: 4b18 ldr r3, [pc, #96] ; (8000fcc <HAL_UART_MspInit+0x84>)
+ 8000f6c: 6b9a ldr r2, [r3, #56] ; 0x38
+ 8000f6e: 4b17 ldr r3, [pc, #92] ; (8000fcc <HAL_UART_MspInit+0x84>)
+ 8000f70: 2180 movs r1, #128 ; 0x80
+ 8000f72: 0289 lsls r1, r1, #10
+ 8000f74: 430a orrs r2, r1
+ 8000f76: 639a str r2, [r3, #56] ; 0x38
__HAL_RCC_GPIOA_CLK_ENABLE();
- 8000f68: 4b14 ldr r3, [pc, #80] ; (8000fbc <HAL_UART_MspInit+0x84>)
- 8000f6a: 6ada ldr r2, [r3, #44] ; 0x2c
- 8000f6c: 4b13 ldr r3, [pc, #76] ; (8000fbc <HAL_UART_MspInit+0x84>)
- 8000f6e: 2101 movs r1, #1
- 8000f70: 430a orrs r2, r1
- 8000f72: 62da str r2, [r3, #44] ; 0x2c
- 8000f74: 4b11 ldr r3, [pc, #68] ; (8000fbc <HAL_UART_MspInit+0x84>)
- 8000f76: 6adb ldr r3, [r3, #44] ; 0x2c
- 8000f78: 2201 movs r2, #1
- 8000f7a: 4013 ands r3, r2
- 8000f7c: 60bb str r3, [r7, #8]
- 8000f7e: 68bb ldr r3, [r7, #8]
+ 8000f78: 4b14 ldr r3, [pc, #80] ; (8000fcc <HAL_UART_MspInit+0x84>)
+ 8000f7a: 6ada ldr r2, [r3, #44] ; 0x2c
+ 8000f7c: 4b13 ldr r3, [pc, #76] ; (8000fcc <HAL_UART_MspInit+0x84>)
+ 8000f7e: 2101 movs r1, #1
+ 8000f80: 430a orrs r2, r1
+ 8000f82: 62da str r2, [r3, #44] ; 0x2c
+ 8000f84: 4b11 ldr r3, [pc, #68] ; (8000fcc <HAL_UART_MspInit+0x84>)
+ 8000f86: 6adb ldr r3, [r3, #44] ; 0x2c
+ 8000f88: 2201 movs r2, #1
+ 8000f8a: 4013 ands r3, r2
+ 8000f8c: 60bb str r3, [r7, #8]
+ 8000f8e: 68bb ldr r3, [r7, #8]
/**USART2 GPIO Configuration
PA1 ------> USART2_DE
PA2 ------> USART2_TX
PA3 ------> USART2_RX
*/
GPIO_InitStruct.Pin = GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3;
- 8000f80: 0021 movs r1, r4
- 8000f82: 187b adds r3, r7, r1
- 8000f84: 220e movs r2, #14
- 8000f86: 601a str r2, [r3, #0]
+ 8000f90: 0021 movs r1, r4
+ 8000f92: 187b adds r3, r7, r1
+ 8000f94: 220e movs r2, #14
+ 8000f96: 601a str r2, [r3, #0]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
- 8000f88: 187b adds r3, r7, r1
- 8000f8a: 2202 movs r2, #2
- 8000f8c: 605a str r2, [r3, #4]
+ 8000f98: 187b adds r3, r7, r1
+ 8000f9a: 2202 movs r2, #2
+ 8000f9c: 605a str r2, [r3, #4]
GPIO_InitStruct.Pull = GPIO_NOPULL;
- 8000f8e: 187b adds r3, r7, r1
- 8000f90: 2200 movs r2, #0
- 8000f92: 609a str r2, [r3, #8]
+ 8000f9e: 187b adds r3, r7, r1
+ 8000fa0: 2200 movs r2, #0
+ 8000fa2: 609a str r2, [r3, #8]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
- 8000f94: 187b adds r3, r7, r1
- 8000f96: 2203 movs r2, #3
- 8000f98: 60da str r2, [r3, #12]
+ 8000fa4: 187b adds r3, r7, r1
+ 8000fa6: 2203 movs r2, #3
+ 8000fa8: 60da str r2, [r3, #12]
GPIO_InitStruct.Alternate = GPIO_AF4_USART2;
- 8000f9a: 187b adds r3, r7, r1
- 8000f9c: 2204 movs r2, #4
- 8000f9e: 611a str r2, [r3, #16]
+ 8000faa: 187b adds r3, r7, r1
+ 8000fac: 2204 movs r2, #4
+ 8000fae: 611a str r2, [r3, #16]
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
- 8000fa0: 187a adds r2, r7, r1
- 8000fa2: 23a0 movs r3, #160 ; 0xa0
- 8000fa4: 05db lsls r3, r3, #23
- 8000fa6: 0011 movs r1, r2
- 8000fa8: 0018 movs r0, r3
- 8000faa: f000 f997 bl 80012dc <HAL_GPIO_Init>
+ 8000fb0: 187a adds r2, r7, r1
+ 8000fb2: 23a0 movs r3, #160 ; 0xa0
+ 8000fb4: 05db lsls r3, r3, #23
+ 8000fb6: 0011 movs r1, r2
+ 8000fb8: 0018 movs r0, r3
+ 8000fba: f000 f997 bl 80012ec <HAL_GPIO_Init>
/* USER CODE BEGIN USART2_MspInit 1 */
/* USER CODE END USART2_MspInit 1 */
}
}
- 8000fae: 46c0 nop ; (mov r8, r8)
- 8000fb0: 46bd mov sp, r7
- 8000fb2: b009 add sp, #36 ; 0x24
- 8000fb4: bd90 pop {r4, r7, pc}
- 8000fb6: 46c0 nop ; (mov r8, r8)
- 8000fb8: 40004400 .word 0x40004400
- 8000fbc: 40021000 .word 0x40021000
+ 8000fbe: 46c0 nop ; (mov r8, r8)
+ 8000fc0: 46bd mov sp, r7
+ 8000fc2: b009 add sp, #36 ; 0x24
+ 8000fc4: bd90 pop {r4, r7, pc}
+ 8000fc6: 46c0 nop ; (mov r8, r8)
+ 8000fc8: 40004400 .word 0x40004400
+ 8000fcc: 40021000 .word 0x40021000
-08000fc0 <NMI_Handler>:
+08000fd0 <NMI_Handler>:
/******************************************************************************/
/**
* @brief This function handles Non maskable Interrupt.
*/
void NMI_Handler(void)
{
- 8000fc0: b580 push {r7, lr}
- 8000fc2: af00 add r7, sp, #0
+ 8000fd0: b580 push {r7, lr}
+ 8000fd2: af00 add r7, sp, #0
/* USER CODE BEGIN NonMaskableInt_IRQn 0 */
/* USER CODE END NonMaskableInt_IRQn 0 */
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
while (1)
- 8000fc4: e7fe b.n 8000fc4 <NMI_Handler+0x4>
+ 8000fd4: e7fe b.n 8000fd4 <NMI_Handler+0x4>
-08000fc6 <HardFault_Handler>:
+08000fd6 <HardFault_Handler>:
/**
* @brief This function handles Hard fault interrupt.
*/
void HardFault_Handler(void)
{
- 8000fc6: b580 push {r7, lr}
- 8000fc8: af00 add r7, sp, #0
+ 8000fd6: b580 push {r7, lr}
+ 8000fd8: af00 add r7, sp, #0
/* USER CODE BEGIN HardFault_IRQn 0 */
/* USER CODE END HardFault_IRQn 0 */
while (1)
- 8000fca: e7fe b.n 8000fca <HardFault_Handler+0x4>
+ 8000fda: e7fe b.n 8000fda <HardFault_Handler+0x4>
-08000fcc <SVC_Handler>:
+08000fdc <SVC_Handler>:
/**
* @brief This function handles System service call via SWI instruction.
*/
void SVC_Handler(void)
{
- 8000fcc: b580 push {r7, lr}
- 8000fce: af00 add r7, sp, #0
+ 8000fdc: b580 push {r7, lr}
+ 8000fde: af00 add r7, sp, #0
/* USER CODE END SVC_IRQn 0 */
/* USER CODE BEGIN SVC_IRQn 1 */
/* USER CODE END SVC_IRQn 1 */
}
- 8000fd0: 46c0 nop ; (mov r8, r8)
- 8000fd2: 46bd mov sp, r7
- 8000fd4: bd80 pop {r7, pc}
+ 8000fe0: 46c0 nop ; (mov r8, r8)
+ 8000fe2: 46bd mov sp, r7
+ 8000fe4: bd80 pop {r7, pc}
-08000fd6 <PendSV_Handler>:
+08000fe6 <PendSV_Handler>:
/**
* @brief This function handles Pendable request for system service.
*/
void PendSV_Handler(void)
{
- 8000fd6: b580 push {r7, lr}
- 8000fd8: af00 add r7, sp, #0
+ 8000fe6: b580 push {r7, lr}
+ 8000fe8: af00 add r7, sp, #0
/* USER CODE END PendSV_IRQn 0 */
/* USER CODE BEGIN PendSV_IRQn 1 */
/* USER CODE END PendSV_IRQn 1 */
}
- 8000fda: 46c0 nop ; (mov r8, r8)
- 8000fdc: 46bd mov sp, r7
- 8000fde: bd80 pop {r7, pc}
+ 8000fea: 46c0 nop ; (mov r8, r8)
+ 8000fec: 46bd mov sp, r7
+ 8000fee: bd80 pop {r7, pc}
-08000fe0 <SysTick_Handler>:
+08000ff0 <SysTick_Handler>:
/**
* @brief This function handles System tick timer.
*/
void SysTick_Handler(void)
{
- 8000fe0: b580 push {r7, lr}
- 8000fe2: af00 add r7, sp, #0
+ 8000ff0: b580 push {r7, lr}
+ 8000ff2: af00 add r7, sp, #0
/* USER CODE BEGIN SysTick_IRQn 0 */
/* USER CODE END SysTick_IRQn 0 */
HAL_IncTick();
- 8000fe4: f000 f886 bl 80010f4 <HAL_IncTick>
+ 8000ff4: f000 f886 bl 8001104 <HAL_IncTick>
/* USER CODE BEGIN SysTick_IRQn 1 */
/* USER CODE END SysTick_IRQn 1 */
}
- 8000fe8: 46c0 nop ; (mov r8, r8)
- 8000fea: 46bd mov sp, r7
- 8000fec: bd80 pop {r7, pc}
+ 8000ff8: 46c0 nop ; (mov r8, r8)
+ 8000ffa: 46bd mov sp, r7
+ 8000ffc: bd80 pop {r7, pc}
-08000fee <SystemInit>:
+08000ffe <SystemInit>:
* @brief Setup the microcontroller system.
* @param None
* @retval None
*/
void SystemInit (void)
{
- 8000fee: b580 push {r7, lr}
- 8000ff0: af00 add r7, sp, #0
+ 8000ffe: b580 push {r7, lr}
+ 8001000: af00 add r7, sp, #0
/* Configure the Vector Table location add offset address ------------------*/
#if defined (USER_VECT_TAB_ADDRESS)
SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
#endif /* USER_VECT_TAB_ADDRESS */
}
- 8000ff2: 46c0 nop ; (mov r8, r8)
- 8000ff4: 46bd mov sp, r7
- 8000ff6: bd80 pop {r7, pc}
+ 8001002: 46c0 nop ; (mov r8, r8)
+ 8001004: 46bd mov sp, r7
+ 8001006: bd80 pop {r7, pc}
-08000ff8 <Reset_Handler>:
+08001008 <Reset_Handler>:
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr r0, =_estack
- 8000ff8: 480d ldr r0, [pc, #52] ; (8001030 <LoopForever+0x2>)
+ 8001008: 480d ldr r0, [pc, #52] ; (8001040 <LoopForever+0x2>)
mov sp, r0 /* set stack pointer */
- 8000ffa: 4685 mov sp, r0
+ 800100a: 4685 mov sp, r0
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
- 8000ffc: 480d ldr r0, [pc, #52] ; (8001034 <LoopForever+0x6>)
+ 800100c: 480d ldr r0, [pc, #52] ; (8001044 <LoopForever+0x6>)
ldr r1, =_edata
- 8000ffe: 490e ldr r1, [pc, #56] ; (8001038 <LoopForever+0xa>)
+ 800100e: 490e ldr r1, [pc, #56] ; (8001048 <LoopForever+0xa>)
ldr r2, =_sidata
- 8001000: 4a0e ldr r2, [pc, #56] ; (800103c <LoopForever+0xe>)
+ 8001010: 4a0e ldr r2, [pc, #56] ; (800104c <LoopForever+0xe>)
movs r3, #0
- 8001002: 2300 movs r3, #0
+ 8001012: 2300 movs r3, #0
b LoopCopyDataInit
- 8001004: e002 b.n 800100c <LoopCopyDataInit>
+ 8001014: e002 b.n 800101c <LoopCopyDataInit>
-08001006 <CopyDataInit>:
+08001016 <CopyDataInit>:
CopyDataInit:
ldr r4, [r2, r3]
- 8001006: 58d4 ldr r4, [r2, r3]
+ 8001016: 58d4 ldr r4, [r2, r3]
str r4, [r0, r3]
- 8001008: 50c4 str r4, [r0, r3]
+ 8001018: 50c4 str r4, [r0, r3]
adds r3, r3, #4
- 800100a: 3304 adds r3, #4
+ 800101a: 3304 adds r3, #4
-0800100c <LoopCopyDataInit>:
+0800101c <LoopCopyDataInit>:
LoopCopyDataInit:
adds r4, r0, r3
- 800100c: 18c4 adds r4, r0, r3
+ 800101c: 18c4 adds r4, r0, r3
cmp r4, r1
- 800100e: 428c cmp r4, r1
+ 800101e: 428c cmp r4, r1
bcc CopyDataInit
- 8001010: d3f9 bcc.n 8001006 <CopyDataInit>
+ 8001020: d3f9 bcc.n 8001016 <CopyDataInit>
/* Zero fill the bss segment. */
ldr r2, =_sbss
- 8001012: 4a0b ldr r2, [pc, #44] ; (8001040 <LoopForever+0x12>)
+ 8001022: 4a0b ldr r2, [pc, #44] ; (8001050 <LoopForever+0x12>)
ldr r4, =_ebss
- 8001014: 4c0b ldr r4, [pc, #44] ; (8001044 <LoopForever+0x16>)
+ 8001024: 4c0b ldr r4, [pc, #44] ; (8001054 <LoopForever+0x16>)
movs r3, #0
- 8001016: 2300 movs r3, #0
+ 8001026: 2300 movs r3, #0
b LoopFillZerobss
- 8001018: e001 b.n 800101e <LoopFillZerobss>
+ 8001028: e001 b.n 800102e <LoopFillZerobss>
-0800101a <FillZerobss>:
+0800102a <FillZerobss>:
FillZerobss:
str r3, [r2]
- 800101a: 6013 str r3, [r2, #0]
+ 800102a: 6013 str r3, [r2, #0]
adds r2, r2, #4
- 800101c: 3204 adds r2, #4
+ 800102c: 3204 adds r2, #4
-0800101e <LoopFillZerobss>:
+0800102e <LoopFillZerobss>:
LoopFillZerobss:
cmp r2, r4
- 800101e: 42a2 cmp r2, r4
+ 800102e: 42a2 cmp r2, r4
bcc FillZerobss
- 8001020: d3fb bcc.n 800101a <FillZerobss>
+ 8001030: d3fb bcc.n 800102a <FillZerobss>
/* Call the clock system intitialization function.*/
bl SystemInit
- 8001022: f7ff ffe4 bl 8000fee <SystemInit>
+ 8001032: f7ff ffe4 bl 8000ffe <SystemInit>
/* Call static constructors */
bl __libc_init_array
- 8001026: f003 f957 bl 80042d8 <__libc_init_array>
+ 8001036: f003 f957 bl 80042e8 <__libc_init_array>
/* Call the application's entry point.*/
bl main
- 800102a: f7ff fad7 bl 80005dc <main>
+ 800103a: f7ff fad7 bl 80005ec <main>
-0800102e <LoopForever>:
+0800103e <LoopForever>:
LoopForever:
b LoopForever
- 800102e: e7fe b.n 800102e <LoopForever>
+ 800103e: e7fe b.n 800103e <LoopForever>
ldr r0, =_estack
- 8001030: 20002000 .word 0x20002000
+ 8001040: 20002000 .word 0x20002000
ldr r0, =_sdata
- 8001034: 20000000 .word 0x20000000
+ 8001044: 20000000 .word 0x20000000
ldr r1, =_edata
- 8001038: 2000000c .word 0x2000000c
+ 8001048: 2000000c .word 0x2000000c
ldr r2, =_sidata
- 800103c: 080043c4 .word 0x080043c4
+ 800104c: 080043d4 .word 0x080043d4
ldr r2, =_sbss
- 8001040: 2000000c .word 0x2000000c
+ 8001050: 2000000c .word 0x2000000c
ldr r4, =_ebss
- 8001044: 20000210 .word 0x20000210
+ 8001054: 20000210 .word 0x20000210
-08001048 <ADC1_COMP_IRQHandler>:
+08001058 <ADC1_COMP_IRQHandler>:
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
- 8001048: e7fe b.n 8001048 <ADC1_COMP_IRQHandler>
+ 8001058: e7fe b.n 8001058 <ADC1_COMP_IRQHandler>
...
-0800104c <HAL_Init>:
+0800105c <HAL_Init>:
* In the default implementation,Systick is used as source of time base.
* the tick variable is incremented each 1ms in its ISR.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_Init(void)
{
- 800104c: b580 push {r7, lr}
- 800104e: b082 sub sp, #8
- 8001050: af00 add r7, sp, #0
+ 800105c: b580 push {r7, lr}
+ 800105e: b082 sub sp, #8
+ 8001060: af00 add r7, sp, #0
HAL_StatusTypeDef status = HAL_OK;
- 8001052: 1dfb adds r3, r7, #7
- 8001054: 2200 movs r2, #0
- 8001056: 701a strb r2, [r3, #0]
+ 8001062: 1dfb adds r3, r7, #7
+ 8001064: 2200 movs r2, #0
+ 8001066: 701a strb r2, [r3, #0]
#if (BUFFER_CACHE_DISABLE != 0)
__HAL_FLASH_BUFFER_CACHE_DISABLE();
#endif /* BUFFER_CACHE_DISABLE */
#if (PREREAD_ENABLE != 0)
__HAL_FLASH_PREREAD_BUFFER_ENABLE();
- 8001058: 4b0b ldr r3, [pc, #44] ; (8001088 <HAL_Init+0x3c>)
- 800105a: 681a ldr r2, [r3, #0]
- 800105c: 4b0a ldr r3, [pc, #40] ; (8001088 <HAL_Init+0x3c>)
- 800105e: 2140 movs r1, #64 ; 0x40
- 8001060: 430a orrs r2, r1
- 8001062: 601a str r2, [r3, #0]
+ 8001068: 4b0b ldr r3, [pc, #44] ; (8001098 <HAL_Init+0x3c>)
+ 800106a: 681a ldr r2, [r3, #0]
+ 800106c: 4b0a ldr r3, [pc, #40] ; (8001098 <HAL_Init+0x3c>)
+ 800106e: 2140 movs r1, #64 ; 0x40
+ 8001070: 430a orrs r2, r1
+ 8001072: 601a str r2, [r3, #0]
#if (PREFETCH_ENABLE != 0)
__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
#endif /* PREFETCH_ENABLE */
/* Use SysTick as time base source and configure 1ms tick (default clock after Reset is MSI) */
if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK)
- 8001064: 2003 movs r0, #3
- 8001066: f000 f811 bl 800108c <HAL_InitTick>
- 800106a: 1e03 subs r3, r0, #0
- 800106c: d003 beq.n 8001076 <HAL_Init+0x2a>
+ 8001074: 2003 movs r0, #3
+ 8001076: f000 f811 bl 800109c <HAL_InitTick>
+ 800107a: 1e03 subs r3, r0, #0
+ 800107c: d003 beq.n 8001086 <HAL_Init+0x2a>
{
status = HAL_ERROR;
- 800106e: 1dfb adds r3, r7, #7
- 8001070: 2201 movs r2, #1
- 8001072: 701a strb r2, [r3, #0]
- 8001074: e001 b.n 800107a <HAL_Init+0x2e>
+ 800107e: 1dfb adds r3, r7, #7
+ 8001080: 2201 movs r2, #1
+ 8001082: 701a strb r2, [r3, #0]
+ 8001084: e001 b.n 800108a <HAL_Init+0x2e>
}
else
{
/* Init the low level hardware */
HAL_MspInit();
- 8001076: f7ff fe6f bl 8000d58 <HAL_MspInit>
+ 8001086: f7ff fe6f bl 8000d68 <HAL_MspInit>
}
/* Return function status */
return status;
- 800107a: 1dfb adds r3, r7, #7
- 800107c: 781b ldrb r3, [r3, #0]
+ 800108a: 1dfb adds r3, r7, #7
+ 800108c: 781b ldrb r3, [r3, #0]
}
- 800107e: 0018 movs r0, r3
- 8001080: 46bd mov sp, r7
- 8001082: b002 add sp, #8
- 8001084: bd80 pop {r7, pc}
- 8001086: 46c0 nop ; (mov r8, r8)
- 8001088: 40022000 .word 0x40022000
+ 800108e: 0018 movs r0, r3
+ 8001090: 46bd mov sp, r7
+ 8001092: b002 add sp, #8
+ 8001094: bd80 pop {r7, pc}
+ 8001096: 46c0 nop ; (mov r8, r8)
+ 8001098: 40022000 .word 0x40022000
-0800108c <HAL_InitTick>:
+0800109c <HAL_InitTick>:
* implementation in user file.
* @param TickPriority Tick interrupt priority.
* @retval HAL status
*/
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{
- 800108c: b590 push {r4, r7, lr}
- 800108e: b083 sub sp, #12
- 8001090: af00 add r7, sp, #0
- 8001092: 6078 str r0, [r7, #4]
+ 800109c: b590 push {r4, r7, lr}
+ 800109e: b083 sub sp, #12
+ 80010a0: af00 add r7, sp, #0
+ 80010a2: 6078 str r0, [r7, #4]
/* Configure the SysTick to have interrupt in 1ms time basis*/
if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U)
- 8001094: 4b14 ldr r3, [pc, #80] ; (80010e8 <HAL_InitTick+0x5c>)
- 8001096: 681c ldr r4, [r3, #0]
- 8001098: 4b14 ldr r3, [pc, #80] ; (80010ec <HAL_InitTick+0x60>)
- 800109a: 781b ldrb r3, [r3, #0]
- 800109c: 0019 movs r1, r3
- 800109e: 23fa movs r3, #250 ; 0xfa
- 80010a0: 0098 lsls r0, r3, #2
- 80010a2: f7ff f831 bl 8000108 <__udivsi3>
- 80010a6: 0003 movs r3, r0
- 80010a8: 0019 movs r1, r3
- 80010aa: 0020 movs r0, r4
- 80010ac: f7ff f82c bl 8000108 <__udivsi3>
- 80010b0: 0003 movs r3, r0
- 80010b2: 0018 movs r0, r3
- 80010b4: f000 f905 bl 80012c2 <HAL_SYSTICK_Config>
- 80010b8: 1e03 subs r3, r0, #0
- 80010ba: d001 beq.n 80010c0 <HAL_InitTick+0x34>
+ 80010a4: 4b14 ldr r3, [pc, #80] ; (80010f8 <HAL_InitTick+0x5c>)
+ 80010a6: 681c ldr r4, [r3, #0]
+ 80010a8: 4b14 ldr r3, [pc, #80] ; (80010fc <HAL_InitTick+0x60>)
+ 80010aa: 781b ldrb r3, [r3, #0]
+ 80010ac: 0019 movs r1, r3
+ 80010ae: 23fa movs r3, #250 ; 0xfa
+ 80010b0: 0098 lsls r0, r3, #2
+ 80010b2: f7ff f829 bl 8000108 <__udivsi3>
+ 80010b6: 0003 movs r3, r0
+ 80010b8: 0019 movs r1, r3
+ 80010ba: 0020 movs r0, r4
+ 80010bc: f7ff f824 bl 8000108 <__udivsi3>
+ 80010c0: 0003 movs r3, r0
+ 80010c2: 0018 movs r0, r3
+ 80010c4: f000 f905 bl 80012d2 <HAL_SYSTICK_Config>
+ 80010c8: 1e03 subs r3, r0, #0
+ 80010ca: d001 beq.n 80010d0 <HAL_InitTick+0x34>
{
return HAL_ERROR;
- 80010bc: 2301 movs r3, #1
- 80010be: e00f b.n 80010e0 <HAL_InitTick+0x54>
+ 80010cc: 2301 movs r3, #1
+ 80010ce: e00f b.n 80010f0 <HAL_InitTick+0x54>
}
/* Configure the SysTick IRQ priority */
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
- 80010c0: 687b ldr r3, [r7, #4]
- 80010c2: 2b03 cmp r3, #3
- 80010c4: d80b bhi.n 80010de <HAL_InitTick+0x52>
+ 80010d0: 687b ldr r3, [r7, #4]
+ 80010d2: 2b03 cmp r3, #3
+ 80010d4: d80b bhi.n 80010ee <HAL_InitTick+0x52>
{
HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
- 80010c6: 6879 ldr r1, [r7, #4]
- 80010c8: 2301 movs r3, #1
- 80010ca: 425b negs r3, r3
- 80010cc: 2200 movs r2, #0
- 80010ce: 0018 movs r0, r3
- 80010d0: f000 f8e2 bl 8001298 <HAL_NVIC_SetPriority>
+ 80010d6: 6879 ldr r1, [r7, #4]
+ 80010d8: 2301 movs r3, #1
+ 80010da: 425b negs r3, r3
+ 80010dc: 2200 movs r2, #0
+ 80010de: 0018 movs r0, r3
+ 80010e0: f000 f8e2 bl 80012a8 <HAL_NVIC_SetPriority>
uwTickPrio = TickPriority;
- 80010d4: 4b06 ldr r3, [pc, #24] ; (80010f0 <HAL_InitTick+0x64>)
- 80010d6: 687a ldr r2, [r7, #4]
- 80010d8: 601a str r2, [r3, #0]
+ 80010e4: 4b06 ldr r3, [pc, #24] ; (8001100 <HAL_InitTick+0x64>)
+ 80010e6: 687a ldr r2, [r7, #4]
+ 80010e8: 601a str r2, [r3, #0]
{
return HAL_ERROR;
}
/* Return function status */
return HAL_OK;
- 80010da: 2300 movs r3, #0
- 80010dc: e000 b.n 80010e0 <HAL_InitTick+0x54>
+ 80010ea: 2300 movs r3, #0
+ 80010ec: e000 b.n 80010f0 <HAL_InitTick+0x54>
return HAL_ERROR;
- 80010de: 2301 movs r3, #1
+ 80010ee: 2301 movs r3, #1
}
- 80010e0: 0018 movs r0, r3
- 80010e2: 46bd mov sp, r7
- 80010e4: b003 add sp, #12
- 80010e6: bd90 pop {r4, r7, pc}
- 80010e8: 20000000 .word 0x20000000
- 80010ec: 20000008 .word 0x20000008
- 80010f0: 20000004 .word 0x20000004
+ 80010f0: 0018 movs r0, r3
+ 80010f2: 46bd mov sp, r7
+ 80010f4: b003 add sp, #12
+ 80010f6: bd90 pop {r4, r7, pc}
+ 80010f8: 20000000 .word 0x20000000
+ 80010fc: 20000008 .word 0x20000008
+ 8001100: 20000004 .word 0x20000004
-080010f4 <HAL_IncTick>:
+08001104 <HAL_IncTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval None
*/
__weak void HAL_IncTick(void)
{
- 80010f4: b580 push {r7, lr}
- 80010f6: af00 add r7, sp, #0
+ 8001104: b580 push {r7, lr}
+ 8001106: af00 add r7, sp, #0
uwTick += uwTickFreq;
- 80010f8: 4b05 ldr r3, [pc, #20] ; (8001110 <HAL_IncTick+0x1c>)
- 80010fa: 781b ldrb r3, [r3, #0]
- 80010fc: 001a movs r2, r3
- 80010fe: 4b05 ldr r3, [pc, #20] ; (8001114 <HAL_IncTick+0x20>)
- 8001100: 681b ldr r3, [r3, #0]
- 8001102: 18d2 adds r2, r2, r3
- 8001104: 4b03 ldr r3, [pc, #12] ; (8001114 <HAL_IncTick+0x20>)
- 8001106: 601a str r2, [r3, #0]
+ 8001108: 4b05 ldr r3, [pc, #20] ; (8001120 <HAL_IncTick+0x1c>)
+ 800110a: 781b ldrb r3, [r3, #0]
+ 800110c: 001a movs r2, r3
+ 800110e: 4b05 ldr r3, [pc, #20] ; (8001124 <HAL_IncTick+0x20>)
+ 8001110: 681b ldr r3, [r3, #0]
+ 8001112: 18d2 adds r2, r2, r3
+ 8001114: 4b03 ldr r3, [pc, #12] ; (8001124 <HAL_IncTick+0x20>)
+ 8001116: 601a str r2, [r3, #0]
}
- 8001108: 46c0 nop ; (mov r8, r8)
- 800110a: 46bd mov sp, r7
- 800110c: bd80 pop {r7, pc}
- 800110e: 46c0 nop ; (mov r8, r8)
- 8001110: 20000008 .word 0x20000008
- 8001114: 2000020c .word 0x2000020c
+ 8001118: 46c0 nop ; (mov r8, r8)
+ 800111a: 46bd mov sp, r7
+ 800111c: bd80 pop {r7, pc}
+ 800111e: 46c0 nop ; (mov r8, r8)
+ 8001120: 20000008 .word 0x20000008
+ 8001124: 2000020c .word 0x2000020c
-08001118 <HAL_GetTick>:
+08001128 <HAL_GetTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval tick value
*/
__weak uint32_t HAL_GetTick(void)
{
- 8001118: b580 push {r7, lr}
- 800111a: af00 add r7, sp, #0
+ 8001128: b580 push {r7, lr}
+ 800112a: af00 add r7, sp, #0
return uwTick;
- 800111c: 4b02 ldr r3, [pc, #8] ; (8001128 <HAL_GetTick+0x10>)
- 800111e: 681b ldr r3, [r3, #0]
+ 800112c: 4b02 ldr r3, [pc, #8] ; (8001138 <HAL_GetTick+0x10>)
+ 800112e: 681b ldr r3, [r3, #0]
}
- 8001120: 0018 movs r0, r3
- 8001122: 46bd mov sp, r7
- 8001124: bd80 pop {r7, pc}
- 8001126: 46c0 nop ; (mov r8, r8)
- 8001128: 2000020c .word 0x2000020c
+ 8001130: 0018 movs r0, r3
+ 8001132: 46bd mov sp, r7
+ 8001134: bd80 pop {r7, pc}
+ 8001136: 46c0 nop ; (mov r8, r8)
+ 8001138: 2000020c .word 0x2000020c
-0800112c <HAL_Delay>:
+0800113c <HAL_Delay>:
* implementations in user file.
* @param Delay specifies the delay time length, in milliseconds.
* @retval None
*/
__weak void HAL_Delay(uint32_t Delay)
{
- 800112c: b580 push {r7, lr}
- 800112e: b084 sub sp, #16
- 8001130: af00 add r7, sp, #0
- 8001132: 6078 str r0, [r7, #4]
+ 800113c: b580 push {r7, lr}
+ 800113e: b084 sub sp, #16
+ 8001140: af00 add r7, sp, #0
+ 8001142: 6078 str r0, [r7, #4]
uint32_t tickstart = HAL_GetTick();
- 8001134: f7ff fff0 bl 8001118 <HAL_GetTick>
- 8001138: 0003 movs r3, r0
- 800113a: 60bb str r3, [r7, #8]
+ 8001144: f7ff fff0 bl 8001128 <HAL_GetTick>
+ 8001148: 0003 movs r3, r0
+ 800114a: 60bb str r3, [r7, #8]
uint32_t wait = Delay;
- 800113c: 687b ldr r3, [r7, #4]
- 800113e: 60fb str r3, [r7, #12]
+ 800114c: 687b ldr r3, [r7, #4]
+ 800114e: 60fb str r3, [r7, #12]
/* Add a freq to guarantee minimum wait */
if (wait < HAL_MAX_DELAY)
- 8001140: 68fb ldr r3, [r7, #12]
- 8001142: 3301 adds r3, #1
- 8001144: d005 beq.n 8001152 <HAL_Delay+0x26>
+ 8001150: 68fb ldr r3, [r7, #12]
+ 8001152: 3301 adds r3, #1
+ 8001154: d005 beq.n 8001162 <HAL_Delay+0x26>
{
wait += (uint32_t)(uwTickFreq);
- 8001146: 4b0a ldr r3, [pc, #40] ; (8001170 <HAL_Delay+0x44>)
- 8001148: 781b ldrb r3, [r3, #0]
- 800114a: 001a movs r2, r3
- 800114c: 68fb ldr r3, [r7, #12]
- 800114e: 189b adds r3, r3, r2
- 8001150: 60fb str r3, [r7, #12]
+ 8001156: 4b0a ldr r3, [pc, #40] ; (8001180 <HAL_Delay+0x44>)
+ 8001158: 781b ldrb r3, [r3, #0]
+ 800115a: 001a movs r2, r3
+ 800115c: 68fb ldr r3, [r7, #12]
+ 800115e: 189b adds r3, r3, r2
+ 8001160: 60fb str r3, [r7, #12]
}
while((HAL_GetTick() - tickstart) < wait)
- 8001152: 46c0 nop ; (mov r8, r8)
- 8001154: f7ff ffe0 bl 8001118 <HAL_GetTick>
- 8001158: 0002 movs r2, r0
- 800115a: 68bb ldr r3, [r7, #8]
- 800115c: 1ad3 subs r3, r2, r3
- 800115e: 68fa ldr r2, [r7, #12]
- 8001160: 429a cmp r2, r3
- 8001162: d8f7 bhi.n 8001154 <HAL_Delay+0x28>
+ 8001162: 46c0 nop ; (mov r8, r8)
+ 8001164: f7ff ffe0 bl 8001128 <HAL_GetTick>
+ 8001168: 0002 movs r2, r0
+ 800116a: 68bb ldr r3, [r7, #8]
+ 800116c: 1ad3 subs r3, r2, r3
+ 800116e: 68fa ldr r2, [r7, #12]
+ 8001170: 429a cmp r2, r3
+ 8001172: d8f7 bhi.n 8001164 <HAL_Delay+0x28>
{
}
}
- 8001164: 46c0 nop ; (mov r8, r8)
- 8001166: 46c0 nop ; (mov r8, r8)
- 8001168: 46bd mov sp, r7
- 800116a: b004 add sp, #16
- 800116c: bd80 pop {r7, pc}
- 800116e: 46c0 nop ; (mov r8, r8)
- 8001170: 20000008 .word 0x20000008
+ 8001174: 46c0 nop ; (mov r8, r8)
+ 8001176: 46c0 nop ; (mov r8, r8)
+ 8001178: 46bd mov sp, r7
+ 800117a: b004 add sp, #16
+ 800117c: bd80 pop {r7, pc}
+ 800117e: 46c0 nop ; (mov r8, r8)
+ 8001180: 20000008 .word 0x20000008
-08001174 <__NVIC_SetPriority>:
+08001184 <__NVIC_SetPriority>:
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
- 8001174: b590 push {r4, r7, lr}
- 8001176: b083 sub sp, #12
- 8001178: af00 add r7, sp, #0
- 800117a: 0002 movs r2, r0
- 800117c: 6039 str r1, [r7, #0]
- 800117e: 1dfb adds r3, r7, #7
- 8001180: 701a strb r2, [r3, #0]
+ 8001184: b590 push {r4, r7, lr}
+ 8001186: b083 sub sp, #12
+ 8001188: af00 add r7, sp, #0
+ 800118a: 0002 movs r2, r0
+ 800118c: 6039 str r1, [r7, #0]
+ 800118e: 1dfb adds r3, r7, #7
+ 8001190: 701a strb r2, [r3, #0]
if ((int32_t)(IRQn) >= 0)
- 8001182: 1dfb adds r3, r7, #7
- 8001184: 781b ldrb r3, [r3, #0]
- 8001186: 2b7f cmp r3, #127 ; 0x7f
- 8001188: d828 bhi.n 80011dc <__NVIC_SetPriority+0x68>
+ 8001192: 1dfb adds r3, r7, #7
+ 8001194: 781b ldrb r3, [r3, #0]
+ 8001196: 2b7f cmp r3, #127 ; 0x7f
+ 8001198: d828 bhi.n 80011ec <__NVIC_SetPriority+0x68>
{
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
- 800118a: 4a2f ldr r2, [pc, #188] ; (8001248 <__NVIC_SetPriority+0xd4>)
- 800118c: 1dfb adds r3, r7, #7
- 800118e: 781b ldrb r3, [r3, #0]
- 8001190: b25b sxtb r3, r3
- 8001192: 089b lsrs r3, r3, #2
- 8001194: 33c0 adds r3, #192 ; 0xc0
- 8001196: 009b lsls r3, r3, #2
- 8001198: 589b ldr r3, [r3, r2]
- 800119a: 1dfa adds r2, r7, #7
- 800119c: 7812 ldrb r2, [r2, #0]
- 800119e: 0011 movs r1, r2
- 80011a0: 2203 movs r2, #3
- 80011a2: 400a ands r2, r1
- 80011a4: 00d2 lsls r2, r2, #3
- 80011a6: 21ff movs r1, #255 ; 0xff
- 80011a8: 4091 lsls r1, r2
- 80011aa: 000a movs r2, r1
- 80011ac: 43d2 mvns r2, r2
- 80011ae: 401a ands r2, r3
- 80011b0: 0011 movs r1, r2
+ 800119a: 4a2f ldr r2, [pc, #188] ; (8001258 <__NVIC_SetPriority+0xd4>)
+ 800119c: 1dfb adds r3, r7, #7
+ 800119e: 781b ldrb r3, [r3, #0]
+ 80011a0: b25b sxtb r3, r3
+ 80011a2: 089b lsrs r3, r3, #2
+ 80011a4: 33c0 adds r3, #192 ; 0xc0
+ 80011a6: 009b lsls r3, r3, #2
+ 80011a8: 589b ldr r3, [r3, r2]
+ 80011aa: 1dfa adds r2, r7, #7
+ 80011ac: 7812 ldrb r2, [r2, #0]
+ 80011ae: 0011 movs r1, r2
+ 80011b0: 2203 movs r2, #3
+ 80011b2: 400a ands r2, r1
+ 80011b4: 00d2 lsls r2, r2, #3
+ 80011b6: 21ff movs r1, #255 ; 0xff
+ 80011b8: 4091 lsls r1, r2
+ 80011ba: 000a movs r2, r1
+ 80011bc: 43d2 mvns r2, r2
+ 80011be: 401a ands r2, r3
+ 80011c0: 0011 movs r1, r2
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
- 80011b2: 683b ldr r3, [r7, #0]
- 80011b4: 019b lsls r3, r3, #6
- 80011b6: 22ff movs r2, #255 ; 0xff
- 80011b8: 401a ands r2, r3
- 80011ba: 1dfb adds r3, r7, #7
- 80011bc: 781b ldrb r3, [r3, #0]
- 80011be: 0018 movs r0, r3
- 80011c0: 2303 movs r3, #3
- 80011c2: 4003 ands r3, r0
- 80011c4: 00db lsls r3, r3, #3
- 80011c6: 409a lsls r2, r3
- NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
- 80011c8: 481f ldr r0, [pc, #124] ; (8001248 <__NVIC_SetPriority+0xd4>)
+ 80011c2: 683b ldr r3, [r7, #0]
+ 80011c4: 019b lsls r3, r3, #6
+ 80011c6: 22ff movs r2, #255 ; 0xff
+ 80011c8: 401a ands r2, r3
80011ca: 1dfb adds r3, r7, #7
80011cc: 781b ldrb r3, [r3, #0]
- 80011ce: b25b sxtb r3, r3
- 80011d0: 089b lsrs r3, r3, #2
- 80011d2: 430a orrs r2, r1
- 80011d4: 33c0 adds r3, #192 ; 0xc0
- 80011d6: 009b lsls r3, r3, #2
- 80011d8: 501a str r2, [r3, r0]
+ 80011ce: 0018 movs r0, r3
+ 80011d0: 2303 movs r3, #3
+ 80011d2: 4003 ands r3, r0
+ 80011d4: 00db lsls r3, r3, #3
+ 80011d6: 409a lsls r2, r3
+ NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ 80011d8: 481f ldr r0, [pc, #124] ; (8001258 <__NVIC_SetPriority+0xd4>)
+ 80011da: 1dfb adds r3, r7, #7
+ 80011dc: 781b ldrb r3, [r3, #0]
+ 80011de: b25b sxtb r3, r3
+ 80011e0: 089b lsrs r3, r3, #2
+ 80011e2: 430a orrs r2, r1
+ 80011e4: 33c0 adds r3, #192 ; 0xc0
+ 80011e6: 009b lsls r3, r3, #2
+ 80011e8: 501a str r2, [r3, r0]
else
{
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
}
- 80011da: e031 b.n 8001240 <__NVIC_SetPriority+0xcc>
+ 80011ea: e031 b.n 8001250 <__NVIC_SetPriority+0xcc>
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
- 80011dc: 4a1b ldr r2, [pc, #108] ; (800124c <__NVIC_SetPriority+0xd8>)
- 80011de: 1dfb adds r3, r7, #7
- 80011e0: 781b ldrb r3, [r3, #0]
- 80011e2: 0019 movs r1, r3
- 80011e4: 230f movs r3, #15
- 80011e6: 400b ands r3, r1
- 80011e8: 3b08 subs r3, #8
- 80011ea: 089b lsrs r3, r3, #2
- 80011ec: 3306 adds r3, #6
- 80011ee: 009b lsls r3, r3, #2
- 80011f0: 18d3 adds r3, r2, r3
- 80011f2: 3304 adds r3, #4
- 80011f4: 681b ldr r3, [r3, #0]
- 80011f6: 1dfa adds r2, r7, #7
- 80011f8: 7812 ldrb r2, [r2, #0]
- 80011fa: 0011 movs r1, r2
- 80011fc: 2203 movs r2, #3
- 80011fe: 400a ands r2, r1
- 8001200: 00d2 lsls r2, r2, #3
- 8001202: 21ff movs r1, #255 ; 0xff
- 8001204: 4091 lsls r1, r2
- 8001206: 000a movs r2, r1
- 8001208: 43d2 mvns r2, r2
- 800120a: 401a ands r2, r3
- 800120c: 0011 movs r1, r2
+ 80011ec: 4a1b ldr r2, [pc, #108] ; (800125c <__NVIC_SetPriority+0xd8>)
+ 80011ee: 1dfb adds r3, r7, #7
+ 80011f0: 781b ldrb r3, [r3, #0]
+ 80011f2: 0019 movs r1, r3
+ 80011f4: 230f movs r3, #15
+ 80011f6: 400b ands r3, r1
+ 80011f8: 3b08 subs r3, #8
+ 80011fa: 089b lsrs r3, r3, #2
+ 80011fc: 3306 adds r3, #6
+ 80011fe: 009b lsls r3, r3, #2
+ 8001200: 18d3 adds r3, r2, r3
+ 8001202: 3304 adds r3, #4
+ 8001204: 681b ldr r3, [r3, #0]
+ 8001206: 1dfa adds r2, r7, #7
+ 8001208: 7812 ldrb r2, [r2, #0]
+ 800120a: 0011 movs r1, r2
+ 800120c: 2203 movs r2, #3
+ 800120e: 400a ands r2, r1
+ 8001210: 00d2 lsls r2, r2, #3
+ 8001212: 21ff movs r1, #255 ; 0xff
+ 8001214: 4091 lsls r1, r2
+ 8001216: 000a movs r2, r1
+ 8001218: 43d2 mvns r2, r2
+ 800121a: 401a ands r2, r3
+ 800121c: 0011 movs r1, r2
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
- 800120e: 683b ldr r3, [r7, #0]
- 8001210: 019b lsls r3, r3, #6
- 8001212: 22ff movs r2, #255 ; 0xff
- 8001214: 401a ands r2, r3
- 8001216: 1dfb adds r3, r7, #7
- 8001218: 781b ldrb r3, [r3, #0]
- 800121a: 0018 movs r0, r3
- 800121c: 2303 movs r3, #3
- 800121e: 4003 ands r3, r0
- 8001220: 00db lsls r3, r3, #3
- 8001222: 409a lsls r2, r3
- SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
- 8001224: 4809 ldr r0, [pc, #36] ; (800124c <__NVIC_SetPriority+0xd8>)
+ 800121e: 683b ldr r3, [r7, #0]
+ 8001220: 019b lsls r3, r3, #6
+ 8001222: 22ff movs r2, #255 ; 0xff
+ 8001224: 401a ands r2, r3
8001226: 1dfb adds r3, r7, #7
8001228: 781b ldrb r3, [r3, #0]
- 800122a: 001c movs r4, r3
- 800122c: 230f movs r3, #15
- 800122e: 4023 ands r3, r4
- 8001230: 3b08 subs r3, #8
- 8001232: 089b lsrs r3, r3, #2
- 8001234: 430a orrs r2, r1
- 8001236: 3306 adds r3, #6
- 8001238: 009b lsls r3, r3, #2
- 800123a: 18c3 adds r3, r0, r3
- 800123c: 3304 adds r3, #4
- 800123e: 601a str r2, [r3, #0]
+ 800122a: 0018 movs r0, r3
+ 800122c: 2303 movs r3, #3
+ 800122e: 4003 ands r3, r0
+ 8001230: 00db lsls r3, r3, #3
+ 8001232: 409a lsls r2, r3
+ SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ 8001234: 4809 ldr r0, [pc, #36] ; (800125c <__NVIC_SetPriority+0xd8>)
+ 8001236: 1dfb adds r3, r7, #7
+ 8001238: 781b ldrb r3, [r3, #0]
+ 800123a: 001c movs r4, r3
+ 800123c: 230f movs r3, #15
+ 800123e: 4023 ands r3, r4
+ 8001240: 3b08 subs r3, #8
+ 8001242: 089b lsrs r3, r3, #2
+ 8001244: 430a orrs r2, r1
+ 8001246: 3306 adds r3, #6
+ 8001248: 009b lsls r3, r3, #2
+ 800124a: 18c3 adds r3, r0, r3
+ 800124c: 3304 adds r3, #4
+ 800124e: 601a str r2, [r3, #0]
}
- 8001240: 46c0 nop ; (mov r8, r8)
- 8001242: 46bd mov sp, r7
- 8001244: b003 add sp, #12
- 8001246: bd90 pop {r4, r7, pc}
- 8001248: e000e100 .word 0xe000e100
- 800124c: e000ed00 .word 0xe000ed00
+ 8001250: 46c0 nop ; (mov r8, r8)
+ 8001252: 46bd mov sp, r7
+ 8001254: b003 add sp, #12
+ 8001256: bd90 pop {r4, r7, pc}
+ 8001258: e000e100 .word 0xe000e100
+ 800125c: e000ed00 .word 0xe000ed00
-08001250 <SysTick_Config>:
+08001260 <SysTick_Config>:
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
- 8001250: b580 push {r7, lr}
- 8001252: b082 sub sp, #8
- 8001254: af00 add r7, sp, #0
- 8001256: 6078 str r0, [r7, #4]
+ 8001260: b580 push {r7, lr}
+ 8001262: b082 sub sp, #8
+ 8001264: af00 add r7, sp, #0
+ 8001266: 6078 str r0, [r7, #4]
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
- 8001258: 687b ldr r3, [r7, #4]
- 800125a: 1e5a subs r2, r3, #1
- 800125c: 2380 movs r3, #128 ; 0x80
- 800125e: 045b lsls r3, r3, #17
- 8001260: 429a cmp r2, r3
- 8001262: d301 bcc.n 8001268 <SysTick_Config+0x18>
+ 8001268: 687b ldr r3, [r7, #4]
+ 800126a: 1e5a subs r2, r3, #1
+ 800126c: 2380 movs r3, #128 ; 0x80
+ 800126e: 045b lsls r3, r3, #17
+ 8001270: 429a cmp r2, r3
+ 8001272: d301 bcc.n 8001278 <SysTick_Config+0x18>
{
return (1UL); /* Reload value impossible */
- 8001264: 2301 movs r3, #1
- 8001266: e010 b.n 800128a <SysTick_Config+0x3a>
+ 8001274: 2301 movs r3, #1
+ 8001276: e010 b.n 800129a <SysTick_Config+0x3a>
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
- 8001268: 4b0a ldr r3, [pc, #40] ; (8001294 <SysTick_Config+0x44>)
- 800126a: 687a ldr r2, [r7, #4]
- 800126c: 3a01 subs r2, #1
- 800126e: 605a str r2, [r3, #4]
+ 8001278: 4b0a ldr r3, [pc, #40] ; (80012a4 <SysTick_Config+0x44>)
+ 800127a: 687a ldr r2, [r7, #4]
+ 800127c: 3a01 subs r2, #1
+ 800127e: 605a str r2, [r3, #4]
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
- 8001270: 2301 movs r3, #1
- 8001272: 425b negs r3, r3
- 8001274: 2103 movs r1, #3
- 8001276: 0018 movs r0, r3
- 8001278: f7ff ff7c bl 8001174 <__NVIC_SetPriority>
+ 8001280: 2301 movs r3, #1
+ 8001282: 425b negs r3, r3
+ 8001284: 2103 movs r1, #3
+ 8001286: 0018 movs r0, r3
+ 8001288: f7ff ff7c bl 8001184 <__NVIC_SetPriority>
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
- 800127c: 4b05 ldr r3, [pc, #20] ; (8001294 <SysTick_Config+0x44>)
- 800127e: 2200 movs r2, #0
- 8001280: 609a str r2, [r3, #8]
+ 800128c: 4b05 ldr r3, [pc, #20] ; (80012a4 <SysTick_Config+0x44>)
+ 800128e: 2200 movs r2, #0
+ 8001290: 609a str r2, [r3, #8]
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
- 8001282: 4b04 ldr r3, [pc, #16] ; (8001294 <SysTick_Config+0x44>)
- 8001284: 2207 movs r2, #7
- 8001286: 601a str r2, [r3, #0]
+ 8001292: 4b04 ldr r3, [pc, #16] ; (80012a4 <SysTick_Config+0x44>)
+ 8001294: 2207 movs r2, #7
+ 8001296: 601a str r2, [r3, #0]
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
- 8001288: 2300 movs r3, #0
+ 8001298: 2300 movs r3, #0
}
- 800128a: 0018 movs r0, r3
- 800128c: 46bd mov sp, r7
- 800128e: b002 add sp, #8
- 8001290: bd80 pop {r7, pc}
- 8001292: 46c0 nop ; (mov r8, r8)
- 8001294: e000e010 .word 0xe000e010
+ 800129a: 0018 movs r0, r3
+ 800129c: 46bd mov sp, r7
+ 800129e: b002 add sp, #8
+ 80012a0: bd80 pop {r7, pc}
+ 80012a2: 46c0 nop ; (mov r8, r8)
+ 80012a4: e000e010 .word 0xe000e010
-08001298 <HAL_NVIC_SetPriority>:
+080012a8 <HAL_NVIC_SetPriority>:
* with stm32l0xx devices, this parameter is a dummy value and it is ignored, because
* no subpriority supported in Cortex M0+ based products.
* @retval None
*/
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
{
- 8001298: b580 push {r7, lr}
- 800129a: b084 sub sp, #16
- 800129c: af00 add r7, sp, #0
- 800129e: 60b9 str r1, [r7, #8]
- 80012a0: 607a str r2, [r7, #4]
- 80012a2: 210f movs r1, #15
- 80012a4: 187b adds r3, r7, r1
- 80012a6: 1c02 adds r2, r0, #0
- 80012a8: 701a strb r2, [r3, #0]
+ 80012a8: b580 push {r7, lr}
+ 80012aa: b084 sub sp, #16
+ 80012ac: af00 add r7, sp, #0
+ 80012ae: 60b9 str r1, [r7, #8]
+ 80012b0: 607a str r2, [r7, #4]
+ 80012b2: 210f movs r1, #15
+ 80012b4: 187b adds r3, r7, r1
+ 80012b6: 1c02 adds r2, r0, #0
+ 80012b8: 701a strb r2, [r3, #0]
/* Check the parameters */
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
NVIC_SetPriority(IRQn,PreemptPriority);
- 80012aa: 68ba ldr r2, [r7, #8]
- 80012ac: 187b adds r3, r7, r1
- 80012ae: 781b ldrb r3, [r3, #0]
- 80012b0: b25b sxtb r3, r3
- 80012b2: 0011 movs r1, r2
- 80012b4: 0018 movs r0, r3
- 80012b6: f7ff ff5d bl 8001174 <__NVIC_SetPriority>
+ 80012ba: 68ba ldr r2, [r7, #8]
+ 80012bc: 187b adds r3, r7, r1
+ 80012be: 781b ldrb r3, [r3, #0]
+ 80012c0: b25b sxtb r3, r3
+ 80012c2: 0011 movs r1, r2
+ 80012c4: 0018 movs r0, r3
+ 80012c6: f7ff ff5d bl 8001184 <__NVIC_SetPriority>
}
- 80012ba: 46c0 nop ; (mov r8, r8)
- 80012bc: 46bd mov sp, r7
- 80012be: b004 add sp, #16
- 80012c0: bd80 pop {r7, pc}
+ 80012ca: 46c0 nop ; (mov r8, r8)
+ 80012cc: 46bd mov sp, r7
+ 80012ce: b004 add sp, #16
+ 80012d0: bd80 pop {r7, pc}
-080012c2 <HAL_SYSTICK_Config>:
+080012d2 <HAL_SYSTICK_Config>:
* @param TicksNumb Specifies the ticks Number of ticks between two interrupts.
* @retval status: - 0 Function succeeded.
* - 1 Function failed.
*/
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
{
- 80012c2: b580 push {r7, lr}
- 80012c4: b082 sub sp, #8
- 80012c6: af00 add r7, sp, #0
- 80012c8: 6078 str r0, [r7, #4]
+ 80012d2: b580 push {r7, lr}
+ 80012d4: b082 sub sp, #8
+ 80012d6: af00 add r7, sp, #0
+ 80012d8: 6078 str r0, [r7, #4]
return SysTick_Config(TicksNumb);
- 80012ca: 687b ldr r3, [r7, #4]
- 80012cc: 0018 movs r0, r3
- 80012ce: f7ff ffbf bl 8001250 <SysTick_Config>
- 80012d2: 0003 movs r3, r0
+ 80012da: 687b ldr r3, [r7, #4]
+ 80012dc: 0018 movs r0, r3
+ 80012de: f7ff ffbf bl 8001260 <SysTick_Config>
+ 80012e2: 0003 movs r3, r0
}
- 80012d4: 0018 movs r0, r3
- 80012d6: 46bd mov sp, r7
- 80012d8: b002 add sp, #8
- 80012da: bd80 pop {r7, pc}
+ 80012e4: 0018 movs r0, r3
+ 80012e6: 46bd mov sp, r7
+ 80012e8: b002 add sp, #8
+ 80012ea: bd80 pop {r7, pc}
-080012dc <HAL_GPIO_Init>:
+080012ec <HAL_GPIO_Init>:
* @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
* the configuration information for the specified GPIO peripheral.
* @retval None
*/
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
{
- 80012dc: b580 push {r7, lr}
- 80012de: b086 sub sp, #24
- 80012e0: af00 add r7, sp, #0
- 80012e2: 6078 str r0, [r7, #4]
- 80012e4: 6039 str r1, [r7, #0]
+ 80012ec: b580 push {r7, lr}
+ 80012ee: b086 sub sp, #24
+ 80012f0: af00 add r7, sp, #0
+ 80012f2: 6078 str r0, [r7, #4]
+ 80012f4: 6039 str r1, [r7, #0]
uint32_t position = 0x00U;
- 80012e6: 2300 movs r3, #0
- 80012e8: 617b str r3, [r7, #20]
+ 80012f6: 2300 movs r3, #0
+ 80012f8: 617b str r3, [r7, #20]
uint32_t iocurrent = 0x00U;
- 80012ea: 2300 movs r3, #0
- 80012ec: 60fb str r3, [r7, #12]
+ 80012fa: 2300 movs r3, #0
+ 80012fc: 60fb str r3, [r7, #12]
uint32_t temp = 0x00U;
- 80012ee: 2300 movs r3, #0
- 80012f0: 613b str r3, [r7, #16]
+ 80012fe: 2300 movs r3, #0
+ 8001300: 613b str r3, [r7, #16]
/* Check the parameters */
assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
assert_param(IS_GPIO_PIN_AVAILABLE(GPIOx, (GPIO_Init->Pin)));
/* Configure the port pins */
while (((GPIO_Init->Pin) >> position) != 0)
- 80012f2: e149 b.n 8001588 <HAL_GPIO_Init+0x2ac>
+ 8001302: e149 b.n 8001598 <HAL_GPIO_Init+0x2ac>
{
/* Get the IO position */
iocurrent = (GPIO_Init->Pin) & (1U << position);
- 80012f4: 683b ldr r3, [r7, #0]
- 80012f6: 681b ldr r3, [r3, #0]
- 80012f8: 2101 movs r1, #1
- 80012fa: 697a ldr r2, [r7, #20]
- 80012fc: 4091 lsls r1, r2
- 80012fe: 000a movs r2, r1
- 8001300: 4013 ands r3, r2
- 8001302: 60fb str r3, [r7, #12]
+ 8001304: 683b ldr r3, [r7, #0]
+ 8001306: 681b ldr r3, [r3, #0]
+ 8001308: 2101 movs r1, #1
+ 800130a: 697a ldr r2, [r7, #20]
+ 800130c: 4091 lsls r1, r2
+ 800130e: 000a movs r2, r1
+ 8001310: 4013 ands r3, r2
+ 8001312: 60fb str r3, [r7, #12]
if (iocurrent)
- 8001304: 68fb ldr r3, [r7, #12]
- 8001306: 2b00 cmp r3, #0
- 8001308: d100 bne.n 800130c <HAL_GPIO_Init+0x30>
- 800130a: e13a b.n 8001582 <HAL_GPIO_Init+0x2a6>
+ 8001314: 68fb ldr r3, [r7, #12]
+ 8001316: 2b00 cmp r3, #0
+ 8001318: d100 bne.n 800131c <HAL_GPIO_Init+0x30>
+ 800131a: e13a b.n 8001592 <HAL_GPIO_Init+0x2a6>
{
/*--------------------- GPIO Mode Configuration ------------------------*/
/* In case of Output or Alternate function mode selection */
if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) ||
- 800130c: 683b ldr r3, [r7, #0]
- 800130e: 685b ldr r3, [r3, #4]
- 8001310: 2203 movs r2, #3
- 8001312: 4013 ands r3, r2
- 8001314: 2b01 cmp r3, #1
- 8001316: d005 beq.n 8001324 <HAL_GPIO_Init+0x48>
+ 800131c: 683b ldr r3, [r7, #0]
+ 800131e: 685b ldr r3, [r3, #4]
+ 8001320: 2203 movs r2, #3
+ 8001322: 4013 ands r3, r2
+ 8001324: 2b01 cmp r3, #1
+ 8001326: d005 beq.n 8001334 <HAL_GPIO_Init+0x48>
((GPIO_Init->Mode & GPIO_MODE) == MODE_AF))
- 8001318: 683b ldr r3, [r7, #0]
- 800131a: 685b ldr r3, [r3, #4]
- 800131c: 2203 movs r2, #3
- 800131e: 4013 ands r3, r2
+ 8001328: 683b ldr r3, [r7, #0]
+ 800132a: 685b ldr r3, [r3, #4]
+ 800132c: 2203 movs r2, #3
+ 800132e: 4013 ands r3, r2
if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) ||
- 8001320: 2b02 cmp r3, #2
- 8001322: d130 bne.n 8001386 <HAL_GPIO_Init+0xaa>
+ 8001330: 2b02 cmp r3, #2
+ 8001332: d130 bne.n 8001396 <HAL_GPIO_Init+0xaa>
{
/* Check the Speed parameter */
assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
/* Configure the IO Speed */
temp = GPIOx->OSPEEDR;
- 8001324: 687b ldr r3, [r7, #4]
- 8001326: 689b ldr r3, [r3, #8]
- 8001328: 613b str r3, [r7, #16]
+ 8001334: 687b ldr r3, [r7, #4]
+ 8001336: 689b ldr r3, [r3, #8]
+ 8001338: 613b str r3, [r7, #16]
temp &= ~(GPIO_OSPEEDER_OSPEED0 << (position * 2U));
- 800132a: 697b ldr r3, [r7, #20]
- 800132c: 005b lsls r3, r3, #1
- 800132e: 2203 movs r2, #3
- 8001330: 409a lsls r2, r3
- 8001332: 0013 movs r3, r2
- 8001334: 43da mvns r2, r3
- 8001336: 693b ldr r3, [r7, #16]
- 8001338: 4013 ands r3, r2
- 800133a: 613b str r3, [r7, #16]
+ 800133a: 697b ldr r3, [r7, #20]
+ 800133c: 005b lsls r3, r3, #1
+ 800133e: 2203 movs r2, #3
+ 8001340: 409a lsls r2, r3
+ 8001342: 0013 movs r3, r2
+ 8001344: 43da mvns r2, r3
+ 8001346: 693b ldr r3, [r7, #16]
+ 8001348: 4013 ands r3, r2
+ 800134a: 613b str r3, [r7, #16]
temp |= (GPIO_Init->Speed << (position * 2U));
- 800133c: 683b ldr r3, [r7, #0]
- 800133e: 68da ldr r2, [r3, #12]
- 8001340: 697b ldr r3, [r7, #20]
- 8001342: 005b lsls r3, r3, #1
- 8001344: 409a lsls r2, r3
- 8001346: 0013 movs r3, r2
- 8001348: 693a ldr r2, [r7, #16]
- 800134a: 4313 orrs r3, r2
- 800134c: 613b str r3, [r7, #16]
+ 800134c: 683b ldr r3, [r7, #0]
+ 800134e: 68da ldr r2, [r3, #12]
+ 8001350: 697b ldr r3, [r7, #20]
+ 8001352: 005b lsls r3, r3, #1
+ 8001354: 409a lsls r2, r3
+ 8001356: 0013 movs r3, r2
+ 8001358: 693a ldr r2, [r7, #16]
+ 800135a: 4313 orrs r3, r2
+ 800135c: 613b str r3, [r7, #16]
GPIOx->OSPEEDR = temp;
- 800134e: 687b ldr r3, [r7, #4]
- 8001350: 693a ldr r2, [r7, #16]
- 8001352: 609a str r2, [r3, #8]
+ 800135e: 687b ldr r3, [r7, #4]
+ 8001360: 693a ldr r2, [r7, #16]
+ 8001362: 609a str r2, [r3, #8]
/* Configure the IO Output Type */
temp = GPIOx->OTYPER;
- 8001354: 687b ldr r3, [r7, #4]
- 8001356: 685b ldr r3, [r3, #4]
- 8001358: 613b str r3, [r7, #16]
- temp &= ~(GPIO_OTYPER_OT_0 << position) ;
- 800135a: 2201 movs r2, #1
- 800135c: 697b ldr r3, [r7, #20]
- 800135e: 409a lsls r2, r3
- 8001360: 0013 movs r3, r2
- 8001362: 43da mvns r2, r3
- 8001364: 693b ldr r3, [r7, #16]
- 8001366: 4013 ands r3, r2
+ 8001364: 687b ldr r3, [r7, #4]
+ 8001366: 685b ldr r3, [r3, #4]
8001368: 613b str r3, [r7, #16]
+ temp &= ~(GPIO_OTYPER_OT_0 << position) ;
+ 800136a: 2201 movs r2, #1
+ 800136c: 697b ldr r3, [r7, #20]
+ 800136e: 409a lsls r2, r3
+ 8001370: 0013 movs r3, r2
+ 8001372: 43da mvns r2, r3
+ 8001374: 693b ldr r3, [r7, #16]
+ 8001376: 4013 ands r3, r2
+ 8001378: 613b str r3, [r7, #16]
temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position);
- 800136a: 683b ldr r3, [r7, #0]
- 800136c: 685b ldr r3, [r3, #4]
- 800136e: 091b lsrs r3, r3, #4
- 8001370: 2201 movs r2, #1
- 8001372: 401a ands r2, r3
- 8001374: 697b ldr r3, [r7, #20]
- 8001376: 409a lsls r2, r3
- 8001378: 0013 movs r3, r2
- 800137a: 693a ldr r2, [r7, #16]
- 800137c: 4313 orrs r3, r2
- 800137e: 613b str r3, [r7, #16]
+ 800137a: 683b ldr r3, [r7, #0]
+ 800137c: 685b ldr r3, [r3, #4]
+ 800137e: 091b lsrs r3, r3, #4
+ 8001380: 2201 movs r2, #1
+ 8001382: 401a ands r2, r3
+ 8001384: 697b ldr r3, [r7, #20]
+ 8001386: 409a lsls r2, r3
+ 8001388: 0013 movs r3, r2
+ 800138a: 693a ldr r2, [r7, #16]
+ 800138c: 4313 orrs r3, r2
+ 800138e: 613b str r3, [r7, #16]
GPIOx->OTYPER = temp;
- 8001380: 687b ldr r3, [r7, #4]
- 8001382: 693a ldr r2, [r7, #16]
- 8001384: 605a str r2, [r3, #4]
+ 8001390: 687b ldr r3, [r7, #4]
+ 8001392: 693a ldr r2, [r7, #16]
+ 8001394: 605a str r2, [r3, #4]
}
if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG)
- 8001386: 683b ldr r3, [r7, #0]
- 8001388: 685b ldr r3, [r3, #4]
- 800138a: 2203 movs r2, #3
- 800138c: 4013 ands r3, r2
- 800138e: 2b03 cmp r3, #3
- 8001390: d017 beq.n 80013c2 <HAL_GPIO_Init+0xe6>
+ 8001396: 683b ldr r3, [r7, #0]
+ 8001398: 685b ldr r3, [r3, #4]
+ 800139a: 2203 movs r2, #3
+ 800139c: 4013 ands r3, r2
+ 800139e: 2b03 cmp r3, #3
+ 80013a0: d017 beq.n 80013d2 <HAL_GPIO_Init+0xe6>
{
/* Check the Pull parameter */
assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
/* Activate the Pull-up or Pull down resistor for the current IO */
temp = GPIOx->PUPDR;
- 8001392: 687b ldr r3, [r7, #4]
- 8001394: 68db ldr r3, [r3, #12]
- 8001396: 613b str r3, [r7, #16]
+ 80013a2: 687b ldr r3, [r7, #4]
+ 80013a4: 68db ldr r3, [r3, #12]
+ 80013a6: 613b str r3, [r7, #16]
temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2U));
- 8001398: 697b ldr r3, [r7, #20]
- 800139a: 005b lsls r3, r3, #1
- 800139c: 2203 movs r2, #3
- 800139e: 409a lsls r2, r3
- 80013a0: 0013 movs r3, r2
- 80013a2: 43da mvns r2, r3
- 80013a4: 693b ldr r3, [r7, #16]
- 80013a6: 4013 ands r3, r2
- 80013a8: 613b str r3, [r7, #16]
+ 80013a8: 697b ldr r3, [r7, #20]
+ 80013aa: 005b lsls r3, r3, #1
+ 80013ac: 2203 movs r2, #3
+ 80013ae: 409a lsls r2, r3
+ 80013b0: 0013 movs r3, r2
+ 80013b2: 43da mvns r2, r3
+ 80013b4: 693b ldr r3, [r7, #16]
+ 80013b6: 4013 ands r3, r2
+ 80013b8: 613b str r3, [r7, #16]
temp |= ((GPIO_Init->Pull) << (position * 2U));
- 80013aa: 683b ldr r3, [r7, #0]
- 80013ac: 689a ldr r2, [r3, #8]
- 80013ae: 697b ldr r3, [r7, #20]
- 80013b0: 005b lsls r3, r3, #1
- 80013b2: 409a lsls r2, r3
- 80013b4: 0013 movs r3, r2
- 80013b6: 693a ldr r2, [r7, #16]
- 80013b8: 4313 orrs r3, r2
- 80013ba: 613b str r3, [r7, #16]
+ 80013ba: 683b ldr r3, [r7, #0]
+ 80013bc: 689a ldr r2, [r3, #8]
+ 80013be: 697b ldr r3, [r7, #20]
+ 80013c0: 005b lsls r3, r3, #1
+ 80013c2: 409a lsls r2, r3
+ 80013c4: 0013 movs r3, r2
+ 80013c6: 693a ldr r2, [r7, #16]
+ 80013c8: 4313 orrs r3, r2
+ 80013ca: 613b str r3, [r7, #16]
GPIOx->PUPDR = temp;
- 80013bc: 687b ldr r3, [r7, #4]
- 80013be: 693a ldr r2, [r7, #16]
- 80013c0: 60da str r2, [r3, #12]
+ 80013cc: 687b ldr r3, [r7, #4]
+ 80013ce: 693a ldr r2, [r7, #16]
+ 80013d0: 60da str r2, [r3, #12]
}
/* In case of Alternate function mode selection */
if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
- 80013c2: 683b ldr r3, [r7, #0]
- 80013c4: 685b ldr r3, [r3, #4]
- 80013c6: 2203 movs r2, #3
- 80013c8: 4013 ands r3, r2
- 80013ca: 2b02 cmp r3, #2
- 80013cc: d123 bne.n 8001416 <HAL_GPIO_Init+0x13a>
+ 80013d2: 683b ldr r3, [r7, #0]
+ 80013d4: 685b ldr r3, [r3, #4]
+ 80013d6: 2203 movs r2, #3
+ 80013d8: 4013 ands r3, r2
+ 80013da: 2b02 cmp r3, #2
+ 80013dc: d123 bne.n 8001426 <HAL_GPIO_Init+0x13a>
/* Check the Alternate function parameters */
assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
/* Configure Alternate function mapped with the current IO */
temp = GPIOx->AFR[position >> 3U];
- 80013ce: 697b ldr r3, [r7, #20]
- 80013d0: 08da lsrs r2, r3, #3
- 80013d2: 687b ldr r3, [r7, #4]
- 80013d4: 3208 adds r2, #8
- 80013d6: 0092 lsls r2, r2, #2
- 80013d8: 58d3 ldr r3, [r2, r3]
- 80013da: 613b str r3, [r7, #16]
+ 80013de: 697b ldr r3, [r7, #20]
+ 80013e0: 08da lsrs r2, r3, #3
+ 80013e2: 687b ldr r3, [r7, #4]
+ 80013e4: 3208 adds r2, #8
+ 80013e6: 0092 lsls r2, r2, #2
+ 80013e8: 58d3 ldr r3, [r2, r3]
+ 80013ea: 613b str r3, [r7, #16]
temp &= ~(0xFUL << ((uint32_t)(position & 0x07UL) * 4U));
- 80013dc: 697b ldr r3, [r7, #20]
- 80013de: 2207 movs r2, #7
- 80013e0: 4013 ands r3, r2
- 80013e2: 009b lsls r3, r3, #2
- 80013e4: 220f movs r2, #15
- 80013e6: 409a lsls r2, r3
- 80013e8: 0013 movs r3, r2
- 80013ea: 43da mvns r2, r3
- 80013ec: 693b ldr r3, [r7, #16]
- 80013ee: 4013 ands r3, r2
- 80013f0: 613b str r3, [r7, #16]
+ 80013ec: 697b ldr r3, [r7, #20]
+ 80013ee: 2207 movs r2, #7
+ 80013f0: 4013 ands r3, r2
+ 80013f2: 009b lsls r3, r3, #2
+ 80013f4: 220f movs r2, #15
+ 80013f6: 409a lsls r2, r3
+ 80013f8: 0013 movs r3, r2
+ 80013fa: 43da mvns r2, r3
+ 80013fc: 693b ldr r3, [r7, #16]
+ 80013fe: 4013 ands r3, r2
+ 8001400: 613b str r3, [r7, #16]
temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & (uint32_t)0x07U) * 4U));
- 80013f2: 683b ldr r3, [r7, #0]
- 80013f4: 691a ldr r2, [r3, #16]
- 80013f6: 697b ldr r3, [r7, #20]
- 80013f8: 2107 movs r1, #7
- 80013fa: 400b ands r3, r1
- 80013fc: 009b lsls r3, r3, #2
- 80013fe: 409a lsls r2, r3
- 8001400: 0013 movs r3, r2
- 8001402: 693a ldr r2, [r7, #16]
- 8001404: 4313 orrs r3, r2
- 8001406: 613b str r3, [r7, #16]
+ 8001402: 683b ldr r3, [r7, #0]
+ 8001404: 691a ldr r2, [r3, #16]
+ 8001406: 697b ldr r3, [r7, #20]
+ 8001408: 2107 movs r1, #7
+ 800140a: 400b ands r3, r1
+ 800140c: 009b lsls r3, r3, #2
+ 800140e: 409a lsls r2, r3
+ 8001410: 0013 movs r3, r2
+ 8001412: 693a ldr r2, [r7, #16]
+ 8001414: 4313 orrs r3, r2
+ 8001416: 613b str r3, [r7, #16]
GPIOx->AFR[position >> 3U] = temp;
- 8001408: 697b ldr r3, [r7, #20]
- 800140a: 08da lsrs r2, r3, #3
- 800140c: 687b ldr r3, [r7, #4]
- 800140e: 3208 adds r2, #8
- 8001410: 0092 lsls r2, r2, #2
- 8001412: 6939 ldr r1, [r7, #16]
- 8001414: 50d1 str r1, [r2, r3]
+ 8001418: 697b ldr r3, [r7, #20]
+ 800141a: 08da lsrs r2, r3, #3
+ 800141c: 687b ldr r3, [r7, #4]
+ 800141e: 3208 adds r2, #8
+ 8001420: 0092 lsls r2, r2, #2
+ 8001422: 6939 ldr r1, [r7, #16]
+ 8001424: 50d1 str r1, [r2, r3]
}
/* Configure IO Direction mode (Input, Output, Alternate or Analog) */
temp = GPIOx->MODER;
- 8001416: 687b ldr r3, [r7, #4]
- 8001418: 681b ldr r3, [r3, #0]
- 800141a: 613b str r3, [r7, #16]
+ 8001426: 687b ldr r3, [r7, #4]
+ 8001428: 681b ldr r3, [r3, #0]
+ 800142a: 613b str r3, [r7, #16]
temp &= ~(GPIO_MODER_MODE0 << (position * 2U));
- 800141c: 697b ldr r3, [r7, #20]
- 800141e: 005b lsls r3, r3, #1
- 8001420: 2203 movs r2, #3
- 8001422: 409a lsls r2, r3
- 8001424: 0013 movs r3, r2
- 8001426: 43da mvns r2, r3
- 8001428: 693b ldr r3, [r7, #16]
- 800142a: 4013 ands r3, r2
- 800142c: 613b str r3, [r7, #16]
+ 800142c: 697b ldr r3, [r7, #20]
+ 800142e: 005b lsls r3, r3, #1
+ 8001430: 2203 movs r2, #3
+ 8001432: 409a lsls r2, r3
+ 8001434: 0013 movs r3, r2
+ 8001436: 43da mvns r2, r3
+ 8001438: 693b ldr r3, [r7, #16]
+ 800143a: 4013 ands r3, r2
+ 800143c: 613b str r3, [r7, #16]
temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U));
- 800142e: 683b ldr r3, [r7, #0]
- 8001430: 685b ldr r3, [r3, #4]
- 8001432: 2203 movs r2, #3
- 8001434: 401a ands r2, r3
- 8001436: 697b ldr r3, [r7, #20]
- 8001438: 005b lsls r3, r3, #1
- 800143a: 409a lsls r2, r3
- 800143c: 0013 movs r3, r2
- 800143e: 693a ldr r2, [r7, #16]
- 8001440: 4313 orrs r3, r2
- 8001442: 613b str r3, [r7, #16]
+ 800143e: 683b ldr r3, [r7, #0]
+ 8001440: 685b ldr r3, [r3, #4]
+ 8001442: 2203 movs r2, #3
+ 8001444: 401a ands r2, r3
+ 8001446: 697b ldr r3, [r7, #20]
+ 8001448: 005b lsls r3, r3, #1
+ 800144a: 409a lsls r2, r3
+ 800144c: 0013 movs r3, r2
+ 800144e: 693a ldr r2, [r7, #16]
+ 8001450: 4313 orrs r3, r2
+ 8001452: 613b str r3, [r7, #16]
GPIOx->MODER = temp;
- 8001444: 687b ldr r3, [r7, #4]
- 8001446: 693a ldr r2, [r7, #16]
- 8001448: 601a str r2, [r3, #0]
+ 8001454: 687b ldr r3, [r7, #4]
+ 8001456: 693a ldr r2, [r7, #16]
+ 8001458: 601a str r2, [r3, #0]
/*--------------------- EXTI Mode Configuration ------------------------*/
/* Configure the External Interrupt or event for the current IO */
if ((GPIO_Init->Mode & EXTI_MODE) != 0x00U)
- 800144a: 683b ldr r3, [r7, #0]
- 800144c: 685a ldr r2, [r3, #4]
- 800144e: 23c0 movs r3, #192 ; 0xc0
- 8001450: 029b lsls r3, r3, #10
- 8001452: 4013 ands r3, r2
- 8001454: d100 bne.n 8001458 <HAL_GPIO_Init+0x17c>
- 8001456: e094 b.n 8001582 <HAL_GPIO_Init+0x2a6>
+ 800145a: 683b ldr r3, [r7, #0]
+ 800145c: 685a ldr r2, [r3, #4]
+ 800145e: 23c0 movs r3, #192 ; 0xc0
+ 8001460: 029b lsls r3, r3, #10
+ 8001462: 4013 ands r3, r2
+ 8001464: d100 bne.n 8001468 <HAL_GPIO_Init+0x17c>
+ 8001466: e094 b.n 8001592 <HAL_GPIO_Init+0x2a6>
{
/* Enable SYSCFG Clock */
__HAL_RCC_SYSCFG_CLK_ENABLE();
- 8001458: 4b51 ldr r3, [pc, #324] ; (80015a0 <HAL_GPIO_Init+0x2c4>)
- 800145a: 6b5a ldr r2, [r3, #52] ; 0x34
- 800145c: 4b50 ldr r3, [pc, #320] ; (80015a0 <HAL_GPIO_Init+0x2c4>)
- 800145e: 2101 movs r1, #1
- 8001460: 430a orrs r2, r1
- 8001462: 635a str r2, [r3, #52] ; 0x34
+ 8001468: 4b51 ldr r3, [pc, #324] ; (80015b0 <HAL_GPIO_Init+0x2c4>)
+ 800146a: 6b5a ldr r2, [r3, #52] ; 0x34
+ 800146c: 4b50 ldr r3, [pc, #320] ; (80015b0 <HAL_GPIO_Init+0x2c4>)
+ 800146e: 2101 movs r1, #1
+ 8001470: 430a orrs r2, r1
+ 8001472: 635a str r2, [r3, #52] ; 0x34
temp = SYSCFG->EXTICR[position >> 2U];
- 8001464: 4a4f ldr r2, [pc, #316] ; (80015a4 <HAL_GPIO_Init+0x2c8>)
- 8001466: 697b ldr r3, [r7, #20]
- 8001468: 089b lsrs r3, r3, #2
- 800146a: 3302 adds r3, #2
- 800146c: 009b lsls r3, r3, #2
- 800146e: 589b ldr r3, [r3, r2]
- 8001470: 613b str r3, [r7, #16]
+ 8001474: 4a4f ldr r2, [pc, #316] ; (80015b4 <HAL_GPIO_Init+0x2c8>)
+ 8001476: 697b ldr r3, [r7, #20]
+ 8001478: 089b lsrs r3, r3, #2
+ 800147a: 3302 adds r3, #2
+ 800147c: 009b lsls r3, r3, #2
+ 800147e: 589b ldr r3, [r3, r2]
+ 8001480: 613b str r3, [r7, #16]
CLEAR_BIT(temp, (0x0FUL) << (4U * (position & 0x03U)));
- 8001472: 697b ldr r3, [r7, #20]
- 8001474: 2203 movs r2, #3
- 8001476: 4013 ands r3, r2
- 8001478: 009b lsls r3, r3, #2
- 800147a: 220f movs r2, #15
- 800147c: 409a lsls r2, r3
- 800147e: 0013 movs r3, r2
- 8001480: 43da mvns r2, r3
- 8001482: 693b ldr r3, [r7, #16]
- 8001484: 4013 ands r3, r2
- 8001486: 613b str r3, [r7, #16]
+ 8001482: 697b ldr r3, [r7, #20]
+ 8001484: 2203 movs r2, #3
+ 8001486: 4013 ands r3, r2
+ 8001488: 009b lsls r3, r3, #2
+ 800148a: 220f movs r2, #15
+ 800148c: 409a lsls r2, r3
+ 800148e: 0013 movs r3, r2
+ 8001490: 43da mvns r2, r3
+ 8001492: 693b ldr r3, [r7, #16]
+ 8001494: 4013 ands r3, r2
+ 8001496: 613b str r3, [r7, #16]
SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03U)));
- 8001488: 687a ldr r2, [r7, #4]
- 800148a: 23a0 movs r3, #160 ; 0xa0
- 800148c: 05db lsls r3, r3, #23
- 800148e: 429a cmp r2, r3
- 8001490: d013 beq.n 80014ba <HAL_GPIO_Init+0x1de>
- 8001492: 687b ldr r3, [r7, #4]
- 8001494: 4a44 ldr r2, [pc, #272] ; (80015a8 <HAL_GPIO_Init+0x2cc>)
- 8001496: 4293 cmp r3, r2
- 8001498: d00d beq.n 80014b6 <HAL_GPIO_Init+0x1da>
- 800149a: 687b ldr r3, [r7, #4]
- 800149c: 4a43 ldr r2, [pc, #268] ; (80015ac <HAL_GPIO_Init+0x2d0>)
- 800149e: 4293 cmp r3, r2
- 80014a0: d007 beq.n 80014b2 <HAL_GPIO_Init+0x1d6>
+ 8001498: 687a ldr r2, [r7, #4]
+ 800149a: 23a0 movs r3, #160 ; 0xa0
+ 800149c: 05db lsls r3, r3, #23
+ 800149e: 429a cmp r2, r3
+ 80014a0: d013 beq.n 80014ca <HAL_GPIO_Init+0x1de>
80014a2: 687b ldr r3, [r7, #4]
- 80014a4: 4a42 ldr r2, [pc, #264] ; (80015b0 <HAL_GPIO_Init+0x2d4>)
+ 80014a4: 4a44 ldr r2, [pc, #272] ; (80015b8 <HAL_GPIO_Init+0x2cc>)
80014a6: 4293 cmp r3, r2
- 80014a8: d101 bne.n 80014ae <HAL_GPIO_Init+0x1d2>
- 80014aa: 2305 movs r3, #5
- 80014ac: e006 b.n 80014bc <HAL_GPIO_Init+0x1e0>
- 80014ae: 2306 movs r3, #6
- 80014b0: e004 b.n 80014bc <HAL_GPIO_Init+0x1e0>
- 80014b2: 2302 movs r3, #2
- 80014b4: e002 b.n 80014bc <HAL_GPIO_Init+0x1e0>
- 80014b6: 2301 movs r3, #1
- 80014b8: e000 b.n 80014bc <HAL_GPIO_Init+0x1e0>
- 80014ba: 2300 movs r3, #0
- 80014bc: 697a ldr r2, [r7, #20]
- 80014be: 2103 movs r1, #3
- 80014c0: 400a ands r2, r1
- 80014c2: 0092 lsls r2, r2, #2
- 80014c4: 4093 lsls r3, r2
- 80014c6: 693a ldr r2, [r7, #16]
- 80014c8: 4313 orrs r3, r2
- 80014ca: 613b str r3, [r7, #16]
- SYSCFG->EXTICR[position >> 2U] = temp;
- 80014cc: 4935 ldr r1, [pc, #212] ; (80015a4 <HAL_GPIO_Init+0x2c8>)
- 80014ce: 697b ldr r3, [r7, #20]
- 80014d0: 089b lsrs r3, r3, #2
- 80014d2: 3302 adds r3, #2
- 80014d4: 009b lsls r3, r3, #2
+ 80014a8: d00d beq.n 80014c6 <HAL_GPIO_Init+0x1da>
+ 80014aa: 687b ldr r3, [r7, #4]
+ 80014ac: 4a43 ldr r2, [pc, #268] ; (80015bc <HAL_GPIO_Init+0x2d0>)
+ 80014ae: 4293 cmp r3, r2
+ 80014b0: d007 beq.n 80014c2 <HAL_GPIO_Init+0x1d6>
+ 80014b2: 687b ldr r3, [r7, #4]
+ 80014b4: 4a42 ldr r2, [pc, #264] ; (80015c0 <HAL_GPIO_Init+0x2d4>)
+ 80014b6: 4293 cmp r3, r2
+ 80014b8: d101 bne.n 80014be <HAL_GPIO_Init+0x1d2>
+ 80014ba: 2305 movs r3, #5
+ 80014bc: e006 b.n 80014cc <HAL_GPIO_Init+0x1e0>
+ 80014be: 2306 movs r3, #6
+ 80014c0: e004 b.n 80014cc <HAL_GPIO_Init+0x1e0>
+ 80014c2: 2302 movs r3, #2
+ 80014c4: e002 b.n 80014cc <HAL_GPIO_Init+0x1e0>
+ 80014c6: 2301 movs r3, #1
+ 80014c8: e000 b.n 80014cc <HAL_GPIO_Init+0x1e0>
+ 80014ca: 2300 movs r3, #0
+ 80014cc: 697a ldr r2, [r7, #20]
+ 80014ce: 2103 movs r1, #3
+ 80014d0: 400a ands r2, r1
+ 80014d2: 0092 lsls r2, r2, #2
+ 80014d4: 4093 lsls r3, r2
80014d6: 693a ldr r2, [r7, #16]
- 80014d8: 505a str r2, [r3, r1]
+ 80014d8: 4313 orrs r3, r2
+ 80014da: 613b str r3, [r7, #16]
+ SYSCFG->EXTICR[position >> 2U] = temp;
+ 80014dc: 4935 ldr r1, [pc, #212] ; (80015b4 <HAL_GPIO_Init+0x2c8>)
+ 80014de: 697b ldr r3, [r7, #20]
+ 80014e0: 089b lsrs r3, r3, #2
+ 80014e2: 3302 adds r3, #2
+ 80014e4: 009b lsls r3, r3, #2
+ 80014e6: 693a ldr r2, [r7, #16]
+ 80014e8: 505a str r2, [r3, r1]
/* Clear EXTI line configuration */
temp = EXTI->IMR;
- 80014da: 4b36 ldr r3, [pc, #216] ; (80015b4 <HAL_GPIO_Init+0x2d8>)
- 80014dc: 681b ldr r3, [r3, #0]
- 80014de: 613b str r3, [r7, #16]
+ 80014ea: 4b36 ldr r3, [pc, #216] ; (80015c4 <HAL_GPIO_Init+0x2d8>)
+ 80014ec: 681b ldr r3, [r3, #0]
+ 80014ee: 613b str r3, [r7, #16]
temp &= ~((uint32_t)iocurrent);
- 80014e0: 68fb ldr r3, [r7, #12]
- 80014e2: 43da mvns r2, r3
- 80014e4: 693b ldr r3, [r7, #16]
- 80014e6: 4013 ands r3, r2
- 80014e8: 613b str r3, [r7, #16]
+ 80014f0: 68fb ldr r3, [r7, #12]
+ 80014f2: 43da mvns r2, r3
+ 80014f4: 693b ldr r3, [r7, #16]
+ 80014f6: 4013 ands r3, r2
+ 80014f8: 613b str r3, [r7, #16]
if ((GPIO_Init->Mode & EXTI_IT) != 0x00U)
- 80014ea: 683b ldr r3, [r7, #0]
- 80014ec: 685a ldr r2, [r3, #4]
- 80014ee: 2380 movs r3, #128 ; 0x80
- 80014f0: 025b lsls r3, r3, #9
- 80014f2: 4013 ands r3, r2
- 80014f4: d003 beq.n 80014fe <HAL_GPIO_Init+0x222>
+ 80014fa: 683b ldr r3, [r7, #0]
+ 80014fc: 685a ldr r2, [r3, #4]
+ 80014fe: 2380 movs r3, #128 ; 0x80
+ 8001500: 025b lsls r3, r3, #9
+ 8001502: 4013 ands r3, r2
+ 8001504: d003 beq.n 800150e <HAL_GPIO_Init+0x222>
{
temp |= iocurrent;
- 80014f6: 693a ldr r2, [r7, #16]
- 80014f8: 68fb ldr r3, [r7, #12]
- 80014fa: 4313 orrs r3, r2
- 80014fc: 613b str r3, [r7, #16]
+ 8001506: 693a ldr r2, [r7, #16]
+ 8001508: 68fb ldr r3, [r7, #12]
+ 800150a: 4313 orrs r3, r2
+ 800150c: 613b str r3, [r7, #16]
}
EXTI->IMR = temp;
- 80014fe: 4b2d ldr r3, [pc, #180] ; (80015b4 <HAL_GPIO_Init+0x2d8>)
- 8001500: 693a ldr r2, [r7, #16]
- 8001502: 601a str r2, [r3, #0]
+ 800150e: 4b2d ldr r3, [pc, #180] ; (80015c4 <HAL_GPIO_Init+0x2d8>)
+ 8001510: 693a ldr r2, [r7, #16]
+ 8001512: 601a str r2, [r3, #0]
temp = EXTI->EMR;
- 8001504: 4b2b ldr r3, [pc, #172] ; (80015b4 <HAL_GPIO_Init+0x2d8>)
- 8001506: 685b ldr r3, [r3, #4]
- 8001508: 613b str r3, [r7, #16]
+ 8001514: 4b2b ldr r3, [pc, #172] ; (80015c4 <HAL_GPIO_Init+0x2d8>)
+ 8001516: 685b ldr r3, [r3, #4]
+ 8001518: 613b str r3, [r7, #16]
temp &= ~((uint32_t)iocurrent);
- 800150a: 68fb ldr r3, [r7, #12]
- 800150c: 43da mvns r2, r3
- 800150e: 693b ldr r3, [r7, #16]
- 8001510: 4013 ands r3, r2
- 8001512: 613b str r3, [r7, #16]
+ 800151a: 68fb ldr r3, [r7, #12]
+ 800151c: 43da mvns r2, r3
+ 800151e: 693b ldr r3, [r7, #16]
+ 8001520: 4013 ands r3, r2
+ 8001522: 613b str r3, [r7, #16]
if ((GPIO_Init->Mode & EXTI_EVT) != 0x00U)
- 8001514: 683b ldr r3, [r7, #0]
- 8001516: 685a ldr r2, [r3, #4]
- 8001518: 2380 movs r3, #128 ; 0x80
- 800151a: 029b lsls r3, r3, #10
- 800151c: 4013 ands r3, r2
- 800151e: d003 beq.n 8001528 <HAL_GPIO_Init+0x24c>
+ 8001524: 683b ldr r3, [r7, #0]
+ 8001526: 685a ldr r2, [r3, #4]
+ 8001528: 2380 movs r3, #128 ; 0x80
+ 800152a: 029b lsls r3, r3, #10
+ 800152c: 4013 ands r3, r2
+ 800152e: d003 beq.n 8001538 <HAL_GPIO_Init+0x24c>
{
temp |= iocurrent;
- 8001520: 693a ldr r2, [r7, #16]
- 8001522: 68fb ldr r3, [r7, #12]
- 8001524: 4313 orrs r3, r2
- 8001526: 613b str r3, [r7, #16]
+ 8001530: 693a ldr r2, [r7, #16]
+ 8001532: 68fb ldr r3, [r7, #12]
+ 8001534: 4313 orrs r3, r2
+ 8001536: 613b str r3, [r7, #16]
}
EXTI->EMR = temp;
- 8001528: 4b22 ldr r3, [pc, #136] ; (80015b4 <HAL_GPIO_Init+0x2d8>)
- 800152a: 693a ldr r2, [r7, #16]
- 800152c: 605a str r2, [r3, #4]
+ 8001538: 4b22 ldr r3, [pc, #136] ; (80015c4 <HAL_GPIO_Init+0x2d8>)
+ 800153a: 693a ldr r2, [r7, #16]
+ 800153c: 605a str r2, [r3, #4]
/* Clear Rising Falling edge configuration */
temp = EXTI->RTSR;
- 800152e: 4b21 ldr r3, [pc, #132] ; (80015b4 <HAL_GPIO_Init+0x2d8>)
- 8001530: 689b ldr r3, [r3, #8]
- 8001532: 613b str r3, [r7, #16]
+ 800153e: 4b21 ldr r3, [pc, #132] ; (80015c4 <HAL_GPIO_Init+0x2d8>)
+ 8001540: 689b ldr r3, [r3, #8]
+ 8001542: 613b str r3, [r7, #16]
temp &= ~((uint32_t)iocurrent);
- 8001534: 68fb ldr r3, [r7, #12]
- 8001536: 43da mvns r2, r3
- 8001538: 693b ldr r3, [r7, #16]
- 800153a: 4013 ands r3, r2
- 800153c: 613b str r3, [r7, #16]
+ 8001544: 68fb ldr r3, [r7, #12]
+ 8001546: 43da mvns r2, r3
+ 8001548: 693b ldr r3, [r7, #16]
+ 800154a: 4013 ands r3, r2
+ 800154c: 613b str r3, [r7, #16]
if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U)
- 800153e: 683b ldr r3, [r7, #0]
- 8001540: 685a ldr r2, [r3, #4]
- 8001542: 2380 movs r3, #128 ; 0x80
- 8001544: 035b lsls r3, r3, #13
- 8001546: 4013 ands r3, r2
- 8001548: d003 beq.n 8001552 <HAL_GPIO_Init+0x276>
+ 800154e: 683b ldr r3, [r7, #0]
+ 8001550: 685a ldr r2, [r3, #4]
+ 8001552: 2380 movs r3, #128 ; 0x80
+ 8001554: 035b lsls r3, r3, #13
+ 8001556: 4013 ands r3, r2
+ 8001558: d003 beq.n 8001562 <HAL_GPIO_Init+0x276>
{
temp |= iocurrent;
- 800154a: 693a ldr r2, [r7, #16]
- 800154c: 68fb ldr r3, [r7, #12]
- 800154e: 4313 orrs r3, r2
- 8001550: 613b str r3, [r7, #16]
+ 800155a: 693a ldr r2, [r7, #16]
+ 800155c: 68fb ldr r3, [r7, #12]
+ 800155e: 4313 orrs r3, r2
+ 8001560: 613b str r3, [r7, #16]
}
EXTI->RTSR = temp;
- 8001552: 4b18 ldr r3, [pc, #96] ; (80015b4 <HAL_GPIO_Init+0x2d8>)
- 8001554: 693a ldr r2, [r7, #16]
- 8001556: 609a str r2, [r3, #8]
+ 8001562: 4b18 ldr r3, [pc, #96] ; (80015c4 <HAL_GPIO_Init+0x2d8>)
+ 8001564: 693a ldr r2, [r7, #16]
+ 8001566: 609a str r2, [r3, #8]
temp = EXTI->FTSR;
- 8001558: 4b16 ldr r3, [pc, #88] ; (80015b4 <HAL_GPIO_Init+0x2d8>)
- 800155a: 68db ldr r3, [r3, #12]
- 800155c: 613b str r3, [r7, #16]
+ 8001568: 4b16 ldr r3, [pc, #88] ; (80015c4 <HAL_GPIO_Init+0x2d8>)
+ 800156a: 68db ldr r3, [r3, #12]
+ 800156c: 613b str r3, [r7, #16]
temp &= ~((uint32_t)iocurrent);
- 800155e: 68fb ldr r3, [r7, #12]
- 8001560: 43da mvns r2, r3
- 8001562: 693b ldr r3, [r7, #16]
- 8001564: 4013 ands r3, r2
- 8001566: 613b str r3, [r7, #16]
+ 800156e: 68fb ldr r3, [r7, #12]
+ 8001570: 43da mvns r2, r3
+ 8001572: 693b ldr r3, [r7, #16]
+ 8001574: 4013 ands r3, r2
+ 8001576: 613b str r3, [r7, #16]
if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U)
- 8001568: 683b ldr r3, [r7, #0]
- 800156a: 685a ldr r2, [r3, #4]
- 800156c: 2380 movs r3, #128 ; 0x80
- 800156e: 039b lsls r3, r3, #14
- 8001570: 4013 ands r3, r2
- 8001572: d003 beq.n 800157c <HAL_GPIO_Init+0x2a0>
+ 8001578: 683b ldr r3, [r7, #0]
+ 800157a: 685a ldr r2, [r3, #4]
+ 800157c: 2380 movs r3, #128 ; 0x80
+ 800157e: 039b lsls r3, r3, #14
+ 8001580: 4013 ands r3, r2
+ 8001582: d003 beq.n 800158c <HAL_GPIO_Init+0x2a0>
{
temp |= iocurrent;
- 8001574: 693a ldr r2, [r7, #16]
- 8001576: 68fb ldr r3, [r7, #12]
- 8001578: 4313 orrs r3, r2
- 800157a: 613b str r3, [r7, #16]
+ 8001584: 693a ldr r2, [r7, #16]
+ 8001586: 68fb ldr r3, [r7, #12]
+ 8001588: 4313 orrs r3, r2
+ 800158a: 613b str r3, [r7, #16]
}
EXTI->FTSR = temp;
- 800157c: 4b0d ldr r3, [pc, #52] ; (80015b4 <HAL_GPIO_Init+0x2d8>)
- 800157e: 693a ldr r2, [r7, #16]
- 8001580: 60da str r2, [r3, #12]
+ 800158c: 4b0d ldr r3, [pc, #52] ; (80015c4 <HAL_GPIO_Init+0x2d8>)
+ 800158e: 693a ldr r2, [r7, #16]
+ 8001590: 60da str r2, [r3, #12]
}
}
position++;
- 8001582: 697b ldr r3, [r7, #20]
- 8001584: 3301 adds r3, #1
- 8001586: 617b str r3, [r7, #20]
+ 8001592: 697b ldr r3, [r7, #20]
+ 8001594: 3301 adds r3, #1
+ 8001596: 617b str r3, [r7, #20]
while (((GPIO_Init->Pin) >> position) != 0)
- 8001588: 683b ldr r3, [r7, #0]
- 800158a: 681a ldr r2, [r3, #0]
- 800158c: 697b ldr r3, [r7, #20]
- 800158e: 40da lsrs r2, r3
- 8001590: 1e13 subs r3, r2, #0
- 8001592: d000 beq.n 8001596 <HAL_GPIO_Init+0x2ba>
- 8001594: e6ae b.n 80012f4 <HAL_GPIO_Init+0x18>
+ 8001598: 683b ldr r3, [r7, #0]
+ 800159a: 681a ldr r2, [r3, #0]
+ 800159c: 697b ldr r3, [r7, #20]
+ 800159e: 40da lsrs r2, r3
+ 80015a0: 1e13 subs r3, r2, #0
+ 80015a2: d000 beq.n 80015a6 <HAL_GPIO_Init+0x2ba>
+ 80015a4: e6ae b.n 8001304 <HAL_GPIO_Init+0x18>
}
}
- 8001596: 46c0 nop ; (mov r8, r8)
- 8001598: 46c0 nop ; (mov r8, r8)
- 800159a: 46bd mov sp, r7
- 800159c: b006 add sp, #24
- 800159e: bd80 pop {r7, pc}
- 80015a0: 40021000 .word 0x40021000
- 80015a4: 40010000 .word 0x40010000
- 80015a8: 50000400 .word 0x50000400
- 80015ac: 50000800 .word 0x50000800
- 80015b0: 50001c00 .word 0x50001c00
- 80015b4: 40010400 .word 0x40010400
+ 80015a6: 46c0 nop ; (mov r8, r8)
+ 80015a8: 46c0 nop ; (mov r8, r8)
+ 80015aa: 46bd mov sp, r7
+ 80015ac: b006 add sp, #24
+ 80015ae: bd80 pop {r7, pc}
+ 80015b0: 40021000 .word 0x40021000
+ 80015b4: 40010000 .word 0x40010000
+ 80015b8: 50000400 .word 0x50000400
+ 80015bc: 50000800 .word 0x50000800
+ 80015c0: 50001c00 .word 0x50001c00
+ 80015c4: 40010400 .word 0x40010400
-080015b8 <HAL_I2C_Init>:
+080015c8 <HAL_I2C_Init>:
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
{
- 80015b8: b580 push {r7, lr}
- 80015ba: b082 sub sp, #8
- 80015bc: af00 add r7, sp, #0
- 80015be: 6078 str r0, [r7, #4]
+ 80015c8: b580 push {r7, lr}
+ 80015ca: b082 sub sp, #8
+ 80015cc: af00 add r7, sp, #0
+ 80015ce: 6078 str r0, [r7, #4]
/* Check the I2C handle allocation */
if (hi2c == NULL)
- 80015c0: 687b ldr r3, [r7, #4]
- 80015c2: 2b00 cmp r3, #0
- 80015c4: d101 bne.n 80015ca <HAL_I2C_Init+0x12>
+ 80015d0: 687b ldr r3, [r7, #4]
+ 80015d2: 2b00 cmp r3, #0
+ 80015d4: d101 bne.n 80015da <HAL_I2C_Init+0x12>
{
return HAL_ERROR;
- 80015c6: 2301 movs r3, #1
- 80015c8: e082 b.n 80016d0 <HAL_I2C_Init+0x118>
+ 80015d6: 2301 movs r3, #1
+ 80015d8: e082 b.n 80016e0 <HAL_I2C_Init+0x118>
assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2));
assert_param(IS_I2C_OWN_ADDRESS2_MASK(hi2c->Init.OwnAddress2Masks));
assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode));
assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode));
if (hi2c->State == HAL_I2C_STATE_RESET)
- 80015ca: 687b ldr r3, [r7, #4]
- 80015cc: 2241 movs r2, #65 ; 0x41
- 80015ce: 5c9b ldrb r3, [r3, r2]
- 80015d0: b2db uxtb r3, r3
- 80015d2: 2b00 cmp r3, #0
- 80015d4: d107 bne.n 80015e6 <HAL_I2C_Init+0x2e>
+ 80015da: 687b ldr r3, [r7, #4]
+ 80015dc: 2241 movs r2, #65 ; 0x41
+ 80015de: 5c9b ldrb r3, [r3, r2]
+ 80015e0: b2db uxtb r3, r3
+ 80015e2: 2b00 cmp r3, #0
+ 80015e4: d107 bne.n 80015f6 <HAL_I2C_Init+0x2e>
{
/* Allocate lock resource and initialize it */
hi2c->Lock = HAL_UNLOCKED;
- 80015d6: 687b ldr r3, [r7, #4]
- 80015d8: 2240 movs r2, #64 ; 0x40
- 80015da: 2100 movs r1, #0
- 80015dc: 5499 strb r1, [r3, r2]
+ 80015e6: 687b ldr r3, [r7, #4]
+ 80015e8: 2240 movs r2, #64 ; 0x40
+ 80015ea: 2100 movs r1, #0
+ 80015ec: 5499 strb r1, [r3, r2]
/* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
hi2c->MspInitCallback(hi2c);
#else
/* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
HAL_I2C_MspInit(hi2c);
- 80015de: 687b ldr r3, [r7, #4]
- 80015e0: 0018 movs r0, r3
- 80015e2: f7ff fbcd bl 8000d80 <HAL_I2C_MspInit>
+ 80015ee: 687b ldr r3, [r7, #4]
+ 80015f0: 0018 movs r0, r3
+ 80015f2: f7ff fbcd bl 8000d90 <HAL_I2C_MspInit>
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
}
hi2c->State = HAL_I2C_STATE_BUSY;
- 80015e6: 687b ldr r3, [r7, #4]
- 80015e8: 2241 movs r2, #65 ; 0x41
- 80015ea: 2124 movs r1, #36 ; 0x24
- 80015ec: 5499 strb r1, [r3, r2]
+ 80015f6: 687b ldr r3, [r7, #4]
+ 80015f8: 2241 movs r2, #65 ; 0x41
+ 80015fa: 2124 movs r1, #36 ; 0x24
+ 80015fc: 5499 strb r1, [r3, r2]
/* Disable the selected I2C peripheral */
__HAL_I2C_DISABLE(hi2c);
- 80015ee: 687b ldr r3, [r7, #4]
- 80015f0: 681b ldr r3, [r3, #0]
- 80015f2: 681a ldr r2, [r3, #0]
- 80015f4: 687b ldr r3, [r7, #4]
- 80015f6: 681b ldr r3, [r3, #0]
- 80015f8: 2101 movs r1, #1
- 80015fa: 438a bics r2, r1
- 80015fc: 601a str r2, [r3, #0]
+ 80015fe: 687b ldr r3, [r7, #4]
+ 8001600: 681b ldr r3, [r3, #0]
+ 8001602: 681a ldr r2, [r3, #0]
+ 8001604: 687b ldr r3, [r7, #4]
+ 8001606: 681b ldr r3, [r3, #0]
+ 8001608: 2101 movs r1, #1
+ 800160a: 438a bics r2, r1
+ 800160c: 601a str r2, [r3, #0]
/*---------------------------- I2Cx TIMINGR Configuration ------------------*/
/* Configure I2Cx: Frequency range */
hi2c->Instance->TIMINGR = hi2c->Init.Timing & TIMING_CLEAR_MASK;
- 80015fe: 687b ldr r3, [r7, #4]
- 8001600: 685a ldr r2, [r3, #4]
- 8001602: 687b ldr r3, [r7, #4]
- 8001604: 681b ldr r3, [r3, #0]
- 8001606: 4934 ldr r1, [pc, #208] ; (80016d8 <HAL_I2C_Init+0x120>)
- 8001608: 400a ands r2, r1
- 800160a: 611a str r2, [r3, #16]
+ 800160e: 687b ldr r3, [r7, #4]
+ 8001610: 685a ldr r2, [r3, #4]
+ 8001612: 687b ldr r3, [r7, #4]
+ 8001614: 681b ldr r3, [r3, #0]
+ 8001616: 4934 ldr r1, [pc, #208] ; (80016e8 <HAL_I2C_Init+0x120>)
+ 8001618: 400a ands r2, r1
+ 800161a: 611a str r2, [r3, #16]
/*---------------------------- I2Cx OAR1 Configuration ---------------------*/
/* Disable Own Address1 before set the Own Address1 configuration */
hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN;
- 800160c: 687b ldr r3, [r7, #4]
- 800160e: 681b ldr r3, [r3, #0]
- 8001610: 689a ldr r2, [r3, #8]
- 8001612: 687b ldr r3, [r7, #4]
- 8001614: 681b ldr r3, [r3, #0]
- 8001616: 4931 ldr r1, [pc, #196] ; (80016dc <HAL_I2C_Init+0x124>)
- 8001618: 400a ands r2, r1
- 800161a: 609a str r2, [r3, #8]
+ 800161c: 687b ldr r3, [r7, #4]
+ 800161e: 681b ldr r3, [r3, #0]
+ 8001620: 689a ldr r2, [r3, #8]
+ 8001622: 687b ldr r3, [r7, #4]
+ 8001624: 681b ldr r3, [r3, #0]
+ 8001626: 4931 ldr r1, [pc, #196] ; (80016ec <HAL_I2C_Init+0x124>)
+ 8001628: 400a ands r2, r1
+ 800162a: 609a str r2, [r3, #8]
/* Configure I2Cx: Own Address1 and ack own address1 mode */
if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
- 800161c: 687b ldr r3, [r7, #4]
- 800161e: 68db ldr r3, [r3, #12]
- 8001620: 2b01 cmp r3, #1
- 8001622: d108 bne.n 8001636 <HAL_I2C_Init+0x7e>
+ 800162c: 687b ldr r3, [r7, #4]
+ 800162e: 68db ldr r3, [r3, #12]
+ 8001630: 2b01 cmp r3, #1
+ 8001632: d108 bne.n 8001646 <HAL_I2C_Init+0x7e>
{
hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1);
- 8001624: 687b ldr r3, [r7, #4]
- 8001626: 689a ldr r2, [r3, #8]
- 8001628: 687b ldr r3, [r7, #4]
- 800162a: 681b ldr r3, [r3, #0]
- 800162c: 2180 movs r1, #128 ; 0x80
- 800162e: 0209 lsls r1, r1, #8
- 8001630: 430a orrs r2, r1
- 8001632: 609a str r2, [r3, #8]
- 8001634: e007 b.n 8001646 <HAL_I2C_Init+0x8e>
+ 8001634: 687b ldr r3, [r7, #4]
+ 8001636: 689a ldr r2, [r3, #8]
+ 8001638: 687b ldr r3, [r7, #4]
+ 800163a: 681b ldr r3, [r3, #0]
+ 800163c: 2180 movs r1, #128 ; 0x80
+ 800163e: 0209 lsls r1, r1, #8
+ 8001640: 430a orrs r2, r1
+ 8001642: 609a str r2, [r3, #8]
+ 8001644: e007 b.n 8001656 <HAL_I2C_Init+0x8e>
}
else /* I2C_ADDRESSINGMODE_10BIT */
{
hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hi2c->Init.OwnAddress1);
- 8001636: 687b ldr r3, [r7, #4]
- 8001638: 689a ldr r2, [r3, #8]
- 800163a: 687b ldr r3, [r7, #4]
- 800163c: 681b ldr r3, [r3, #0]
- 800163e: 2184 movs r1, #132 ; 0x84
- 8001640: 0209 lsls r1, r1, #8
- 8001642: 430a orrs r2, r1
- 8001644: 609a str r2, [r3, #8]
+ 8001646: 687b ldr r3, [r7, #4]
+ 8001648: 689a ldr r2, [r3, #8]
+ 800164a: 687b ldr r3, [r7, #4]
+ 800164c: 681b ldr r3, [r3, #0]
+ 800164e: 2184 movs r1, #132 ; 0x84
+ 8001650: 0209 lsls r1, r1, #8
+ 8001652: 430a orrs r2, r1
+ 8001654: 609a str r2, [r3, #8]
}
/*---------------------------- I2Cx CR2 Configuration ----------------------*/
/* Configure I2Cx: Addressing Master mode */
if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
- 8001646: 687b ldr r3, [r7, #4]
- 8001648: 68db ldr r3, [r3, #12]
- 800164a: 2b02 cmp r3, #2
- 800164c: d104 bne.n 8001658 <HAL_I2C_Init+0xa0>
+ 8001656: 687b ldr r3, [r7, #4]
+ 8001658: 68db ldr r3, [r3, #12]
+ 800165a: 2b02 cmp r3, #2
+ 800165c: d104 bne.n 8001668 <HAL_I2C_Init+0xa0>
{
hi2c->Instance->CR2 = (I2C_CR2_ADD10);
- 800164e: 687b ldr r3, [r7, #4]
- 8001650: 681b ldr r3, [r3, #0]
- 8001652: 2280 movs r2, #128 ; 0x80
- 8001654: 0112 lsls r2, r2, #4
- 8001656: 605a str r2, [r3, #4]
+ 800165e: 687b ldr r3, [r7, #4]
+ 8001660: 681b ldr r3, [r3, #0]
+ 8001662: 2280 movs r2, #128 ; 0x80
+ 8001664: 0112 lsls r2, r2, #4
+ 8001666: 605a str r2, [r3, #4]
}
/* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */
hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK);
- 8001658: 687b ldr r3, [r7, #4]
- 800165a: 681b ldr r3, [r3, #0]
- 800165c: 685a ldr r2, [r3, #4]
- 800165e: 687b ldr r3, [r7, #4]
- 8001660: 681b ldr r3, [r3, #0]
- 8001662: 491f ldr r1, [pc, #124] ; (80016e0 <HAL_I2C_Init+0x128>)
- 8001664: 430a orrs r2, r1
- 8001666: 605a str r2, [r3, #4]
+ 8001668: 687b ldr r3, [r7, #4]
+ 800166a: 681b ldr r3, [r3, #0]
+ 800166c: 685a ldr r2, [r3, #4]
+ 800166e: 687b ldr r3, [r7, #4]
+ 8001670: 681b ldr r3, [r3, #0]
+ 8001672: 491f ldr r1, [pc, #124] ; (80016f0 <HAL_I2C_Init+0x128>)
+ 8001674: 430a orrs r2, r1
+ 8001676: 605a str r2, [r3, #4]
/*---------------------------- I2Cx OAR2 Configuration ---------------------*/
/* Disable Own Address2 before set the Own Address2 configuration */
hi2c->Instance->OAR2 &= ~I2C_DUALADDRESS_ENABLE;
- 8001668: 687b ldr r3, [r7, #4]
- 800166a: 681b ldr r3, [r3, #0]
- 800166c: 68da ldr r2, [r3, #12]
- 800166e: 687b ldr r3, [r7, #4]
- 8001670: 681b ldr r3, [r3, #0]
- 8001672: 491a ldr r1, [pc, #104] ; (80016dc <HAL_I2C_Init+0x124>)
- 8001674: 400a ands r2, r1
- 8001676: 60da str r2, [r3, #12]
+ 8001678: 687b ldr r3, [r7, #4]
+ 800167a: 681b ldr r3, [r3, #0]
+ 800167c: 68da ldr r2, [r3, #12]
+ 800167e: 687b ldr r3, [r7, #4]
+ 8001680: 681b ldr r3, [r3, #0]
+ 8001682: 491a ldr r1, [pc, #104] ; (80016ec <HAL_I2C_Init+0x124>)
+ 8001684: 400a ands r2, r1
+ 8001686: 60da str r2, [r3, #12]
/* Configure I2Cx: Dual mode and Own Address2 */
hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | \
- 8001678: 687b ldr r3, [r7, #4]
- 800167a: 691a ldr r2, [r3, #16]
- 800167c: 687b ldr r3, [r7, #4]
- 800167e: 695b ldr r3, [r3, #20]
- 8001680: 431a orrs r2, r3
- 8001682: 0011 movs r1, r2
+ 8001688: 687b ldr r3, [r7, #4]
+ 800168a: 691a ldr r2, [r3, #16]
+ 800168c: 687b ldr r3, [r7, #4]
+ 800168e: 695b ldr r3, [r3, #20]
+ 8001690: 431a orrs r2, r3
+ 8001692: 0011 movs r1, r2
(hi2c->Init.OwnAddress2Masks << 8));
- 8001684: 687b ldr r3, [r7, #4]
- 8001686: 699b ldr r3, [r3, #24]
- 8001688: 021a lsls r2, r3, #8
+ 8001694: 687b ldr r3, [r7, #4]
+ 8001696: 699b ldr r3, [r3, #24]
+ 8001698: 021a lsls r2, r3, #8
hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | \
- 800168a: 687b ldr r3, [r7, #4]
- 800168c: 681b ldr r3, [r3, #0]
- 800168e: 430a orrs r2, r1
- 8001690: 60da str r2, [r3, #12]
+ 800169a: 687b ldr r3, [r7, #4]
+ 800169c: 681b ldr r3, [r3, #0]
+ 800169e: 430a orrs r2, r1
+ 80016a0: 60da str r2, [r3, #12]
/*---------------------------- I2Cx CR1 Configuration ----------------------*/
/* Configure I2Cx: Generalcall and NoStretch mode */
hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode);
- 8001692: 687b ldr r3, [r7, #4]
- 8001694: 69d9 ldr r1, [r3, #28]
- 8001696: 687b ldr r3, [r7, #4]
- 8001698: 6a1a ldr r2, [r3, #32]
- 800169a: 687b ldr r3, [r7, #4]
- 800169c: 681b ldr r3, [r3, #0]
- 800169e: 430a orrs r2, r1
- 80016a0: 601a str r2, [r3, #0]
-
- /* Enable the selected I2C peripheral */
- __HAL_I2C_ENABLE(hi2c);
80016a2: 687b ldr r3, [r7, #4]
- 80016a4: 681b ldr r3, [r3, #0]
- 80016a6: 681a ldr r2, [r3, #0]
- 80016a8: 687b ldr r3, [r7, #4]
- 80016aa: 681b ldr r3, [r3, #0]
- 80016ac: 2101 movs r1, #1
+ 80016a4: 69d9 ldr r1, [r3, #28]
+ 80016a6: 687b ldr r3, [r7, #4]
+ 80016a8: 6a1a ldr r2, [r3, #32]
+ 80016aa: 687b ldr r3, [r7, #4]
+ 80016ac: 681b ldr r3, [r3, #0]
80016ae: 430a orrs r2, r1
80016b0: 601a str r2, [r3, #0]
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+ /* Enable the selected I2C peripheral */
+ __HAL_I2C_ENABLE(hi2c);
80016b2: 687b ldr r3, [r7, #4]
- 80016b4: 2200 movs r2, #0
- 80016b6: 645a str r2, [r3, #68] ; 0x44
- hi2c->State = HAL_I2C_STATE_READY;
+ 80016b4: 681b ldr r3, [r3, #0]
+ 80016b6: 681a ldr r2, [r3, #0]
80016b8: 687b ldr r3, [r7, #4]
- 80016ba: 2241 movs r2, #65 ; 0x41
- 80016bc: 2120 movs r1, #32
- 80016be: 5499 strb r1, [r3, r2]
+ 80016ba: 681b ldr r3, [r3, #0]
+ 80016bc: 2101 movs r1, #1
+ 80016be: 430a orrs r2, r1
+ 80016c0: 601a str r2, [r3, #0]
+
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+ 80016c2: 687b ldr r3, [r7, #4]
+ 80016c4: 2200 movs r2, #0
+ 80016c6: 645a str r2, [r3, #68] ; 0x44
+ hi2c->State = HAL_I2C_STATE_READY;
+ 80016c8: 687b ldr r3, [r7, #4]
+ 80016ca: 2241 movs r2, #65 ; 0x41
+ 80016cc: 2120 movs r1, #32
+ 80016ce: 5499 strb r1, [r3, r2]
hi2c->PreviousState = I2C_STATE_NONE;
- 80016c0: 687b ldr r3, [r7, #4]
- 80016c2: 2200 movs r2, #0
- 80016c4: 631a str r2, [r3, #48] ; 0x30
+ 80016d0: 687b ldr r3, [r7, #4]
+ 80016d2: 2200 movs r2, #0
+ 80016d4: 631a str r2, [r3, #48] ; 0x30
hi2c->Mode = HAL_I2C_MODE_NONE;
- 80016c6: 687b ldr r3, [r7, #4]
- 80016c8: 2242 movs r2, #66 ; 0x42
- 80016ca: 2100 movs r1, #0
- 80016cc: 5499 strb r1, [r3, r2]
+ 80016d6: 687b ldr r3, [r7, #4]
+ 80016d8: 2242 movs r2, #66 ; 0x42
+ 80016da: 2100 movs r1, #0
+ 80016dc: 5499 strb r1, [r3, r2]
return HAL_OK;
- 80016ce: 2300 movs r3, #0
+ 80016de: 2300 movs r3, #0
}
- 80016d0: 0018 movs r0, r3
- 80016d2: 46bd mov sp, r7
- 80016d4: b002 add sp, #8
- 80016d6: bd80 pop {r7, pc}
- 80016d8: f0ffffff .word 0xf0ffffff
- 80016dc: ffff7fff .word 0xffff7fff
- 80016e0: 02008000 .word 0x02008000
+ 80016e0: 0018 movs r0, r3
+ 80016e2: 46bd mov sp, r7
+ 80016e4: b002 add sp, #8
+ 80016e6: bd80 pop {r7, pc}
+ 80016e8: f0ffffff .word 0xf0ffffff
+ 80016ec: ffff7fff .word 0xffff7fff
+ 80016f0: 02008000 .word 0x02008000
-080016e4 <HAL_I2C_Master_Transmit>:
+080016f4 <HAL_I2C_Master_Transmit>:
* @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
uint16_t Size, uint32_t Timeout)
{
- 80016e4: b590 push {r4, r7, lr}
- 80016e6: b089 sub sp, #36 ; 0x24
- 80016e8: af02 add r7, sp, #8
- 80016ea: 60f8 str r0, [r7, #12]
- 80016ec: 0008 movs r0, r1
- 80016ee: 607a str r2, [r7, #4]
- 80016f0: 0019 movs r1, r3
- 80016f2: 230a movs r3, #10
- 80016f4: 18fb adds r3, r7, r3
- 80016f6: 1c02 adds r2, r0, #0
- 80016f8: 801a strh r2, [r3, #0]
- 80016fa: 2308 movs r3, #8
- 80016fc: 18fb adds r3, r7, r3
- 80016fe: 1c0a adds r2, r1, #0
- 8001700: 801a strh r2, [r3, #0]
+ 80016f4: b590 push {r4, r7, lr}
+ 80016f6: b089 sub sp, #36 ; 0x24
+ 80016f8: af02 add r7, sp, #8
+ 80016fa: 60f8 str r0, [r7, #12]
+ 80016fc: 0008 movs r0, r1
+ 80016fe: 607a str r2, [r7, #4]
+ 8001700: 0019 movs r1, r3
+ 8001702: 230a movs r3, #10
+ 8001704: 18fb adds r3, r7, r3
+ 8001706: 1c02 adds r2, r0, #0
+ 8001708: 801a strh r2, [r3, #0]
+ 800170a: 2308 movs r3, #8
+ 800170c: 18fb adds r3, r7, r3
+ 800170e: 1c0a adds r2, r1, #0
+ 8001710: 801a strh r2, [r3, #0]
uint32_t tickstart;
if (hi2c->State == HAL_I2C_STATE_READY)
- 8001702: 68fb ldr r3, [r7, #12]
- 8001704: 2241 movs r2, #65 ; 0x41
- 8001706: 5c9b ldrb r3, [r3, r2]
- 8001708: b2db uxtb r3, r3
- 800170a: 2b20 cmp r3, #32
- 800170c: d000 beq.n 8001710 <HAL_I2C_Master_Transmit+0x2c>
- 800170e: e0e7 b.n 80018e0 <HAL_I2C_Master_Transmit+0x1fc>
+ 8001712: 68fb ldr r3, [r7, #12]
+ 8001714: 2241 movs r2, #65 ; 0x41
+ 8001716: 5c9b ldrb r3, [r3, r2]
+ 8001718: b2db uxtb r3, r3
+ 800171a: 2b20 cmp r3, #32
+ 800171c: d000 beq.n 8001720 <HAL_I2C_Master_Transmit+0x2c>
+ 800171e: e0e7 b.n 80018f0 <HAL_I2C_Master_Transmit+0x1fc>
{
/* Process Locked */
__HAL_LOCK(hi2c);
- 8001710: 68fb ldr r3, [r7, #12]
- 8001712: 2240 movs r2, #64 ; 0x40
- 8001714: 5c9b ldrb r3, [r3, r2]
- 8001716: 2b01 cmp r3, #1
- 8001718: d101 bne.n 800171e <HAL_I2C_Master_Transmit+0x3a>
- 800171a: 2302 movs r3, #2
- 800171c: e0e1 b.n 80018e2 <HAL_I2C_Master_Transmit+0x1fe>
- 800171e: 68fb ldr r3, [r7, #12]
- 8001720: 2240 movs r2, #64 ; 0x40
- 8001722: 2101 movs r1, #1
- 8001724: 5499 strb r1, [r3, r2]
+ 8001720: 68fb ldr r3, [r7, #12]
+ 8001722: 2240 movs r2, #64 ; 0x40
+ 8001724: 5c9b ldrb r3, [r3, r2]
+ 8001726: 2b01 cmp r3, #1
+ 8001728: d101 bne.n 800172e <HAL_I2C_Master_Transmit+0x3a>
+ 800172a: 2302 movs r3, #2
+ 800172c: e0e1 b.n 80018f2 <HAL_I2C_Master_Transmit+0x1fe>
+ 800172e: 68fb ldr r3, [r7, #12]
+ 8001730: 2240 movs r2, #64 ; 0x40
+ 8001732: 2101 movs r1, #1
+ 8001734: 5499 strb r1, [r3, r2]
/* Init tickstart for timeout management*/
tickstart = HAL_GetTick();
- 8001726: f7ff fcf7 bl 8001118 <HAL_GetTick>
- 800172a: 0003 movs r3, r0
- 800172c: 617b str r3, [r7, #20]
+ 8001736: f7ff fcf7 bl 8001128 <HAL_GetTick>
+ 800173a: 0003 movs r3, r0
+ 800173c: 617b str r3, [r7, #20]
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
- 800172e: 2380 movs r3, #128 ; 0x80
- 8001730: 0219 lsls r1, r3, #8
- 8001732: 68f8 ldr r0, [r7, #12]
- 8001734: 697b ldr r3, [r7, #20]
- 8001736: 9300 str r3, [sp, #0]
- 8001738: 2319 movs r3, #25
- 800173a: 2201 movs r2, #1
- 800173c: f000 fb9a bl 8001e74 <I2C_WaitOnFlagUntilTimeout>
- 8001740: 1e03 subs r3, r0, #0
- 8001742: d001 beq.n 8001748 <HAL_I2C_Master_Transmit+0x64>
+ 800173e: 2380 movs r3, #128 ; 0x80
+ 8001740: 0219 lsls r1, r3, #8
+ 8001742: 68f8 ldr r0, [r7, #12]
+ 8001744: 697b ldr r3, [r7, #20]
+ 8001746: 9300 str r3, [sp, #0]
+ 8001748: 2319 movs r3, #25
+ 800174a: 2201 movs r2, #1
+ 800174c: f000 fb9a bl 8001e84 <I2C_WaitOnFlagUntilTimeout>
+ 8001750: 1e03 subs r3, r0, #0
+ 8001752: d001 beq.n 8001758 <HAL_I2C_Master_Transmit+0x64>
{
return HAL_ERROR;
- 8001744: 2301 movs r3, #1
- 8001746: e0cc b.n 80018e2 <HAL_I2C_Master_Transmit+0x1fe>
+ 8001754: 2301 movs r3, #1
+ 8001756: e0cc b.n 80018f2 <HAL_I2C_Master_Transmit+0x1fe>
}
hi2c->State = HAL_I2C_STATE_BUSY_TX;
- 8001748: 68fb ldr r3, [r7, #12]
- 800174a: 2241 movs r2, #65 ; 0x41
- 800174c: 2121 movs r1, #33 ; 0x21
- 800174e: 5499 strb r1, [r3, r2]
- hi2c->Mode = HAL_I2C_MODE_MASTER;
- 8001750: 68fb ldr r3, [r7, #12]
- 8001752: 2242 movs r2, #66 ; 0x42
- 8001754: 2110 movs r1, #16
- 8001756: 5499 strb r1, [r3, r2]
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
8001758: 68fb ldr r3, [r7, #12]
- 800175a: 2200 movs r2, #0
- 800175c: 645a str r2, [r3, #68] ; 0x44
+ 800175a: 2241 movs r2, #65 ; 0x41
+ 800175c: 2121 movs r1, #33 ; 0x21
+ 800175e: 5499 strb r1, [r3, r2]
+ hi2c->Mode = HAL_I2C_MODE_MASTER;
+ 8001760: 68fb ldr r3, [r7, #12]
+ 8001762: 2242 movs r2, #66 ; 0x42
+ 8001764: 2110 movs r1, #16
+ 8001766: 5499 strb r1, [r3, r2]
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+ 8001768: 68fb ldr r3, [r7, #12]
+ 800176a: 2200 movs r2, #0
+ 800176c: 645a str r2, [r3, #68] ; 0x44
/* Prepare transfer parameters */
hi2c->pBuffPtr = pData;
- 800175e: 68fb ldr r3, [r7, #12]
- 8001760: 687a ldr r2, [r7, #4]
- 8001762: 625a str r2, [r3, #36] ; 0x24
- hi2c->XferCount = Size;
- 8001764: 68fb ldr r3, [r7, #12]
- 8001766: 2208 movs r2, #8
- 8001768: 18ba adds r2, r7, r2
- 800176a: 8812 ldrh r2, [r2, #0]
- 800176c: 855a strh r2, [r3, #42] ; 0x2a
- hi2c->XferISR = NULL;
800176e: 68fb ldr r3, [r7, #12]
- 8001770: 2200 movs r2, #0
- 8001772: 635a str r2, [r3, #52] ; 0x34
+ 8001770: 687a ldr r2, [r7, #4]
+ 8001772: 625a str r2, [r3, #36] ; 0x24
+ hi2c->XferCount = Size;
+ 8001774: 68fb ldr r3, [r7, #12]
+ 8001776: 2208 movs r2, #8
+ 8001778: 18ba adds r2, r7, r2
+ 800177a: 8812 ldrh r2, [r2, #0]
+ 800177c: 855a strh r2, [r3, #42] ; 0x2a
+ hi2c->XferISR = NULL;
+ 800177e: 68fb ldr r3, [r7, #12]
+ 8001780: 2200 movs r2, #0
+ 8001782: 635a str r2, [r3, #52] ; 0x34
/* Send Slave Address */
/* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
if (hi2c->XferCount > MAX_NBYTE_SIZE)
- 8001774: 68fb ldr r3, [r7, #12]
- 8001776: 8d5b ldrh r3, [r3, #42] ; 0x2a
- 8001778: b29b uxth r3, r3
- 800177a: 2bff cmp r3, #255 ; 0xff
- 800177c: d911 bls.n 80017a2 <HAL_I2C_Master_Transmit+0xbe>
+ 8001784: 68fb ldr r3, [r7, #12]
+ 8001786: 8d5b ldrh r3, [r3, #42] ; 0x2a
+ 8001788: b29b uxth r3, r3
+ 800178a: 2bff cmp r3, #255 ; 0xff
+ 800178c: d911 bls.n 80017b2 <HAL_I2C_Master_Transmit+0xbe>
{
hi2c->XferSize = MAX_NBYTE_SIZE;
- 800177e: 68fb ldr r3, [r7, #12]
- 8001780: 22ff movs r2, #255 ; 0xff
- 8001782: 851a strh r2, [r3, #40] ; 0x28
+ 800178e: 68fb ldr r3, [r7, #12]
+ 8001790: 22ff movs r2, #255 ; 0xff
+ 8001792: 851a strh r2, [r3, #40] ; 0x28
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
- 8001784: 68fb ldr r3, [r7, #12]
- 8001786: 8d1b ldrh r3, [r3, #40] ; 0x28
- 8001788: b2da uxtb r2, r3
- 800178a: 2380 movs r3, #128 ; 0x80
- 800178c: 045c lsls r4, r3, #17
- 800178e: 230a movs r3, #10
- 8001790: 18fb adds r3, r7, r3
- 8001792: 8819 ldrh r1, [r3, #0]
- 8001794: 68f8 ldr r0, [r7, #12]
- 8001796: 4b55 ldr r3, [pc, #340] ; (80018ec <HAL_I2C_Master_Transmit+0x208>)
- 8001798: 9300 str r3, [sp, #0]
- 800179a: 0023 movs r3, r4
- 800179c: f000 fd0a bl 80021b4 <I2C_TransferConfig>
- 80017a0: e075 b.n 800188e <HAL_I2C_Master_Transmit+0x1aa>
+ 8001794: 68fb ldr r3, [r7, #12]
+ 8001796: 8d1b ldrh r3, [r3, #40] ; 0x28
+ 8001798: b2da uxtb r2, r3
+ 800179a: 2380 movs r3, #128 ; 0x80
+ 800179c: 045c lsls r4, r3, #17
+ 800179e: 230a movs r3, #10
+ 80017a0: 18fb adds r3, r7, r3
+ 80017a2: 8819 ldrh r1, [r3, #0]
+ 80017a4: 68f8 ldr r0, [r7, #12]
+ 80017a6: 4b55 ldr r3, [pc, #340] ; (80018fc <HAL_I2C_Master_Transmit+0x208>)
+ 80017a8: 9300 str r3, [sp, #0]
+ 80017aa: 0023 movs r3, r4
+ 80017ac: f000 fd0a bl 80021c4 <I2C_TransferConfig>
+ 80017b0: e075 b.n 800189e <HAL_I2C_Master_Transmit+0x1aa>
I2C_GENERATE_START_WRITE);
}
else
{
hi2c->XferSize = hi2c->XferCount;
- 80017a2: 68fb ldr r3, [r7, #12]
- 80017a4: 8d5b ldrh r3, [r3, #42] ; 0x2a
- 80017a6: b29a uxth r2, r3
- 80017a8: 68fb ldr r3, [r7, #12]
- 80017aa: 851a strh r2, [r3, #40] ; 0x28
+ 80017b2: 68fb ldr r3, [r7, #12]
+ 80017b4: 8d5b ldrh r3, [r3, #42] ; 0x2a
+ 80017b6: b29a uxth r2, r3
+ 80017b8: 68fb ldr r3, [r7, #12]
+ 80017ba: 851a strh r2, [r3, #40] ; 0x28
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
- 80017ac: 68fb ldr r3, [r7, #12]
- 80017ae: 8d1b ldrh r3, [r3, #40] ; 0x28
- 80017b0: b2da uxtb r2, r3
- 80017b2: 2380 movs r3, #128 ; 0x80
- 80017b4: 049c lsls r4, r3, #18
- 80017b6: 230a movs r3, #10
- 80017b8: 18fb adds r3, r7, r3
- 80017ba: 8819 ldrh r1, [r3, #0]
- 80017bc: 68f8 ldr r0, [r7, #12]
- 80017be: 4b4b ldr r3, [pc, #300] ; (80018ec <HAL_I2C_Master_Transmit+0x208>)
- 80017c0: 9300 str r3, [sp, #0]
- 80017c2: 0023 movs r3, r4
- 80017c4: f000 fcf6 bl 80021b4 <I2C_TransferConfig>
+ 80017bc: 68fb ldr r3, [r7, #12]
+ 80017be: 8d1b ldrh r3, [r3, #40] ; 0x28
+ 80017c0: b2da uxtb r2, r3
+ 80017c2: 2380 movs r3, #128 ; 0x80
+ 80017c4: 049c lsls r4, r3, #18
+ 80017c6: 230a movs r3, #10
+ 80017c8: 18fb adds r3, r7, r3
+ 80017ca: 8819 ldrh r1, [r3, #0]
+ 80017cc: 68f8 ldr r0, [r7, #12]
+ 80017ce: 4b4b ldr r3, [pc, #300] ; (80018fc <HAL_I2C_Master_Transmit+0x208>)
+ 80017d0: 9300 str r3, [sp, #0]
+ 80017d2: 0023 movs r3, r4
+ 80017d4: f000 fcf6 bl 80021c4 <I2C_TransferConfig>
I2C_GENERATE_START_WRITE);
}
while (hi2c->XferCount > 0U)
- 80017c8: e061 b.n 800188e <HAL_I2C_Master_Transmit+0x1aa>
+ 80017d8: e061 b.n 800189e <HAL_I2C_Master_Transmit+0x1aa>
{
/* Wait until TXIS flag is set */
if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
- 80017ca: 697a ldr r2, [r7, #20]
- 80017cc: 6ab9 ldr r1, [r7, #40] ; 0x28
- 80017ce: 68fb ldr r3, [r7, #12]
- 80017d0: 0018 movs r0, r3
- 80017d2: f000 fb8e bl 8001ef2 <I2C_WaitOnTXISFlagUntilTimeout>
- 80017d6: 1e03 subs r3, r0, #0
- 80017d8: d001 beq.n 80017de <HAL_I2C_Master_Transmit+0xfa>
+ 80017da: 697a ldr r2, [r7, #20]
+ 80017dc: 6ab9 ldr r1, [r7, #40] ; 0x28
+ 80017de: 68fb ldr r3, [r7, #12]
+ 80017e0: 0018 movs r0, r3
+ 80017e2: f000 fb8e bl 8001f02 <I2C_WaitOnTXISFlagUntilTimeout>
+ 80017e6: 1e03 subs r3, r0, #0
+ 80017e8: d001 beq.n 80017ee <HAL_I2C_Master_Transmit+0xfa>
{
return HAL_ERROR;
- 80017da: 2301 movs r3, #1
- 80017dc: e081 b.n 80018e2 <HAL_I2C_Master_Transmit+0x1fe>
+ 80017ea: 2301 movs r3, #1
+ 80017ec: e081 b.n 80018f2 <HAL_I2C_Master_Transmit+0x1fe>
}
/* Write data to TXDR */
hi2c->Instance->TXDR = *hi2c->pBuffPtr;
- 80017de: 68fb ldr r3, [r7, #12]
- 80017e0: 6a5b ldr r3, [r3, #36] ; 0x24
- 80017e2: 781a ldrb r2, [r3, #0]
- 80017e4: 68fb ldr r3, [r7, #12]
- 80017e6: 681b ldr r3, [r3, #0]
- 80017e8: 629a str r2, [r3, #40] ; 0x28
+ 80017ee: 68fb ldr r3, [r7, #12]
+ 80017f0: 6a5b ldr r3, [r3, #36] ; 0x24
+ 80017f2: 781a ldrb r2, [r3, #0]
+ 80017f4: 68fb ldr r3, [r7, #12]
+ 80017f6: 681b ldr r3, [r3, #0]
+ 80017f8: 629a str r2, [r3, #40] ; 0x28
/* Increment Buffer pointer */
hi2c->pBuffPtr++;
- 80017ea: 68fb ldr r3, [r7, #12]
- 80017ec: 6a5b ldr r3, [r3, #36] ; 0x24
- 80017ee: 1c5a adds r2, r3, #1
- 80017f0: 68fb ldr r3, [r7, #12]
- 80017f2: 625a str r2, [r3, #36] ; 0x24
+ 80017fa: 68fb ldr r3, [r7, #12]
+ 80017fc: 6a5b ldr r3, [r3, #36] ; 0x24
+ 80017fe: 1c5a adds r2, r3, #1
+ 8001800: 68fb ldr r3, [r7, #12]
+ 8001802: 625a str r2, [r3, #36] ; 0x24
hi2c->XferCount--;
- 80017f4: 68fb ldr r3, [r7, #12]
- 80017f6: 8d5b ldrh r3, [r3, #42] ; 0x2a
- 80017f8: b29b uxth r3, r3
- 80017fa: 3b01 subs r3, #1
- 80017fc: b29a uxth r2, r3
- 80017fe: 68fb ldr r3, [r7, #12]
- 8001800: 855a strh r2, [r3, #42] ; 0x2a
+ 8001804: 68fb ldr r3, [r7, #12]
+ 8001806: 8d5b ldrh r3, [r3, #42] ; 0x2a
+ 8001808: b29b uxth r3, r3
+ 800180a: 3b01 subs r3, #1
+ 800180c: b29a uxth r2, r3
+ 800180e: 68fb ldr r3, [r7, #12]
+ 8001810: 855a strh r2, [r3, #42] ; 0x2a
hi2c->XferSize--;
- 8001802: 68fb ldr r3, [r7, #12]
- 8001804: 8d1b ldrh r3, [r3, #40] ; 0x28
- 8001806: 3b01 subs r3, #1
- 8001808: b29a uxth r2, r3
- 800180a: 68fb ldr r3, [r7, #12]
- 800180c: 851a strh r2, [r3, #40] ; 0x28
+ 8001812: 68fb ldr r3, [r7, #12]
+ 8001814: 8d1b ldrh r3, [r3, #40] ; 0x28
+ 8001816: 3b01 subs r3, #1
+ 8001818: b29a uxth r2, r3
+ 800181a: 68fb ldr r3, [r7, #12]
+ 800181c: 851a strh r2, [r3, #40] ; 0x28
if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
- 800180e: 68fb ldr r3, [r7, #12]
- 8001810: 8d5b ldrh r3, [r3, #42] ; 0x2a
- 8001812: b29b uxth r3, r3
- 8001814: 2b00 cmp r3, #0
- 8001816: d03a beq.n 800188e <HAL_I2C_Master_Transmit+0x1aa>
- 8001818: 68fb ldr r3, [r7, #12]
- 800181a: 8d1b ldrh r3, [r3, #40] ; 0x28
- 800181c: 2b00 cmp r3, #0
- 800181e: d136 bne.n 800188e <HAL_I2C_Master_Transmit+0x1aa>
+ 800181e: 68fb ldr r3, [r7, #12]
+ 8001820: 8d5b ldrh r3, [r3, #42] ; 0x2a
+ 8001822: b29b uxth r3, r3
+ 8001824: 2b00 cmp r3, #0
+ 8001826: d03a beq.n 800189e <HAL_I2C_Master_Transmit+0x1aa>
+ 8001828: 68fb ldr r3, [r7, #12]
+ 800182a: 8d1b ldrh r3, [r3, #40] ; 0x28
+ 800182c: 2b00 cmp r3, #0
+ 800182e: d136 bne.n 800189e <HAL_I2C_Master_Transmit+0x1aa>
{
/* Wait until TCR flag is set */
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
- 8001820: 6aba ldr r2, [r7, #40] ; 0x28
- 8001822: 68f8 ldr r0, [r7, #12]
- 8001824: 697b ldr r3, [r7, #20]
- 8001826: 9300 str r3, [sp, #0]
- 8001828: 0013 movs r3, r2
- 800182a: 2200 movs r2, #0
- 800182c: 2180 movs r1, #128 ; 0x80
- 800182e: f000 fb21 bl 8001e74 <I2C_WaitOnFlagUntilTimeout>
- 8001832: 1e03 subs r3, r0, #0
- 8001834: d001 beq.n 800183a <HAL_I2C_Master_Transmit+0x156>
+ 8001830: 6aba ldr r2, [r7, #40] ; 0x28
+ 8001832: 68f8 ldr r0, [r7, #12]
+ 8001834: 697b ldr r3, [r7, #20]
+ 8001836: 9300 str r3, [sp, #0]
+ 8001838: 0013 movs r3, r2
+ 800183a: 2200 movs r2, #0
+ 800183c: 2180 movs r1, #128 ; 0x80
+ 800183e: f000 fb21 bl 8001e84 <I2C_WaitOnFlagUntilTimeout>
+ 8001842: 1e03 subs r3, r0, #0
+ 8001844: d001 beq.n 800184a <HAL_I2C_Master_Transmit+0x156>
{
return HAL_ERROR;
- 8001836: 2301 movs r3, #1
- 8001838: e053 b.n 80018e2 <HAL_I2C_Master_Transmit+0x1fe>
+ 8001846: 2301 movs r3, #1
+ 8001848: e053 b.n 80018f2 <HAL_I2C_Master_Transmit+0x1fe>
}
if (hi2c->XferCount > MAX_NBYTE_SIZE)
- 800183a: 68fb ldr r3, [r7, #12]
- 800183c: 8d5b ldrh r3, [r3, #42] ; 0x2a
- 800183e: b29b uxth r3, r3
- 8001840: 2bff cmp r3, #255 ; 0xff
- 8001842: d911 bls.n 8001868 <HAL_I2C_Master_Transmit+0x184>
+ 800184a: 68fb ldr r3, [r7, #12]
+ 800184c: 8d5b ldrh r3, [r3, #42] ; 0x2a
+ 800184e: b29b uxth r3, r3
+ 8001850: 2bff cmp r3, #255 ; 0xff
+ 8001852: d911 bls.n 8001878 <HAL_I2C_Master_Transmit+0x184>
{
hi2c->XferSize = MAX_NBYTE_SIZE;
- 8001844: 68fb ldr r3, [r7, #12]
- 8001846: 22ff movs r2, #255 ; 0xff
- 8001848: 851a strh r2, [r3, #40] ; 0x28
+ 8001854: 68fb ldr r3, [r7, #12]
+ 8001856: 22ff movs r2, #255 ; 0xff
+ 8001858: 851a strh r2, [r3, #40] ; 0x28
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
- 800184a: 68fb ldr r3, [r7, #12]
- 800184c: 8d1b ldrh r3, [r3, #40] ; 0x28
- 800184e: b2da uxtb r2, r3
- 8001850: 2380 movs r3, #128 ; 0x80
- 8001852: 045c lsls r4, r3, #17
- 8001854: 230a movs r3, #10
- 8001856: 18fb adds r3, r7, r3
- 8001858: 8819 ldrh r1, [r3, #0]
- 800185a: 68f8 ldr r0, [r7, #12]
- 800185c: 2300 movs r3, #0
- 800185e: 9300 str r3, [sp, #0]
- 8001860: 0023 movs r3, r4
- 8001862: f000 fca7 bl 80021b4 <I2C_TransferConfig>
- 8001866: e012 b.n 800188e <HAL_I2C_Master_Transmit+0x1aa>
+ 800185a: 68fb ldr r3, [r7, #12]
+ 800185c: 8d1b ldrh r3, [r3, #40] ; 0x28
+ 800185e: b2da uxtb r2, r3
+ 8001860: 2380 movs r3, #128 ; 0x80
+ 8001862: 045c lsls r4, r3, #17
+ 8001864: 230a movs r3, #10
+ 8001866: 18fb adds r3, r7, r3
+ 8001868: 8819 ldrh r1, [r3, #0]
+ 800186a: 68f8 ldr r0, [r7, #12]
+ 800186c: 2300 movs r3, #0
+ 800186e: 9300 str r3, [sp, #0]
+ 8001870: 0023 movs r3, r4
+ 8001872: f000 fca7 bl 80021c4 <I2C_TransferConfig>
+ 8001876: e012 b.n 800189e <HAL_I2C_Master_Transmit+0x1aa>
I2C_NO_STARTSTOP);
}
else
{
hi2c->XferSize = hi2c->XferCount;
- 8001868: 68fb ldr r3, [r7, #12]
- 800186a: 8d5b ldrh r3, [r3, #42] ; 0x2a
- 800186c: b29a uxth r2, r3
- 800186e: 68fb ldr r3, [r7, #12]
- 8001870: 851a strh r2, [r3, #40] ; 0x28
+ 8001878: 68fb ldr r3, [r7, #12]
+ 800187a: 8d5b ldrh r3, [r3, #42] ; 0x2a
+ 800187c: b29a uxth r2, r3
+ 800187e: 68fb ldr r3, [r7, #12]
+ 8001880: 851a strh r2, [r3, #40] ; 0x28
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
- 8001872: 68fb ldr r3, [r7, #12]
- 8001874: 8d1b ldrh r3, [r3, #40] ; 0x28
- 8001876: b2da uxtb r2, r3
- 8001878: 2380 movs r3, #128 ; 0x80
- 800187a: 049c lsls r4, r3, #18
- 800187c: 230a movs r3, #10
- 800187e: 18fb adds r3, r7, r3
- 8001880: 8819 ldrh r1, [r3, #0]
- 8001882: 68f8 ldr r0, [r7, #12]
- 8001884: 2300 movs r3, #0
- 8001886: 9300 str r3, [sp, #0]
- 8001888: 0023 movs r3, r4
- 800188a: f000 fc93 bl 80021b4 <I2C_TransferConfig>
+ 8001882: 68fb ldr r3, [r7, #12]
+ 8001884: 8d1b ldrh r3, [r3, #40] ; 0x28
+ 8001886: b2da uxtb r2, r3
+ 8001888: 2380 movs r3, #128 ; 0x80
+ 800188a: 049c lsls r4, r3, #18
+ 800188c: 230a movs r3, #10
+ 800188e: 18fb adds r3, r7, r3
+ 8001890: 8819 ldrh r1, [r3, #0]
+ 8001892: 68f8 ldr r0, [r7, #12]
+ 8001894: 2300 movs r3, #0
+ 8001896: 9300 str r3, [sp, #0]
+ 8001898: 0023 movs r3, r4
+ 800189a: f000 fc93 bl 80021c4 <I2C_TransferConfig>
while (hi2c->XferCount > 0U)
- 800188e: 68fb ldr r3, [r7, #12]
- 8001890: 8d5b ldrh r3, [r3, #42] ; 0x2a
- 8001892: b29b uxth r3, r3
- 8001894: 2b00 cmp r3, #0
- 8001896: d198 bne.n 80017ca <HAL_I2C_Master_Transmit+0xe6>
+ 800189e: 68fb ldr r3, [r7, #12]
+ 80018a0: 8d5b ldrh r3, [r3, #42] ; 0x2a
+ 80018a2: b29b uxth r3, r3
+ 80018a4: 2b00 cmp r3, #0
+ 80018a6: d198 bne.n 80017da <HAL_I2C_Master_Transmit+0xe6>
}
}
/* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
/* Wait until STOPF flag is set */
if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
- 8001898: 697a ldr r2, [r7, #20]
- 800189a: 6ab9 ldr r1, [r7, #40] ; 0x28
- 800189c: 68fb ldr r3, [r7, #12]
- 800189e: 0018 movs r0, r3
- 80018a0: f000 fb66 bl 8001f70 <I2C_WaitOnSTOPFlagUntilTimeout>
- 80018a4: 1e03 subs r3, r0, #0
- 80018a6: d001 beq.n 80018ac <HAL_I2C_Master_Transmit+0x1c8>
+ 80018a8: 697a ldr r2, [r7, #20]
+ 80018aa: 6ab9 ldr r1, [r7, #40] ; 0x28
+ 80018ac: 68fb ldr r3, [r7, #12]
+ 80018ae: 0018 movs r0, r3
+ 80018b0: f000 fb66 bl 8001f80 <I2C_WaitOnSTOPFlagUntilTimeout>
+ 80018b4: 1e03 subs r3, r0, #0
+ 80018b6: d001 beq.n 80018bc <HAL_I2C_Master_Transmit+0x1c8>
{
return HAL_ERROR;
- 80018a8: 2301 movs r3, #1
- 80018aa: e01a b.n 80018e2 <HAL_I2C_Master_Transmit+0x1fe>
+ 80018b8: 2301 movs r3, #1
+ 80018ba: e01a b.n 80018f2 <HAL_I2C_Master_Transmit+0x1fe>
}
/* Clear STOP Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
- 80018ac: 68fb ldr r3, [r7, #12]
- 80018ae: 681b ldr r3, [r3, #0]
- 80018b0: 2220 movs r2, #32
- 80018b2: 61da str r2, [r3, #28]
+ 80018bc: 68fb ldr r3, [r7, #12]
+ 80018be: 681b ldr r3, [r3, #0]
+ 80018c0: 2220 movs r2, #32
+ 80018c2: 61da str r2, [r3, #28]
/* Clear Configuration Register 2 */
I2C_RESET_CR2(hi2c);
- 80018b4: 68fb ldr r3, [r7, #12]
- 80018b6: 681b ldr r3, [r3, #0]
- 80018b8: 685a ldr r2, [r3, #4]
- 80018ba: 68fb ldr r3, [r7, #12]
- 80018bc: 681b ldr r3, [r3, #0]
- 80018be: 490c ldr r1, [pc, #48] ; (80018f0 <HAL_I2C_Master_Transmit+0x20c>)
- 80018c0: 400a ands r2, r1
- 80018c2: 605a str r2, [r3, #4]
+ 80018c4: 68fb ldr r3, [r7, #12]
+ 80018c6: 681b ldr r3, [r3, #0]
+ 80018c8: 685a ldr r2, [r3, #4]
+ 80018ca: 68fb ldr r3, [r7, #12]
+ 80018cc: 681b ldr r3, [r3, #0]
+ 80018ce: 490c ldr r1, [pc, #48] ; (8001900 <HAL_I2C_Master_Transmit+0x20c>)
+ 80018d0: 400a ands r2, r1
+ 80018d2: 605a str r2, [r3, #4]
hi2c->State = HAL_I2C_STATE_READY;
- 80018c4: 68fb ldr r3, [r7, #12]
- 80018c6: 2241 movs r2, #65 ; 0x41
- 80018c8: 2120 movs r1, #32
- 80018ca: 5499 strb r1, [r3, r2]
+ 80018d4: 68fb ldr r3, [r7, #12]
+ 80018d6: 2241 movs r2, #65 ; 0x41
+ 80018d8: 2120 movs r1, #32
+ 80018da: 5499 strb r1, [r3, r2]
hi2c->Mode = HAL_I2C_MODE_NONE;
- 80018cc: 68fb ldr r3, [r7, #12]
- 80018ce: 2242 movs r2, #66 ; 0x42
- 80018d0: 2100 movs r1, #0
- 80018d2: 5499 strb r1, [r3, r2]
+ 80018dc: 68fb ldr r3, [r7, #12]
+ 80018de: 2242 movs r2, #66 ; 0x42
+ 80018e0: 2100 movs r1, #0
+ 80018e2: 5499 strb r1, [r3, r2]
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
- 80018d4: 68fb ldr r3, [r7, #12]
- 80018d6: 2240 movs r2, #64 ; 0x40
- 80018d8: 2100 movs r1, #0
- 80018da: 5499 strb r1, [r3, r2]
+ 80018e4: 68fb ldr r3, [r7, #12]
+ 80018e6: 2240 movs r2, #64 ; 0x40
+ 80018e8: 2100 movs r1, #0
+ 80018ea: 5499 strb r1, [r3, r2]
return HAL_OK;
- 80018dc: 2300 movs r3, #0
- 80018de: e000 b.n 80018e2 <HAL_I2C_Master_Transmit+0x1fe>
+ 80018ec: 2300 movs r3, #0
+ 80018ee: e000 b.n 80018f2 <HAL_I2C_Master_Transmit+0x1fe>
}
else
{
return HAL_BUSY;
- 80018e0: 2302 movs r3, #2
+ 80018f0: 2302 movs r3, #2
}
}
- 80018e2: 0018 movs r0, r3
- 80018e4: 46bd mov sp, r7
- 80018e6: b007 add sp, #28
- 80018e8: bd90 pop {r4, r7, pc}
- 80018ea: 46c0 nop ; (mov r8, r8)
- 80018ec: 80002000 .word 0x80002000
- 80018f0: fe00e800 .word 0xfe00e800
+ 80018f2: 0018 movs r0, r3
+ 80018f4: 46bd mov sp, r7
+ 80018f6: b007 add sp, #28
+ 80018f8: bd90 pop {r4, r7, pc}
+ 80018fa: 46c0 nop ; (mov r8, r8)
+ 80018fc: 80002000 .word 0x80002000
+ 8001900: fe00e800 .word 0xfe00e800
-080018f4 <HAL_I2C_Master_Receive>:
+08001904 <HAL_I2C_Master_Receive>:
* @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
uint16_t Size, uint32_t Timeout)
{
- 80018f4: b590 push {r4, r7, lr}
- 80018f6: b089 sub sp, #36 ; 0x24
- 80018f8: af02 add r7, sp, #8
- 80018fa: 60f8 str r0, [r7, #12]
- 80018fc: 0008 movs r0, r1
- 80018fe: 607a str r2, [r7, #4]
- 8001900: 0019 movs r1, r3
- 8001902: 230a movs r3, #10
- 8001904: 18fb adds r3, r7, r3
- 8001906: 1c02 adds r2, r0, #0
- 8001908: 801a strh r2, [r3, #0]
- 800190a: 2308 movs r3, #8
- 800190c: 18fb adds r3, r7, r3
- 800190e: 1c0a adds r2, r1, #0
- 8001910: 801a strh r2, [r3, #0]
+ 8001904: b590 push {r4, r7, lr}
+ 8001906: b089 sub sp, #36 ; 0x24
+ 8001908: af02 add r7, sp, #8
+ 800190a: 60f8 str r0, [r7, #12]
+ 800190c: 0008 movs r0, r1
+ 800190e: 607a str r2, [r7, #4]
+ 8001910: 0019 movs r1, r3
+ 8001912: 230a movs r3, #10
+ 8001914: 18fb adds r3, r7, r3
+ 8001916: 1c02 adds r2, r0, #0
+ 8001918: 801a strh r2, [r3, #0]
+ 800191a: 2308 movs r3, #8
+ 800191c: 18fb adds r3, r7, r3
+ 800191e: 1c0a adds r2, r1, #0
+ 8001920: 801a strh r2, [r3, #0]
uint32_t tickstart;
if (hi2c->State == HAL_I2C_STATE_READY)
- 8001912: 68fb ldr r3, [r7, #12]
- 8001914: 2241 movs r2, #65 ; 0x41
- 8001916: 5c9b ldrb r3, [r3, r2]
- 8001918: b2db uxtb r3, r3
- 800191a: 2b20 cmp r3, #32
- 800191c: d000 beq.n 8001920 <HAL_I2C_Master_Receive+0x2c>
- 800191e: e0e8 b.n 8001af2 <HAL_I2C_Master_Receive+0x1fe>
+ 8001922: 68fb ldr r3, [r7, #12]
+ 8001924: 2241 movs r2, #65 ; 0x41
+ 8001926: 5c9b ldrb r3, [r3, r2]
+ 8001928: b2db uxtb r3, r3
+ 800192a: 2b20 cmp r3, #32
+ 800192c: d000 beq.n 8001930 <HAL_I2C_Master_Receive+0x2c>
+ 800192e: e0e8 b.n 8001b02 <HAL_I2C_Master_Receive+0x1fe>
{
/* Process Locked */
__HAL_LOCK(hi2c);
- 8001920: 68fb ldr r3, [r7, #12]
- 8001922: 2240 movs r2, #64 ; 0x40
- 8001924: 5c9b ldrb r3, [r3, r2]
- 8001926: 2b01 cmp r3, #1
- 8001928: d101 bne.n 800192e <HAL_I2C_Master_Receive+0x3a>
- 800192a: 2302 movs r3, #2
- 800192c: e0e2 b.n 8001af4 <HAL_I2C_Master_Receive+0x200>
- 800192e: 68fb ldr r3, [r7, #12]
- 8001930: 2240 movs r2, #64 ; 0x40
- 8001932: 2101 movs r1, #1
- 8001934: 5499 strb r1, [r3, r2]
+ 8001930: 68fb ldr r3, [r7, #12]
+ 8001932: 2240 movs r2, #64 ; 0x40
+ 8001934: 5c9b ldrb r3, [r3, r2]
+ 8001936: 2b01 cmp r3, #1
+ 8001938: d101 bne.n 800193e <HAL_I2C_Master_Receive+0x3a>
+ 800193a: 2302 movs r3, #2
+ 800193c: e0e2 b.n 8001b04 <HAL_I2C_Master_Receive+0x200>
+ 800193e: 68fb ldr r3, [r7, #12]
+ 8001940: 2240 movs r2, #64 ; 0x40
+ 8001942: 2101 movs r1, #1
+ 8001944: 5499 strb r1, [r3, r2]
/* Init tickstart for timeout management*/
tickstart = HAL_GetTick();
- 8001936: f7ff fbef bl 8001118 <HAL_GetTick>
- 800193a: 0003 movs r3, r0
- 800193c: 617b str r3, [r7, #20]
+ 8001946: f7ff fbef bl 8001128 <HAL_GetTick>
+ 800194a: 0003 movs r3, r0
+ 800194c: 617b str r3, [r7, #20]
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
- 800193e: 2380 movs r3, #128 ; 0x80
- 8001940: 0219 lsls r1, r3, #8
- 8001942: 68f8 ldr r0, [r7, #12]
- 8001944: 697b ldr r3, [r7, #20]
- 8001946: 9300 str r3, [sp, #0]
- 8001948: 2319 movs r3, #25
- 800194a: 2201 movs r2, #1
- 800194c: f000 fa92 bl 8001e74 <I2C_WaitOnFlagUntilTimeout>
- 8001950: 1e03 subs r3, r0, #0
- 8001952: d001 beq.n 8001958 <HAL_I2C_Master_Receive+0x64>
+ 800194e: 2380 movs r3, #128 ; 0x80
+ 8001950: 0219 lsls r1, r3, #8
+ 8001952: 68f8 ldr r0, [r7, #12]
+ 8001954: 697b ldr r3, [r7, #20]
+ 8001956: 9300 str r3, [sp, #0]
+ 8001958: 2319 movs r3, #25
+ 800195a: 2201 movs r2, #1
+ 800195c: f000 fa92 bl 8001e84 <I2C_WaitOnFlagUntilTimeout>
+ 8001960: 1e03 subs r3, r0, #0
+ 8001962: d001 beq.n 8001968 <HAL_I2C_Master_Receive+0x64>
{
return HAL_ERROR;
- 8001954: 2301 movs r3, #1
- 8001956: e0cd b.n 8001af4 <HAL_I2C_Master_Receive+0x200>
+ 8001964: 2301 movs r3, #1
+ 8001966: e0cd b.n 8001b04 <HAL_I2C_Master_Receive+0x200>
}
hi2c->State = HAL_I2C_STATE_BUSY_RX;
- 8001958: 68fb ldr r3, [r7, #12]
- 800195a: 2241 movs r2, #65 ; 0x41
- 800195c: 2122 movs r1, #34 ; 0x22
- 800195e: 5499 strb r1, [r3, r2]
- hi2c->Mode = HAL_I2C_MODE_MASTER;
- 8001960: 68fb ldr r3, [r7, #12]
- 8001962: 2242 movs r2, #66 ; 0x42
- 8001964: 2110 movs r1, #16
- 8001966: 5499 strb r1, [r3, r2]
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
8001968: 68fb ldr r3, [r7, #12]
- 800196a: 2200 movs r2, #0
- 800196c: 645a str r2, [r3, #68] ; 0x44
+ 800196a: 2241 movs r2, #65 ; 0x41
+ 800196c: 2122 movs r1, #34 ; 0x22
+ 800196e: 5499 strb r1, [r3, r2]
+ hi2c->Mode = HAL_I2C_MODE_MASTER;
+ 8001970: 68fb ldr r3, [r7, #12]
+ 8001972: 2242 movs r2, #66 ; 0x42
+ 8001974: 2110 movs r1, #16
+ 8001976: 5499 strb r1, [r3, r2]
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+ 8001978: 68fb ldr r3, [r7, #12]
+ 800197a: 2200 movs r2, #0
+ 800197c: 645a str r2, [r3, #68] ; 0x44
/* Prepare transfer parameters */
hi2c->pBuffPtr = pData;
- 800196e: 68fb ldr r3, [r7, #12]
- 8001970: 687a ldr r2, [r7, #4]
- 8001972: 625a str r2, [r3, #36] ; 0x24
- hi2c->XferCount = Size;
- 8001974: 68fb ldr r3, [r7, #12]
- 8001976: 2208 movs r2, #8
- 8001978: 18ba adds r2, r7, r2
- 800197a: 8812 ldrh r2, [r2, #0]
- 800197c: 855a strh r2, [r3, #42] ; 0x2a
- hi2c->XferISR = NULL;
800197e: 68fb ldr r3, [r7, #12]
- 8001980: 2200 movs r2, #0
- 8001982: 635a str r2, [r3, #52] ; 0x34
+ 8001980: 687a ldr r2, [r7, #4]
+ 8001982: 625a str r2, [r3, #36] ; 0x24
+ hi2c->XferCount = Size;
+ 8001984: 68fb ldr r3, [r7, #12]
+ 8001986: 2208 movs r2, #8
+ 8001988: 18ba adds r2, r7, r2
+ 800198a: 8812 ldrh r2, [r2, #0]
+ 800198c: 855a strh r2, [r3, #42] ; 0x2a
+ hi2c->XferISR = NULL;
+ 800198e: 68fb ldr r3, [r7, #12]
+ 8001990: 2200 movs r2, #0
+ 8001992: 635a str r2, [r3, #52] ; 0x34
/* Send Slave Address */
/* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
if (hi2c->XferCount > MAX_NBYTE_SIZE)
- 8001984: 68fb ldr r3, [r7, #12]
- 8001986: 8d5b ldrh r3, [r3, #42] ; 0x2a
- 8001988: b29b uxth r3, r3
- 800198a: 2bff cmp r3, #255 ; 0xff
- 800198c: d911 bls.n 80019b2 <HAL_I2C_Master_Receive+0xbe>
+ 8001994: 68fb ldr r3, [r7, #12]
+ 8001996: 8d5b ldrh r3, [r3, #42] ; 0x2a
+ 8001998: b29b uxth r3, r3
+ 800199a: 2bff cmp r3, #255 ; 0xff
+ 800199c: d911 bls.n 80019c2 <HAL_I2C_Master_Receive+0xbe>
{
hi2c->XferSize = MAX_NBYTE_SIZE;
- 800198e: 68fb ldr r3, [r7, #12]
- 8001990: 22ff movs r2, #255 ; 0xff
- 8001992: 851a strh r2, [r3, #40] ; 0x28
+ 800199e: 68fb ldr r3, [r7, #12]
+ 80019a0: 22ff movs r2, #255 ; 0xff
+ 80019a2: 851a strh r2, [r3, #40] ; 0x28
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
- 8001994: 68fb ldr r3, [r7, #12]
- 8001996: 8d1b ldrh r3, [r3, #40] ; 0x28
- 8001998: b2da uxtb r2, r3
- 800199a: 2380 movs r3, #128 ; 0x80
- 800199c: 045c lsls r4, r3, #17
- 800199e: 230a movs r3, #10
- 80019a0: 18fb adds r3, r7, r3
- 80019a2: 8819 ldrh r1, [r3, #0]
- 80019a4: 68f8 ldr r0, [r7, #12]
- 80019a6: 4b55 ldr r3, [pc, #340] ; (8001afc <HAL_I2C_Master_Receive+0x208>)
- 80019a8: 9300 str r3, [sp, #0]
- 80019aa: 0023 movs r3, r4
- 80019ac: f000 fc02 bl 80021b4 <I2C_TransferConfig>
- 80019b0: e076 b.n 8001aa0 <HAL_I2C_Master_Receive+0x1ac>
+ 80019a4: 68fb ldr r3, [r7, #12]
+ 80019a6: 8d1b ldrh r3, [r3, #40] ; 0x28
+ 80019a8: b2da uxtb r2, r3
+ 80019aa: 2380 movs r3, #128 ; 0x80
+ 80019ac: 045c lsls r4, r3, #17
+ 80019ae: 230a movs r3, #10
+ 80019b0: 18fb adds r3, r7, r3
+ 80019b2: 8819 ldrh r1, [r3, #0]
+ 80019b4: 68f8 ldr r0, [r7, #12]
+ 80019b6: 4b55 ldr r3, [pc, #340] ; (8001b0c <HAL_I2C_Master_Receive+0x208>)
+ 80019b8: 9300 str r3, [sp, #0]
+ 80019ba: 0023 movs r3, r4
+ 80019bc: f000 fc02 bl 80021c4 <I2C_TransferConfig>
+ 80019c0: e076 b.n 8001ab0 <HAL_I2C_Master_Receive+0x1ac>
I2C_GENERATE_START_READ);
}
else
{
hi2c->XferSize = hi2c->XferCount;
- 80019b2: 68fb ldr r3, [r7, #12]
- 80019b4: 8d5b ldrh r3, [r3, #42] ; 0x2a
- 80019b6: b29a uxth r2, r3
- 80019b8: 68fb ldr r3, [r7, #12]
- 80019ba: 851a strh r2, [r3, #40] ; 0x28
+ 80019c2: 68fb ldr r3, [r7, #12]
+ 80019c4: 8d5b ldrh r3, [r3, #42] ; 0x2a
+ 80019c6: b29a uxth r2, r3
+ 80019c8: 68fb ldr r3, [r7, #12]
+ 80019ca: 851a strh r2, [r3, #40] ; 0x28
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
- 80019bc: 68fb ldr r3, [r7, #12]
- 80019be: 8d1b ldrh r3, [r3, #40] ; 0x28
- 80019c0: b2da uxtb r2, r3
- 80019c2: 2380 movs r3, #128 ; 0x80
- 80019c4: 049c lsls r4, r3, #18
- 80019c6: 230a movs r3, #10
- 80019c8: 18fb adds r3, r7, r3
- 80019ca: 8819 ldrh r1, [r3, #0]
- 80019cc: 68f8 ldr r0, [r7, #12]
- 80019ce: 4b4b ldr r3, [pc, #300] ; (8001afc <HAL_I2C_Master_Receive+0x208>)
- 80019d0: 9300 str r3, [sp, #0]
- 80019d2: 0023 movs r3, r4
- 80019d4: f000 fbee bl 80021b4 <I2C_TransferConfig>
+ 80019cc: 68fb ldr r3, [r7, #12]
+ 80019ce: 8d1b ldrh r3, [r3, #40] ; 0x28
+ 80019d0: b2da uxtb r2, r3
+ 80019d2: 2380 movs r3, #128 ; 0x80
+ 80019d4: 049c lsls r4, r3, #18
+ 80019d6: 230a movs r3, #10
+ 80019d8: 18fb adds r3, r7, r3
+ 80019da: 8819 ldrh r1, [r3, #0]
+ 80019dc: 68f8 ldr r0, [r7, #12]
+ 80019de: 4b4b ldr r3, [pc, #300] ; (8001b0c <HAL_I2C_Master_Receive+0x208>)
+ 80019e0: 9300 str r3, [sp, #0]
+ 80019e2: 0023 movs r3, r4
+ 80019e4: f000 fbee bl 80021c4 <I2C_TransferConfig>
I2C_GENERATE_START_READ);
}
while (hi2c->XferCount > 0U)
- 80019d8: e062 b.n 8001aa0 <HAL_I2C_Master_Receive+0x1ac>
+ 80019e8: e062 b.n 8001ab0 <HAL_I2C_Master_Receive+0x1ac>
{
/* Wait until RXNE flag is set */
if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
- 80019da: 697a ldr r2, [r7, #20]
- 80019dc: 6ab9 ldr r1, [r7, #40] ; 0x28
- 80019de: 68fb ldr r3, [r7, #12]
- 80019e0: 0018 movs r0, r3
- 80019e2: f000 fb01 bl 8001fe8 <I2C_WaitOnRXNEFlagUntilTimeout>
- 80019e6: 1e03 subs r3, r0, #0
- 80019e8: d001 beq.n 80019ee <HAL_I2C_Master_Receive+0xfa>
+ 80019ea: 697a ldr r2, [r7, #20]
+ 80019ec: 6ab9 ldr r1, [r7, #40] ; 0x28
+ 80019ee: 68fb ldr r3, [r7, #12]
+ 80019f0: 0018 movs r0, r3
+ 80019f2: f000 fb01 bl 8001ff8 <I2C_WaitOnRXNEFlagUntilTimeout>
+ 80019f6: 1e03 subs r3, r0, #0
+ 80019f8: d001 beq.n 80019fe <HAL_I2C_Master_Receive+0xfa>
{
return HAL_ERROR;
- 80019ea: 2301 movs r3, #1
- 80019ec: e082 b.n 8001af4 <HAL_I2C_Master_Receive+0x200>
+ 80019fa: 2301 movs r3, #1
+ 80019fc: e082 b.n 8001b04 <HAL_I2C_Master_Receive+0x200>
}
/* Read data from RXDR */
*hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
- 80019ee: 68fb ldr r3, [r7, #12]
- 80019f0: 681b ldr r3, [r3, #0]
- 80019f2: 6a5a ldr r2, [r3, #36] ; 0x24
- 80019f4: 68fb ldr r3, [r7, #12]
- 80019f6: 6a5b ldr r3, [r3, #36] ; 0x24
- 80019f8: b2d2 uxtb r2, r2
- 80019fa: 701a strb r2, [r3, #0]
+ 80019fe: 68fb ldr r3, [r7, #12]
+ 8001a00: 681b ldr r3, [r3, #0]
+ 8001a02: 6a5a ldr r2, [r3, #36] ; 0x24
+ 8001a04: 68fb ldr r3, [r7, #12]
+ 8001a06: 6a5b ldr r3, [r3, #36] ; 0x24
+ 8001a08: b2d2 uxtb r2, r2
+ 8001a0a: 701a strb r2, [r3, #0]
/* Increment Buffer pointer */
hi2c->pBuffPtr++;
- 80019fc: 68fb ldr r3, [r7, #12]
- 80019fe: 6a5b ldr r3, [r3, #36] ; 0x24
- 8001a00: 1c5a adds r2, r3, #1
- 8001a02: 68fb ldr r3, [r7, #12]
- 8001a04: 625a str r2, [r3, #36] ; 0x24
+ 8001a0c: 68fb ldr r3, [r7, #12]
+ 8001a0e: 6a5b ldr r3, [r3, #36] ; 0x24
+ 8001a10: 1c5a adds r2, r3, #1
+ 8001a12: 68fb ldr r3, [r7, #12]
+ 8001a14: 625a str r2, [r3, #36] ; 0x24
hi2c->XferSize--;
- 8001a06: 68fb ldr r3, [r7, #12]
- 8001a08: 8d1b ldrh r3, [r3, #40] ; 0x28
- 8001a0a: 3b01 subs r3, #1
- 8001a0c: b29a uxth r2, r3
- 8001a0e: 68fb ldr r3, [r7, #12]
- 8001a10: 851a strh r2, [r3, #40] ; 0x28
+ 8001a16: 68fb ldr r3, [r7, #12]
+ 8001a18: 8d1b ldrh r3, [r3, #40] ; 0x28
+ 8001a1a: 3b01 subs r3, #1
+ 8001a1c: b29a uxth r2, r3
+ 8001a1e: 68fb ldr r3, [r7, #12]
+ 8001a20: 851a strh r2, [r3, #40] ; 0x28
hi2c->XferCount--;
- 8001a12: 68fb ldr r3, [r7, #12]
- 8001a14: 8d5b ldrh r3, [r3, #42] ; 0x2a
- 8001a16: b29b uxth r3, r3
- 8001a18: 3b01 subs r3, #1
- 8001a1a: b29a uxth r2, r3
- 8001a1c: 68fb ldr r3, [r7, #12]
- 8001a1e: 855a strh r2, [r3, #42] ; 0x2a
+ 8001a22: 68fb ldr r3, [r7, #12]
+ 8001a24: 8d5b ldrh r3, [r3, #42] ; 0x2a
+ 8001a26: b29b uxth r3, r3
+ 8001a28: 3b01 subs r3, #1
+ 8001a2a: b29a uxth r2, r3
+ 8001a2c: 68fb ldr r3, [r7, #12]
+ 8001a2e: 855a strh r2, [r3, #42] ; 0x2a
if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
- 8001a20: 68fb ldr r3, [r7, #12]
- 8001a22: 8d5b ldrh r3, [r3, #42] ; 0x2a
- 8001a24: b29b uxth r3, r3
- 8001a26: 2b00 cmp r3, #0
- 8001a28: d03a beq.n 8001aa0 <HAL_I2C_Master_Receive+0x1ac>
- 8001a2a: 68fb ldr r3, [r7, #12]
- 8001a2c: 8d1b ldrh r3, [r3, #40] ; 0x28
- 8001a2e: 2b00 cmp r3, #0
- 8001a30: d136 bne.n 8001aa0 <HAL_I2C_Master_Receive+0x1ac>
+ 8001a30: 68fb ldr r3, [r7, #12]
+ 8001a32: 8d5b ldrh r3, [r3, #42] ; 0x2a
+ 8001a34: b29b uxth r3, r3
+ 8001a36: 2b00 cmp r3, #0
+ 8001a38: d03a beq.n 8001ab0 <HAL_I2C_Master_Receive+0x1ac>
+ 8001a3a: 68fb ldr r3, [r7, #12]
+ 8001a3c: 8d1b ldrh r3, [r3, #40] ; 0x28
+ 8001a3e: 2b00 cmp r3, #0
+ 8001a40: d136 bne.n 8001ab0 <HAL_I2C_Master_Receive+0x1ac>
{
/* Wait until TCR flag is set */
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
- 8001a32: 6aba ldr r2, [r7, #40] ; 0x28
- 8001a34: 68f8 ldr r0, [r7, #12]
- 8001a36: 697b ldr r3, [r7, #20]
- 8001a38: 9300 str r3, [sp, #0]
- 8001a3a: 0013 movs r3, r2
- 8001a3c: 2200 movs r2, #0
- 8001a3e: 2180 movs r1, #128 ; 0x80
- 8001a40: f000 fa18 bl 8001e74 <I2C_WaitOnFlagUntilTimeout>
- 8001a44: 1e03 subs r3, r0, #0
- 8001a46: d001 beq.n 8001a4c <HAL_I2C_Master_Receive+0x158>
+ 8001a42: 6aba ldr r2, [r7, #40] ; 0x28
+ 8001a44: 68f8 ldr r0, [r7, #12]
+ 8001a46: 697b ldr r3, [r7, #20]
+ 8001a48: 9300 str r3, [sp, #0]
+ 8001a4a: 0013 movs r3, r2
+ 8001a4c: 2200 movs r2, #0
+ 8001a4e: 2180 movs r1, #128 ; 0x80
+ 8001a50: f000 fa18 bl 8001e84 <I2C_WaitOnFlagUntilTimeout>
+ 8001a54: 1e03 subs r3, r0, #0
+ 8001a56: d001 beq.n 8001a5c <HAL_I2C_Master_Receive+0x158>
{
return HAL_ERROR;
- 8001a48: 2301 movs r3, #1
- 8001a4a: e053 b.n 8001af4 <HAL_I2C_Master_Receive+0x200>
+ 8001a58: 2301 movs r3, #1
+ 8001a5a: e053 b.n 8001b04 <HAL_I2C_Master_Receive+0x200>
}
if (hi2c->XferCount > MAX_NBYTE_SIZE)
- 8001a4c: 68fb ldr r3, [r7, #12]
- 8001a4e: 8d5b ldrh r3, [r3, #42] ; 0x2a
- 8001a50: b29b uxth r3, r3
- 8001a52: 2bff cmp r3, #255 ; 0xff
- 8001a54: d911 bls.n 8001a7a <HAL_I2C_Master_Receive+0x186>
+ 8001a5c: 68fb ldr r3, [r7, #12]
+ 8001a5e: 8d5b ldrh r3, [r3, #42] ; 0x2a
+ 8001a60: b29b uxth r3, r3
+ 8001a62: 2bff cmp r3, #255 ; 0xff
+ 8001a64: d911 bls.n 8001a8a <HAL_I2C_Master_Receive+0x186>
{
hi2c->XferSize = MAX_NBYTE_SIZE;
- 8001a56: 68fb ldr r3, [r7, #12]
- 8001a58: 22ff movs r2, #255 ; 0xff
- 8001a5a: 851a strh r2, [r3, #40] ; 0x28
+ 8001a66: 68fb ldr r3, [r7, #12]
+ 8001a68: 22ff movs r2, #255 ; 0xff
+ 8001a6a: 851a strh r2, [r3, #40] ; 0x28
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
- 8001a5c: 68fb ldr r3, [r7, #12]
- 8001a5e: 8d1b ldrh r3, [r3, #40] ; 0x28
- 8001a60: b2da uxtb r2, r3
- 8001a62: 2380 movs r3, #128 ; 0x80
- 8001a64: 045c lsls r4, r3, #17
- 8001a66: 230a movs r3, #10
- 8001a68: 18fb adds r3, r7, r3
- 8001a6a: 8819 ldrh r1, [r3, #0]
- 8001a6c: 68f8 ldr r0, [r7, #12]
- 8001a6e: 2300 movs r3, #0
- 8001a70: 9300 str r3, [sp, #0]
- 8001a72: 0023 movs r3, r4
- 8001a74: f000 fb9e bl 80021b4 <I2C_TransferConfig>
- 8001a78: e012 b.n 8001aa0 <HAL_I2C_Master_Receive+0x1ac>
+ 8001a6c: 68fb ldr r3, [r7, #12]
+ 8001a6e: 8d1b ldrh r3, [r3, #40] ; 0x28
+ 8001a70: b2da uxtb r2, r3
+ 8001a72: 2380 movs r3, #128 ; 0x80
+ 8001a74: 045c lsls r4, r3, #17
+ 8001a76: 230a movs r3, #10
+ 8001a78: 18fb adds r3, r7, r3
+ 8001a7a: 8819 ldrh r1, [r3, #0]
+ 8001a7c: 68f8 ldr r0, [r7, #12]
+ 8001a7e: 2300 movs r3, #0
+ 8001a80: 9300 str r3, [sp, #0]
+ 8001a82: 0023 movs r3, r4
+ 8001a84: f000 fb9e bl 80021c4 <I2C_TransferConfig>
+ 8001a88: e012 b.n 8001ab0 <HAL_I2C_Master_Receive+0x1ac>
I2C_NO_STARTSTOP);
}
else
{
hi2c->XferSize = hi2c->XferCount;
- 8001a7a: 68fb ldr r3, [r7, #12]
- 8001a7c: 8d5b ldrh r3, [r3, #42] ; 0x2a
- 8001a7e: b29a uxth r2, r3
- 8001a80: 68fb ldr r3, [r7, #12]
- 8001a82: 851a strh r2, [r3, #40] ; 0x28
+ 8001a8a: 68fb ldr r3, [r7, #12]
+ 8001a8c: 8d5b ldrh r3, [r3, #42] ; 0x2a
+ 8001a8e: b29a uxth r2, r3
+ 8001a90: 68fb ldr r3, [r7, #12]
+ 8001a92: 851a strh r2, [r3, #40] ; 0x28
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
- 8001a84: 68fb ldr r3, [r7, #12]
- 8001a86: 8d1b ldrh r3, [r3, #40] ; 0x28
- 8001a88: b2da uxtb r2, r3
- 8001a8a: 2380 movs r3, #128 ; 0x80
- 8001a8c: 049c lsls r4, r3, #18
- 8001a8e: 230a movs r3, #10
- 8001a90: 18fb adds r3, r7, r3
- 8001a92: 8819 ldrh r1, [r3, #0]
- 8001a94: 68f8 ldr r0, [r7, #12]
- 8001a96: 2300 movs r3, #0
- 8001a98: 9300 str r3, [sp, #0]
- 8001a9a: 0023 movs r3, r4
- 8001a9c: f000 fb8a bl 80021b4 <I2C_TransferConfig>
+ 8001a94: 68fb ldr r3, [r7, #12]
+ 8001a96: 8d1b ldrh r3, [r3, #40] ; 0x28
+ 8001a98: b2da uxtb r2, r3
+ 8001a9a: 2380 movs r3, #128 ; 0x80
+ 8001a9c: 049c lsls r4, r3, #18
+ 8001a9e: 230a movs r3, #10
+ 8001aa0: 18fb adds r3, r7, r3
+ 8001aa2: 8819 ldrh r1, [r3, #0]
+ 8001aa4: 68f8 ldr r0, [r7, #12]
+ 8001aa6: 2300 movs r3, #0
+ 8001aa8: 9300 str r3, [sp, #0]
+ 8001aaa: 0023 movs r3, r4
+ 8001aac: f000 fb8a bl 80021c4 <I2C_TransferConfig>
while (hi2c->XferCount > 0U)
- 8001aa0: 68fb ldr r3, [r7, #12]
- 8001aa2: 8d5b ldrh r3, [r3, #42] ; 0x2a
- 8001aa4: b29b uxth r3, r3
- 8001aa6: 2b00 cmp r3, #0
- 8001aa8: d197 bne.n 80019da <HAL_I2C_Master_Receive+0xe6>
+ 8001ab0: 68fb ldr r3, [r7, #12]
+ 8001ab2: 8d5b ldrh r3, [r3, #42] ; 0x2a
+ 8001ab4: b29b uxth r3, r3
+ 8001ab6: 2b00 cmp r3, #0
+ 8001ab8: d197 bne.n 80019ea <HAL_I2C_Master_Receive+0xe6>
}
}
/* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
/* Wait until STOPF flag is set */
if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
- 8001aaa: 697a ldr r2, [r7, #20]
- 8001aac: 6ab9 ldr r1, [r7, #40] ; 0x28
- 8001aae: 68fb ldr r3, [r7, #12]
- 8001ab0: 0018 movs r0, r3
- 8001ab2: f000 fa5d bl 8001f70 <I2C_WaitOnSTOPFlagUntilTimeout>
- 8001ab6: 1e03 subs r3, r0, #0
- 8001ab8: d001 beq.n 8001abe <HAL_I2C_Master_Receive+0x1ca>
+ 8001aba: 697a ldr r2, [r7, #20]
+ 8001abc: 6ab9 ldr r1, [r7, #40] ; 0x28
+ 8001abe: 68fb ldr r3, [r7, #12]
+ 8001ac0: 0018 movs r0, r3
+ 8001ac2: f000 fa5d bl 8001f80 <I2C_WaitOnSTOPFlagUntilTimeout>
+ 8001ac6: 1e03 subs r3, r0, #0
+ 8001ac8: d001 beq.n 8001ace <HAL_I2C_Master_Receive+0x1ca>
{
return HAL_ERROR;
- 8001aba: 2301 movs r3, #1
- 8001abc: e01a b.n 8001af4 <HAL_I2C_Master_Receive+0x200>
+ 8001aca: 2301 movs r3, #1
+ 8001acc: e01a b.n 8001b04 <HAL_I2C_Master_Receive+0x200>
}
/* Clear STOP Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
- 8001abe: 68fb ldr r3, [r7, #12]
- 8001ac0: 681b ldr r3, [r3, #0]
- 8001ac2: 2220 movs r2, #32
- 8001ac4: 61da str r2, [r3, #28]
+ 8001ace: 68fb ldr r3, [r7, #12]
+ 8001ad0: 681b ldr r3, [r3, #0]
+ 8001ad2: 2220 movs r2, #32
+ 8001ad4: 61da str r2, [r3, #28]
/* Clear Configuration Register 2 */
I2C_RESET_CR2(hi2c);
- 8001ac6: 68fb ldr r3, [r7, #12]
- 8001ac8: 681b ldr r3, [r3, #0]
- 8001aca: 685a ldr r2, [r3, #4]
- 8001acc: 68fb ldr r3, [r7, #12]
- 8001ace: 681b ldr r3, [r3, #0]
- 8001ad0: 490b ldr r1, [pc, #44] ; (8001b00 <HAL_I2C_Master_Receive+0x20c>)
- 8001ad2: 400a ands r2, r1
- 8001ad4: 605a str r2, [r3, #4]
+ 8001ad6: 68fb ldr r3, [r7, #12]
+ 8001ad8: 681b ldr r3, [r3, #0]
+ 8001ada: 685a ldr r2, [r3, #4]
+ 8001adc: 68fb ldr r3, [r7, #12]
+ 8001ade: 681b ldr r3, [r3, #0]
+ 8001ae0: 490b ldr r1, [pc, #44] ; (8001b10 <HAL_I2C_Master_Receive+0x20c>)
+ 8001ae2: 400a ands r2, r1
+ 8001ae4: 605a str r2, [r3, #4]
hi2c->State = HAL_I2C_STATE_READY;
- 8001ad6: 68fb ldr r3, [r7, #12]
- 8001ad8: 2241 movs r2, #65 ; 0x41
- 8001ada: 2120 movs r1, #32
- 8001adc: 5499 strb r1, [r3, r2]
+ 8001ae6: 68fb ldr r3, [r7, #12]
+ 8001ae8: 2241 movs r2, #65 ; 0x41
+ 8001aea: 2120 movs r1, #32
+ 8001aec: 5499 strb r1, [r3, r2]
hi2c->Mode = HAL_I2C_MODE_NONE;
- 8001ade: 68fb ldr r3, [r7, #12]
- 8001ae0: 2242 movs r2, #66 ; 0x42
- 8001ae2: 2100 movs r1, #0
- 8001ae4: 5499 strb r1, [r3, r2]
+ 8001aee: 68fb ldr r3, [r7, #12]
+ 8001af0: 2242 movs r2, #66 ; 0x42
+ 8001af2: 2100 movs r1, #0
+ 8001af4: 5499 strb r1, [r3, r2]
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
- 8001ae6: 68fb ldr r3, [r7, #12]
- 8001ae8: 2240 movs r2, #64 ; 0x40
- 8001aea: 2100 movs r1, #0
- 8001aec: 5499 strb r1, [r3, r2]
+ 8001af6: 68fb ldr r3, [r7, #12]
+ 8001af8: 2240 movs r2, #64 ; 0x40
+ 8001afa: 2100 movs r1, #0
+ 8001afc: 5499 strb r1, [r3, r2]
return HAL_OK;
- 8001aee: 2300 movs r3, #0
- 8001af0: e000 b.n 8001af4 <HAL_I2C_Master_Receive+0x200>
+ 8001afe: 2300 movs r3, #0
+ 8001b00: e000 b.n 8001b04 <HAL_I2C_Master_Receive+0x200>
}
else
{
return HAL_BUSY;
- 8001af2: 2302 movs r3, #2
+ 8001b02: 2302 movs r3, #2
}
}
- 8001af4: 0018 movs r0, r3
- 8001af6: 46bd mov sp, r7
- 8001af8: b007 add sp, #28
- 8001afa: bd90 pop {r4, r7, pc}
- 8001afc: 80002400 .word 0x80002400
- 8001b00: fe00e800 .word 0xfe00e800
+ 8001b04: 0018 movs r0, r3
+ 8001b06: 46bd mov sp, r7
+ 8001b08: b007 add sp, #28
+ 8001b0a: bd90 pop {r4, r7, pc}
+ 8001b0c: 80002400 .word 0x80002400
+ 8001b10: fe00e800 .word 0xfe00e800
-08001b04 <HAL_I2C_Mem_Read>:
+08001b14 <HAL_I2C_Mem_Read>:
* @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
- 8001b04: b590 push {r4, r7, lr}
- 8001b06: b089 sub sp, #36 ; 0x24
- 8001b08: af02 add r7, sp, #8
- 8001b0a: 60f8 str r0, [r7, #12]
- 8001b0c: 000c movs r4, r1
- 8001b0e: 0010 movs r0, r2
- 8001b10: 0019 movs r1, r3
- 8001b12: 230a movs r3, #10
- 8001b14: 18fb adds r3, r7, r3
- 8001b16: 1c22 adds r2, r4, #0
- 8001b18: 801a strh r2, [r3, #0]
- 8001b1a: 2308 movs r3, #8
- 8001b1c: 18fb adds r3, r7, r3
- 8001b1e: 1c02 adds r2, r0, #0
- 8001b20: 801a strh r2, [r3, #0]
- 8001b22: 1dbb adds r3, r7, #6
- 8001b24: 1c0a adds r2, r1, #0
- 8001b26: 801a strh r2, [r3, #0]
+ 8001b14: b590 push {r4, r7, lr}
+ 8001b16: b089 sub sp, #36 ; 0x24
+ 8001b18: af02 add r7, sp, #8
+ 8001b1a: 60f8 str r0, [r7, #12]
+ 8001b1c: 000c movs r4, r1
+ 8001b1e: 0010 movs r0, r2
+ 8001b20: 0019 movs r1, r3
+ 8001b22: 230a movs r3, #10
+ 8001b24: 18fb adds r3, r7, r3
+ 8001b26: 1c22 adds r2, r4, #0
+ 8001b28: 801a strh r2, [r3, #0]
+ 8001b2a: 2308 movs r3, #8
+ 8001b2c: 18fb adds r3, r7, r3
+ 8001b2e: 1c02 adds r2, r0, #0
+ 8001b30: 801a strh r2, [r3, #0]
+ 8001b32: 1dbb adds r3, r7, #6
+ 8001b34: 1c0a adds r2, r1, #0
+ 8001b36: 801a strh r2, [r3, #0]
uint32_t tickstart;
/* Check the parameters */
assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
if (hi2c->State == HAL_I2C_STATE_READY)
- 8001b28: 68fb ldr r3, [r7, #12]
- 8001b2a: 2241 movs r2, #65 ; 0x41
- 8001b2c: 5c9b ldrb r3, [r3, r2]
- 8001b2e: b2db uxtb r3, r3
- 8001b30: 2b20 cmp r3, #32
- 8001b32: d000 beq.n 8001b36 <HAL_I2C_Mem_Read+0x32>
- 8001b34: e110 b.n 8001d58 <HAL_I2C_Mem_Read+0x254>
+ 8001b38: 68fb ldr r3, [r7, #12]
+ 8001b3a: 2241 movs r2, #65 ; 0x41
+ 8001b3c: 5c9b ldrb r3, [r3, r2]
+ 8001b3e: b2db uxtb r3, r3
+ 8001b40: 2b20 cmp r3, #32
+ 8001b42: d000 beq.n 8001b46 <HAL_I2C_Mem_Read+0x32>
+ 8001b44: e110 b.n 8001d68 <HAL_I2C_Mem_Read+0x254>
{
if ((pData == NULL) || (Size == 0U))
- 8001b36: 6abb ldr r3, [r7, #40] ; 0x28
- 8001b38: 2b00 cmp r3, #0
- 8001b3a: d004 beq.n 8001b46 <HAL_I2C_Mem_Read+0x42>
- 8001b3c: 232c movs r3, #44 ; 0x2c
- 8001b3e: 18fb adds r3, r7, r3
- 8001b40: 881b ldrh r3, [r3, #0]
- 8001b42: 2b00 cmp r3, #0
- 8001b44: d105 bne.n 8001b52 <HAL_I2C_Mem_Read+0x4e>
+ 8001b46: 6abb ldr r3, [r7, #40] ; 0x28
+ 8001b48: 2b00 cmp r3, #0
+ 8001b4a: d004 beq.n 8001b56 <HAL_I2C_Mem_Read+0x42>
+ 8001b4c: 232c movs r3, #44 ; 0x2c
+ 8001b4e: 18fb adds r3, r7, r3
+ 8001b50: 881b ldrh r3, [r3, #0]
+ 8001b52: 2b00 cmp r3, #0
+ 8001b54: d105 bne.n 8001b62 <HAL_I2C_Mem_Read+0x4e>
{
hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
- 8001b46: 68fb ldr r3, [r7, #12]
- 8001b48: 2280 movs r2, #128 ; 0x80
- 8001b4a: 0092 lsls r2, r2, #2
- 8001b4c: 645a str r2, [r3, #68] ; 0x44
+ 8001b56: 68fb ldr r3, [r7, #12]
+ 8001b58: 2280 movs r2, #128 ; 0x80
+ 8001b5a: 0092 lsls r2, r2, #2
+ 8001b5c: 645a str r2, [r3, #68] ; 0x44
return HAL_ERROR;
- 8001b4e: 2301 movs r3, #1
- 8001b50: e103 b.n 8001d5a <HAL_I2C_Mem_Read+0x256>
+ 8001b5e: 2301 movs r3, #1
+ 8001b60: e103 b.n 8001d6a <HAL_I2C_Mem_Read+0x256>
}
/* Process Locked */
__HAL_LOCK(hi2c);
- 8001b52: 68fb ldr r3, [r7, #12]
- 8001b54: 2240 movs r2, #64 ; 0x40
- 8001b56: 5c9b ldrb r3, [r3, r2]
- 8001b58: 2b01 cmp r3, #1
- 8001b5a: d101 bne.n 8001b60 <HAL_I2C_Mem_Read+0x5c>
- 8001b5c: 2302 movs r3, #2
- 8001b5e: e0fc b.n 8001d5a <HAL_I2C_Mem_Read+0x256>
- 8001b60: 68fb ldr r3, [r7, #12]
- 8001b62: 2240 movs r2, #64 ; 0x40
- 8001b64: 2101 movs r1, #1
- 8001b66: 5499 strb r1, [r3, r2]
+ 8001b62: 68fb ldr r3, [r7, #12]
+ 8001b64: 2240 movs r2, #64 ; 0x40
+ 8001b66: 5c9b ldrb r3, [r3, r2]
+ 8001b68: 2b01 cmp r3, #1
+ 8001b6a: d101 bne.n 8001b70 <HAL_I2C_Mem_Read+0x5c>
+ 8001b6c: 2302 movs r3, #2
+ 8001b6e: e0fc b.n 8001d6a <HAL_I2C_Mem_Read+0x256>
+ 8001b70: 68fb ldr r3, [r7, #12]
+ 8001b72: 2240 movs r2, #64 ; 0x40
+ 8001b74: 2101 movs r1, #1
+ 8001b76: 5499 strb r1, [r3, r2]
/* Init tickstart for timeout management*/
tickstart = HAL_GetTick();
- 8001b68: f7ff fad6 bl 8001118 <HAL_GetTick>
- 8001b6c: 0003 movs r3, r0
- 8001b6e: 617b str r3, [r7, #20]
+ 8001b78: f7ff fad6 bl 8001128 <HAL_GetTick>
+ 8001b7c: 0003 movs r3, r0
+ 8001b7e: 617b str r3, [r7, #20]
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
- 8001b70: 2380 movs r3, #128 ; 0x80
- 8001b72: 0219 lsls r1, r3, #8
- 8001b74: 68f8 ldr r0, [r7, #12]
- 8001b76: 697b ldr r3, [r7, #20]
- 8001b78: 9300 str r3, [sp, #0]
- 8001b7a: 2319 movs r3, #25
- 8001b7c: 2201 movs r2, #1
- 8001b7e: f000 f979 bl 8001e74 <I2C_WaitOnFlagUntilTimeout>
- 8001b82: 1e03 subs r3, r0, #0
- 8001b84: d001 beq.n 8001b8a <HAL_I2C_Mem_Read+0x86>
+ 8001b80: 2380 movs r3, #128 ; 0x80
+ 8001b82: 0219 lsls r1, r3, #8
+ 8001b84: 68f8 ldr r0, [r7, #12]
+ 8001b86: 697b ldr r3, [r7, #20]
+ 8001b88: 9300 str r3, [sp, #0]
+ 8001b8a: 2319 movs r3, #25
+ 8001b8c: 2201 movs r2, #1
+ 8001b8e: f000 f979 bl 8001e84 <I2C_WaitOnFlagUntilTimeout>
+ 8001b92: 1e03 subs r3, r0, #0
+ 8001b94: d001 beq.n 8001b9a <HAL_I2C_Mem_Read+0x86>
{
return HAL_ERROR;
- 8001b86: 2301 movs r3, #1
- 8001b88: e0e7 b.n 8001d5a <HAL_I2C_Mem_Read+0x256>
+ 8001b96: 2301 movs r3, #1
+ 8001b98: e0e7 b.n 8001d6a <HAL_I2C_Mem_Read+0x256>
}
hi2c->State = HAL_I2C_STATE_BUSY_RX;
- 8001b8a: 68fb ldr r3, [r7, #12]
- 8001b8c: 2241 movs r2, #65 ; 0x41
- 8001b8e: 2122 movs r1, #34 ; 0x22
- 8001b90: 5499 strb r1, [r3, r2]
- hi2c->Mode = HAL_I2C_MODE_MEM;
- 8001b92: 68fb ldr r3, [r7, #12]
- 8001b94: 2242 movs r2, #66 ; 0x42
- 8001b96: 2140 movs r1, #64 ; 0x40
- 8001b98: 5499 strb r1, [r3, r2]
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
8001b9a: 68fb ldr r3, [r7, #12]
- 8001b9c: 2200 movs r2, #0
- 8001b9e: 645a str r2, [r3, #68] ; 0x44
+ 8001b9c: 2241 movs r2, #65 ; 0x41
+ 8001b9e: 2122 movs r1, #34 ; 0x22
+ 8001ba0: 5499 strb r1, [r3, r2]
+ hi2c->Mode = HAL_I2C_MODE_MEM;
+ 8001ba2: 68fb ldr r3, [r7, #12]
+ 8001ba4: 2242 movs r2, #66 ; 0x42
+ 8001ba6: 2140 movs r1, #64 ; 0x40
+ 8001ba8: 5499 strb r1, [r3, r2]
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+ 8001baa: 68fb ldr r3, [r7, #12]
+ 8001bac: 2200 movs r2, #0
+ 8001bae: 645a str r2, [r3, #68] ; 0x44
/* Prepare transfer parameters */
hi2c->pBuffPtr = pData;
- 8001ba0: 68fb ldr r3, [r7, #12]
- 8001ba2: 6aba ldr r2, [r7, #40] ; 0x28
- 8001ba4: 625a str r2, [r3, #36] ; 0x24
- hi2c->XferCount = Size;
- 8001ba6: 68fb ldr r3, [r7, #12]
- 8001ba8: 222c movs r2, #44 ; 0x2c
- 8001baa: 18ba adds r2, r7, r2
- 8001bac: 8812 ldrh r2, [r2, #0]
- 8001bae: 855a strh r2, [r3, #42] ; 0x2a
- hi2c->XferISR = NULL;
8001bb0: 68fb ldr r3, [r7, #12]
- 8001bb2: 2200 movs r2, #0
- 8001bb4: 635a str r2, [r3, #52] ; 0x34
+ 8001bb2: 6aba ldr r2, [r7, #40] ; 0x28
+ 8001bb4: 625a str r2, [r3, #36] ; 0x24
+ hi2c->XferCount = Size;
+ 8001bb6: 68fb ldr r3, [r7, #12]
+ 8001bb8: 222c movs r2, #44 ; 0x2c
+ 8001bba: 18ba adds r2, r7, r2
+ 8001bbc: 8812 ldrh r2, [r2, #0]
+ 8001bbe: 855a strh r2, [r3, #42] ; 0x2a
+ hi2c->XferISR = NULL;
+ 8001bc0: 68fb ldr r3, [r7, #12]
+ 8001bc2: 2200 movs r2, #0
+ 8001bc4: 635a str r2, [r3, #52] ; 0x34
/* Send Slave Address and Memory Address */
if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
- 8001bb6: 1dbb adds r3, r7, #6
- 8001bb8: 881c ldrh r4, [r3, #0]
- 8001bba: 2308 movs r3, #8
- 8001bbc: 18fb adds r3, r7, r3
- 8001bbe: 881a ldrh r2, [r3, #0]
- 8001bc0: 230a movs r3, #10
- 8001bc2: 18fb adds r3, r7, r3
- 8001bc4: 8819 ldrh r1, [r3, #0]
- 8001bc6: 68f8 ldr r0, [r7, #12]
- 8001bc8: 697b ldr r3, [r7, #20]
- 8001bca: 9301 str r3, [sp, #4]
- 8001bcc: 6b3b ldr r3, [r7, #48] ; 0x30
- 8001bce: 9300 str r3, [sp, #0]
- 8001bd0: 0023 movs r3, r4
- 8001bd2: f000 f8cb bl 8001d6c <I2C_RequestMemoryRead>
- 8001bd6: 1e03 subs r3, r0, #0
- 8001bd8: d005 beq.n 8001be6 <HAL_I2C_Mem_Read+0xe2>
+ 8001bc6: 1dbb adds r3, r7, #6
+ 8001bc8: 881c ldrh r4, [r3, #0]
+ 8001bca: 2308 movs r3, #8
+ 8001bcc: 18fb adds r3, r7, r3
+ 8001bce: 881a ldrh r2, [r3, #0]
+ 8001bd0: 230a movs r3, #10
+ 8001bd2: 18fb adds r3, r7, r3
+ 8001bd4: 8819 ldrh r1, [r3, #0]
+ 8001bd6: 68f8 ldr r0, [r7, #12]
+ 8001bd8: 697b ldr r3, [r7, #20]
+ 8001bda: 9301 str r3, [sp, #4]
+ 8001bdc: 6b3b ldr r3, [r7, #48] ; 0x30
+ 8001bde: 9300 str r3, [sp, #0]
+ 8001be0: 0023 movs r3, r4
+ 8001be2: f000 f8cb bl 8001d7c <I2C_RequestMemoryRead>
+ 8001be6: 1e03 subs r3, r0, #0
+ 8001be8: d005 beq.n 8001bf6 <HAL_I2C_Mem_Read+0xe2>
{
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
- 8001bda: 68fb ldr r3, [r7, #12]
- 8001bdc: 2240 movs r2, #64 ; 0x40
- 8001bde: 2100 movs r1, #0
- 8001be0: 5499 strb r1, [r3, r2]
+ 8001bea: 68fb ldr r3, [r7, #12]
+ 8001bec: 2240 movs r2, #64 ; 0x40
+ 8001bee: 2100 movs r1, #0
+ 8001bf0: 5499 strb r1, [r3, r2]
return HAL_ERROR;
- 8001be2: 2301 movs r3, #1
- 8001be4: e0b9 b.n 8001d5a <HAL_I2C_Mem_Read+0x256>
+ 8001bf2: 2301 movs r3, #1
+ 8001bf4: e0b9 b.n 8001d6a <HAL_I2C_Mem_Read+0x256>
}
/* Send Slave Address */
/* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
if (hi2c->XferCount > MAX_NBYTE_SIZE)
- 8001be6: 68fb ldr r3, [r7, #12]
- 8001be8: 8d5b ldrh r3, [r3, #42] ; 0x2a
- 8001bea: b29b uxth r3, r3
- 8001bec: 2bff cmp r3, #255 ; 0xff
- 8001bee: d911 bls.n 8001c14 <HAL_I2C_Mem_Read+0x110>
+ 8001bf6: 68fb ldr r3, [r7, #12]
+ 8001bf8: 8d5b ldrh r3, [r3, #42] ; 0x2a
+ 8001bfa: b29b uxth r3, r3
+ 8001bfc: 2bff cmp r3, #255 ; 0xff
+ 8001bfe: d911 bls.n 8001c24 <HAL_I2C_Mem_Read+0x110>
{
hi2c->XferSize = MAX_NBYTE_SIZE;
- 8001bf0: 68fb ldr r3, [r7, #12]
- 8001bf2: 22ff movs r2, #255 ; 0xff
- 8001bf4: 851a strh r2, [r3, #40] ; 0x28
+ 8001c00: 68fb ldr r3, [r7, #12]
+ 8001c02: 22ff movs r2, #255 ; 0xff
+ 8001c04: 851a strh r2, [r3, #40] ; 0x28
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
- 8001bf6: 68fb ldr r3, [r7, #12]
- 8001bf8: 8d1b ldrh r3, [r3, #40] ; 0x28
- 8001bfa: b2da uxtb r2, r3
- 8001bfc: 2380 movs r3, #128 ; 0x80
- 8001bfe: 045c lsls r4, r3, #17
- 8001c00: 230a movs r3, #10
- 8001c02: 18fb adds r3, r7, r3
- 8001c04: 8819 ldrh r1, [r3, #0]
- 8001c06: 68f8 ldr r0, [r7, #12]
- 8001c08: 4b56 ldr r3, [pc, #344] ; (8001d64 <HAL_I2C_Mem_Read+0x260>)
- 8001c0a: 9300 str r3, [sp, #0]
- 8001c0c: 0023 movs r3, r4
- 8001c0e: f000 fad1 bl 80021b4 <I2C_TransferConfig>
- 8001c12: e012 b.n 8001c3a <HAL_I2C_Mem_Read+0x136>
+ 8001c06: 68fb ldr r3, [r7, #12]
+ 8001c08: 8d1b ldrh r3, [r3, #40] ; 0x28
+ 8001c0a: b2da uxtb r2, r3
+ 8001c0c: 2380 movs r3, #128 ; 0x80
+ 8001c0e: 045c lsls r4, r3, #17
+ 8001c10: 230a movs r3, #10
+ 8001c12: 18fb adds r3, r7, r3
+ 8001c14: 8819 ldrh r1, [r3, #0]
+ 8001c16: 68f8 ldr r0, [r7, #12]
+ 8001c18: 4b56 ldr r3, [pc, #344] ; (8001d74 <HAL_I2C_Mem_Read+0x260>)
+ 8001c1a: 9300 str r3, [sp, #0]
+ 8001c1c: 0023 movs r3, r4
+ 8001c1e: f000 fad1 bl 80021c4 <I2C_TransferConfig>
+ 8001c22: e012 b.n 8001c4a <HAL_I2C_Mem_Read+0x136>
I2C_GENERATE_START_READ);
}
else
{
hi2c->XferSize = hi2c->XferCount;
- 8001c14: 68fb ldr r3, [r7, #12]
- 8001c16: 8d5b ldrh r3, [r3, #42] ; 0x2a
- 8001c18: b29a uxth r2, r3
- 8001c1a: 68fb ldr r3, [r7, #12]
- 8001c1c: 851a strh r2, [r3, #40] ; 0x28
+ 8001c24: 68fb ldr r3, [r7, #12]
+ 8001c26: 8d5b ldrh r3, [r3, #42] ; 0x2a
+ 8001c28: b29a uxth r2, r3
+ 8001c2a: 68fb ldr r3, [r7, #12]
+ 8001c2c: 851a strh r2, [r3, #40] ; 0x28
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
- 8001c1e: 68fb ldr r3, [r7, #12]
- 8001c20: 8d1b ldrh r3, [r3, #40] ; 0x28
- 8001c22: b2da uxtb r2, r3
- 8001c24: 2380 movs r3, #128 ; 0x80
- 8001c26: 049c lsls r4, r3, #18
- 8001c28: 230a movs r3, #10
- 8001c2a: 18fb adds r3, r7, r3
- 8001c2c: 8819 ldrh r1, [r3, #0]
- 8001c2e: 68f8 ldr r0, [r7, #12]
- 8001c30: 4b4c ldr r3, [pc, #304] ; (8001d64 <HAL_I2C_Mem_Read+0x260>)
- 8001c32: 9300 str r3, [sp, #0]
- 8001c34: 0023 movs r3, r4
- 8001c36: f000 fabd bl 80021b4 <I2C_TransferConfig>
+ 8001c2e: 68fb ldr r3, [r7, #12]
+ 8001c30: 8d1b ldrh r3, [r3, #40] ; 0x28
+ 8001c32: b2da uxtb r2, r3
+ 8001c34: 2380 movs r3, #128 ; 0x80
+ 8001c36: 049c lsls r4, r3, #18
+ 8001c38: 230a movs r3, #10
+ 8001c3a: 18fb adds r3, r7, r3
+ 8001c3c: 8819 ldrh r1, [r3, #0]
+ 8001c3e: 68f8 ldr r0, [r7, #12]
+ 8001c40: 4b4c ldr r3, [pc, #304] ; (8001d74 <HAL_I2C_Mem_Read+0x260>)
+ 8001c42: 9300 str r3, [sp, #0]
+ 8001c44: 0023 movs r3, r4
+ 8001c46: f000 fabd bl 80021c4 <I2C_TransferConfig>
}
do
{
/* Wait until RXNE flag is set */
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK)
- 8001c3a: 6b3a ldr r2, [r7, #48] ; 0x30
- 8001c3c: 68f8 ldr r0, [r7, #12]
- 8001c3e: 697b ldr r3, [r7, #20]
- 8001c40: 9300 str r3, [sp, #0]
- 8001c42: 0013 movs r3, r2
- 8001c44: 2200 movs r2, #0
- 8001c46: 2104 movs r1, #4
- 8001c48: f000 f914 bl 8001e74 <I2C_WaitOnFlagUntilTimeout>
- 8001c4c: 1e03 subs r3, r0, #0
- 8001c4e: d001 beq.n 8001c54 <HAL_I2C_Mem_Read+0x150>
+ 8001c4a: 6b3a ldr r2, [r7, #48] ; 0x30
+ 8001c4c: 68f8 ldr r0, [r7, #12]
+ 8001c4e: 697b ldr r3, [r7, #20]
+ 8001c50: 9300 str r3, [sp, #0]
+ 8001c52: 0013 movs r3, r2
+ 8001c54: 2200 movs r2, #0
+ 8001c56: 2104 movs r1, #4
+ 8001c58: f000 f914 bl 8001e84 <I2C_WaitOnFlagUntilTimeout>
+ 8001c5c: 1e03 subs r3, r0, #0
+ 8001c5e: d001 beq.n 8001c64 <HAL_I2C_Mem_Read+0x150>
{
return HAL_ERROR;
- 8001c50: 2301 movs r3, #1
- 8001c52: e082 b.n 8001d5a <HAL_I2C_Mem_Read+0x256>
+ 8001c60: 2301 movs r3, #1
+ 8001c62: e082 b.n 8001d6a <HAL_I2C_Mem_Read+0x256>
}
/* Read data from RXDR */
*hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
- 8001c54: 68fb ldr r3, [r7, #12]
- 8001c56: 681b ldr r3, [r3, #0]
- 8001c58: 6a5a ldr r2, [r3, #36] ; 0x24
- 8001c5a: 68fb ldr r3, [r7, #12]
- 8001c5c: 6a5b ldr r3, [r3, #36] ; 0x24
- 8001c5e: b2d2 uxtb r2, r2
- 8001c60: 701a strb r2, [r3, #0]
+ 8001c64: 68fb ldr r3, [r7, #12]
+ 8001c66: 681b ldr r3, [r3, #0]
+ 8001c68: 6a5a ldr r2, [r3, #36] ; 0x24
+ 8001c6a: 68fb ldr r3, [r7, #12]
+ 8001c6c: 6a5b ldr r3, [r3, #36] ; 0x24
+ 8001c6e: b2d2 uxtb r2, r2
+ 8001c70: 701a strb r2, [r3, #0]
/* Increment Buffer pointer */
hi2c->pBuffPtr++;
- 8001c62: 68fb ldr r3, [r7, #12]
- 8001c64: 6a5b ldr r3, [r3, #36] ; 0x24
- 8001c66: 1c5a adds r2, r3, #1
- 8001c68: 68fb ldr r3, [r7, #12]
- 8001c6a: 625a str r2, [r3, #36] ; 0x24
+ 8001c72: 68fb ldr r3, [r7, #12]
+ 8001c74: 6a5b ldr r3, [r3, #36] ; 0x24
+ 8001c76: 1c5a adds r2, r3, #1
+ 8001c78: 68fb ldr r3, [r7, #12]
+ 8001c7a: 625a str r2, [r3, #36] ; 0x24
hi2c->XferSize--;
- 8001c6c: 68fb ldr r3, [r7, #12]
- 8001c6e: 8d1b ldrh r3, [r3, #40] ; 0x28
- 8001c70: 3b01 subs r3, #1
- 8001c72: b29a uxth r2, r3
- 8001c74: 68fb ldr r3, [r7, #12]
- 8001c76: 851a strh r2, [r3, #40] ; 0x28
+ 8001c7c: 68fb ldr r3, [r7, #12]
+ 8001c7e: 8d1b ldrh r3, [r3, #40] ; 0x28
+ 8001c80: 3b01 subs r3, #1
+ 8001c82: b29a uxth r2, r3
+ 8001c84: 68fb ldr r3, [r7, #12]
+ 8001c86: 851a strh r2, [r3, #40] ; 0x28
hi2c->XferCount--;
- 8001c78: 68fb ldr r3, [r7, #12]
- 8001c7a: 8d5b ldrh r3, [r3, #42] ; 0x2a
- 8001c7c: b29b uxth r3, r3
- 8001c7e: 3b01 subs r3, #1
- 8001c80: b29a uxth r2, r3
- 8001c82: 68fb ldr r3, [r7, #12]
- 8001c84: 855a strh r2, [r3, #42] ; 0x2a
+ 8001c88: 68fb ldr r3, [r7, #12]
+ 8001c8a: 8d5b ldrh r3, [r3, #42] ; 0x2a
+ 8001c8c: b29b uxth r3, r3
+ 8001c8e: 3b01 subs r3, #1
+ 8001c90: b29a uxth r2, r3
+ 8001c92: 68fb ldr r3, [r7, #12]
+ 8001c94: 855a strh r2, [r3, #42] ; 0x2a
if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
- 8001c86: 68fb ldr r3, [r7, #12]
- 8001c88: 8d5b ldrh r3, [r3, #42] ; 0x2a
- 8001c8a: b29b uxth r3, r3
- 8001c8c: 2b00 cmp r3, #0
- 8001c8e: d03a beq.n 8001d06 <HAL_I2C_Mem_Read+0x202>
- 8001c90: 68fb ldr r3, [r7, #12]
- 8001c92: 8d1b ldrh r3, [r3, #40] ; 0x28
- 8001c94: 2b00 cmp r3, #0
- 8001c96: d136 bne.n 8001d06 <HAL_I2C_Mem_Read+0x202>
+ 8001c96: 68fb ldr r3, [r7, #12]
+ 8001c98: 8d5b ldrh r3, [r3, #42] ; 0x2a
+ 8001c9a: b29b uxth r3, r3
+ 8001c9c: 2b00 cmp r3, #0
+ 8001c9e: d03a beq.n 8001d16 <HAL_I2C_Mem_Read+0x202>
+ 8001ca0: 68fb ldr r3, [r7, #12]
+ 8001ca2: 8d1b ldrh r3, [r3, #40] ; 0x28
+ 8001ca4: 2b00 cmp r3, #0
+ 8001ca6: d136 bne.n 8001d16 <HAL_I2C_Mem_Read+0x202>
{
/* Wait until TCR flag is set */
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
- 8001c98: 6b3a ldr r2, [r7, #48] ; 0x30
- 8001c9a: 68f8 ldr r0, [r7, #12]
- 8001c9c: 697b ldr r3, [r7, #20]
- 8001c9e: 9300 str r3, [sp, #0]
- 8001ca0: 0013 movs r3, r2
- 8001ca2: 2200 movs r2, #0
- 8001ca4: 2180 movs r1, #128 ; 0x80
- 8001ca6: f000 f8e5 bl 8001e74 <I2C_WaitOnFlagUntilTimeout>
- 8001caa: 1e03 subs r3, r0, #0
- 8001cac: d001 beq.n 8001cb2 <HAL_I2C_Mem_Read+0x1ae>
+ 8001ca8: 6b3a ldr r2, [r7, #48] ; 0x30
+ 8001caa: 68f8 ldr r0, [r7, #12]
+ 8001cac: 697b ldr r3, [r7, #20]
+ 8001cae: 9300 str r3, [sp, #0]
+ 8001cb0: 0013 movs r3, r2
+ 8001cb2: 2200 movs r2, #0
+ 8001cb4: 2180 movs r1, #128 ; 0x80
+ 8001cb6: f000 f8e5 bl 8001e84 <I2C_WaitOnFlagUntilTimeout>
+ 8001cba: 1e03 subs r3, r0, #0
+ 8001cbc: d001 beq.n 8001cc2 <HAL_I2C_Mem_Read+0x1ae>
{
return HAL_ERROR;
- 8001cae: 2301 movs r3, #1
- 8001cb0: e053 b.n 8001d5a <HAL_I2C_Mem_Read+0x256>
+ 8001cbe: 2301 movs r3, #1
+ 8001cc0: e053 b.n 8001d6a <HAL_I2C_Mem_Read+0x256>
}
if (hi2c->XferCount > MAX_NBYTE_SIZE)
- 8001cb2: 68fb ldr r3, [r7, #12]
- 8001cb4: 8d5b ldrh r3, [r3, #42] ; 0x2a
- 8001cb6: b29b uxth r3, r3
- 8001cb8: 2bff cmp r3, #255 ; 0xff
- 8001cba: d911 bls.n 8001ce0 <HAL_I2C_Mem_Read+0x1dc>
+ 8001cc2: 68fb ldr r3, [r7, #12]
+ 8001cc4: 8d5b ldrh r3, [r3, #42] ; 0x2a
+ 8001cc6: b29b uxth r3, r3
+ 8001cc8: 2bff cmp r3, #255 ; 0xff
+ 8001cca: d911 bls.n 8001cf0 <HAL_I2C_Mem_Read+0x1dc>
{
hi2c->XferSize = MAX_NBYTE_SIZE;
- 8001cbc: 68fb ldr r3, [r7, #12]
- 8001cbe: 22ff movs r2, #255 ; 0xff
- 8001cc0: 851a strh r2, [r3, #40] ; 0x28
+ 8001ccc: 68fb ldr r3, [r7, #12]
+ 8001cce: 22ff movs r2, #255 ; 0xff
+ 8001cd0: 851a strh r2, [r3, #40] ; 0x28
I2C_TransferConfig(hi2c, DevAddress, (uint8_t) hi2c->XferSize, I2C_RELOAD_MODE,
- 8001cc2: 68fb ldr r3, [r7, #12]
- 8001cc4: 8d1b ldrh r3, [r3, #40] ; 0x28
- 8001cc6: b2da uxtb r2, r3
- 8001cc8: 2380 movs r3, #128 ; 0x80
- 8001cca: 045c lsls r4, r3, #17
- 8001ccc: 230a movs r3, #10
- 8001cce: 18fb adds r3, r7, r3
- 8001cd0: 8819 ldrh r1, [r3, #0]
- 8001cd2: 68f8 ldr r0, [r7, #12]
- 8001cd4: 2300 movs r3, #0
- 8001cd6: 9300 str r3, [sp, #0]
- 8001cd8: 0023 movs r3, r4
- 8001cda: f000 fa6b bl 80021b4 <I2C_TransferConfig>
- 8001cde: e012 b.n 8001d06 <HAL_I2C_Mem_Read+0x202>
+ 8001cd2: 68fb ldr r3, [r7, #12]
+ 8001cd4: 8d1b ldrh r3, [r3, #40] ; 0x28
+ 8001cd6: b2da uxtb r2, r3
+ 8001cd8: 2380 movs r3, #128 ; 0x80
+ 8001cda: 045c lsls r4, r3, #17
+ 8001cdc: 230a movs r3, #10
+ 8001cde: 18fb adds r3, r7, r3
+ 8001ce0: 8819 ldrh r1, [r3, #0]
+ 8001ce2: 68f8 ldr r0, [r7, #12]
+ 8001ce4: 2300 movs r3, #0
+ 8001ce6: 9300 str r3, [sp, #0]
+ 8001ce8: 0023 movs r3, r4
+ 8001cea: f000 fa6b bl 80021c4 <I2C_TransferConfig>
+ 8001cee: e012 b.n 8001d16 <HAL_I2C_Mem_Read+0x202>
I2C_NO_STARTSTOP);
}
else
{
hi2c->XferSize = hi2c->XferCount;
- 8001ce0: 68fb ldr r3, [r7, #12]
- 8001ce2: 8d5b ldrh r3, [r3, #42] ; 0x2a
- 8001ce4: b29a uxth r2, r3
- 8001ce6: 68fb ldr r3, [r7, #12]
- 8001ce8: 851a strh r2, [r3, #40] ; 0x28
+ 8001cf0: 68fb ldr r3, [r7, #12]
+ 8001cf2: 8d5b ldrh r3, [r3, #42] ; 0x2a
+ 8001cf4: b29a uxth r2, r3
+ 8001cf6: 68fb ldr r3, [r7, #12]
+ 8001cf8: 851a strh r2, [r3, #40] ; 0x28
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
- 8001cea: 68fb ldr r3, [r7, #12]
- 8001cec: 8d1b ldrh r3, [r3, #40] ; 0x28
- 8001cee: b2da uxtb r2, r3
- 8001cf0: 2380 movs r3, #128 ; 0x80
- 8001cf2: 049c lsls r4, r3, #18
- 8001cf4: 230a movs r3, #10
- 8001cf6: 18fb adds r3, r7, r3
- 8001cf8: 8819 ldrh r1, [r3, #0]
- 8001cfa: 68f8 ldr r0, [r7, #12]
- 8001cfc: 2300 movs r3, #0
- 8001cfe: 9300 str r3, [sp, #0]
- 8001d00: 0023 movs r3, r4
- 8001d02: f000 fa57 bl 80021b4 <I2C_TransferConfig>
+ 8001cfa: 68fb ldr r3, [r7, #12]
+ 8001cfc: 8d1b ldrh r3, [r3, #40] ; 0x28
+ 8001cfe: b2da uxtb r2, r3
+ 8001d00: 2380 movs r3, #128 ; 0x80
+ 8001d02: 049c lsls r4, r3, #18
+ 8001d04: 230a movs r3, #10
+ 8001d06: 18fb adds r3, r7, r3
+ 8001d08: 8819 ldrh r1, [r3, #0]
+ 8001d0a: 68f8 ldr r0, [r7, #12]
+ 8001d0c: 2300 movs r3, #0
+ 8001d0e: 9300 str r3, [sp, #0]
+ 8001d10: 0023 movs r3, r4
+ 8001d12: f000 fa57 bl 80021c4 <I2C_TransferConfig>
I2C_NO_STARTSTOP);
}
}
} while (hi2c->XferCount > 0U);
- 8001d06: 68fb ldr r3, [r7, #12]
- 8001d08: 8d5b ldrh r3, [r3, #42] ; 0x2a
- 8001d0a: b29b uxth r3, r3
- 8001d0c: 2b00 cmp r3, #0
- 8001d0e: d194 bne.n 8001c3a <HAL_I2C_Mem_Read+0x136>
+ 8001d16: 68fb ldr r3, [r7, #12]
+ 8001d18: 8d5b ldrh r3, [r3, #42] ; 0x2a
+ 8001d1a: b29b uxth r3, r3
+ 8001d1c: 2b00 cmp r3, #0
+ 8001d1e: d194 bne.n 8001c4a <HAL_I2C_Mem_Read+0x136>
/* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
/* Wait until STOPF flag is reset */
if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
- 8001d10: 697a ldr r2, [r7, #20]
- 8001d12: 6b39 ldr r1, [r7, #48] ; 0x30
- 8001d14: 68fb ldr r3, [r7, #12]
- 8001d16: 0018 movs r0, r3
- 8001d18: f000 f92a bl 8001f70 <I2C_WaitOnSTOPFlagUntilTimeout>
- 8001d1c: 1e03 subs r3, r0, #0
- 8001d1e: d001 beq.n 8001d24 <HAL_I2C_Mem_Read+0x220>
+ 8001d20: 697a ldr r2, [r7, #20]
+ 8001d22: 6b39 ldr r1, [r7, #48] ; 0x30
+ 8001d24: 68fb ldr r3, [r7, #12]
+ 8001d26: 0018 movs r0, r3
+ 8001d28: f000 f92a bl 8001f80 <I2C_WaitOnSTOPFlagUntilTimeout>
+ 8001d2c: 1e03 subs r3, r0, #0
+ 8001d2e: d001 beq.n 8001d34 <HAL_I2C_Mem_Read+0x220>
{
return HAL_ERROR;
- 8001d20: 2301 movs r3, #1
- 8001d22: e01a b.n 8001d5a <HAL_I2C_Mem_Read+0x256>
+ 8001d30: 2301 movs r3, #1
+ 8001d32: e01a b.n 8001d6a <HAL_I2C_Mem_Read+0x256>
}
/* Clear STOP Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
- 8001d24: 68fb ldr r3, [r7, #12]
- 8001d26: 681b ldr r3, [r3, #0]
- 8001d28: 2220 movs r2, #32
- 8001d2a: 61da str r2, [r3, #28]
+ 8001d34: 68fb ldr r3, [r7, #12]
+ 8001d36: 681b ldr r3, [r3, #0]
+ 8001d38: 2220 movs r2, #32
+ 8001d3a: 61da str r2, [r3, #28]
/* Clear Configuration Register 2 */
I2C_RESET_CR2(hi2c);
- 8001d2c: 68fb ldr r3, [r7, #12]
- 8001d2e: 681b ldr r3, [r3, #0]
- 8001d30: 685a ldr r2, [r3, #4]
- 8001d32: 68fb ldr r3, [r7, #12]
- 8001d34: 681b ldr r3, [r3, #0]
- 8001d36: 490c ldr r1, [pc, #48] ; (8001d68 <HAL_I2C_Mem_Read+0x264>)
- 8001d38: 400a ands r2, r1
- 8001d3a: 605a str r2, [r3, #4]
+ 8001d3c: 68fb ldr r3, [r7, #12]
+ 8001d3e: 681b ldr r3, [r3, #0]
+ 8001d40: 685a ldr r2, [r3, #4]
+ 8001d42: 68fb ldr r3, [r7, #12]
+ 8001d44: 681b ldr r3, [r3, #0]
+ 8001d46: 490c ldr r1, [pc, #48] ; (8001d78 <HAL_I2C_Mem_Read+0x264>)
+ 8001d48: 400a ands r2, r1
+ 8001d4a: 605a str r2, [r3, #4]
hi2c->State = HAL_I2C_STATE_READY;
- 8001d3c: 68fb ldr r3, [r7, #12]
- 8001d3e: 2241 movs r2, #65 ; 0x41
- 8001d40: 2120 movs r1, #32
- 8001d42: 5499 strb r1, [r3, r2]
+ 8001d4c: 68fb ldr r3, [r7, #12]
+ 8001d4e: 2241 movs r2, #65 ; 0x41
+ 8001d50: 2120 movs r1, #32
+ 8001d52: 5499 strb r1, [r3, r2]
hi2c->Mode = HAL_I2C_MODE_NONE;
- 8001d44: 68fb ldr r3, [r7, #12]
- 8001d46: 2242 movs r2, #66 ; 0x42
- 8001d48: 2100 movs r1, #0
- 8001d4a: 5499 strb r1, [r3, r2]
+ 8001d54: 68fb ldr r3, [r7, #12]
+ 8001d56: 2242 movs r2, #66 ; 0x42
+ 8001d58: 2100 movs r1, #0
+ 8001d5a: 5499 strb r1, [r3, r2]
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
- 8001d4c: 68fb ldr r3, [r7, #12]
- 8001d4e: 2240 movs r2, #64 ; 0x40
- 8001d50: 2100 movs r1, #0
- 8001d52: 5499 strb r1, [r3, r2]
+ 8001d5c: 68fb ldr r3, [r7, #12]
+ 8001d5e: 2240 movs r2, #64 ; 0x40
+ 8001d60: 2100 movs r1, #0
+ 8001d62: 5499 strb r1, [r3, r2]
return HAL_OK;
- 8001d54: 2300 movs r3, #0
- 8001d56: e000 b.n 8001d5a <HAL_I2C_Mem_Read+0x256>
+ 8001d64: 2300 movs r3, #0
+ 8001d66: e000 b.n 8001d6a <HAL_I2C_Mem_Read+0x256>
}
else
{
return HAL_BUSY;
- 8001d58: 2302 movs r3, #2
+ 8001d68: 2302 movs r3, #2
}
}
- 8001d5a: 0018 movs r0, r3
- 8001d5c: 46bd mov sp, r7
- 8001d5e: b007 add sp, #28
- 8001d60: bd90 pop {r4, r7, pc}
- 8001d62: 46c0 nop ; (mov r8, r8)
- 8001d64: 80002400 .word 0x80002400
- 8001d68: fe00e800 .word 0xfe00e800
+ 8001d6a: 0018 movs r0, r3
+ 8001d6c: 46bd mov sp, r7
+ 8001d6e: b007 add sp, #28
+ 8001d70: bd90 pop {r4, r7, pc}
+ 8001d72: 46c0 nop ; (mov r8, r8)
+ 8001d74: 80002400 .word 0x80002400
+ 8001d78: fe00e800 .word 0xfe00e800
-08001d6c <I2C_RequestMemoryRead>:
+08001d7c <I2C_RequestMemoryRead>:
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout,
uint32_t Tickstart)
{
- 8001d6c: b5b0 push {r4, r5, r7, lr}
- 8001d6e: b086 sub sp, #24
- 8001d70: af02 add r7, sp, #8
- 8001d72: 60f8 str r0, [r7, #12]
- 8001d74: 000c movs r4, r1
- 8001d76: 0010 movs r0, r2
- 8001d78: 0019 movs r1, r3
- 8001d7a: 250a movs r5, #10
- 8001d7c: 197b adds r3, r7, r5
- 8001d7e: 1c22 adds r2, r4, #0
- 8001d80: 801a strh r2, [r3, #0]
- 8001d82: 2308 movs r3, #8
- 8001d84: 18fb adds r3, r7, r3
- 8001d86: 1c02 adds r2, r0, #0
- 8001d88: 801a strh r2, [r3, #0]
- 8001d8a: 1dbb adds r3, r7, #6
- 8001d8c: 1c0a adds r2, r1, #0
- 8001d8e: 801a strh r2, [r3, #0]
+ 8001d7c: b5b0 push {r4, r5, r7, lr}
+ 8001d7e: b086 sub sp, #24
+ 8001d80: af02 add r7, sp, #8
+ 8001d82: 60f8 str r0, [r7, #12]
+ 8001d84: 000c movs r4, r1
+ 8001d86: 0010 movs r0, r2
+ 8001d88: 0019 movs r1, r3
+ 8001d8a: 250a movs r5, #10
+ 8001d8c: 197b adds r3, r7, r5
+ 8001d8e: 1c22 adds r2, r4, #0
+ 8001d90: 801a strh r2, [r3, #0]
+ 8001d92: 2308 movs r3, #8
+ 8001d94: 18fb adds r3, r7, r3
+ 8001d96: 1c02 adds r2, r0, #0
+ 8001d98: 801a strh r2, [r3, #0]
+ 8001d9a: 1dbb adds r3, r7, #6
+ 8001d9c: 1c0a adds r2, r1, #0
+ 8001d9e: 801a strh r2, [r3, #0]
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE);
- 8001d90: 1dbb adds r3, r7, #6
- 8001d92: 881b ldrh r3, [r3, #0]
- 8001d94: b2da uxtb r2, r3
- 8001d96: 197b adds r3, r7, r5
- 8001d98: 8819 ldrh r1, [r3, #0]
- 8001d9a: 68f8 ldr r0, [r7, #12]
- 8001d9c: 4b23 ldr r3, [pc, #140] ; (8001e2c <I2C_RequestMemoryRead+0xc0>)
- 8001d9e: 9300 str r3, [sp, #0]
- 8001da0: 2300 movs r3, #0
- 8001da2: f000 fa07 bl 80021b4 <I2C_TransferConfig>
+ 8001da0: 1dbb adds r3, r7, #6
+ 8001da2: 881b ldrh r3, [r3, #0]
+ 8001da4: b2da uxtb r2, r3
+ 8001da6: 197b adds r3, r7, r5
+ 8001da8: 8819 ldrh r1, [r3, #0]
+ 8001daa: 68f8 ldr r0, [r7, #12]
+ 8001dac: 4b23 ldr r3, [pc, #140] ; (8001e3c <I2C_RequestMemoryRead+0xc0>)
+ 8001dae: 9300 str r3, [sp, #0]
+ 8001db0: 2300 movs r3, #0
+ 8001db2: f000 fa07 bl 80021c4 <I2C_TransferConfig>
/* Wait until TXIS flag is set */
if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
- 8001da6: 6a7a ldr r2, [r7, #36] ; 0x24
- 8001da8: 6a39 ldr r1, [r7, #32]
- 8001daa: 68fb ldr r3, [r7, #12]
- 8001dac: 0018 movs r0, r3
- 8001dae: f000 f8a0 bl 8001ef2 <I2C_WaitOnTXISFlagUntilTimeout>
- 8001db2: 1e03 subs r3, r0, #0
- 8001db4: d001 beq.n 8001dba <I2C_RequestMemoryRead+0x4e>
+ 8001db6: 6a7a ldr r2, [r7, #36] ; 0x24
+ 8001db8: 6a39 ldr r1, [r7, #32]
+ 8001dba: 68fb ldr r3, [r7, #12]
+ 8001dbc: 0018 movs r0, r3
+ 8001dbe: f000 f8a0 bl 8001f02 <I2C_WaitOnTXISFlagUntilTimeout>
+ 8001dc2: 1e03 subs r3, r0, #0
+ 8001dc4: d001 beq.n 8001dca <I2C_RequestMemoryRead+0x4e>
{
return HAL_ERROR;
- 8001db6: 2301 movs r3, #1
- 8001db8: e033 b.n 8001e22 <I2C_RequestMemoryRead+0xb6>
+ 8001dc6: 2301 movs r3, #1
+ 8001dc8: e033 b.n 8001e32 <I2C_RequestMemoryRead+0xb6>
}
/* If Memory address size is 8Bit */
if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
- 8001dba: 1dbb adds r3, r7, #6
- 8001dbc: 881b ldrh r3, [r3, #0]
- 8001dbe: 2b01 cmp r3, #1
- 8001dc0: d107 bne.n 8001dd2 <I2C_RequestMemoryRead+0x66>
+ 8001dca: 1dbb adds r3, r7, #6
+ 8001dcc: 881b ldrh r3, [r3, #0]
+ 8001dce: 2b01 cmp r3, #1
+ 8001dd0: d107 bne.n 8001de2 <I2C_RequestMemoryRead+0x66>
{
/* Send Memory Address */
hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
- 8001dc2: 2308 movs r3, #8
- 8001dc4: 18fb adds r3, r7, r3
- 8001dc6: 881b ldrh r3, [r3, #0]
- 8001dc8: b2da uxtb r2, r3
- 8001dca: 68fb ldr r3, [r7, #12]
- 8001dcc: 681b ldr r3, [r3, #0]
- 8001dce: 629a str r2, [r3, #40] ; 0x28
- 8001dd0: e019 b.n 8001e06 <I2C_RequestMemoryRead+0x9a>
+ 8001dd2: 2308 movs r3, #8
+ 8001dd4: 18fb adds r3, r7, r3
+ 8001dd6: 881b ldrh r3, [r3, #0]
+ 8001dd8: b2da uxtb r2, r3
+ 8001dda: 68fb ldr r3, [r7, #12]
+ 8001ddc: 681b ldr r3, [r3, #0]
+ 8001dde: 629a str r2, [r3, #40] ; 0x28
+ 8001de0: e019 b.n 8001e16 <I2C_RequestMemoryRead+0x9a>
}
/* If Memory address size is 16Bit */
else
{
/* Send MSB of Memory Address */
hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
- 8001dd2: 2308 movs r3, #8
- 8001dd4: 18fb adds r3, r7, r3
- 8001dd6: 881b ldrh r3, [r3, #0]
- 8001dd8: 0a1b lsrs r3, r3, #8
- 8001dda: b29b uxth r3, r3
- 8001ddc: b2da uxtb r2, r3
- 8001dde: 68fb ldr r3, [r7, #12]
- 8001de0: 681b ldr r3, [r3, #0]
- 8001de2: 629a str r2, [r3, #40] ; 0x28
+ 8001de2: 2308 movs r3, #8
+ 8001de4: 18fb adds r3, r7, r3
+ 8001de6: 881b ldrh r3, [r3, #0]
+ 8001de8: 0a1b lsrs r3, r3, #8
+ 8001dea: b29b uxth r3, r3
+ 8001dec: b2da uxtb r2, r3
+ 8001dee: 68fb ldr r3, [r7, #12]
+ 8001df0: 681b ldr r3, [r3, #0]
+ 8001df2: 629a str r2, [r3, #40] ; 0x28
/* Wait until TXIS flag is set */
if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
- 8001de4: 6a7a ldr r2, [r7, #36] ; 0x24
- 8001de6: 6a39 ldr r1, [r7, #32]
- 8001de8: 68fb ldr r3, [r7, #12]
- 8001dea: 0018 movs r0, r3
- 8001dec: f000 f881 bl 8001ef2 <I2C_WaitOnTXISFlagUntilTimeout>
- 8001df0: 1e03 subs r3, r0, #0
- 8001df2: d001 beq.n 8001df8 <I2C_RequestMemoryRead+0x8c>
+ 8001df4: 6a7a ldr r2, [r7, #36] ; 0x24
+ 8001df6: 6a39 ldr r1, [r7, #32]
+ 8001df8: 68fb ldr r3, [r7, #12]
+ 8001dfa: 0018 movs r0, r3
+ 8001dfc: f000 f881 bl 8001f02 <I2C_WaitOnTXISFlagUntilTimeout>
+ 8001e00: 1e03 subs r3, r0, #0
+ 8001e02: d001 beq.n 8001e08 <I2C_RequestMemoryRead+0x8c>
{
return HAL_ERROR;
- 8001df4: 2301 movs r3, #1
- 8001df6: e014 b.n 8001e22 <I2C_RequestMemoryRead+0xb6>
+ 8001e04: 2301 movs r3, #1
+ 8001e06: e014 b.n 8001e32 <I2C_RequestMemoryRead+0xb6>
}
/* Send LSB of Memory Address */
hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
- 8001df8: 2308 movs r3, #8
- 8001dfa: 18fb adds r3, r7, r3
- 8001dfc: 881b ldrh r3, [r3, #0]
- 8001dfe: b2da uxtb r2, r3
- 8001e00: 68fb ldr r3, [r7, #12]
- 8001e02: 681b ldr r3, [r3, #0]
- 8001e04: 629a str r2, [r3, #40] ; 0x28
+ 8001e08: 2308 movs r3, #8
+ 8001e0a: 18fb adds r3, r7, r3
+ 8001e0c: 881b ldrh r3, [r3, #0]
+ 8001e0e: b2da uxtb r2, r3
+ 8001e10: 68fb ldr r3, [r7, #12]
+ 8001e12: 681b ldr r3, [r3, #0]
+ 8001e14: 629a str r2, [r3, #40] ; 0x28
}
/* Wait until TC flag is set */
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TC, RESET, Timeout, Tickstart) != HAL_OK)
- 8001e06: 6a3a ldr r2, [r7, #32]
- 8001e08: 68f8 ldr r0, [r7, #12]
- 8001e0a: 6a7b ldr r3, [r7, #36] ; 0x24
- 8001e0c: 9300 str r3, [sp, #0]
- 8001e0e: 0013 movs r3, r2
- 8001e10: 2200 movs r2, #0
- 8001e12: 2140 movs r1, #64 ; 0x40
- 8001e14: f000 f82e bl 8001e74 <I2C_WaitOnFlagUntilTimeout>
- 8001e18: 1e03 subs r3, r0, #0
- 8001e1a: d001 beq.n 8001e20 <I2C_RequestMemoryRead+0xb4>
+ 8001e16: 6a3a ldr r2, [r7, #32]
+ 8001e18: 68f8 ldr r0, [r7, #12]
+ 8001e1a: 6a7b ldr r3, [r7, #36] ; 0x24
+ 8001e1c: 9300 str r3, [sp, #0]
+ 8001e1e: 0013 movs r3, r2
+ 8001e20: 2200 movs r2, #0
+ 8001e22: 2140 movs r1, #64 ; 0x40
+ 8001e24: f000 f82e bl 8001e84 <I2C_WaitOnFlagUntilTimeout>
+ 8001e28: 1e03 subs r3, r0, #0
+ 8001e2a: d001 beq.n 8001e30 <I2C_RequestMemoryRead+0xb4>
{
return HAL_ERROR;
- 8001e1c: 2301 movs r3, #1
- 8001e1e: e000 b.n 8001e22 <I2C_RequestMemoryRead+0xb6>
+ 8001e2c: 2301 movs r3, #1
+ 8001e2e: e000 b.n 8001e32 <I2C_RequestMemoryRead+0xb6>
}
return HAL_OK;
- 8001e20: 2300 movs r3, #0
+ 8001e30: 2300 movs r3, #0
}
- 8001e22: 0018 movs r0, r3
- 8001e24: 46bd mov sp, r7
- 8001e26: b004 add sp, #16
- 8001e28: bdb0 pop {r4, r5, r7, pc}
- 8001e2a: 46c0 nop ; (mov r8, r8)
- 8001e2c: 80002000 .word 0x80002000
+ 8001e32: 0018 movs r0, r3
+ 8001e34: 46bd mov sp, r7
+ 8001e36: b004 add sp, #16
+ 8001e38: bdb0 pop {r4, r5, r7, pc}
+ 8001e3a: 46c0 nop ; (mov r8, r8)
+ 8001e3c: 80002000 .word 0x80002000
-08001e30 <I2C_Flush_TXDR>:
+08001e40 <I2C_Flush_TXDR>:
* @brief I2C Tx data register flush process.
* @param hi2c I2C handle.
* @retval None
*/
static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c)
{
- 8001e30: b580 push {r7, lr}
- 8001e32: b082 sub sp, #8
- 8001e34: af00 add r7, sp, #0
- 8001e36: 6078 str r0, [r7, #4]
+ 8001e40: b580 push {r7, lr}
+ 8001e42: b082 sub sp, #8
+ 8001e44: af00 add r7, sp, #0
+ 8001e46: 6078 str r0, [r7, #4]
/* If a pending TXIS flag is set */
/* Write a dummy data in TXDR to clear it */
if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) != RESET)
- 8001e38: 687b ldr r3, [r7, #4]
- 8001e3a: 681b ldr r3, [r3, #0]
- 8001e3c: 699b ldr r3, [r3, #24]
- 8001e3e: 2202 movs r2, #2
- 8001e40: 4013 ands r3, r2
- 8001e42: 2b02 cmp r3, #2
- 8001e44: d103 bne.n 8001e4e <I2C_Flush_TXDR+0x1e>
+ 8001e48: 687b ldr r3, [r7, #4]
+ 8001e4a: 681b ldr r3, [r3, #0]
+ 8001e4c: 699b ldr r3, [r3, #24]
+ 8001e4e: 2202 movs r2, #2
+ 8001e50: 4013 ands r3, r2
+ 8001e52: 2b02 cmp r3, #2
+ 8001e54: d103 bne.n 8001e5e <I2C_Flush_TXDR+0x1e>
{
hi2c->Instance->TXDR = 0x00U;
- 8001e46: 687b ldr r3, [r7, #4]
- 8001e48: 681b ldr r3, [r3, #0]
- 8001e4a: 2200 movs r2, #0
- 8001e4c: 629a str r2, [r3, #40] ; 0x28
+ 8001e56: 687b ldr r3, [r7, #4]
+ 8001e58: 681b ldr r3, [r3, #0]
+ 8001e5a: 2200 movs r2, #0
+ 8001e5c: 629a str r2, [r3, #40] ; 0x28
}
/* Flush TX register if not empty */
if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET)
- 8001e4e: 687b ldr r3, [r7, #4]
- 8001e50: 681b ldr r3, [r3, #0]
- 8001e52: 699b ldr r3, [r3, #24]
- 8001e54: 2201 movs r2, #1
- 8001e56: 4013 ands r3, r2
- 8001e58: 2b01 cmp r3, #1
- 8001e5a: d007 beq.n 8001e6c <I2C_Flush_TXDR+0x3c>
+ 8001e5e: 687b ldr r3, [r7, #4]
+ 8001e60: 681b ldr r3, [r3, #0]
+ 8001e62: 699b ldr r3, [r3, #24]
+ 8001e64: 2201 movs r2, #1
+ 8001e66: 4013 ands r3, r2
+ 8001e68: 2b01 cmp r3, #1
+ 8001e6a: d007 beq.n 8001e7c <I2C_Flush_TXDR+0x3c>
{
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_TXE);
- 8001e5c: 687b ldr r3, [r7, #4]
- 8001e5e: 681b ldr r3, [r3, #0]
- 8001e60: 699a ldr r2, [r3, #24]
- 8001e62: 687b ldr r3, [r7, #4]
- 8001e64: 681b ldr r3, [r3, #0]
- 8001e66: 2101 movs r1, #1
- 8001e68: 430a orrs r2, r1
- 8001e6a: 619a str r2, [r3, #24]
+ 8001e6c: 687b ldr r3, [r7, #4]
+ 8001e6e: 681b ldr r3, [r3, #0]
+ 8001e70: 699a ldr r2, [r3, #24]
+ 8001e72: 687b ldr r3, [r7, #4]
+ 8001e74: 681b ldr r3, [r3, #0]
+ 8001e76: 2101 movs r1, #1
+ 8001e78: 430a orrs r2, r1
+ 8001e7a: 619a str r2, [r3, #24]
}
}
- 8001e6c: 46c0 nop ; (mov r8, r8)
- 8001e6e: 46bd mov sp, r7
- 8001e70: b002 add sp, #8
- 8001e72: bd80 pop {r7, pc}
+ 8001e7c: 46c0 nop ; (mov r8, r8)
+ 8001e7e: 46bd mov sp, r7
+ 8001e80: b002 add sp, #8
+ 8001e82: bd80 pop {r7, pc}
-08001e74 <I2C_WaitOnFlagUntilTimeout>:
+08001e84 <I2C_WaitOnFlagUntilTimeout>:
* @param Tickstart Tick start value
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status,
uint32_t Timeout, uint32_t Tickstart)
{
- 8001e74: b580 push {r7, lr}
- 8001e76: b084 sub sp, #16
- 8001e78: af00 add r7, sp, #0
- 8001e7a: 60f8 str r0, [r7, #12]
- 8001e7c: 60b9 str r1, [r7, #8]
- 8001e7e: 603b str r3, [r7, #0]
- 8001e80: 1dfb adds r3, r7, #7
- 8001e82: 701a strb r2, [r3, #0]
+ 8001e84: b580 push {r7, lr}
+ 8001e86: b084 sub sp, #16
+ 8001e88: af00 add r7, sp, #0
+ 8001e8a: 60f8 str r0, [r7, #12]
+ 8001e8c: 60b9 str r1, [r7, #8]
+ 8001e8e: 603b str r3, [r7, #0]
+ 8001e90: 1dfb adds r3, r7, #7
+ 8001e92: 701a strb r2, [r3, #0]
while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)
- 8001e84: e021 b.n 8001eca <I2C_WaitOnFlagUntilTimeout+0x56>
+ 8001e94: e021 b.n 8001eda <I2C_WaitOnFlagUntilTimeout+0x56>
{
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
- 8001e86: 683b ldr r3, [r7, #0]
- 8001e88: 3301 adds r3, #1
- 8001e8a: d01e beq.n 8001eca <I2C_WaitOnFlagUntilTimeout+0x56>
+ 8001e96: 683b ldr r3, [r7, #0]
+ 8001e98: 3301 adds r3, #1
+ 8001e9a: d01e beq.n 8001eda <I2C_WaitOnFlagUntilTimeout+0x56>
{
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
- 8001e8c: f7ff f944 bl 8001118 <HAL_GetTick>
- 8001e90: 0002 movs r2, r0
- 8001e92: 69bb ldr r3, [r7, #24]
- 8001e94: 1ad3 subs r3, r2, r3
- 8001e96: 683a ldr r2, [r7, #0]
- 8001e98: 429a cmp r2, r3
- 8001e9a: d302 bcc.n 8001ea2 <I2C_WaitOnFlagUntilTimeout+0x2e>
- 8001e9c: 683b ldr r3, [r7, #0]
- 8001e9e: 2b00 cmp r3, #0
- 8001ea0: d113 bne.n 8001eca <I2C_WaitOnFlagUntilTimeout+0x56>
+ 8001e9c: f7ff f944 bl 8001128 <HAL_GetTick>
+ 8001ea0: 0002 movs r2, r0
+ 8001ea2: 69bb ldr r3, [r7, #24]
+ 8001ea4: 1ad3 subs r3, r2, r3
+ 8001ea6: 683a ldr r2, [r7, #0]
+ 8001ea8: 429a cmp r2, r3
+ 8001eaa: d302 bcc.n 8001eb2 <I2C_WaitOnFlagUntilTimeout+0x2e>
+ 8001eac: 683b ldr r3, [r7, #0]
+ 8001eae: 2b00 cmp r3, #0
+ 8001eb0: d113 bne.n 8001eda <I2C_WaitOnFlagUntilTimeout+0x56>
{
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
- 8001ea2: 68fb ldr r3, [r7, #12]
- 8001ea4: 6c5b ldr r3, [r3, #68] ; 0x44
- 8001ea6: 2220 movs r2, #32
- 8001ea8: 431a orrs r2, r3
- 8001eaa: 68fb ldr r3, [r7, #12]
- 8001eac: 645a str r2, [r3, #68] ; 0x44
+ 8001eb2: 68fb ldr r3, [r7, #12]
+ 8001eb4: 6c5b ldr r3, [r3, #68] ; 0x44
+ 8001eb6: 2220 movs r2, #32
+ 8001eb8: 431a orrs r2, r3
+ 8001eba: 68fb ldr r3, [r7, #12]
+ 8001ebc: 645a str r2, [r3, #68] ; 0x44
hi2c->State = HAL_I2C_STATE_READY;
- 8001eae: 68fb ldr r3, [r7, #12]
- 8001eb0: 2241 movs r2, #65 ; 0x41
- 8001eb2: 2120 movs r1, #32
- 8001eb4: 5499 strb r1, [r3, r2]
+ 8001ebe: 68fb ldr r3, [r7, #12]
+ 8001ec0: 2241 movs r2, #65 ; 0x41
+ 8001ec2: 2120 movs r1, #32
+ 8001ec4: 5499 strb r1, [r3, r2]
hi2c->Mode = HAL_I2C_MODE_NONE;
- 8001eb6: 68fb ldr r3, [r7, #12]
- 8001eb8: 2242 movs r2, #66 ; 0x42
- 8001eba: 2100 movs r1, #0
- 8001ebc: 5499 strb r1, [r3, r2]
+ 8001ec6: 68fb ldr r3, [r7, #12]
+ 8001ec8: 2242 movs r2, #66 ; 0x42
+ 8001eca: 2100 movs r1, #0
+ 8001ecc: 5499 strb r1, [r3, r2]
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
- 8001ebe: 68fb ldr r3, [r7, #12]
- 8001ec0: 2240 movs r2, #64 ; 0x40
- 8001ec2: 2100 movs r1, #0
- 8001ec4: 5499 strb r1, [r3, r2]
+ 8001ece: 68fb ldr r3, [r7, #12]
+ 8001ed0: 2240 movs r2, #64 ; 0x40
+ 8001ed2: 2100 movs r1, #0
+ 8001ed4: 5499 strb r1, [r3, r2]
return HAL_ERROR;
- 8001ec6: 2301 movs r3, #1
- 8001ec8: e00f b.n 8001eea <I2C_WaitOnFlagUntilTimeout+0x76>
+ 8001ed6: 2301 movs r3, #1
+ 8001ed8: e00f b.n 8001efa <I2C_WaitOnFlagUntilTimeout+0x76>
while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)
- 8001eca: 68fb ldr r3, [r7, #12]
- 8001ecc: 681b ldr r3, [r3, #0]
- 8001ece: 699b ldr r3, [r3, #24]
- 8001ed0: 68ba ldr r2, [r7, #8]
- 8001ed2: 4013 ands r3, r2
- 8001ed4: 68ba ldr r2, [r7, #8]
- 8001ed6: 1ad3 subs r3, r2, r3
- 8001ed8: 425a negs r2, r3
- 8001eda: 4153 adcs r3, r2
- 8001edc: b2db uxtb r3, r3
- 8001ede: 001a movs r2, r3
- 8001ee0: 1dfb adds r3, r7, #7
- 8001ee2: 781b ldrb r3, [r3, #0]
- 8001ee4: 429a cmp r2, r3
- 8001ee6: d0ce beq.n 8001e86 <I2C_WaitOnFlagUntilTimeout+0x12>
+ 8001eda: 68fb ldr r3, [r7, #12]
+ 8001edc: 681b ldr r3, [r3, #0]
+ 8001ede: 699b ldr r3, [r3, #24]
+ 8001ee0: 68ba ldr r2, [r7, #8]
+ 8001ee2: 4013 ands r3, r2
+ 8001ee4: 68ba ldr r2, [r7, #8]
+ 8001ee6: 1ad3 subs r3, r2, r3
+ 8001ee8: 425a negs r2, r3
+ 8001eea: 4153 adcs r3, r2
+ 8001eec: b2db uxtb r3, r3
+ 8001eee: 001a movs r2, r3
+ 8001ef0: 1dfb adds r3, r7, #7
+ 8001ef2: 781b ldrb r3, [r3, #0]
+ 8001ef4: 429a cmp r2, r3
+ 8001ef6: d0ce beq.n 8001e96 <I2C_WaitOnFlagUntilTimeout+0x12>
}
}
}
return HAL_OK;
- 8001ee8: 2300 movs r3, #0
+ 8001ef8: 2300 movs r3, #0
}
- 8001eea: 0018 movs r0, r3
- 8001eec: 46bd mov sp, r7
- 8001eee: b004 add sp, #16
- 8001ef0: bd80 pop {r7, pc}
+ 8001efa: 0018 movs r0, r3
+ 8001efc: 46bd mov sp, r7
+ 8001efe: b004 add sp, #16
+ 8001f00: bd80 pop {r7, pc}
-08001ef2 <I2C_WaitOnTXISFlagUntilTimeout>:
+08001f02 <I2C_WaitOnTXISFlagUntilTimeout>:
* @param Tickstart Tick start value
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
uint32_t Tickstart)
{
- 8001ef2: b580 push {r7, lr}
- 8001ef4: b084 sub sp, #16
- 8001ef6: af00 add r7, sp, #0
- 8001ef8: 60f8 str r0, [r7, #12]
- 8001efa: 60b9 str r1, [r7, #8]
- 8001efc: 607a str r2, [r7, #4]
+ 8001f02: b580 push {r7, lr}
+ 8001f04: b084 sub sp, #16
+ 8001f06: af00 add r7, sp, #0
+ 8001f08: 60f8 str r0, [r7, #12]
+ 8001f0a: 60b9 str r1, [r7, #8]
+ 8001f0c: 607a str r2, [r7, #4]
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET)
- 8001efe: e02b b.n 8001f58 <I2C_WaitOnTXISFlagUntilTimeout+0x66>
+ 8001f0e: e02b b.n 8001f68 <I2C_WaitOnTXISFlagUntilTimeout+0x66>
{
/* Check if a NACK is detected */
if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK)
- 8001f00: 687a ldr r2, [r7, #4]
- 8001f02: 68b9 ldr r1, [r7, #8]
- 8001f04: 68fb ldr r3, [r7, #12]
- 8001f06: 0018 movs r0, r3
- 8001f08: f000 f8da bl 80020c0 <I2C_IsAcknowledgeFailed>
- 8001f0c: 1e03 subs r3, r0, #0
- 8001f0e: d001 beq.n 8001f14 <I2C_WaitOnTXISFlagUntilTimeout+0x22>
+ 8001f10: 687a ldr r2, [r7, #4]
+ 8001f12: 68b9 ldr r1, [r7, #8]
+ 8001f14: 68fb ldr r3, [r7, #12]
+ 8001f16: 0018 movs r0, r3
+ 8001f18: f000 f8da bl 80020d0 <I2C_IsAcknowledgeFailed>
+ 8001f1c: 1e03 subs r3, r0, #0
+ 8001f1e: d001 beq.n 8001f24 <I2C_WaitOnTXISFlagUntilTimeout+0x22>
{
return HAL_ERROR;
- 8001f10: 2301 movs r3, #1
- 8001f12: e029 b.n 8001f68 <I2C_WaitOnTXISFlagUntilTimeout+0x76>
+ 8001f20: 2301 movs r3, #1
+ 8001f22: e029 b.n 8001f78 <I2C_WaitOnTXISFlagUntilTimeout+0x76>
}
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
- 8001f14: 68bb ldr r3, [r7, #8]
- 8001f16: 3301 adds r3, #1
- 8001f18: d01e beq.n 8001f58 <I2C_WaitOnTXISFlagUntilTimeout+0x66>
+ 8001f24: 68bb ldr r3, [r7, #8]
+ 8001f26: 3301 adds r3, #1
+ 8001f28: d01e beq.n 8001f68 <I2C_WaitOnTXISFlagUntilTimeout+0x66>
{
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
- 8001f1a: f7ff f8fd bl 8001118 <HAL_GetTick>
- 8001f1e: 0002 movs r2, r0
- 8001f20: 687b ldr r3, [r7, #4]
- 8001f22: 1ad3 subs r3, r2, r3
- 8001f24: 68ba ldr r2, [r7, #8]
- 8001f26: 429a cmp r2, r3
- 8001f28: d302 bcc.n 8001f30 <I2C_WaitOnTXISFlagUntilTimeout+0x3e>
- 8001f2a: 68bb ldr r3, [r7, #8]
- 8001f2c: 2b00 cmp r3, #0
- 8001f2e: d113 bne.n 8001f58 <I2C_WaitOnTXISFlagUntilTimeout+0x66>
+ 8001f2a: f7ff f8fd bl 8001128 <HAL_GetTick>
+ 8001f2e: 0002 movs r2, r0
+ 8001f30: 687b ldr r3, [r7, #4]
+ 8001f32: 1ad3 subs r3, r2, r3
+ 8001f34: 68ba ldr r2, [r7, #8]
+ 8001f36: 429a cmp r2, r3
+ 8001f38: d302 bcc.n 8001f40 <I2C_WaitOnTXISFlagUntilTimeout+0x3e>
+ 8001f3a: 68bb ldr r3, [r7, #8]
+ 8001f3c: 2b00 cmp r3, #0
+ 8001f3e: d113 bne.n 8001f68 <I2C_WaitOnTXISFlagUntilTimeout+0x66>
{
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
- 8001f30: 68fb ldr r3, [r7, #12]
- 8001f32: 6c5b ldr r3, [r3, #68] ; 0x44
- 8001f34: 2220 movs r2, #32
- 8001f36: 431a orrs r2, r3
- 8001f38: 68fb ldr r3, [r7, #12]
- 8001f3a: 645a str r2, [r3, #68] ; 0x44
+ 8001f40: 68fb ldr r3, [r7, #12]
+ 8001f42: 6c5b ldr r3, [r3, #68] ; 0x44
+ 8001f44: 2220 movs r2, #32
+ 8001f46: 431a orrs r2, r3
+ 8001f48: 68fb ldr r3, [r7, #12]
+ 8001f4a: 645a str r2, [r3, #68] ; 0x44
hi2c->State = HAL_I2C_STATE_READY;
- 8001f3c: 68fb ldr r3, [r7, #12]
- 8001f3e: 2241 movs r2, #65 ; 0x41
- 8001f40: 2120 movs r1, #32
- 8001f42: 5499 strb r1, [r3, r2]
+ 8001f4c: 68fb ldr r3, [r7, #12]
+ 8001f4e: 2241 movs r2, #65 ; 0x41
+ 8001f50: 2120 movs r1, #32
+ 8001f52: 5499 strb r1, [r3, r2]
hi2c->Mode = HAL_I2C_MODE_NONE;
- 8001f44: 68fb ldr r3, [r7, #12]
- 8001f46: 2242 movs r2, #66 ; 0x42
- 8001f48: 2100 movs r1, #0
- 8001f4a: 5499 strb r1, [r3, r2]
+ 8001f54: 68fb ldr r3, [r7, #12]
+ 8001f56: 2242 movs r2, #66 ; 0x42
+ 8001f58: 2100 movs r1, #0
+ 8001f5a: 5499 strb r1, [r3, r2]
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
- 8001f4c: 68fb ldr r3, [r7, #12]
- 8001f4e: 2240 movs r2, #64 ; 0x40
- 8001f50: 2100 movs r1, #0
- 8001f52: 5499 strb r1, [r3, r2]
+ 8001f5c: 68fb ldr r3, [r7, #12]
+ 8001f5e: 2240 movs r2, #64 ; 0x40
+ 8001f60: 2100 movs r1, #0
+ 8001f62: 5499 strb r1, [r3, r2]
return HAL_ERROR;
- 8001f54: 2301 movs r3, #1
- 8001f56: e007 b.n 8001f68 <I2C_WaitOnTXISFlagUntilTimeout+0x76>
+ 8001f64: 2301 movs r3, #1
+ 8001f66: e007 b.n 8001f78 <I2C_WaitOnTXISFlagUntilTimeout+0x76>
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET)
- 8001f58: 68fb ldr r3, [r7, #12]
- 8001f5a: 681b ldr r3, [r3, #0]
- 8001f5c: 699b ldr r3, [r3, #24]
- 8001f5e: 2202 movs r2, #2
- 8001f60: 4013 ands r3, r2
- 8001f62: 2b02 cmp r3, #2
- 8001f64: d1cc bne.n 8001f00 <I2C_WaitOnTXISFlagUntilTimeout+0xe>
+ 8001f68: 68fb ldr r3, [r7, #12]
+ 8001f6a: 681b ldr r3, [r3, #0]
+ 8001f6c: 699b ldr r3, [r3, #24]
+ 8001f6e: 2202 movs r2, #2
+ 8001f70: 4013 ands r3, r2
+ 8001f72: 2b02 cmp r3, #2
+ 8001f74: d1cc bne.n 8001f10 <I2C_WaitOnTXISFlagUntilTimeout+0xe>
}
}
}
return HAL_OK;
- 8001f66: 2300 movs r3, #0
+ 8001f76: 2300 movs r3, #0
}
- 8001f68: 0018 movs r0, r3
- 8001f6a: 46bd mov sp, r7
- 8001f6c: b004 add sp, #16
- 8001f6e: bd80 pop {r7, pc}
+ 8001f78: 0018 movs r0, r3
+ 8001f7a: 46bd mov sp, r7
+ 8001f7c: b004 add sp, #16
+ 8001f7e: bd80 pop {r7, pc}
-08001f70 <I2C_WaitOnSTOPFlagUntilTimeout>:
+08001f80 <I2C_WaitOnSTOPFlagUntilTimeout>:
* @param Tickstart Tick start value
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
uint32_t Tickstart)
{
- 8001f70: b580 push {r7, lr}
- 8001f72: b084 sub sp, #16
- 8001f74: af00 add r7, sp, #0
- 8001f76: 60f8 str r0, [r7, #12]
- 8001f78: 60b9 str r1, [r7, #8]
- 8001f7a: 607a str r2, [r7, #4]
+ 8001f80: b580 push {r7, lr}
+ 8001f82: b084 sub sp, #16
+ 8001f84: af00 add r7, sp, #0
+ 8001f86: 60f8 str r0, [r7, #12]
+ 8001f88: 60b9 str r1, [r7, #8]
+ 8001f8a: 607a str r2, [r7, #4]
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
- 8001f7c: e028 b.n 8001fd0 <I2C_WaitOnSTOPFlagUntilTimeout+0x60>
+ 8001f8c: e028 b.n 8001fe0 <I2C_WaitOnSTOPFlagUntilTimeout+0x60>
{
/* Check if a NACK is detected */
if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK)
- 8001f7e: 687a ldr r2, [r7, #4]
- 8001f80: 68b9 ldr r1, [r7, #8]
- 8001f82: 68fb ldr r3, [r7, #12]
- 8001f84: 0018 movs r0, r3
- 8001f86: f000 f89b bl 80020c0 <I2C_IsAcknowledgeFailed>
- 8001f8a: 1e03 subs r3, r0, #0
- 8001f8c: d001 beq.n 8001f92 <I2C_WaitOnSTOPFlagUntilTimeout+0x22>
+ 8001f8e: 687a ldr r2, [r7, #4]
+ 8001f90: 68b9 ldr r1, [r7, #8]
+ 8001f92: 68fb ldr r3, [r7, #12]
+ 8001f94: 0018 movs r0, r3
+ 8001f96: f000 f89b bl 80020d0 <I2C_IsAcknowledgeFailed>
+ 8001f9a: 1e03 subs r3, r0, #0
+ 8001f9c: d001 beq.n 8001fa2 <I2C_WaitOnSTOPFlagUntilTimeout+0x22>
{
return HAL_ERROR;
- 8001f8e: 2301 movs r3, #1
- 8001f90: e026 b.n 8001fe0 <I2C_WaitOnSTOPFlagUntilTimeout+0x70>
+ 8001f9e: 2301 movs r3, #1
+ 8001fa0: e026 b.n 8001ff0 <I2C_WaitOnSTOPFlagUntilTimeout+0x70>
}
/* Check for the Timeout */
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
- 8001f92: f7ff f8c1 bl 8001118 <HAL_GetTick>
- 8001f96: 0002 movs r2, r0
- 8001f98: 687b ldr r3, [r7, #4]
- 8001f9a: 1ad3 subs r3, r2, r3
- 8001f9c: 68ba ldr r2, [r7, #8]
- 8001f9e: 429a cmp r2, r3
- 8001fa0: d302 bcc.n 8001fa8 <I2C_WaitOnSTOPFlagUntilTimeout+0x38>
- 8001fa2: 68bb ldr r3, [r7, #8]
- 8001fa4: 2b00 cmp r3, #0
- 8001fa6: d113 bne.n 8001fd0 <I2C_WaitOnSTOPFlagUntilTimeout+0x60>
+ 8001fa2: f7ff f8c1 bl 8001128 <HAL_GetTick>
+ 8001fa6: 0002 movs r2, r0
+ 8001fa8: 687b ldr r3, [r7, #4]
+ 8001faa: 1ad3 subs r3, r2, r3
+ 8001fac: 68ba ldr r2, [r7, #8]
+ 8001fae: 429a cmp r2, r3
+ 8001fb0: d302 bcc.n 8001fb8 <I2C_WaitOnSTOPFlagUntilTimeout+0x38>
+ 8001fb2: 68bb ldr r3, [r7, #8]
+ 8001fb4: 2b00 cmp r3, #0
+ 8001fb6: d113 bne.n 8001fe0 <I2C_WaitOnSTOPFlagUntilTimeout+0x60>
{
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
- 8001fa8: 68fb ldr r3, [r7, #12]
- 8001faa: 6c5b ldr r3, [r3, #68] ; 0x44
- 8001fac: 2220 movs r2, #32
- 8001fae: 431a orrs r2, r3
- 8001fb0: 68fb ldr r3, [r7, #12]
- 8001fb2: 645a str r2, [r3, #68] ; 0x44
+ 8001fb8: 68fb ldr r3, [r7, #12]
+ 8001fba: 6c5b ldr r3, [r3, #68] ; 0x44
+ 8001fbc: 2220 movs r2, #32
+ 8001fbe: 431a orrs r2, r3
+ 8001fc0: 68fb ldr r3, [r7, #12]
+ 8001fc2: 645a str r2, [r3, #68] ; 0x44
hi2c->State = HAL_I2C_STATE_READY;
- 8001fb4: 68fb ldr r3, [r7, #12]
- 8001fb6: 2241 movs r2, #65 ; 0x41
- 8001fb8: 2120 movs r1, #32
- 8001fba: 5499 strb r1, [r3, r2]
+ 8001fc4: 68fb ldr r3, [r7, #12]
+ 8001fc6: 2241 movs r2, #65 ; 0x41
+ 8001fc8: 2120 movs r1, #32
+ 8001fca: 5499 strb r1, [r3, r2]
hi2c->Mode = HAL_I2C_MODE_NONE;
- 8001fbc: 68fb ldr r3, [r7, #12]
- 8001fbe: 2242 movs r2, #66 ; 0x42
- 8001fc0: 2100 movs r1, #0
- 8001fc2: 5499 strb r1, [r3, r2]
+ 8001fcc: 68fb ldr r3, [r7, #12]
+ 8001fce: 2242 movs r2, #66 ; 0x42
+ 8001fd0: 2100 movs r1, #0
+ 8001fd2: 5499 strb r1, [r3, r2]
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
- 8001fc4: 68fb ldr r3, [r7, #12]
- 8001fc6: 2240 movs r2, #64 ; 0x40
- 8001fc8: 2100 movs r1, #0
- 8001fca: 5499 strb r1, [r3, r2]
+ 8001fd4: 68fb ldr r3, [r7, #12]
+ 8001fd6: 2240 movs r2, #64 ; 0x40
+ 8001fd8: 2100 movs r1, #0
+ 8001fda: 5499 strb r1, [r3, r2]
return HAL_ERROR;
- 8001fcc: 2301 movs r3, #1
- 8001fce: e007 b.n 8001fe0 <I2C_WaitOnSTOPFlagUntilTimeout+0x70>
+ 8001fdc: 2301 movs r3, #1
+ 8001fde: e007 b.n 8001ff0 <I2C_WaitOnSTOPFlagUntilTimeout+0x70>
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
- 8001fd0: 68fb ldr r3, [r7, #12]
- 8001fd2: 681b ldr r3, [r3, #0]
- 8001fd4: 699b ldr r3, [r3, #24]
- 8001fd6: 2220 movs r2, #32
- 8001fd8: 4013 ands r3, r2
- 8001fda: 2b20 cmp r3, #32
- 8001fdc: d1cf bne.n 8001f7e <I2C_WaitOnSTOPFlagUntilTimeout+0xe>
+ 8001fe0: 68fb ldr r3, [r7, #12]
+ 8001fe2: 681b ldr r3, [r3, #0]
+ 8001fe4: 699b ldr r3, [r3, #24]
+ 8001fe6: 2220 movs r2, #32
+ 8001fe8: 4013 ands r3, r2
+ 8001fea: 2b20 cmp r3, #32
+ 8001fec: d1cf bne.n 8001f8e <I2C_WaitOnSTOPFlagUntilTimeout+0xe>
}
}
return HAL_OK;
- 8001fde: 2300 movs r3, #0
+ 8001fee: 2300 movs r3, #0
}
- 8001fe0: 0018 movs r0, r3
- 8001fe2: 46bd mov sp, r7
- 8001fe4: b004 add sp, #16
- 8001fe6: bd80 pop {r7, pc}
+ 8001ff0: 0018 movs r0, r3
+ 8001ff2: 46bd mov sp, r7
+ 8001ff4: b004 add sp, #16
+ 8001ff6: bd80 pop {r7, pc}
-08001fe8 <I2C_WaitOnRXNEFlagUntilTimeout>:
+08001ff8 <I2C_WaitOnRXNEFlagUntilTimeout>:
* @param Tickstart Tick start value
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
uint32_t Tickstart)
{
- 8001fe8: b580 push {r7, lr}
- 8001fea: b084 sub sp, #16
- 8001fec: af00 add r7, sp, #0
- 8001fee: 60f8 str r0, [r7, #12]
- 8001ff0: 60b9 str r1, [r7, #8]
- 8001ff2: 607a str r2, [r7, #4]
+ 8001ff8: b580 push {r7, lr}
+ 8001ffa: b084 sub sp, #16
+ 8001ffc: af00 add r7, sp, #0
+ 8001ffe: 60f8 str r0, [r7, #12]
+ 8002000: 60b9 str r1, [r7, #8]
+ 8002002: 607a str r2, [r7, #4]
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)
- 8001ff4: e055 b.n 80020a2 <I2C_WaitOnRXNEFlagUntilTimeout+0xba>
+ 8002004: e055 b.n 80020b2 <I2C_WaitOnRXNEFlagUntilTimeout+0xba>
{
/* Check if a NACK is detected */
if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK)
- 8001ff6: 687a ldr r2, [r7, #4]
- 8001ff8: 68b9 ldr r1, [r7, #8]
- 8001ffa: 68fb ldr r3, [r7, #12]
- 8001ffc: 0018 movs r0, r3
- 8001ffe: f000 f85f bl 80020c0 <I2C_IsAcknowledgeFailed>
- 8002002: 1e03 subs r3, r0, #0
- 8002004: d001 beq.n 800200a <I2C_WaitOnRXNEFlagUntilTimeout+0x22>
+ 8002006: 687a ldr r2, [r7, #4]
+ 8002008: 68b9 ldr r1, [r7, #8]
+ 800200a: 68fb ldr r3, [r7, #12]
+ 800200c: 0018 movs r0, r3
+ 800200e: f000 f85f bl 80020d0 <I2C_IsAcknowledgeFailed>
+ 8002012: 1e03 subs r3, r0, #0
+ 8002014: d001 beq.n 800201a <I2C_WaitOnRXNEFlagUntilTimeout+0x22>
{
return HAL_ERROR;
- 8002006: 2301 movs r3, #1
- 8002008: e053 b.n 80020b2 <I2C_WaitOnRXNEFlagUntilTimeout+0xca>
+ 8002016: 2301 movs r3, #1
+ 8002018: e053 b.n 80020c2 <I2C_WaitOnRXNEFlagUntilTimeout+0xca>
}
/* Check if a STOPF is detected */
if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)
- 800200a: 68fb ldr r3, [r7, #12]
- 800200c: 681b ldr r3, [r3, #0]
- 800200e: 699b ldr r3, [r3, #24]
- 8002010: 2220 movs r2, #32
- 8002012: 4013 ands r3, r2
- 8002014: 2b20 cmp r3, #32
- 8002016: d129 bne.n 800206c <I2C_WaitOnRXNEFlagUntilTimeout+0x84>
+ 800201a: 68fb ldr r3, [r7, #12]
+ 800201c: 681b ldr r3, [r3, #0]
+ 800201e: 699b ldr r3, [r3, #24]
+ 8002020: 2220 movs r2, #32
+ 8002022: 4013 ands r3, r2
+ 8002024: 2b20 cmp r3, #32
+ 8002026: d129 bne.n 800207c <I2C_WaitOnRXNEFlagUntilTimeout+0x84>
{
/* Check if an RXNE is pending */
/* Store Last receive data if any */
if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) && (hi2c->XferSize > 0U))
- 8002018: 68fb ldr r3, [r7, #12]
- 800201a: 681b ldr r3, [r3, #0]
- 800201c: 699b ldr r3, [r3, #24]
- 800201e: 2204 movs r2, #4
- 8002020: 4013 ands r3, r2
- 8002022: 2b04 cmp r3, #4
- 8002024: d105 bne.n 8002032 <I2C_WaitOnRXNEFlagUntilTimeout+0x4a>
- 8002026: 68fb ldr r3, [r7, #12]
- 8002028: 8d1b ldrh r3, [r3, #40] ; 0x28
- 800202a: 2b00 cmp r3, #0
- 800202c: d001 beq.n 8002032 <I2C_WaitOnRXNEFlagUntilTimeout+0x4a>
+ 8002028: 68fb ldr r3, [r7, #12]
+ 800202a: 681b ldr r3, [r3, #0]
+ 800202c: 699b ldr r3, [r3, #24]
+ 800202e: 2204 movs r2, #4
+ 8002030: 4013 ands r3, r2
+ 8002032: 2b04 cmp r3, #4
+ 8002034: d105 bne.n 8002042 <I2C_WaitOnRXNEFlagUntilTimeout+0x4a>
+ 8002036: 68fb ldr r3, [r7, #12]
+ 8002038: 8d1b ldrh r3, [r3, #40] ; 0x28
+ 800203a: 2b00 cmp r3, #0
+ 800203c: d001 beq.n 8002042 <I2C_WaitOnRXNEFlagUntilTimeout+0x4a>
{
/* Return HAL_OK */
/* The Reading of data from RXDR will be done in caller function */
return HAL_OK;
- 800202e: 2300 movs r3, #0
- 8002030: e03f b.n 80020b2 <I2C_WaitOnRXNEFlagUntilTimeout+0xca>
+ 800203e: 2300 movs r3, #0
+ 8002040: e03f b.n 80020c2 <I2C_WaitOnRXNEFlagUntilTimeout+0xca>
}
else
{
/* Clear STOP Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
- 8002032: 68fb ldr r3, [r7, #12]
- 8002034: 681b ldr r3, [r3, #0]
- 8002036: 2220 movs r2, #32
- 8002038: 61da str r2, [r3, #28]
+ 8002042: 68fb ldr r3, [r7, #12]
+ 8002044: 681b ldr r3, [r3, #0]
+ 8002046: 2220 movs r2, #32
+ 8002048: 61da str r2, [r3, #28]
/* Clear Configuration Register 2 */
I2C_RESET_CR2(hi2c);
- 800203a: 68fb ldr r3, [r7, #12]
- 800203c: 681b ldr r3, [r3, #0]
- 800203e: 685a ldr r2, [r3, #4]
- 8002040: 68fb ldr r3, [r7, #12]
- 8002042: 681b ldr r3, [r3, #0]
- 8002044: 491d ldr r1, [pc, #116] ; (80020bc <I2C_WaitOnRXNEFlagUntilTimeout+0xd4>)
- 8002046: 400a ands r2, r1
- 8002048: 605a str r2, [r3, #4]
+ 800204a: 68fb ldr r3, [r7, #12]
+ 800204c: 681b ldr r3, [r3, #0]
+ 800204e: 685a ldr r2, [r3, #4]
+ 8002050: 68fb ldr r3, [r7, #12]
+ 8002052: 681b ldr r3, [r3, #0]
+ 8002054: 491d ldr r1, [pc, #116] ; (80020cc <I2C_WaitOnRXNEFlagUntilTimeout+0xd4>)
+ 8002056: 400a ands r2, r1
+ 8002058: 605a str r2, [r3, #4]
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
- 800204a: 68fb ldr r3, [r7, #12]
- 800204c: 2200 movs r2, #0
- 800204e: 645a str r2, [r3, #68] ; 0x44
+ 800205a: 68fb ldr r3, [r7, #12]
+ 800205c: 2200 movs r2, #0
+ 800205e: 645a str r2, [r3, #68] ; 0x44
hi2c->State = HAL_I2C_STATE_READY;
- 8002050: 68fb ldr r3, [r7, #12]
- 8002052: 2241 movs r2, #65 ; 0x41
- 8002054: 2120 movs r1, #32
- 8002056: 5499 strb r1, [r3, r2]
+ 8002060: 68fb ldr r3, [r7, #12]
+ 8002062: 2241 movs r2, #65 ; 0x41
+ 8002064: 2120 movs r1, #32
+ 8002066: 5499 strb r1, [r3, r2]
hi2c->Mode = HAL_I2C_MODE_NONE;
- 8002058: 68fb ldr r3, [r7, #12]
- 800205a: 2242 movs r2, #66 ; 0x42
- 800205c: 2100 movs r1, #0
- 800205e: 5499 strb r1, [r3, r2]
+ 8002068: 68fb ldr r3, [r7, #12]
+ 800206a: 2242 movs r2, #66 ; 0x42
+ 800206c: 2100 movs r1, #0
+ 800206e: 5499 strb r1, [r3, r2]
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
- 8002060: 68fb ldr r3, [r7, #12]
- 8002062: 2240 movs r2, #64 ; 0x40
- 8002064: 2100 movs r1, #0
- 8002066: 5499 strb r1, [r3, r2]
+ 8002070: 68fb ldr r3, [r7, #12]
+ 8002072: 2240 movs r2, #64 ; 0x40
+ 8002074: 2100 movs r1, #0
+ 8002076: 5499 strb r1, [r3, r2]
return HAL_ERROR;
- 8002068: 2301 movs r3, #1
- 800206a: e022 b.n 80020b2 <I2C_WaitOnRXNEFlagUntilTimeout+0xca>
+ 8002078: 2301 movs r3, #1
+ 800207a: e022 b.n 80020c2 <I2C_WaitOnRXNEFlagUntilTimeout+0xca>
}
}
/* Check for the Timeout */
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
- 800206c: f7ff f854 bl 8001118 <HAL_GetTick>
- 8002070: 0002 movs r2, r0
- 8002072: 687b ldr r3, [r7, #4]
- 8002074: 1ad3 subs r3, r2, r3
- 8002076: 68ba ldr r2, [r7, #8]
- 8002078: 429a cmp r2, r3
- 800207a: d302 bcc.n 8002082 <I2C_WaitOnRXNEFlagUntilTimeout+0x9a>
- 800207c: 68bb ldr r3, [r7, #8]
- 800207e: 2b00 cmp r3, #0
- 8002080: d10f bne.n 80020a2 <I2C_WaitOnRXNEFlagUntilTimeout+0xba>
+ 800207c: f7ff f854 bl 8001128 <HAL_GetTick>
+ 8002080: 0002 movs r2, r0
+ 8002082: 687b ldr r3, [r7, #4]
+ 8002084: 1ad3 subs r3, r2, r3
+ 8002086: 68ba ldr r2, [r7, #8]
+ 8002088: 429a cmp r2, r3
+ 800208a: d302 bcc.n 8002092 <I2C_WaitOnRXNEFlagUntilTimeout+0x9a>
+ 800208c: 68bb ldr r3, [r7, #8]
+ 800208e: 2b00 cmp r3, #0
+ 8002090: d10f bne.n 80020b2 <I2C_WaitOnRXNEFlagUntilTimeout+0xba>
{
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
- 8002082: 68fb ldr r3, [r7, #12]
- 8002084: 6c5b ldr r3, [r3, #68] ; 0x44
- 8002086: 2220 movs r2, #32
- 8002088: 431a orrs r2, r3
- 800208a: 68fb ldr r3, [r7, #12]
- 800208c: 645a str r2, [r3, #68] ; 0x44
+ 8002092: 68fb ldr r3, [r7, #12]
+ 8002094: 6c5b ldr r3, [r3, #68] ; 0x44
+ 8002096: 2220 movs r2, #32
+ 8002098: 431a orrs r2, r3
+ 800209a: 68fb ldr r3, [r7, #12]
+ 800209c: 645a str r2, [r3, #68] ; 0x44
hi2c->State = HAL_I2C_STATE_READY;
- 800208e: 68fb ldr r3, [r7, #12]
- 8002090: 2241 movs r2, #65 ; 0x41
- 8002092: 2120 movs r1, #32
- 8002094: 5499 strb r1, [r3, r2]
+ 800209e: 68fb ldr r3, [r7, #12]
+ 80020a0: 2241 movs r2, #65 ; 0x41
+ 80020a2: 2120 movs r1, #32
+ 80020a4: 5499 strb r1, [r3, r2]
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
- 8002096: 68fb ldr r3, [r7, #12]
- 8002098: 2240 movs r2, #64 ; 0x40
- 800209a: 2100 movs r1, #0
- 800209c: 5499 strb r1, [r3, r2]
+ 80020a6: 68fb ldr r3, [r7, #12]
+ 80020a8: 2240 movs r2, #64 ; 0x40
+ 80020aa: 2100 movs r1, #0
+ 80020ac: 5499 strb r1, [r3, r2]
return HAL_ERROR;
- 800209e: 2301 movs r3, #1
- 80020a0: e007 b.n 80020b2 <I2C_WaitOnRXNEFlagUntilTimeout+0xca>
+ 80020ae: 2301 movs r3, #1
+ 80020b0: e007 b.n 80020c2 <I2C_WaitOnRXNEFlagUntilTimeout+0xca>
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)
- 80020a2: 68fb ldr r3, [r7, #12]
- 80020a4: 681b ldr r3, [r3, #0]
- 80020a6: 699b ldr r3, [r3, #24]
- 80020a8: 2204 movs r2, #4
- 80020aa: 4013 ands r3, r2
- 80020ac: 2b04 cmp r3, #4
- 80020ae: d1a2 bne.n 8001ff6 <I2C_WaitOnRXNEFlagUntilTimeout+0xe>
+ 80020b2: 68fb ldr r3, [r7, #12]
+ 80020b4: 681b ldr r3, [r3, #0]
+ 80020b6: 699b ldr r3, [r3, #24]
+ 80020b8: 2204 movs r2, #4
+ 80020ba: 4013 ands r3, r2
+ 80020bc: 2b04 cmp r3, #4
+ 80020be: d1a2 bne.n 8002006 <I2C_WaitOnRXNEFlagUntilTimeout+0xe>
}
}
return HAL_OK;
- 80020b0: 2300 movs r3, #0
+ 80020c0: 2300 movs r3, #0
}
- 80020b2: 0018 movs r0, r3
- 80020b4: 46bd mov sp, r7
- 80020b6: b004 add sp, #16
- 80020b8: bd80 pop {r7, pc}
- 80020ba: 46c0 nop ; (mov r8, r8)
- 80020bc: fe00e800 .word 0xfe00e800
+ 80020c2: 0018 movs r0, r3
+ 80020c4: 46bd mov sp, r7
+ 80020c6: b004 add sp, #16
+ 80020c8: bd80 pop {r7, pc}
+ 80020ca: 46c0 nop ; (mov r8, r8)
+ 80020cc: fe00e800 .word 0xfe00e800
-080020c0 <I2C_IsAcknowledgeFailed>:
+080020d0 <I2C_IsAcknowledgeFailed>:
* @param Timeout Timeout duration
* @param Tickstart Tick start value
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
{
- 80020c0: b580 push {r7, lr}
- 80020c2: b084 sub sp, #16
- 80020c4: af00 add r7, sp, #0
- 80020c6: 60f8 str r0, [r7, #12]
- 80020c8: 60b9 str r1, [r7, #8]
- 80020ca: 607a str r2, [r7, #4]
+ 80020d0: b580 push {r7, lr}
+ 80020d2: b084 sub sp, #16
+ 80020d4: af00 add r7, sp, #0
+ 80020d6: 60f8 str r0, [r7, #12]
+ 80020d8: 60b9 str r1, [r7, #8]
+ 80020da: 607a str r2, [r7, #4]
if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
- 80020cc: 68fb ldr r3, [r7, #12]
- 80020ce: 681b ldr r3, [r3, #0]
- 80020d0: 699b ldr r3, [r3, #24]
- 80020d2: 2210 movs r2, #16
- 80020d4: 4013 ands r3, r2
- 80020d6: 2b10 cmp r3, #16
- 80020d8: d164 bne.n 80021a4 <I2C_IsAcknowledgeFailed+0xe4>
+ 80020dc: 68fb ldr r3, [r7, #12]
+ 80020de: 681b ldr r3, [r3, #0]
+ 80020e0: 699b ldr r3, [r3, #24]
+ 80020e2: 2210 movs r2, #16
+ 80020e4: 4013 ands r3, r2
+ 80020e6: 2b10 cmp r3, #16
+ 80020e8: d164 bne.n 80021b4 <I2C_IsAcknowledgeFailed+0xe4>
{
/* In case of Soft End condition, generate the STOP condition */
if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
- 80020da: 68fb ldr r3, [r7, #12]
- 80020dc: 681b ldr r3, [r3, #0]
- 80020de: 685a ldr r2, [r3, #4]
- 80020e0: 2380 movs r3, #128 ; 0x80
- 80020e2: 049b lsls r3, r3, #18
- 80020e4: 401a ands r2, r3
- 80020e6: 2380 movs r3, #128 ; 0x80
- 80020e8: 049b lsls r3, r3, #18
- 80020ea: 429a cmp r2, r3
- 80020ec: d02b beq.n 8002146 <I2C_IsAcknowledgeFailed+0x86>
+ 80020ea: 68fb ldr r3, [r7, #12]
+ 80020ec: 681b ldr r3, [r3, #0]
+ 80020ee: 685a ldr r2, [r3, #4]
+ 80020f0: 2380 movs r3, #128 ; 0x80
+ 80020f2: 049b lsls r3, r3, #18
+ 80020f4: 401a ands r2, r3
+ 80020f6: 2380 movs r3, #128 ; 0x80
+ 80020f8: 049b lsls r3, r3, #18
+ 80020fa: 429a cmp r2, r3
+ 80020fc: d02b beq.n 8002156 <I2C_IsAcknowledgeFailed+0x86>
{
/* Generate Stop */
hi2c->Instance->CR2 |= I2C_CR2_STOP;
- 80020ee: 68fb ldr r3, [r7, #12]
- 80020f0: 681b ldr r3, [r3, #0]
- 80020f2: 685a ldr r2, [r3, #4]
- 80020f4: 68fb ldr r3, [r7, #12]
- 80020f6: 681b ldr r3, [r3, #0]
- 80020f8: 2180 movs r1, #128 ; 0x80
- 80020fa: 01c9 lsls r1, r1, #7
- 80020fc: 430a orrs r2, r1
- 80020fe: 605a str r2, [r3, #4]
+ 80020fe: 68fb ldr r3, [r7, #12]
+ 8002100: 681b ldr r3, [r3, #0]
+ 8002102: 685a ldr r2, [r3, #4]
+ 8002104: 68fb ldr r3, [r7, #12]
+ 8002106: 681b ldr r3, [r3, #0]
+ 8002108: 2180 movs r1, #128 ; 0x80
+ 800210a: 01c9 lsls r1, r1, #7
+ 800210c: 430a orrs r2, r1
+ 800210e: 605a str r2, [r3, #4]
}
/* Wait until STOP Flag is reset */
/* AutoEnd should be initiate after AF */
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
- 8002100: e021 b.n 8002146 <I2C_IsAcknowledgeFailed+0x86>
+ 8002110: e021 b.n 8002156 <I2C_IsAcknowledgeFailed+0x86>
{
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
- 8002102: 68bb ldr r3, [r7, #8]
- 8002104: 3301 adds r3, #1
- 8002106: d01e beq.n 8002146 <I2C_IsAcknowledgeFailed+0x86>
+ 8002112: 68bb ldr r3, [r7, #8]
+ 8002114: 3301 adds r3, #1
+ 8002116: d01e beq.n 8002156 <I2C_IsAcknowledgeFailed+0x86>
{
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
- 8002108: f7ff f806 bl 8001118 <HAL_GetTick>
- 800210c: 0002 movs r2, r0
- 800210e: 687b ldr r3, [r7, #4]
- 8002110: 1ad3 subs r3, r2, r3
- 8002112: 68ba ldr r2, [r7, #8]
- 8002114: 429a cmp r2, r3
- 8002116: d302 bcc.n 800211e <I2C_IsAcknowledgeFailed+0x5e>
- 8002118: 68bb ldr r3, [r7, #8]
- 800211a: 2b00 cmp r3, #0
- 800211c: d113 bne.n 8002146 <I2C_IsAcknowledgeFailed+0x86>
+ 8002118: f7ff f806 bl 8001128 <HAL_GetTick>
+ 800211c: 0002 movs r2, r0
+ 800211e: 687b ldr r3, [r7, #4]
+ 8002120: 1ad3 subs r3, r2, r3
+ 8002122: 68ba ldr r2, [r7, #8]
+ 8002124: 429a cmp r2, r3
+ 8002126: d302 bcc.n 800212e <I2C_IsAcknowledgeFailed+0x5e>
+ 8002128: 68bb ldr r3, [r7, #8]
+ 800212a: 2b00 cmp r3, #0
+ 800212c: d113 bne.n 8002156 <I2C_IsAcknowledgeFailed+0x86>
{
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
- 800211e: 68fb ldr r3, [r7, #12]
- 8002120: 6c5b ldr r3, [r3, #68] ; 0x44
- 8002122: 2220 movs r2, #32
- 8002124: 431a orrs r2, r3
- 8002126: 68fb ldr r3, [r7, #12]
- 8002128: 645a str r2, [r3, #68] ; 0x44
+ 800212e: 68fb ldr r3, [r7, #12]
+ 8002130: 6c5b ldr r3, [r3, #68] ; 0x44
+ 8002132: 2220 movs r2, #32
+ 8002134: 431a orrs r2, r3
+ 8002136: 68fb ldr r3, [r7, #12]
+ 8002138: 645a str r2, [r3, #68] ; 0x44
hi2c->State = HAL_I2C_STATE_READY;
- 800212a: 68fb ldr r3, [r7, #12]
- 800212c: 2241 movs r2, #65 ; 0x41
- 800212e: 2120 movs r1, #32
- 8002130: 5499 strb r1, [r3, r2]
+ 800213a: 68fb ldr r3, [r7, #12]
+ 800213c: 2241 movs r2, #65 ; 0x41
+ 800213e: 2120 movs r1, #32
+ 8002140: 5499 strb r1, [r3, r2]
hi2c->Mode = HAL_I2C_MODE_NONE;
- 8002132: 68fb ldr r3, [r7, #12]
- 8002134: 2242 movs r2, #66 ; 0x42
- 8002136: 2100 movs r1, #0
- 8002138: 5499 strb r1, [r3, r2]
+ 8002142: 68fb ldr r3, [r7, #12]
+ 8002144: 2242 movs r2, #66 ; 0x42
+ 8002146: 2100 movs r1, #0
+ 8002148: 5499 strb r1, [r3, r2]
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
- 800213a: 68fb ldr r3, [r7, #12]
- 800213c: 2240 movs r2, #64 ; 0x40
- 800213e: 2100 movs r1, #0
- 8002140: 5499 strb r1, [r3, r2]
+ 800214a: 68fb ldr r3, [r7, #12]
+ 800214c: 2240 movs r2, #64 ; 0x40
+ 800214e: 2100 movs r1, #0
+ 8002150: 5499 strb r1, [r3, r2]
return HAL_ERROR;
- 8002142: 2301 movs r3, #1
- 8002144: e02f b.n 80021a6 <I2C_IsAcknowledgeFailed+0xe6>
+ 8002152: 2301 movs r3, #1
+ 8002154: e02f b.n 80021b6 <I2C_IsAcknowledgeFailed+0xe6>
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
- 8002146: 68fb ldr r3, [r7, #12]
- 8002148: 681b ldr r3, [r3, #0]
- 800214a: 699b ldr r3, [r3, #24]
- 800214c: 2220 movs r2, #32
- 800214e: 4013 ands r3, r2
- 8002150: 2b20 cmp r3, #32
- 8002152: d1d6 bne.n 8002102 <I2C_IsAcknowledgeFailed+0x42>
+ 8002156: 68fb ldr r3, [r7, #12]
+ 8002158: 681b ldr r3, [r3, #0]
+ 800215a: 699b ldr r3, [r3, #24]
+ 800215c: 2220 movs r2, #32
+ 800215e: 4013 ands r3, r2
+ 8002160: 2b20 cmp r3, #32
+ 8002162: d1d6 bne.n 8002112 <I2C_IsAcknowledgeFailed+0x42>
}
}
}
/* Clear NACKF Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
- 8002154: 68fb ldr r3, [r7, #12]
- 8002156: 681b ldr r3, [r3, #0]
- 8002158: 2210 movs r2, #16
- 800215a: 61da str r2, [r3, #28]
+ 8002164: 68fb ldr r3, [r7, #12]
+ 8002166: 681b ldr r3, [r3, #0]
+ 8002168: 2210 movs r2, #16
+ 800216a: 61da str r2, [r3, #28]
/* Clear STOP Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
- 800215c: 68fb ldr r3, [r7, #12]
- 800215e: 681b ldr r3, [r3, #0]
- 8002160: 2220 movs r2, #32
- 8002162: 61da str r2, [r3, #28]
+ 800216c: 68fb ldr r3, [r7, #12]
+ 800216e: 681b ldr r3, [r3, #0]
+ 8002170: 2220 movs r2, #32
+ 8002172: 61da str r2, [r3, #28]
/* Flush TX register */
I2C_Flush_TXDR(hi2c);
- 8002164: 68fb ldr r3, [r7, #12]
- 8002166: 0018 movs r0, r3
- 8002168: f7ff fe62 bl 8001e30 <I2C_Flush_TXDR>
+ 8002174: 68fb ldr r3, [r7, #12]
+ 8002176: 0018 movs r0, r3
+ 8002178: f7ff fe62 bl 8001e40 <I2C_Flush_TXDR>
/* Clear Configuration Register 2 */
I2C_RESET_CR2(hi2c);
- 800216c: 68fb ldr r3, [r7, #12]
- 800216e: 681b ldr r3, [r3, #0]
- 8002170: 685a ldr r2, [r3, #4]
- 8002172: 68fb ldr r3, [r7, #12]
- 8002174: 681b ldr r3, [r3, #0]
- 8002176: 490e ldr r1, [pc, #56] ; (80021b0 <I2C_IsAcknowledgeFailed+0xf0>)
- 8002178: 400a ands r2, r1
- 800217a: 605a str r2, [r3, #4]
+ 800217c: 68fb ldr r3, [r7, #12]
+ 800217e: 681b ldr r3, [r3, #0]
+ 8002180: 685a ldr r2, [r3, #4]
+ 8002182: 68fb ldr r3, [r7, #12]
+ 8002184: 681b ldr r3, [r3, #0]
+ 8002186: 490e ldr r1, [pc, #56] ; (80021c0 <I2C_IsAcknowledgeFailed+0xf0>)
+ 8002188: 400a ands r2, r1
+ 800218a: 605a str r2, [r3, #4]
hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
- 800217c: 68fb ldr r3, [r7, #12]
- 800217e: 6c5b ldr r3, [r3, #68] ; 0x44
- 8002180: 2204 movs r2, #4
- 8002182: 431a orrs r2, r3
- 8002184: 68fb ldr r3, [r7, #12]
- 8002186: 645a str r2, [r3, #68] ; 0x44
+ 800218c: 68fb ldr r3, [r7, #12]
+ 800218e: 6c5b ldr r3, [r3, #68] ; 0x44
+ 8002190: 2204 movs r2, #4
+ 8002192: 431a orrs r2, r3
+ 8002194: 68fb ldr r3, [r7, #12]
+ 8002196: 645a str r2, [r3, #68] ; 0x44
hi2c->State = HAL_I2C_STATE_READY;
- 8002188: 68fb ldr r3, [r7, #12]
- 800218a: 2241 movs r2, #65 ; 0x41
- 800218c: 2120 movs r1, #32
- 800218e: 5499 strb r1, [r3, r2]
+ 8002198: 68fb ldr r3, [r7, #12]
+ 800219a: 2241 movs r2, #65 ; 0x41
+ 800219c: 2120 movs r1, #32
+ 800219e: 5499 strb r1, [r3, r2]
hi2c->Mode = HAL_I2C_MODE_NONE;
- 8002190: 68fb ldr r3, [r7, #12]
- 8002192: 2242 movs r2, #66 ; 0x42
- 8002194: 2100 movs r1, #0
- 8002196: 5499 strb r1, [r3, r2]
+ 80021a0: 68fb ldr r3, [r7, #12]
+ 80021a2: 2242 movs r2, #66 ; 0x42
+ 80021a4: 2100 movs r1, #0
+ 80021a6: 5499 strb r1, [r3, r2]
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
- 8002198: 68fb ldr r3, [r7, #12]
- 800219a: 2240 movs r2, #64 ; 0x40
- 800219c: 2100 movs r1, #0
- 800219e: 5499 strb r1, [r3, r2]
+ 80021a8: 68fb ldr r3, [r7, #12]
+ 80021aa: 2240 movs r2, #64 ; 0x40
+ 80021ac: 2100 movs r1, #0
+ 80021ae: 5499 strb r1, [r3, r2]
return HAL_ERROR;
- 80021a0: 2301 movs r3, #1
- 80021a2: e000 b.n 80021a6 <I2C_IsAcknowledgeFailed+0xe6>
+ 80021b0: 2301 movs r3, #1
+ 80021b2: e000 b.n 80021b6 <I2C_IsAcknowledgeFailed+0xe6>
}
return HAL_OK;
- 80021a4: 2300 movs r3, #0
+ 80021b4: 2300 movs r3, #0
}
- 80021a6: 0018 movs r0, r3
- 80021a8: 46bd mov sp, r7
- 80021aa: b004 add sp, #16
- 80021ac: bd80 pop {r7, pc}
- 80021ae: 46c0 nop ; (mov r8, r8)
- 80021b0: fe00e800 .word 0xfe00e800
+ 80021b6: 0018 movs r0, r3
+ 80021b8: 46bd mov sp, r7
+ 80021ba: b004 add sp, #16
+ 80021bc: bd80 pop {r7, pc}
+ 80021be: 46c0 nop ; (mov r8, r8)
+ 80021c0: fe00e800 .word 0xfe00e800
-080021b4 <I2C_TransferConfig>:
+080021c4 <I2C_TransferConfig>:
* @arg @ref I2C_GENERATE_START_WRITE Generate Restart for write request.
* @retval None
*/
static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode,
uint32_t Request)
{
- 80021b4: b590 push {r4, r7, lr}
- 80021b6: b085 sub sp, #20
- 80021b8: af00 add r7, sp, #0
- 80021ba: 60f8 str r0, [r7, #12]
- 80021bc: 0008 movs r0, r1
- 80021be: 0011 movs r1, r2
- 80021c0: 607b str r3, [r7, #4]
- 80021c2: 240a movs r4, #10
- 80021c4: 193b adds r3, r7, r4
- 80021c6: 1c02 adds r2, r0, #0
- 80021c8: 801a strh r2, [r3, #0]
- 80021ca: 2009 movs r0, #9
- 80021cc: 183b adds r3, r7, r0
- 80021ce: 1c0a adds r2, r1, #0
- 80021d0: 701a strb r2, [r3, #0]
+ 80021c4: b590 push {r4, r7, lr}
+ 80021c6: b085 sub sp, #20
+ 80021c8: af00 add r7, sp, #0
+ 80021ca: 60f8 str r0, [r7, #12]
+ 80021cc: 0008 movs r0, r1
+ 80021ce: 0011 movs r1, r2
+ 80021d0: 607b str r3, [r7, #4]
+ 80021d2: 240a movs r4, #10
+ 80021d4: 193b adds r3, r7, r4
+ 80021d6: 1c02 adds r2, r0, #0
+ 80021d8: 801a strh r2, [r3, #0]
+ 80021da: 2009 movs r0, #9
+ 80021dc: 183b adds r3, r7, r0
+ 80021de: 1c0a adds r2, r1, #0
+ 80021e0: 701a strb r2, [r3, #0]
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
assert_param(IS_TRANSFER_MODE(Mode));
assert_param(IS_TRANSFER_REQUEST(Request));
/* update CR2 register */
MODIFY_REG(hi2c->Instance->CR2,
- 80021d2: 68fb ldr r3, [r7, #12]
- 80021d4: 681b ldr r3, [r3, #0]
- 80021d6: 685b ldr r3, [r3, #4]
- 80021d8: 6a3a ldr r2, [r7, #32]
- 80021da: 0d51 lsrs r1, r2, #21
- 80021dc: 2280 movs r2, #128 ; 0x80
- 80021de: 00d2 lsls r2, r2, #3
- 80021e0: 400a ands r2, r1
- 80021e2: 490e ldr r1, [pc, #56] ; (800221c <I2C_TransferConfig+0x68>)
- 80021e4: 430a orrs r2, r1
- 80021e6: 43d2 mvns r2, r2
- 80021e8: 401a ands r2, r3
- 80021ea: 0011 movs r1, r2
- 80021ec: 193b adds r3, r7, r4
- 80021ee: 881b ldrh r3, [r3, #0]
- 80021f0: 059b lsls r3, r3, #22
- 80021f2: 0d9a lsrs r2, r3, #22
- 80021f4: 183b adds r3, r7, r0
- 80021f6: 781b ldrb r3, [r3, #0]
- 80021f8: 0418 lsls r0, r3, #16
- 80021fa: 23ff movs r3, #255 ; 0xff
- 80021fc: 041b lsls r3, r3, #16
- 80021fe: 4003 ands r3, r0
- 8002200: 431a orrs r2, r3
- 8002202: 687b ldr r3, [r7, #4]
- 8002204: 431a orrs r2, r3
- 8002206: 6a3b ldr r3, [r7, #32]
- 8002208: 431a orrs r2, r3
- 800220a: 68fb ldr r3, [r7, #12]
- 800220c: 681b ldr r3, [r3, #0]
- 800220e: 430a orrs r2, r1
- 8002210: 605a str r2, [r3, #4]
+ 80021e2: 68fb ldr r3, [r7, #12]
+ 80021e4: 681b ldr r3, [r3, #0]
+ 80021e6: 685b ldr r3, [r3, #4]
+ 80021e8: 6a3a ldr r2, [r7, #32]
+ 80021ea: 0d51 lsrs r1, r2, #21
+ 80021ec: 2280 movs r2, #128 ; 0x80
+ 80021ee: 00d2 lsls r2, r2, #3
+ 80021f0: 400a ands r2, r1
+ 80021f2: 490e ldr r1, [pc, #56] ; (800222c <I2C_TransferConfig+0x68>)
+ 80021f4: 430a orrs r2, r1
+ 80021f6: 43d2 mvns r2, r2
+ 80021f8: 401a ands r2, r3
+ 80021fa: 0011 movs r1, r2
+ 80021fc: 193b adds r3, r7, r4
+ 80021fe: 881b ldrh r3, [r3, #0]
+ 8002200: 059b lsls r3, r3, #22
+ 8002202: 0d9a lsrs r2, r3, #22
+ 8002204: 183b adds r3, r7, r0
+ 8002206: 781b ldrb r3, [r3, #0]
+ 8002208: 0418 lsls r0, r3, #16
+ 800220a: 23ff movs r3, #255 ; 0xff
+ 800220c: 041b lsls r3, r3, #16
+ 800220e: 4003 ands r3, r0
+ 8002210: 431a orrs r2, r3
+ 8002212: 687b ldr r3, [r7, #4]
+ 8002214: 431a orrs r2, r3
+ 8002216: 6a3b ldr r3, [r7, #32]
+ 8002218: 431a orrs r2, r3
+ 800221a: 68fb ldr r3, [r7, #12]
+ 800221c: 681b ldr r3, [r3, #0]
+ 800221e: 430a orrs r2, r1
+ 8002220: 605a str r2, [r3, #4]
(I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | \
I2C_CR2_START | I2C_CR2_STOP)), \
(uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \
(((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \
(uint32_t)Mode | (uint32_t)Request));
}
- 8002212: 46c0 nop ; (mov r8, r8)
- 8002214: 46bd mov sp, r7
- 8002216: b005 add sp, #20
- 8002218: bd90 pop {r4, r7, pc}
- 800221a: 46c0 nop ; (mov r8, r8)
- 800221c: 03ff63ff .word 0x03ff63ff
+ 8002222: 46c0 nop ; (mov r8, r8)
+ 8002224: 46bd mov sp, r7
+ 8002226: b005 add sp, #20
+ 8002228: bd90 pop {r4, r7, pc}
+ 800222a: 46c0 nop ; (mov r8, r8)
+ 800222c: 03ff63ff .word 0x03ff63ff
-08002220 <HAL_I2CEx_ConfigAnalogFilter>:
+08002230 <HAL_I2CEx_ConfigAnalogFilter>:
* the configuration information for the specified I2Cx peripheral.
* @param AnalogFilter New state of the Analog filter.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter)
{
- 8002220: b580 push {r7, lr}
- 8002222: b082 sub sp, #8
- 8002224: af00 add r7, sp, #0
- 8002226: 6078 str r0, [r7, #4]
- 8002228: 6039 str r1, [r7, #0]
+ 8002230: b580 push {r7, lr}
+ 8002232: b082 sub sp, #8
+ 8002234: af00 add r7, sp, #0
+ 8002236: 6078 str r0, [r7, #4]
+ 8002238: 6039 str r1, [r7, #0]
/* Check the parameters */
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter));
if (hi2c->State == HAL_I2C_STATE_READY)
- 800222a: 687b ldr r3, [r7, #4]
- 800222c: 2241 movs r2, #65 ; 0x41
- 800222e: 5c9b ldrb r3, [r3, r2]
- 8002230: b2db uxtb r3, r3
- 8002232: 2b20 cmp r3, #32
- 8002234: d138 bne.n 80022a8 <HAL_I2CEx_ConfigAnalogFilter+0x88>
+ 800223a: 687b ldr r3, [r7, #4]
+ 800223c: 2241 movs r2, #65 ; 0x41
+ 800223e: 5c9b ldrb r3, [r3, r2]
+ 8002240: b2db uxtb r3, r3
+ 8002242: 2b20 cmp r3, #32
+ 8002244: d138 bne.n 80022b8 <HAL_I2CEx_ConfigAnalogFilter+0x88>
{
/* Process Locked */
__HAL_LOCK(hi2c);
- 8002236: 687b ldr r3, [r7, #4]
- 8002238: 2240 movs r2, #64 ; 0x40
- 800223a: 5c9b ldrb r3, [r3, r2]
- 800223c: 2b01 cmp r3, #1
- 800223e: d101 bne.n 8002244 <HAL_I2CEx_ConfigAnalogFilter+0x24>
- 8002240: 2302 movs r3, #2
- 8002242: e032 b.n 80022aa <HAL_I2CEx_ConfigAnalogFilter+0x8a>
- 8002244: 687b ldr r3, [r7, #4]
- 8002246: 2240 movs r2, #64 ; 0x40
- 8002248: 2101 movs r1, #1
- 800224a: 5499 strb r1, [r3, r2]
+ 8002246: 687b ldr r3, [r7, #4]
+ 8002248: 2240 movs r2, #64 ; 0x40
+ 800224a: 5c9b ldrb r3, [r3, r2]
+ 800224c: 2b01 cmp r3, #1
+ 800224e: d101 bne.n 8002254 <HAL_I2CEx_ConfigAnalogFilter+0x24>
+ 8002250: 2302 movs r3, #2
+ 8002252: e032 b.n 80022ba <HAL_I2CEx_ConfigAnalogFilter+0x8a>
+ 8002254: 687b ldr r3, [r7, #4]
+ 8002256: 2240 movs r2, #64 ; 0x40
+ 8002258: 2101 movs r1, #1
+ 800225a: 5499 strb r1, [r3, r2]
hi2c->State = HAL_I2C_STATE_BUSY;
- 800224c: 687b ldr r3, [r7, #4]
- 800224e: 2241 movs r2, #65 ; 0x41
- 8002250: 2124 movs r1, #36 ; 0x24
- 8002252: 5499 strb r1, [r3, r2]
+ 800225c: 687b ldr r3, [r7, #4]
+ 800225e: 2241 movs r2, #65 ; 0x41
+ 8002260: 2124 movs r1, #36 ; 0x24
+ 8002262: 5499 strb r1, [r3, r2]
/* Disable the selected I2C peripheral */
__HAL_I2C_DISABLE(hi2c);
- 8002254: 687b ldr r3, [r7, #4]
- 8002256: 681b ldr r3, [r3, #0]
- 8002258: 681a ldr r2, [r3, #0]
- 800225a: 687b ldr r3, [r7, #4]
- 800225c: 681b ldr r3, [r3, #0]
- 800225e: 2101 movs r1, #1
- 8002260: 438a bics r2, r1
- 8002262: 601a str r2, [r3, #0]
-
- /* Reset I2Cx ANOFF bit */
- hi2c->Instance->CR1 &= ~(I2C_CR1_ANFOFF);
8002264: 687b ldr r3, [r7, #4]
8002266: 681b ldr r3, [r3, #0]
8002268: 681a ldr r2, [r3, #0]
800226a: 687b ldr r3, [r7, #4]
800226c: 681b ldr r3, [r3, #0]
- 800226e: 4911 ldr r1, [pc, #68] ; (80022b4 <HAL_I2CEx_ConfigAnalogFilter+0x94>)
- 8002270: 400a ands r2, r1
+ 800226e: 2101 movs r1, #1
+ 8002270: 438a bics r2, r1
8002272: 601a str r2, [r3, #0]
+ /* Reset I2Cx ANOFF bit */
+ hi2c->Instance->CR1 &= ~(I2C_CR1_ANFOFF);
+ 8002274: 687b ldr r3, [r7, #4]
+ 8002276: 681b ldr r3, [r3, #0]
+ 8002278: 681a ldr r2, [r3, #0]
+ 800227a: 687b ldr r3, [r7, #4]
+ 800227c: 681b ldr r3, [r3, #0]
+ 800227e: 4911 ldr r1, [pc, #68] ; (80022c4 <HAL_I2CEx_ConfigAnalogFilter+0x94>)
+ 8002280: 400a ands r2, r1
+ 8002282: 601a str r2, [r3, #0]
+
/* Set analog filter bit*/
hi2c->Instance->CR1 |= AnalogFilter;
- 8002274: 687b ldr r3, [r7, #4]
- 8002276: 681b ldr r3, [r3, #0]
- 8002278: 6819 ldr r1, [r3, #0]
- 800227a: 687b ldr r3, [r7, #4]
- 800227c: 681b ldr r3, [r3, #0]
- 800227e: 683a ldr r2, [r7, #0]
- 8002280: 430a orrs r2, r1
- 8002282: 601a str r2, [r3, #0]
-
- __HAL_I2C_ENABLE(hi2c);
8002284: 687b ldr r3, [r7, #4]
8002286: 681b ldr r3, [r3, #0]
- 8002288: 681a ldr r2, [r3, #0]
+ 8002288: 6819 ldr r1, [r3, #0]
800228a: 687b ldr r3, [r7, #4]
800228c: 681b ldr r3, [r3, #0]
- 800228e: 2101 movs r1, #1
+ 800228e: 683a ldr r2, [r7, #0]
8002290: 430a orrs r2, r1
8002292: 601a str r2, [r3, #0]
- hi2c->State = HAL_I2C_STATE_READY;
+ __HAL_I2C_ENABLE(hi2c);
8002294: 687b ldr r3, [r7, #4]
- 8002296: 2241 movs r2, #65 ; 0x41
- 8002298: 2120 movs r1, #32
- 800229a: 5499 strb r1, [r3, r2]
+ 8002296: 681b ldr r3, [r3, #0]
+ 8002298: 681a ldr r2, [r3, #0]
+ 800229a: 687b ldr r3, [r7, #4]
+ 800229c: 681b ldr r3, [r3, #0]
+ 800229e: 2101 movs r1, #1
+ 80022a0: 430a orrs r2, r1
+ 80022a2: 601a str r2, [r3, #0]
+
+ hi2c->State = HAL_I2C_STATE_READY;
+ 80022a4: 687b ldr r3, [r7, #4]
+ 80022a6: 2241 movs r2, #65 ; 0x41
+ 80022a8: 2120 movs r1, #32
+ 80022aa: 5499 strb r1, [r3, r2]
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
- 800229c: 687b ldr r3, [r7, #4]
- 800229e: 2240 movs r2, #64 ; 0x40
- 80022a0: 2100 movs r1, #0
- 80022a2: 5499 strb r1, [r3, r2]
+ 80022ac: 687b ldr r3, [r7, #4]
+ 80022ae: 2240 movs r2, #64 ; 0x40
+ 80022b0: 2100 movs r1, #0
+ 80022b2: 5499 strb r1, [r3, r2]
return HAL_OK;
- 80022a4: 2300 movs r3, #0
- 80022a6: e000 b.n 80022aa <HAL_I2CEx_ConfigAnalogFilter+0x8a>
+ 80022b4: 2300 movs r3, #0
+ 80022b6: e000 b.n 80022ba <HAL_I2CEx_ConfigAnalogFilter+0x8a>
}
else
{
return HAL_BUSY;
- 80022a8: 2302 movs r3, #2
+ 80022b8: 2302 movs r3, #2
}
}
- 80022aa: 0018 movs r0, r3
- 80022ac: 46bd mov sp, r7
- 80022ae: b002 add sp, #8
- 80022b0: bd80 pop {r7, pc}
- 80022b2: 46c0 nop ; (mov r8, r8)
- 80022b4: ffffefff .word 0xffffefff
+ 80022ba: 0018 movs r0, r3
+ 80022bc: 46bd mov sp, r7
+ 80022be: b002 add sp, #8
+ 80022c0: bd80 pop {r7, pc}
+ 80022c2: 46c0 nop ; (mov r8, r8)
+ 80022c4: ffffefff .word 0xffffefff
-080022b8 <HAL_I2CEx_ConfigDigitalFilter>:
+080022c8 <HAL_I2CEx_ConfigDigitalFilter>:
* the configuration information for the specified I2Cx peripheral.
* @param DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter)
{
- 80022b8: b580 push {r7, lr}
- 80022ba: b084 sub sp, #16
- 80022bc: af00 add r7, sp, #0
- 80022be: 6078 str r0, [r7, #4]
- 80022c0: 6039 str r1, [r7, #0]
+ 80022c8: b580 push {r7, lr}
+ 80022ca: b084 sub sp, #16
+ 80022cc: af00 add r7, sp, #0
+ 80022ce: 6078 str r0, [r7, #4]
+ 80022d0: 6039 str r1, [r7, #0]
/* Check the parameters */
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter));
if (hi2c->State == HAL_I2C_STATE_READY)
- 80022c2: 687b ldr r3, [r7, #4]
- 80022c4: 2241 movs r2, #65 ; 0x41
- 80022c6: 5c9b ldrb r3, [r3, r2]
- 80022c8: b2db uxtb r3, r3
- 80022ca: 2b20 cmp r3, #32
- 80022cc: d139 bne.n 8002342 <HAL_I2CEx_ConfigDigitalFilter+0x8a>
+ 80022d2: 687b ldr r3, [r7, #4]
+ 80022d4: 2241 movs r2, #65 ; 0x41
+ 80022d6: 5c9b ldrb r3, [r3, r2]
+ 80022d8: b2db uxtb r3, r3
+ 80022da: 2b20 cmp r3, #32
+ 80022dc: d139 bne.n 8002352 <HAL_I2CEx_ConfigDigitalFilter+0x8a>
{
/* Process Locked */
__HAL_LOCK(hi2c);
- 80022ce: 687b ldr r3, [r7, #4]
- 80022d0: 2240 movs r2, #64 ; 0x40
- 80022d2: 5c9b ldrb r3, [r3, r2]
- 80022d4: 2b01 cmp r3, #1
- 80022d6: d101 bne.n 80022dc <HAL_I2CEx_ConfigDigitalFilter+0x24>
- 80022d8: 2302 movs r3, #2
- 80022da: e033 b.n 8002344 <HAL_I2CEx_ConfigDigitalFilter+0x8c>
- 80022dc: 687b ldr r3, [r7, #4]
- 80022de: 2240 movs r2, #64 ; 0x40
- 80022e0: 2101 movs r1, #1
- 80022e2: 5499 strb r1, [r3, r2]
+ 80022de: 687b ldr r3, [r7, #4]
+ 80022e0: 2240 movs r2, #64 ; 0x40
+ 80022e2: 5c9b ldrb r3, [r3, r2]
+ 80022e4: 2b01 cmp r3, #1
+ 80022e6: d101 bne.n 80022ec <HAL_I2CEx_ConfigDigitalFilter+0x24>
+ 80022e8: 2302 movs r3, #2
+ 80022ea: e033 b.n 8002354 <HAL_I2CEx_ConfigDigitalFilter+0x8c>
+ 80022ec: 687b ldr r3, [r7, #4]
+ 80022ee: 2240 movs r2, #64 ; 0x40
+ 80022f0: 2101 movs r1, #1
+ 80022f2: 5499 strb r1, [r3, r2]
hi2c->State = HAL_I2C_STATE_BUSY;
- 80022e4: 687b ldr r3, [r7, #4]
- 80022e6: 2241 movs r2, #65 ; 0x41
- 80022e8: 2124 movs r1, #36 ; 0x24
- 80022ea: 5499 strb r1, [r3, r2]
+ 80022f4: 687b ldr r3, [r7, #4]
+ 80022f6: 2241 movs r2, #65 ; 0x41
+ 80022f8: 2124 movs r1, #36 ; 0x24
+ 80022fa: 5499 strb r1, [r3, r2]
/* Disable the selected I2C peripheral */
__HAL_I2C_DISABLE(hi2c);
- 80022ec: 687b ldr r3, [r7, #4]
- 80022ee: 681b ldr r3, [r3, #0]
- 80022f0: 681a ldr r2, [r3, #0]
- 80022f2: 687b ldr r3, [r7, #4]
- 80022f4: 681b ldr r3, [r3, #0]
- 80022f6: 2101 movs r1, #1
- 80022f8: 438a bics r2, r1
- 80022fa: 601a str r2, [r3, #0]
+ 80022fc: 687b ldr r3, [r7, #4]
+ 80022fe: 681b ldr r3, [r3, #0]
+ 8002300: 681a ldr r2, [r3, #0]
+ 8002302: 687b ldr r3, [r7, #4]
+ 8002304: 681b ldr r3, [r3, #0]
+ 8002306: 2101 movs r1, #1
+ 8002308: 438a bics r2, r1
+ 800230a: 601a str r2, [r3, #0]
/* Get the old register value */
tmpreg = hi2c->Instance->CR1;
- 80022fc: 687b ldr r3, [r7, #4]
- 80022fe: 681b ldr r3, [r3, #0]
- 8002300: 681b ldr r3, [r3, #0]
- 8002302: 60fb str r3, [r7, #12]
+ 800230c: 687b ldr r3, [r7, #4]
+ 800230e: 681b ldr r3, [r3, #0]
+ 8002310: 681b ldr r3, [r3, #0]
+ 8002312: 60fb str r3, [r7, #12]
/* Reset I2Cx DNF bits [11:8] */
tmpreg &= ~(I2C_CR1_DNF);
- 8002304: 68fb ldr r3, [r7, #12]
- 8002306: 4a11 ldr r2, [pc, #68] ; (800234c <HAL_I2CEx_ConfigDigitalFilter+0x94>)
- 8002308: 4013 ands r3, r2
- 800230a: 60fb str r3, [r7, #12]
+ 8002314: 68fb ldr r3, [r7, #12]
+ 8002316: 4a11 ldr r2, [pc, #68] ; (800235c <HAL_I2CEx_ConfigDigitalFilter+0x94>)
+ 8002318: 4013 ands r3, r2
+ 800231a: 60fb str r3, [r7, #12]
/* Set I2Cx DNF coefficient */
tmpreg |= DigitalFilter << 8U;
- 800230c: 683b ldr r3, [r7, #0]
- 800230e: 021b lsls r3, r3, #8
- 8002310: 68fa ldr r2, [r7, #12]
- 8002312: 4313 orrs r3, r2
- 8002314: 60fb str r3, [r7, #12]
+ 800231c: 683b ldr r3, [r7, #0]
+ 800231e: 021b lsls r3, r3, #8
+ 8002320: 68fa ldr r2, [r7, #12]
+ 8002322: 4313 orrs r3, r2
+ 8002324: 60fb str r3, [r7, #12]
/* Store the new register value */
hi2c->Instance->CR1 = tmpreg;
- 8002316: 687b ldr r3, [r7, #4]
- 8002318: 681b ldr r3, [r3, #0]
- 800231a: 68fa ldr r2, [r7, #12]
- 800231c: 601a str r2, [r3, #0]
-
- __HAL_I2C_ENABLE(hi2c);
- 800231e: 687b ldr r3, [r7, #4]
- 8002320: 681b ldr r3, [r3, #0]
- 8002322: 681a ldr r2, [r3, #0]
- 8002324: 687b ldr r3, [r7, #4]
- 8002326: 681b ldr r3, [r3, #0]
- 8002328: 2101 movs r1, #1
- 800232a: 430a orrs r2, r1
+ 8002326: 687b ldr r3, [r7, #4]
+ 8002328: 681b ldr r3, [r3, #0]
+ 800232a: 68fa ldr r2, [r7, #12]
800232c: 601a str r2, [r3, #0]
- hi2c->State = HAL_I2C_STATE_READY;
+ __HAL_I2C_ENABLE(hi2c);
800232e: 687b ldr r3, [r7, #4]
- 8002330: 2241 movs r2, #65 ; 0x41
- 8002332: 2120 movs r1, #32
- 8002334: 5499 strb r1, [r3, r2]
+ 8002330: 681b ldr r3, [r3, #0]
+ 8002332: 681a ldr r2, [r3, #0]
+ 8002334: 687b ldr r3, [r7, #4]
+ 8002336: 681b ldr r3, [r3, #0]
+ 8002338: 2101 movs r1, #1
+ 800233a: 430a orrs r2, r1
+ 800233c: 601a str r2, [r3, #0]
+
+ hi2c->State = HAL_I2C_STATE_READY;
+ 800233e: 687b ldr r3, [r7, #4]
+ 8002340: 2241 movs r2, #65 ; 0x41
+ 8002342: 2120 movs r1, #32
+ 8002344: 5499 strb r1, [r3, r2]
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
- 8002336: 687b ldr r3, [r7, #4]
- 8002338: 2240 movs r2, #64 ; 0x40
- 800233a: 2100 movs r1, #0
- 800233c: 5499 strb r1, [r3, r2]
+ 8002346: 687b ldr r3, [r7, #4]
+ 8002348: 2240 movs r2, #64 ; 0x40
+ 800234a: 2100 movs r1, #0
+ 800234c: 5499 strb r1, [r3, r2]
return HAL_OK;
- 800233e: 2300 movs r3, #0
- 8002340: e000 b.n 8002344 <HAL_I2CEx_ConfigDigitalFilter+0x8c>
+ 800234e: 2300 movs r3, #0
+ 8002350: e000 b.n 8002354 <HAL_I2CEx_ConfigDigitalFilter+0x8c>
}
else
{
return HAL_BUSY;
- 8002342: 2302 movs r3, #2
+ 8002352: 2302 movs r3, #2
}
}
- 8002344: 0018 movs r0, r3
- 8002346: 46bd mov sp, r7
- 8002348: b004 add sp, #16
- 800234a: bd80 pop {r7, pc}
- 800234c: fffff0ff .word 0xfffff0ff
+ 8002354: 0018 movs r0, r3
+ 8002356: 46bd mov sp, r7
+ 8002358: b004 add sp, #16
+ 800235a: bd80 pop {r7, pc}
+ 800235c: fffff0ff .word 0xfffff0ff
-08002350 <HAL_RCC_OscConfig>:
+08002360 <HAL_RCC_OscConfig>:
* supported by this macro. User should request a transition to HSE Off
* first and then HSE On or HSE Bypass.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
{
- 8002350: b5b0 push {r4, r5, r7, lr}
- 8002352: b08a sub sp, #40 ; 0x28
- 8002354: af00 add r7, sp, #0
- 8002356: 6078 str r0, [r7, #4]
+ 8002360: b5b0 push {r4, r5, r7, lr}
+ 8002362: b08a sub sp, #40 ; 0x28
+ 8002364: af00 add r7, sp, #0
+ 8002366: 6078 str r0, [r7, #4]
uint32_t hsi_state;
HAL_StatusTypeDef status;
uint32_t sysclk_source, pll_config;
/* Check Null pointer */
if(RCC_OscInitStruct == NULL)
- 8002358: 687b ldr r3, [r7, #4]
- 800235a: 2b00 cmp r3, #0
- 800235c: d102 bne.n 8002364 <HAL_RCC_OscConfig+0x14>
+ 8002368: 687b ldr r3, [r7, #4]
+ 800236a: 2b00 cmp r3, #0
+ 800236c: d102 bne.n 8002374 <HAL_RCC_OscConfig+0x14>
{
return HAL_ERROR;
- 800235e: 2301 movs r3, #1
- 8002360: f000 fb6c bl 8002a3c <HAL_RCC_OscConfig+0x6ec>
+ 800236e: 2301 movs r3, #1
+ 8002370: f000 fb6c bl 8002a4c <HAL_RCC_OscConfig+0x6ec>
}
/* Check the parameters */
assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
sysclk_source = __HAL_RCC_GET_SYSCLK_SOURCE();
- 8002364: 4bc8 ldr r3, [pc, #800] ; (8002688 <HAL_RCC_OscConfig+0x338>)
- 8002366: 68db ldr r3, [r3, #12]
- 8002368: 220c movs r2, #12
- 800236a: 4013 ands r3, r2
- 800236c: 61fb str r3, [r7, #28]
+ 8002374: 4bc8 ldr r3, [pc, #800] ; (8002698 <HAL_RCC_OscConfig+0x338>)
+ 8002376: 68db ldr r3, [r3, #12]
+ 8002378: 220c movs r2, #12
+ 800237a: 4013 ands r3, r2
+ 800237c: 61fb str r3, [r7, #28]
pll_config = __HAL_RCC_GET_PLL_OSCSOURCE();
- 800236e: 4bc6 ldr r3, [pc, #792] ; (8002688 <HAL_RCC_OscConfig+0x338>)
- 8002370: 68da ldr r2, [r3, #12]
- 8002372: 2380 movs r3, #128 ; 0x80
- 8002374: 025b lsls r3, r3, #9
- 8002376: 4013 ands r3, r2
- 8002378: 61bb str r3, [r7, #24]
+ 800237e: 4bc6 ldr r3, [pc, #792] ; (8002698 <HAL_RCC_OscConfig+0x338>)
+ 8002380: 68da ldr r2, [r3, #12]
+ 8002382: 2380 movs r3, #128 ; 0x80
+ 8002384: 025b lsls r3, r3, #9
+ 8002386: 4013 ands r3, r2
+ 8002388: 61bb str r3, [r7, #24]
/*------------------------------- HSE Configuration ------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
- 800237a: 687b ldr r3, [r7, #4]
- 800237c: 681b ldr r3, [r3, #0]
- 800237e: 2201 movs r2, #1
- 8002380: 4013 ands r3, r2
- 8002382: d100 bne.n 8002386 <HAL_RCC_OscConfig+0x36>
- 8002384: e07d b.n 8002482 <HAL_RCC_OscConfig+0x132>
+ 800238a: 687b ldr r3, [r7, #4]
+ 800238c: 681b ldr r3, [r3, #0]
+ 800238e: 2201 movs r2, #1
+ 8002390: 4013 ands r3, r2
+ 8002392: d100 bne.n 8002396 <HAL_RCC_OscConfig+0x36>
+ 8002394: e07d b.n 8002492 <HAL_RCC_OscConfig+0x132>
{
/* Check the parameters */
assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
/* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
if((sysclk_source == RCC_SYSCLKSOURCE_STATUS_HSE)
- 8002386: 69fb ldr r3, [r7, #28]
- 8002388: 2b08 cmp r3, #8
- 800238a: d007 beq.n 800239c <HAL_RCC_OscConfig+0x4c>
+ 8002396: 69fb ldr r3, [r7, #28]
+ 8002398: 2b08 cmp r3, #8
+ 800239a: d007 beq.n 80023ac <HAL_RCC_OscConfig+0x4c>
|| ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pll_config == RCC_PLLSOURCE_HSE)))
- 800238c: 69fb ldr r3, [r7, #28]
- 800238e: 2b0c cmp r3, #12
- 8002390: d112 bne.n 80023b8 <HAL_RCC_OscConfig+0x68>
- 8002392: 69ba ldr r2, [r7, #24]
- 8002394: 2380 movs r3, #128 ; 0x80
- 8002396: 025b lsls r3, r3, #9
- 8002398: 429a cmp r2, r3
- 800239a: d10d bne.n 80023b8 <HAL_RCC_OscConfig+0x68>
+ 800239c: 69fb ldr r3, [r7, #28]
+ 800239e: 2b0c cmp r3, #12
+ 80023a0: d112 bne.n 80023c8 <HAL_RCC_OscConfig+0x68>
+ 80023a2: 69ba ldr r2, [r7, #24]
+ 80023a4: 2380 movs r3, #128 ; 0x80
+ 80023a6: 025b lsls r3, r3, #9
+ 80023a8: 429a cmp r2, r3
+ 80023aa: d10d bne.n 80023c8 <HAL_RCC_OscConfig+0x68>
{
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
- 800239c: 4bba ldr r3, [pc, #744] ; (8002688 <HAL_RCC_OscConfig+0x338>)
- 800239e: 681a ldr r2, [r3, #0]
- 80023a0: 2380 movs r3, #128 ; 0x80
- 80023a2: 029b lsls r3, r3, #10
- 80023a4: 4013 ands r3, r2
- 80023a6: d100 bne.n 80023aa <HAL_RCC_OscConfig+0x5a>
- 80023a8: e06a b.n 8002480 <HAL_RCC_OscConfig+0x130>
- 80023aa: 687b ldr r3, [r7, #4]
- 80023ac: 685b ldr r3, [r3, #4]
- 80023ae: 2b00 cmp r3, #0
- 80023b0: d166 bne.n 8002480 <HAL_RCC_OscConfig+0x130>
+ 80023ac: 4bba ldr r3, [pc, #744] ; (8002698 <HAL_RCC_OscConfig+0x338>)
+ 80023ae: 681a ldr r2, [r3, #0]
+ 80023b0: 2380 movs r3, #128 ; 0x80
+ 80023b2: 029b lsls r3, r3, #10
+ 80023b4: 4013 ands r3, r2
+ 80023b6: d100 bne.n 80023ba <HAL_RCC_OscConfig+0x5a>
+ 80023b8: e06a b.n 8002490 <HAL_RCC_OscConfig+0x130>
+ 80023ba: 687b ldr r3, [r7, #4]
+ 80023bc: 685b ldr r3, [r3, #4]
+ 80023be: 2b00 cmp r3, #0
+ 80023c0: d166 bne.n 8002490 <HAL_RCC_OscConfig+0x130>
{
return HAL_ERROR;
- 80023b2: 2301 movs r3, #1
- 80023b4: f000 fb42 bl 8002a3c <HAL_RCC_OscConfig+0x6ec>
+ 80023c2: 2301 movs r3, #1
+ 80023c4: f000 fb42 bl 8002a4c <HAL_RCC_OscConfig+0x6ec>
}
}
else
{
/* Set the new HSE configuration ---------------------------------------*/
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
- 80023b8: 687b ldr r3, [r7, #4]
- 80023ba: 685a ldr r2, [r3, #4]
- 80023bc: 2380 movs r3, #128 ; 0x80
- 80023be: 025b lsls r3, r3, #9
- 80023c0: 429a cmp r2, r3
- 80023c2: d107 bne.n 80023d4 <HAL_RCC_OscConfig+0x84>
- 80023c4: 4bb0 ldr r3, [pc, #704] ; (8002688 <HAL_RCC_OscConfig+0x338>)
- 80023c6: 681a ldr r2, [r3, #0]
- 80023c8: 4baf ldr r3, [pc, #700] ; (8002688 <HAL_RCC_OscConfig+0x338>)
- 80023ca: 2180 movs r1, #128 ; 0x80
- 80023cc: 0249 lsls r1, r1, #9
- 80023ce: 430a orrs r2, r1
- 80023d0: 601a str r2, [r3, #0]
- 80023d2: e027 b.n 8002424 <HAL_RCC_OscConfig+0xd4>
- 80023d4: 687b ldr r3, [r7, #4]
- 80023d6: 685a ldr r2, [r3, #4]
- 80023d8: 23a0 movs r3, #160 ; 0xa0
- 80023da: 02db lsls r3, r3, #11
- 80023dc: 429a cmp r2, r3
- 80023de: d10e bne.n 80023fe <HAL_RCC_OscConfig+0xae>
- 80023e0: 4ba9 ldr r3, [pc, #676] ; (8002688 <HAL_RCC_OscConfig+0x338>)
- 80023e2: 681a ldr r2, [r3, #0]
- 80023e4: 4ba8 ldr r3, [pc, #672] ; (8002688 <HAL_RCC_OscConfig+0x338>)
- 80023e6: 2180 movs r1, #128 ; 0x80
- 80023e8: 02c9 lsls r1, r1, #11
- 80023ea: 430a orrs r2, r1
- 80023ec: 601a str r2, [r3, #0]
- 80023ee: 4ba6 ldr r3, [pc, #664] ; (8002688 <HAL_RCC_OscConfig+0x338>)
- 80023f0: 681a ldr r2, [r3, #0]
- 80023f2: 4ba5 ldr r3, [pc, #660] ; (8002688 <HAL_RCC_OscConfig+0x338>)
- 80023f4: 2180 movs r1, #128 ; 0x80
- 80023f6: 0249 lsls r1, r1, #9
- 80023f8: 430a orrs r2, r1
- 80023fa: 601a str r2, [r3, #0]
- 80023fc: e012 b.n 8002424 <HAL_RCC_OscConfig+0xd4>
- 80023fe: 4ba2 ldr r3, [pc, #648] ; (8002688 <HAL_RCC_OscConfig+0x338>)
+ 80023c8: 687b ldr r3, [r7, #4]
+ 80023ca: 685a ldr r2, [r3, #4]
+ 80023cc: 2380 movs r3, #128 ; 0x80
+ 80023ce: 025b lsls r3, r3, #9
+ 80023d0: 429a cmp r2, r3
+ 80023d2: d107 bne.n 80023e4 <HAL_RCC_OscConfig+0x84>
+ 80023d4: 4bb0 ldr r3, [pc, #704] ; (8002698 <HAL_RCC_OscConfig+0x338>)
+ 80023d6: 681a ldr r2, [r3, #0]
+ 80023d8: 4baf ldr r3, [pc, #700] ; (8002698 <HAL_RCC_OscConfig+0x338>)
+ 80023da: 2180 movs r1, #128 ; 0x80
+ 80023dc: 0249 lsls r1, r1, #9
+ 80023de: 430a orrs r2, r1
+ 80023e0: 601a str r2, [r3, #0]
+ 80023e2: e027 b.n 8002434 <HAL_RCC_OscConfig+0xd4>
+ 80023e4: 687b ldr r3, [r7, #4]
+ 80023e6: 685a ldr r2, [r3, #4]
+ 80023e8: 23a0 movs r3, #160 ; 0xa0
+ 80023ea: 02db lsls r3, r3, #11
+ 80023ec: 429a cmp r2, r3
+ 80023ee: d10e bne.n 800240e <HAL_RCC_OscConfig+0xae>
+ 80023f0: 4ba9 ldr r3, [pc, #676] ; (8002698 <HAL_RCC_OscConfig+0x338>)
+ 80023f2: 681a ldr r2, [r3, #0]
+ 80023f4: 4ba8 ldr r3, [pc, #672] ; (8002698 <HAL_RCC_OscConfig+0x338>)
+ 80023f6: 2180 movs r1, #128 ; 0x80
+ 80023f8: 02c9 lsls r1, r1, #11
+ 80023fa: 430a orrs r2, r1
+ 80023fc: 601a str r2, [r3, #0]
+ 80023fe: 4ba6 ldr r3, [pc, #664] ; (8002698 <HAL_RCC_OscConfig+0x338>)
8002400: 681a ldr r2, [r3, #0]
- 8002402: 4ba1 ldr r3, [pc, #644] ; (8002688 <HAL_RCC_OscConfig+0x338>)
- 8002404: 49a1 ldr r1, [pc, #644] ; (800268c <HAL_RCC_OscConfig+0x33c>)
- 8002406: 400a ands r2, r1
- 8002408: 601a str r2, [r3, #0]
- 800240a: 4b9f ldr r3, [pc, #636] ; (8002688 <HAL_RCC_OscConfig+0x338>)
- 800240c: 681a ldr r2, [r3, #0]
- 800240e: 2380 movs r3, #128 ; 0x80
- 8002410: 025b lsls r3, r3, #9
- 8002412: 4013 ands r3, r2
- 8002414: 60fb str r3, [r7, #12]
- 8002416: 68fb ldr r3, [r7, #12]
- 8002418: 4b9b ldr r3, [pc, #620] ; (8002688 <HAL_RCC_OscConfig+0x338>)
- 800241a: 681a ldr r2, [r3, #0]
- 800241c: 4b9a ldr r3, [pc, #616] ; (8002688 <HAL_RCC_OscConfig+0x338>)
- 800241e: 499c ldr r1, [pc, #624] ; (8002690 <HAL_RCC_OscConfig+0x340>)
- 8002420: 400a ands r2, r1
- 8002422: 601a str r2, [r3, #0]
+ 8002402: 4ba5 ldr r3, [pc, #660] ; (8002698 <HAL_RCC_OscConfig+0x338>)
+ 8002404: 2180 movs r1, #128 ; 0x80
+ 8002406: 0249 lsls r1, r1, #9
+ 8002408: 430a orrs r2, r1
+ 800240a: 601a str r2, [r3, #0]
+ 800240c: e012 b.n 8002434 <HAL_RCC_OscConfig+0xd4>
+ 800240e: 4ba2 ldr r3, [pc, #648] ; (8002698 <HAL_RCC_OscConfig+0x338>)
+ 8002410: 681a ldr r2, [r3, #0]
+ 8002412: 4ba1 ldr r3, [pc, #644] ; (8002698 <HAL_RCC_OscConfig+0x338>)
+ 8002414: 49a1 ldr r1, [pc, #644] ; (800269c <HAL_RCC_OscConfig+0x33c>)
+ 8002416: 400a ands r2, r1
+ 8002418: 601a str r2, [r3, #0]
+ 800241a: 4b9f ldr r3, [pc, #636] ; (8002698 <HAL_RCC_OscConfig+0x338>)
+ 800241c: 681a ldr r2, [r3, #0]
+ 800241e: 2380 movs r3, #128 ; 0x80
+ 8002420: 025b lsls r3, r3, #9
+ 8002422: 4013 ands r3, r2
+ 8002424: 60fb str r3, [r7, #12]
+ 8002426: 68fb ldr r3, [r7, #12]
+ 8002428: 4b9b ldr r3, [pc, #620] ; (8002698 <HAL_RCC_OscConfig+0x338>)
+ 800242a: 681a ldr r2, [r3, #0]
+ 800242c: 4b9a ldr r3, [pc, #616] ; (8002698 <HAL_RCC_OscConfig+0x338>)
+ 800242e: 499c ldr r1, [pc, #624] ; (80026a0 <HAL_RCC_OscConfig+0x340>)
+ 8002430: 400a ands r2, r1
+ 8002432: 601a str r2, [r3, #0]
/* Check the HSE State */
if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
- 8002424: 687b ldr r3, [r7, #4]
- 8002426: 685b ldr r3, [r3, #4]
- 8002428: 2b00 cmp r3, #0
- 800242a: d014 beq.n 8002456 <HAL_RCC_OscConfig+0x106>
+ 8002434: 687b ldr r3, [r7, #4]
+ 8002436: 685b ldr r3, [r3, #4]
+ 8002438: 2b00 cmp r3, #0
+ 800243a: d014 beq.n 8002466 <HAL_RCC_OscConfig+0x106>
{
/* Get Start Tick */
tickstart = HAL_GetTick();
- 800242c: f7fe fe74 bl 8001118 <HAL_GetTick>
- 8002430: 0003 movs r3, r0
- 8002432: 617b str r3, [r7, #20]
+ 800243c: f7fe fe74 bl 8001128 <HAL_GetTick>
+ 8002440: 0003 movs r3, r0
+ 8002442: 617b str r3, [r7, #20]
/* Wait till HSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U)
- 8002434: e008 b.n 8002448 <HAL_RCC_OscConfig+0xf8>
+ 8002444: e008 b.n 8002458 <HAL_RCC_OscConfig+0xf8>
{
if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
- 8002436: f7fe fe6f bl 8001118 <HAL_GetTick>
- 800243a: 0002 movs r2, r0
- 800243c: 697b ldr r3, [r7, #20]
- 800243e: 1ad3 subs r3, r2, r3
- 8002440: 2b64 cmp r3, #100 ; 0x64
- 8002442: d901 bls.n 8002448 <HAL_RCC_OscConfig+0xf8>
+ 8002446: f7fe fe6f bl 8001128 <HAL_GetTick>
+ 800244a: 0002 movs r2, r0
+ 800244c: 697b ldr r3, [r7, #20]
+ 800244e: 1ad3 subs r3, r2, r3
+ 8002450: 2b64 cmp r3, #100 ; 0x64
+ 8002452: d901 bls.n 8002458 <HAL_RCC_OscConfig+0xf8>
{
return HAL_TIMEOUT;
- 8002444: 2303 movs r3, #3
- 8002446: e2f9 b.n 8002a3c <HAL_RCC_OscConfig+0x6ec>
+ 8002454: 2303 movs r3, #3
+ 8002456: e2f9 b.n 8002a4c <HAL_RCC_OscConfig+0x6ec>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U)
- 8002448: 4b8f ldr r3, [pc, #572] ; (8002688 <HAL_RCC_OscConfig+0x338>)
- 800244a: 681a ldr r2, [r3, #0]
- 800244c: 2380 movs r3, #128 ; 0x80
- 800244e: 029b lsls r3, r3, #10
- 8002450: 4013 ands r3, r2
- 8002452: d0f0 beq.n 8002436 <HAL_RCC_OscConfig+0xe6>
- 8002454: e015 b.n 8002482 <HAL_RCC_OscConfig+0x132>
+ 8002458: 4b8f ldr r3, [pc, #572] ; (8002698 <HAL_RCC_OscConfig+0x338>)
+ 800245a: 681a ldr r2, [r3, #0]
+ 800245c: 2380 movs r3, #128 ; 0x80
+ 800245e: 029b lsls r3, r3, #10
+ 8002460: 4013 ands r3, r2
+ 8002462: d0f0 beq.n 8002446 <HAL_RCC_OscConfig+0xe6>
+ 8002464: e015 b.n 8002492 <HAL_RCC_OscConfig+0x132>
}
}
else
{
/* Get Start Tick */
tickstart = HAL_GetTick();
- 8002456: f7fe fe5f bl 8001118 <HAL_GetTick>
- 800245a: 0003 movs r3, r0
- 800245c: 617b str r3, [r7, #20]
+ 8002466: f7fe fe5f bl 8001128 <HAL_GetTick>
+ 800246a: 0003 movs r3, r0
+ 800246c: 617b str r3, [r7, #20]
/* Wait till HSE is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U)
- 800245e: e008 b.n 8002472 <HAL_RCC_OscConfig+0x122>
+ 800246e: e008 b.n 8002482 <HAL_RCC_OscConfig+0x122>
{
if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
- 8002460: f7fe fe5a bl 8001118 <HAL_GetTick>
- 8002464: 0002 movs r2, r0
- 8002466: 697b ldr r3, [r7, #20]
- 8002468: 1ad3 subs r3, r2, r3
- 800246a: 2b64 cmp r3, #100 ; 0x64
- 800246c: d901 bls.n 8002472 <HAL_RCC_OscConfig+0x122>
+ 8002470: f7fe fe5a bl 8001128 <HAL_GetTick>
+ 8002474: 0002 movs r2, r0
+ 8002476: 697b ldr r3, [r7, #20]
+ 8002478: 1ad3 subs r3, r2, r3
+ 800247a: 2b64 cmp r3, #100 ; 0x64
+ 800247c: d901 bls.n 8002482 <HAL_RCC_OscConfig+0x122>
{
return HAL_TIMEOUT;
- 800246e: 2303 movs r3, #3
- 8002470: e2e4 b.n 8002a3c <HAL_RCC_OscConfig+0x6ec>
+ 800247e: 2303 movs r3, #3
+ 8002480: e2e4 b.n 8002a4c <HAL_RCC_OscConfig+0x6ec>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U)
- 8002472: 4b85 ldr r3, [pc, #532] ; (8002688 <HAL_RCC_OscConfig+0x338>)
- 8002474: 681a ldr r2, [r3, #0]
- 8002476: 2380 movs r3, #128 ; 0x80
- 8002478: 029b lsls r3, r3, #10
- 800247a: 4013 ands r3, r2
- 800247c: d1f0 bne.n 8002460 <HAL_RCC_OscConfig+0x110>
- 800247e: e000 b.n 8002482 <HAL_RCC_OscConfig+0x132>
+ 8002482: 4b85 ldr r3, [pc, #532] ; (8002698 <HAL_RCC_OscConfig+0x338>)
+ 8002484: 681a ldr r2, [r3, #0]
+ 8002486: 2380 movs r3, #128 ; 0x80
+ 8002488: 029b lsls r3, r3, #10
+ 800248a: 4013 ands r3, r2
+ 800248c: d1f0 bne.n 8002470 <HAL_RCC_OscConfig+0x110>
+ 800248e: e000 b.n 8002492 <HAL_RCC_OscConfig+0x132>
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
- 8002480: 46c0 nop ; (mov r8, r8)
+ 8002490: 46c0 nop ; (mov r8, r8)
}
}
}
}
/*----------------------------- HSI Configuration --------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
- 8002482: 687b ldr r3, [r7, #4]
- 8002484: 681b ldr r3, [r3, #0]
- 8002486: 2202 movs r2, #2
- 8002488: 4013 ands r3, r2
- 800248a: d100 bne.n 800248e <HAL_RCC_OscConfig+0x13e>
- 800248c: e099 b.n 80025c2 <HAL_RCC_OscConfig+0x272>
+ 8002492: 687b ldr r3, [r7, #4]
+ 8002494: 681b ldr r3, [r3, #0]
+ 8002496: 2202 movs r2, #2
+ 8002498: 4013 ands r3, r2
+ 800249a: d100 bne.n 800249e <HAL_RCC_OscConfig+0x13e>
+ 800249c: e099 b.n 80025d2 <HAL_RCC_OscConfig+0x272>
{
/* Check the parameters */
assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
hsi_state = RCC_OscInitStruct->HSIState;
- 800248e: 687b ldr r3, [r7, #4]
- 8002490: 68db ldr r3, [r3, #12]
- 8002492: 627b str r3, [r7, #36] ; 0x24
+ 800249e: 687b ldr r3, [r7, #4]
+ 80024a0: 68db ldr r3, [r3, #12]
+ 80024a2: 627b str r3, [r7, #36] ; 0x24
#if defined(RCC_CR_HSIOUTEN)
if((hsi_state & RCC_HSI_OUTEN) != 0U)
- 8002494: 6a7b ldr r3, [r7, #36] ; 0x24
- 8002496: 2220 movs r2, #32
- 8002498: 4013 ands r3, r2
- 800249a: d009 beq.n 80024b0 <HAL_RCC_OscConfig+0x160>
+ 80024a4: 6a7b ldr r3, [r7, #36] ; 0x24
+ 80024a6: 2220 movs r2, #32
+ 80024a8: 4013 ands r3, r2
+ 80024aa: d009 beq.n 80024c0 <HAL_RCC_OscConfig+0x160>
{
/* HSI Output enable for timer requested */
SET_BIT(RCC->CR, RCC_CR_HSIOUTEN);
- 800249c: 4b7a ldr r3, [pc, #488] ; (8002688 <HAL_RCC_OscConfig+0x338>)
- 800249e: 681a ldr r2, [r3, #0]
- 80024a0: 4b79 ldr r3, [pc, #484] ; (8002688 <HAL_RCC_OscConfig+0x338>)
- 80024a2: 2120 movs r1, #32
- 80024a4: 430a orrs r2, r1
- 80024a6: 601a str r2, [r3, #0]
+ 80024ac: 4b7a ldr r3, [pc, #488] ; (8002698 <HAL_RCC_OscConfig+0x338>)
+ 80024ae: 681a ldr r2, [r3, #0]
+ 80024b0: 4b79 ldr r3, [pc, #484] ; (8002698 <HAL_RCC_OscConfig+0x338>)
+ 80024b2: 2120 movs r1, #32
+ 80024b4: 430a orrs r2, r1
+ 80024b6: 601a str r2, [r3, #0]
hsi_state &= ~RCC_CR_HSIOUTEN;
- 80024a8: 6a7b ldr r3, [r7, #36] ; 0x24
- 80024aa: 2220 movs r2, #32
- 80024ac: 4393 bics r3, r2
- 80024ae: 627b str r3, [r7, #36] ; 0x24
+ 80024b8: 6a7b ldr r3, [r7, #36] ; 0x24
+ 80024ba: 2220 movs r2, #32
+ 80024bc: 4393 bics r3, r2
+ 80024be: 627b str r3, [r7, #36] ; 0x24
}
#endif
/* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
if((sysclk_source == RCC_SYSCLKSOURCE_STATUS_HSI)
- 80024b0: 69fb ldr r3, [r7, #28]
- 80024b2: 2b04 cmp r3, #4
- 80024b4: d005 beq.n 80024c2 <HAL_RCC_OscConfig+0x172>
+ 80024c0: 69fb ldr r3, [r7, #28]
+ 80024c2: 2b04 cmp r3, #4
+ 80024c4: d005 beq.n 80024d2 <HAL_RCC_OscConfig+0x172>
|| ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pll_config == RCC_PLLSOURCE_HSI)))
- 80024b6: 69fb ldr r3, [r7, #28]
- 80024b8: 2b0c cmp r3, #12
- 80024ba: d13e bne.n 800253a <HAL_RCC_OscConfig+0x1ea>
- 80024bc: 69bb ldr r3, [r7, #24]
- 80024be: 2b00 cmp r3, #0
- 80024c0: d13b bne.n 800253a <HAL_RCC_OscConfig+0x1ea>
+ 80024c6: 69fb ldr r3, [r7, #28]
+ 80024c8: 2b0c cmp r3, #12
+ 80024ca: d13e bne.n 800254a <HAL_RCC_OscConfig+0x1ea>
+ 80024cc: 69bb ldr r3, [r7, #24]
+ 80024ce: 2b00 cmp r3, #0
+ 80024d0: d13b bne.n 800254a <HAL_RCC_OscConfig+0x1ea>
{
/* When HSI is used as system clock it will not disabled */
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (hsi_state == RCC_HSI_OFF))
- 80024c2: 4b71 ldr r3, [pc, #452] ; (8002688 <HAL_RCC_OscConfig+0x338>)
- 80024c4: 681b ldr r3, [r3, #0]
- 80024c6: 2204 movs r2, #4
- 80024c8: 4013 ands r3, r2
- 80024ca: d004 beq.n 80024d6 <HAL_RCC_OscConfig+0x186>
- 80024cc: 6a7b ldr r3, [r7, #36] ; 0x24
- 80024ce: 2b00 cmp r3, #0
- 80024d0: d101 bne.n 80024d6 <HAL_RCC_OscConfig+0x186>
+ 80024d2: 4b71 ldr r3, [pc, #452] ; (8002698 <HAL_RCC_OscConfig+0x338>)
+ 80024d4: 681b ldr r3, [r3, #0]
+ 80024d6: 2204 movs r2, #4
+ 80024d8: 4013 ands r3, r2
+ 80024da: d004 beq.n 80024e6 <HAL_RCC_OscConfig+0x186>
+ 80024dc: 6a7b ldr r3, [r7, #36] ; 0x24
+ 80024de: 2b00 cmp r3, #0
+ 80024e0: d101 bne.n 80024e6 <HAL_RCC_OscConfig+0x186>
{
return HAL_ERROR;
- 80024d2: 2301 movs r3, #1
- 80024d4: e2b2 b.n 8002a3c <HAL_RCC_OscConfig+0x6ec>
+ 80024e2: 2301 movs r3, #1
+ 80024e4: e2b2 b.n 8002a4c <HAL_RCC_OscConfig+0x6ec>
}
/* Otherwise, just the calibration and HSI or HSIdiv4 are allowed */
else
{
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
- 80024d6: 4b6c ldr r3, [pc, #432] ; (8002688 <HAL_RCC_OscConfig+0x338>)
- 80024d8: 685b ldr r3, [r3, #4]
- 80024da: 4a6e ldr r2, [pc, #440] ; (8002694 <HAL_RCC_OscConfig+0x344>)
- 80024dc: 4013 ands r3, r2
- 80024de: 0019 movs r1, r3
- 80024e0: 687b ldr r3, [r7, #4]
- 80024e2: 691b ldr r3, [r3, #16]
- 80024e4: 021a lsls r2, r3, #8
- 80024e6: 4b68 ldr r3, [pc, #416] ; (8002688 <HAL_RCC_OscConfig+0x338>)
- 80024e8: 430a orrs r2, r1
- 80024ea: 605a str r2, [r3, #4]
+ 80024e6: 4b6c ldr r3, [pc, #432] ; (8002698 <HAL_RCC_OscConfig+0x338>)
+ 80024e8: 685b ldr r3, [r3, #4]
+ 80024ea: 4a6e ldr r2, [pc, #440] ; (80026a4 <HAL_RCC_OscConfig+0x344>)
+ 80024ec: 4013 ands r3, r2
+ 80024ee: 0019 movs r1, r3
+ 80024f0: 687b ldr r3, [r7, #4]
+ 80024f2: 691b ldr r3, [r3, #16]
+ 80024f4: 021a lsls r2, r3, #8
+ 80024f6: 4b68 ldr r3, [pc, #416] ; (8002698 <HAL_RCC_OscConfig+0x338>)
+ 80024f8: 430a orrs r2, r1
+ 80024fa: 605a str r2, [r3, #4]
/* Enable the Internal High Speed oscillator (HSI or HSIdiv4) */
__HAL_RCC_HSI_CONFIG(hsi_state);
- 80024ec: 4b66 ldr r3, [pc, #408] ; (8002688 <HAL_RCC_OscConfig+0x338>)
- 80024ee: 681b ldr r3, [r3, #0]
- 80024f0: 2209 movs r2, #9
- 80024f2: 4393 bics r3, r2
- 80024f4: 0019 movs r1, r3
- 80024f6: 4b64 ldr r3, [pc, #400] ; (8002688 <HAL_RCC_OscConfig+0x338>)
- 80024f8: 6a7a ldr r2, [r7, #36] ; 0x24
- 80024fa: 430a orrs r2, r1
- 80024fc: 601a str r2, [r3, #0]
+ 80024fc: 4b66 ldr r3, [pc, #408] ; (8002698 <HAL_RCC_OscConfig+0x338>)
+ 80024fe: 681b ldr r3, [r3, #0]
+ 8002500: 2209 movs r2, #9
+ 8002502: 4393 bics r3, r2
+ 8002504: 0019 movs r1, r3
+ 8002506: 4b64 ldr r3, [pc, #400] ; (8002698 <HAL_RCC_OscConfig+0x338>)
+ 8002508: 6a7a ldr r2, [r7, #36] ; 0x24
+ 800250a: 430a orrs r2, r1
+ 800250c: 601a str r2, [r3, #0]
}
/* Update the SystemCoreClock global variable */
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_Pos];
- 80024fe: f000 fbeb bl 8002cd8 <HAL_RCC_GetSysClockFreq>
- 8002502: 0001 movs r1, r0
- 8002504: 4b60 ldr r3, [pc, #384] ; (8002688 <HAL_RCC_OscConfig+0x338>)
- 8002506: 68db ldr r3, [r3, #12]
- 8002508: 091b lsrs r3, r3, #4
- 800250a: 220f movs r2, #15
- 800250c: 4013 ands r3, r2
- 800250e: 4a62 ldr r2, [pc, #392] ; (8002698 <HAL_RCC_OscConfig+0x348>)
- 8002510: 5cd3 ldrb r3, [r2, r3]
- 8002512: 000a movs r2, r1
- 8002514: 40da lsrs r2, r3
- 8002516: 4b61 ldr r3, [pc, #388] ; (800269c <HAL_RCC_OscConfig+0x34c>)
- 8002518: 601a str r2, [r3, #0]
+ 800250e: f000 fbeb bl 8002ce8 <HAL_RCC_GetSysClockFreq>
+ 8002512: 0001 movs r1, r0
+ 8002514: 4b60 ldr r3, [pc, #384] ; (8002698 <HAL_RCC_OscConfig+0x338>)
+ 8002516: 68db ldr r3, [r3, #12]
+ 8002518: 091b lsrs r3, r3, #4
+ 800251a: 220f movs r2, #15
+ 800251c: 4013 ands r3, r2
+ 800251e: 4a62 ldr r2, [pc, #392] ; (80026a8 <HAL_RCC_OscConfig+0x348>)
+ 8002520: 5cd3 ldrb r3, [r2, r3]
+ 8002522: 000a movs r2, r1
+ 8002524: 40da lsrs r2, r3
+ 8002526: 4b61 ldr r3, [pc, #388] ; (80026ac <HAL_RCC_OscConfig+0x34c>)
+ 8002528: 601a str r2, [r3, #0]
/* Configure the source of time base considering new system clocks settings*/
status = HAL_InitTick (uwTickPrio);
- 800251a: 4b61 ldr r3, [pc, #388] ; (80026a0 <HAL_RCC_OscConfig+0x350>)
- 800251c: 681b ldr r3, [r3, #0]
- 800251e: 2513 movs r5, #19
- 8002520: 197c adds r4, r7, r5
- 8002522: 0018 movs r0, r3
- 8002524: f7fe fdb2 bl 800108c <HAL_InitTick>
- 8002528: 0003 movs r3, r0
- 800252a: 7023 strb r3, [r4, #0]
+ 800252a: 4b61 ldr r3, [pc, #388] ; (80026b0 <HAL_RCC_OscConfig+0x350>)
+ 800252c: 681b ldr r3, [r3, #0]
+ 800252e: 2513 movs r5, #19
+ 8002530: 197c adds r4, r7, r5
+ 8002532: 0018 movs r0, r3
+ 8002534: f7fe fdb2 bl 800109c <HAL_InitTick>
+ 8002538: 0003 movs r3, r0
+ 800253a: 7023 strb r3, [r4, #0]
if(status != HAL_OK)
- 800252c: 197b adds r3, r7, r5
- 800252e: 781b ldrb r3, [r3, #0]
- 8002530: 2b00 cmp r3, #0
- 8002532: d046 beq.n 80025c2 <HAL_RCC_OscConfig+0x272>
+ 800253c: 197b adds r3, r7, r5
+ 800253e: 781b ldrb r3, [r3, #0]
+ 8002540: 2b00 cmp r3, #0
+ 8002542: d046 beq.n 80025d2 <HAL_RCC_OscConfig+0x272>
{
return status;
- 8002534: 197b adds r3, r7, r5
- 8002536: 781b ldrb r3, [r3, #0]
- 8002538: e280 b.n 8002a3c <HAL_RCC_OscConfig+0x6ec>
+ 8002544: 197b adds r3, r7, r5
+ 8002546: 781b ldrb r3, [r3, #0]
+ 8002548: e280 b.n 8002a4c <HAL_RCC_OscConfig+0x6ec>
}
}
else
{
/* Check the HSI State */
if(hsi_state != RCC_HSI_OFF)
- 800253a: 6a7b ldr r3, [r7, #36] ; 0x24
- 800253c: 2b00 cmp r3, #0
- 800253e: d027 beq.n 8002590 <HAL_RCC_OscConfig+0x240>
+ 800254a: 6a7b ldr r3, [r7, #36] ; 0x24
+ 800254c: 2b00 cmp r3, #0
+ 800254e: d027 beq.n 80025a0 <HAL_RCC_OscConfig+0x240>
{
/* Enable the Internal High Speed oscillator (HSI or HSIdiv4) */
__HAL_RCC_HSI_CONFIG(hsi_state);
- 8002540: 4b51 ldr r3, [pc, #324] ; (8002688 <HAL_RCC_OscConfig+0x338>)
- 8002542: 681b ldr r3, [r3, #0]
- 8002544: 2209 movs r2, #9
- 8002546: 4393 bics r3, r2
- 8002548: 0019 movs r1, r3
- 800254a: 4b4f ldr r3, [pc, #316] ; (8002688 <HAL_RCC_OscConfig+0x338>)
- 800254c: 6a7a ldr r2, [r7, #36] ; 0x24
- 800254e: 430a orrs r2, r1
- 8002550: 601a str r2, [r3, #0]
+ 8002550: 4b51 ldr r3, [pc, #324] ; (8002698 <HAL_RCC_OscConfig+0x338>)
+ 8002552: 681b ldr r3, [r3, #0]
+ 8002554: 2209 movs r2, #9
+ 8002556: 4393 bics r3, r2
+ 8002558: 0019 movs r1, r3
+ 800255a: 4b4f ldr r3, [pc, #316] ; (8002698 <HAL_RCC_OscConfig+0x338>)
+ 800255c: 6a7a ldr r2, [r7, #36] ; 0x24
+ 800255e: 430a orrs r2, r1
+ 8002560: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
- 8002552: f7fe fde1 bl 8001118 <HAL_GetTick>
- 8002556: 0003 movs r3, r0
- 8002558: 617b str r3, [r7, #20]
+ 8002562: f7fe fde1 bl 8001128 <HAL_GetTick>
+ 8002566: 0003 movs r3, r0
+ 8002568: 617b str r3, [r7, #20]
/* Wait till HSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U)
- 800255a: e008 b.n 800256e <HAL_RCC_OscConfig+0x21e>
+ 800256a: e008 b.n 800257e <HAL_RCC_OscConfig+0x21e>
{
if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
- 800255c: f7fe fddc bl 8001118 <HAL_GetTick>
- 8002560: 0002 movs r2, r0
- 8002562: 697b ldr r3, [r7, #20]
- 8002564: 1ad3 subs r3, r2, r3
- 8002566: 2b02 cmp r3, #2
- 8002568: d901 bls.n 800256e <HAL_RCC_OscConfig+0x21e>
+ 800256c: f7fe fddc bl 8001128 <HAL_GetTick>
+ 8002570: 0002 movs r2, r0
+ 8002572: 697b ldr r3, [r7, #20]
+ 8002574: 1ad3 subs r3, r2, r3
+ 8002576: 2b02 cmp r3, #2
+ 8002578: d901 bls.n 800257e <HAL_RCC_OscConfig+0x21e>
{
return HAL_TIMEOUT;
- 800256a: 2303 movs r3, #3
- 800256c: e266 b.n 8002a3c <HAL_RCC_OscConfig+0x6ec>
+ 800257a: 2303 movs r3, #3
+ 800257c: e266 b.n 8002a4c <HAL_RCC_OscConfig+0x6ec>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U)
- 800256e: 4b46 ldr r3, [pc, #280] ; (8002688 <HAL_RCC_OscConfig+0x338>)
- 8002570: 681b ldr r3, [r3, #0]
- 8002572: 2204 movs r2, #4
- 8002574: 4013 ands r3, r2
- 8002576: d0f1 beq.n 800255c <HAL_RCC_OscConfig+0x20c>
+ 800257e: 4b46 ldr r3, [pc, #280] ; (8002698 <HAL_RCC_OscConfig+0x338>)
+ 8002580: 681b ldr r3, [r3, #0]
+ 8002582: 2204 movs r2, #4
+ 8002584: 4013 ands r3, r2
+ 8002586: d0f1 beq.n 800256c <HAL_RCC_OscConfig+0x20c>
}
}
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
- 8002578: 4b43 ldr r3, [pc, #268] ; (8002688 <HAL_RCC_OscConfig+0x338>)
- 800257a: 685b ldr r3, [r3, #4]
- 800257c: 4a45 ldr r2, [pc, #276] ; (8002694 <HAL_RCC_OscConfig+0x344>)
- 800257e: 4013 ands r3, r2
- 8002580: 0019 movs r1, r3
- 8002582: 687b ldr r3, [r7, #4]
- 8002584: 691b ldr r3, [r3, #16]
- 8002586: 021a lsls r2, r3, #8
- 8002588: 4b3f ldr r3, [pc, #252] ; (8002688 <HAL_RCC_OscConfig+0x338>)
- 800258a: 430a orrs r2, r1
- 800258c: 605a str r2, [r3, #4]
- 800258e: e018 b.n 80025c2 <HAL_RCC_OscConfig+0x272>
+ 8002588: 4b43 ldr r3, [pc, #268] ; (8002698 <HAL_RCC_OscConfig+0x338>)
+ 800258a: 685b ldr r3, [r3, #4]
+ 800258c: 4a45 ldr r2, [pc, #276] ; (80026a4 <HAL_RCC_OscConfig+0x344>)
+ 800258e: 4013 ands r3, r2
+ 8002590: 0019 movs r1, r3
+ 8002592: 687b ldr r3, [r7, #4]
+ 8002594: 691b ldr r3, [r3, #16]
+ 8002596: 021a lsls r2, r3, #8
+ 8002598: 4b3f ldr r3, [pc, #252] ; (8002698 <HAL_RCC_OscConfig+0x338>)
+ 800259a: 430a orrs r2, r1
+ 800259c: 605a str r2, [r3, #4]
+ 800259e: e018 b.n 80025d2 <HAL_RCC_OscConfig+0x272>
}
else
{
/* Disable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_DISABLE();
- 8002590: 4b3d ldr r3, [pc, #244] ; (8002688 <HAL_RCC_OscConfig+0x338>)
- 8002592: 681a ldr r2, [r3, #0]
- 8002594: 4b3c ldr r3, [pc, #240] ; (8002688 <HAL_RCC_OscConfig+0x338>)
- 8002596: 2101 movs r1, #1
- 8002598: 438a bics r2, r1
- 800259a: 601a str r2, [r3, #0]
+ 80025a0: 4b3d ldr r3, [pc, #244] ; (8002698 <HAL_RCC_OscConfig+0x338>)
+ 80025a2: 681a ldr r2, [r3, #0]
+ 80025a4: 4b3c ldr r3, [pc, #240] ; (8002698 <HAL_RCC_OscConfig+0x338>)
+ 80025a6: 2101 movs r1, #1
+ 80025a8: 438a bics r2, r1
+ 80025aa: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
- 800259c: f7fe fdbc bl 8001118 <HAL_GetTick>
- 80025a0: 0003 movs r3, r0
- 80025a2: 617b str r3, [r7, #20]
+ 80025ac: f7fe fdbc bl 8001128 <HAL_GetTick>
+ 80025b0: 0003 movs r3, r0
+ 80025b2: 617b str r3, [r7, #20]
/* Wait till HSI is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U)
- 80025a4: e008 b.n 80025b8 <HAL_RCC_OscConfig+0x268>
+ 80025b4: e008 b.n 80025c8 <HAL_RCC_OscConfig+0x268>
{
if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
- 80025a6: f7fe fdb7 bl 8001118 <HAL_GetTick>
- 80025aa: 0002 movs r2, r0
- 80025ac: 697b ldr r3, [r7, #20]
- 80025ae: 1ad3 subs r3, r2, r3
- 80025b0: 2b02 cmp r3, #2
- 80025b2: d901 bls.n 80025b8 <HAL_RCC_OscConfig+0x268>
+ 80025b6: f7fe fdb7 bl 8001128 <HAL_GetTick>
+ 80025ba: 0002 movs r2, r0
+ 80025bc: 697b ldr r3, [r7, #20]
+ 80025be: 1ad3 subs r3, r2, r3
+ 80025c0: 2b02 cmp r3, #2
+ 80025c2: d901 bls.n 80025c8 <HAL_RCC_OscConfig+0x268>
{
return HAL_TIMEOUT;
- 80025b4: 2303 movs r3, #3
- 80025b6: e241 b.n 8002a3c <HAL_RCC_OscConfig+0x6ec>
+ 80025c4: 2303 movs r3, #3
+ 80025c6: e241 b.n 8002a4c <HAL_RCC_OscConfig+0x6ec>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U)
- 80025b8: 4b33 ldr r3, [pc, #204] ; (8002688 <HAL_RCC_OscConfig+0x338>)
- 80025ba: 681b ldr r3, [r3, #0]
- 80025bc: 2204 movs r2, #4
- 80025be: 4013 ands r3, r2
- 80025c0: d1f1 bne.n 80025a6 <HAL_RCC_OscConfig+0x256>
+ 80025c8: 4b33 ldr r3, [pc, #204] ; (8002698 <HAL_RCC_OscConfig+0x338>)
+ 80025ca: 681b ldr r3, [r3, #0]
+ 80025cc: 2204 movs r2, #4
+ 80025ce: 4013 ands r3, r2
+ 80025d0: d1f1 bne.n 80025b6 <HAL_RCC_OscConfig+0x256>
}
}
}
}
/*----------------------------- MSI Configuration --------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI)
- 80025c2: 687b ldr r3, [r7, #4]
- 80025c4: 681b ldr r3, [r3, #0]
- 80025c6: 2210 movs r2, #16
- 80025c8: 4013 ands r3, r2
- 80025ca: d100 bne.n 80025ce <HAL_RCC_OscConfig+0x27e>
- 80025cc: e0a1 b.n 8002712 <HAL_RCC_OscConfig+0x3c2>
+ 80025d2: 687b ldr r3, [r7, #4]
+ 80025d4: 681b ldr r3, [r3, #0]
+ 80025d6: 2210 movs r2, #16
+ 80025d8: 4013 ands r3, r2
+ 80025da: d100 bne.n 80025de <HAL_RCC_OscConfig+0x27e>
+ 80025dc: e0a1 b.n 8002722 <HAL_RCC_OscConfig+0x3c2>
{
/* When the MSI is used as system clock it will not be disabled */
if(sysclk_source == RCC_CFGR_SWS_MSI)
- 80025ce: 69fb ldr r3, [r7, #28]
- 80025d0: 2b00 cmp r3, #0
- 80025d2: d140 bne.n 8002656 <HAL_RCC_OscConfig+0x306>
+ 80025de: 69fb ldr r3, [r7, #28]
+ 80025e0: 2b00 cmp r3, #0
+ 80025e2: d140 bne.n 8002666 <HAL_RCC_OscConfig+0x306>
{
if((__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) != 0U) && (RCC_OscInitStruct->MSIState == RCC_MSI_OFF))
- 80025d4: 4b2c ldr r3, [pc, #176] ; (8002688 <HAL_RCC_OscConfig+0x338>)
- 80025d6: 681a ldr r2, [r3, #0]
- 80025d8: 2380 movs r3, #128 ; 0x80
- 80025da: 009b lsls r3, r3, #2
- 80025dc: 4013 ands r3, r2
- 80025de: d005 beq.n 80025ec <HAL_RCC_OscConfig+0x29c>
- 80025e0: 687b ldr r3, [r7, #4]
- 80025e2: 699b ldr r3, [r3, #24]
- 80025e4: 2b00 cmp r3, #0
- 80025e6: d101 bne.n 80025ec <HAL_RCC_OscConfig+0x29c>
+ 80025e4: 4b2c ldr r3, [pc, #176] ; (8002698 <HAL_RCC_OscConfig+0x338>)
+ 80025e6: 681a ldr r2, [r3, #0]
+ 80025e8: 2380 movs r3, #128 ; 0x80
+ 80025ea: 009b lsls r3, r3, #2
+ 80025ec: 4013 ands r3, r2
+ 80025ee: d005 beq.n 80025fc <HAL_RCC_OscConfig+0x29c>
+ 80025f0: 687b ldr r3, [r7, #4]
+ 80025f2: 699b ldr r3, [r3, #24]
+ 80025f4: 2b00 cmp r3, #0
+ 80025f6: d101 bne.n 80025fc <HAL_RCC_OscConfig+0x29c>
{
return HAL_ERROR;
- 80025e8: 2301 movs r3, #1
- 80025ea: e227 b.n 8002a3c <HAL_RCC_OscConfig+0x6ec>
+ 80025f8: 2301 movs r3, #1
+ 80025fa: e227 b.n 8002a4c <HAL_RCC_OscConfig+0x6ec>
/* Check MSICalibrationValue and MSIClockRange input parameters */
assert_param(IS_RCC_MSICALIBRATION_VALUE(RCC_OscInitStruct->MSICalibrationValue));
assert_param(IS_RCC_MSI_CLOCK_RANGE(RCC_OscInitStruct->MSIClockRange));
/* Selects the Multiple Speed oscillator (MSI) clock range .*/
__HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);
- 80025ec: 4b26 ldr r3, [pc, #152] ; (8002688 <HAL_RCC_OscConfig+0x338>)
- 80025ee: 685b ldr r3, [r3, #4]
- 80025f0: 4a2c ldr r2, [pc, #176] ; (80026a4 <HAL_RCC_OscConfig+0x354>)
- 80025f2: 4013 ands r3, r2
- 80025f4: 0019 movs r1, r3
- 80025f6: 687b ldr r3, [r7, #4]
- 80025f8: 6a1a ldr r2, [r3, #32]
- 80025fa: 4b23 ldr r3, [pc, #140] ; (8002688 <HAL_RCC_OscConfig+0x338>)
- 80025fc: 430a orrs r2, r1
- 80025fe: 605a str r2, [r3, #4]
+ 80025fc: 4b26 ldr r3, [pc, #152] ; (8002698 <HAL_RCC_OscConfig+0x338>)
+ 80025fe: 685b ldr r3, [r3, #4]
+ 8002600: 4a2c ldr r2, [pc, #176] ; (80026b4 <HAL_RCC_OscConfig+0x354>)
+ 8002602: 4013 ands r3, r2
+ 8002604: 0019 movs r1, r3
+ 8002606: 687b ldr r3, [r7, #4]
+ 8002608: 6a1a ldr r2, [r3, #32]
+ 800260a: 4b23 ldr r3, [pc, #140] ; (8002698 <HAL_RCC_OscConfig+0x338>)
+ 800260c: 430a orrs r2, r1
+ 800260e: 605a str r2, [r3, #4]
/* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/
__HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);
- 8002600: 4b21 ldr r3, [pc, #132] ; (8002688 <HAL_RCC_OscConfig+0x338>)
- 8002602: 685b ldr r3, [r3, #4]
- 8002604: 021b lsls r3, r3, #8
- 8002606: 0a19 lsrs r1, r3, #8
- 8002608: 687b ldr r3, [r7, #4]
- 800260a: 69db ldr r3, [r3, #28]
- 800260c: 061a lsls r2, r3, #24
- 800260e: 4b1e ldr r3, [pc, #120] ; (8002688 <HAL_RCC_OscConfig+0x338>)
- 8002610: 430a orrs r2, r1
- 8002612: 605a str r2, [r3, #4]
+ 8002610: 4b21 ldr r3, [pc, #132] ; (8002698 <HAL_RCC_OscConfig+0x338>)
+ 8002612: 685b ldr r3, [r3, #4]
+ 8002614: 021b lsls r3, r3, #8
+ 8002616: 0a19 lsrs r1, r3, #8
+ 8002618: 687b ldr r3, [r7, #4]
+ 800261a: 69db ldr r3, [r3, #28]
+ 800261c: 061a lsls r2, r3, #24
+ 800261e: 4b1e ldr r3, [pc, #120] ; (8002698 <HAL_RCC_OscConfig+0x338>)
+ 8002620: 430a orrs r2, r1
+ 8002622: 605a str r2, [r3, #4]
/* Update the SystemCoreClock global variable */
SystemCoreClock = (32768U * (1UL << ((RCC_OscInitStruct->MSIClockRange >> RCC_ICSCR_MSIRANGE_Pos) + 1U)))
- 8002614: 687b ldr r3, [r7, #4]
- 8002616: 6a1b ldr r3, [r3, #32]
- 8002618: 0b5b lsrs r3, r3, #13
- 800261a: 3301 adds r3, #1
- 800261c: 2280 movs r2, #128 ; 0x80
- 800261e: 0212 lsls r2, r2, #8
- 8002620: 409a lsls r2, r3
+ 8002624: 687b ldr r3, [r7, #4]
+ 8002626: 6a1b ldr r3, [r3, #32]
+ 8002628: 0b5b lsrs r3, r3, #13
+ 800262a: 3301 adds r3, #1
+ 800262c: 2280 movs r2, #128 ; 0x80
+ 800262e: 0212 lsls r2, r2, #8
+ 8002630: 409a lsls r2, r3
>> AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
- 8002622: 4b19 ldr r3, [pc, #100] ; (8002688 <HAL_RCC_OscConfig+0x338>)
- 8002624: 68db ldr r3, [r3, #12]
- 8002626: 091b lsrs r3, r3, #4
- 8002628: 210f movs r1, #15
- 800262a: 400b ands r3, r1
- 800262c: 491a ldr r1, [pc, #104] ; (8002698 <HAL_RCC_OscConfig+0x348>)
- 800262e: 5ccb ldrb r3, [r1, r3]
- 8002630: 40da lsrs r2, r3
+ 8002632: 4b19 ldr r3, [pc, #100] ; (8002698 <HAL_RCC_OscConfig+0x338>)
+ 8002634: 68db ldr r3, [r3, #12]
+ 8002636: 091b lsrs r3, r3, #4
+ 8002638: 210f movs r1, #15
+ 800263a: 400b ands r3, r1
+ 800263c: 491a ldr r1, [pc, #104] ; (80026a8 <HAL_RCC_OscConfig+0x348>)
+ 800263e: 5ccb ldrb r3, [r1, r3]
+ 8002640: 40da lsrs r2, r3
SystemCoreClock = (32768U * (1UL << ((RCC_OscInitStruct->MSIClockRange >> RCC_ICSCR_MSIRANGE_Pos) + 1U)))
- 8002632: 4b1a ldr r3, [pc, #104] ; (800269c <HAL_RCC_OscConfig+0x34c>)
- 8002634: 601a str r2, [r3, #0]
+ 8002642: 4b1a ldr r3, [pc, #104] ; (80026ac <HAL_RCC_OscConfig+0x34c>)
+ 8002644: 601a str r2, [r3, #0]
/* Configure the source of time base considering new system clocks settings*/
status = HAL_InitTick (uwTickPrio);
- 8002636: 4b1a ldr r3, [pc, #104] ; (80026a0 <HAL_RCC_OscConfig+0x350>)
- 8002638: 681b ldr r3, [r3, #0]
- 800263a: 2513 movs r5, #19
- 800263c: 197c adds r4, r7, r5
- 800263e: 0018 movs r0, r3
- 8002640: f7fe fd24 bl 800108c <HAL_InitTick>
- 8002644: 0003 movs r3, r0
- 8002646: 7023 strb r3, [r4, #0]
+ 8002646: 4b1a ldr r3, [pc, #104] ; (80026b0 <HAL_RCC_OscConfig+0x350>)
+ 8002648: 681b ldr r3, [r3, #0]
+ 800264a: 2513 movs r5, #19
+ 800264c: 197c adds r4, r7, r5
+ 800264e: 0018 movs r0, r3
+ 8002650: f7fe fd24 bl 800109c <HAL_InitTick>
+ 8002654: 0003 movs r3, r0
+ 8002656: 7023 strb r3, [r4, #0]
if(status != HAL_OK)
- 8002648: 197b adds r3, r7, r5
- 800264a: 781b ldrb r3, [r3, #0]
- 800264c: 2b00 cmp r3, #0
- 800264e: d060 beq.n 8002712 <HAL_RCC_OscConfig+0x3c2>
+ 8002658: 197b adds r3, r7, r5
+ 800265a: 781b ldrb r3, [r3, #0]
+ 800265c: 2b00 cmp r3, #0
+ 800265e: d060 beq.n 8002722 <HAL_RCC_OscConfig+0x3c2>
{
return status;
- 8002650: 197b adds r3, r7, r5
- 8002652: 781b ldrb r3, [r3, #0]
- 8002654: e1f2 b.n 8002a3c <HAL_RCC_OscConfig+0x6ec>
+ 8002660: 197b adds r3, r7, r5
+ 8002662: 781b ldrb r3, [r3, #0]
+ 8002664: e1f2 b.n 8002a4c <HAL_RCC_OscConfig+0x6ec>
{
/* Check MSI State */
assert_param(IS_RCC_MSI(RCC_OscInitStruct->MSIState));
/* Check the MSI State */
if(RCC_OscInitStruct->MSIState != RCC_MSI_OFF)
- 8002656: 687b ldr r3, [r7, #4]
- 8002658: 699b ldr r3, [r3, #24]
- 800265a: 2b00 cmp r3, #0
- 800265c: d03f beq.n 80026de <HAL_RCC_OscConfig+0x38e>
+ 8002666: 687b ldr r3, [r7, #4]
+ 8002668: 699b ldr r3, [r3, #24]
+ 800266a: 2b00 cmp r3, #0
+ 800266c: d03f beq.n 80026ee <HAL_RCC_OscConfig+0x38e>
{
/* Enable the Multi Speed oscillator (MSI). */
__HAL_RCC_MSI_ENABLE();
- 800265e: 4b0a ldr r3, [pc, #40] ; (8002688 <HAL_RCC_OscConfig+0x338>)
- 8002660: 681a ldr r2, [r3, #0]
- 8002662: 4b09 ldr r3, [pc, #36] ; (8002688 <HAL_RCC_OscConfig+0x338>)
- 8002664: 2180 movs r1, #128 ; 0x80
- 8002666: 0049 lsls r1, r1, #1
- 8002668: 430a orrs r2, r1
- 800266a: 601a str r2, [r3, #0]
+ 800266e: 4b0a ldr r3, [pc, #40] ; (8002698 <HAL_RCC_OscConfig+0x338>)
+ 8002670: 681a ldr r2, [r3, #0]
+ 8002672: 4b09 ldr r3, [pc, #36] ; (8002698 <HAL_RCC_OscConfig+0x338>)
+ 8002674: 2180 movs r1, #128 ; 0x80
+ 8002676: 0049 lsls r1, r1, #1
+ 8002678: 430a orrs r2, r1
+ 800267a: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
- 800266c: f7fe fd54 bl 8001118 <HAL_GetTick>
- 8002670: 0003 movs r3, r0
- 8002672: 617b str r3, [r7, #20]
+ 800267c: f7fe fd54 bl 8001128 <HAL_GetTick>
+ 8002680: 0003 movs r3, r0
+ 8002682: 617b str r3, [r7, #20]
/* Wait till MSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) == 0U)
- 8002674: e018 b.n 80026a8 <HAL_RCC_OscConfig+0x358>
+ 8002684: e018 b.n 80026b8 <HAL_RCC_OscConfig+0x358>
{
if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE)
- 8002676: f7fe fd4f bl 8001118 <HAL_GetTick>
- 800267a: 0002 movs r2, r0
- 800267c: 697b ldr r3, [r7, #20]
- 800267e: 1ad3 subs r3, r2, r3
- 8002680: 2b02 cmp r3, #2
- 8002682: d911 bls.n 80026a8 <HAL_RCC_OscConfig+0x358>
+ 8002686: f7fe fd4f bl 8001128 <HAL_GetTick>
+ 800268a: 0002 movs r2, r0
+ 800268c: 697b ldr r3, [r7, #20]
+ 800268e: 1ad3 subs r3, r2, r3
+ 8002690: 2b02 cmp r3, #2
+ 8002692: d911 bls.n 80026b8 <HAL_RCC_OscConfig+0x358>
{
return HAL_TIMEOUT;
- 8002684: 2303 movs r3, #3
- 8002686: e1d9 b.n 8002a3c <HAL_RCC_OscConfig+0x6ec>
- 8002688: 40021000 .word 0x40021000
- 800268c: fffeffff .word 0xfffeffff
- 8002690: fffbffff .word 0xfffbffff
- 8002694: ffffe0ff .word 0xffffe0ff
- 8002698: 08004348 .word 0x08004348
- 800269c: 20000000 .word 0x20000000
- 80026a0: 20000004 .word 0x20000004
- 80026a4: ffff1fff .word 0xffff1fff
+ 8002694: 2303 movs r3, #3
+ 8002696: e1d9 b.n 8002a4c <HAL_RCC_OscConfig+0x6ec>
+ 8002698: 40021000 .word 0x40021000
+ 800269c: fffeffff .word 0xfffeffff
+ 80026a0: fffbffff .word 0xfffbffff
+ 80026a4: ffffe0ff .word 0xffffe0ff
+ 80026a8: 08004358 .word 0x08004358
+ 80026ac: 20000000 .word 0x20000000
+ 80026b0: 20000004 .word 0x20000004
+ 80026b4: ffff1fff .word 0xffff1fff
while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) == 0U)
- 80026a8: 4bc9 ldr r3, [pc, #804] ; (80029d0 <HAL_RCC_OscConfig+0x680>)
- 80026aa: 681a ldr r2, [r3, #0]
- 80026ac: 2380 movs r3, #128 ; 0x80
- 80026ae: 009b lsls r3, r3, #2
- 80026b0: 4013 ands r3, r2
- 80026b2: d0e0 beq.n 8002676 <HAL_RCC_OscConfig+0x326>
+ 80026b8: 4bc9 ldr r3, [pc, #804] ; (80029e0 <HAL_RCC_OscConfig+0x680>)
+ 80026ba: 681a ldr r2, [r3, #0]
+ 80026bc: 2380 movs r3, #128 ; 0x80
+ 80026be: 009b lsls r3, r3, #2
+ 80026c0: 4013 ands r3, r2
+ 80026c2: d0e0 beq.n 8002686 <HAL_RCC_OscConfig+0x326>
/* Check MSICalibrationValue and MSIClockRange input parameters */
assert_param(IS_RCC_MSICALIBRATION_VALUE(RCC_OscInitStruct->MSICalibrationValue));
assert_param(IS_RCC_MSI_CLOCK_RANGE(RCC_OscInitStruct->MSIClockRange));
/* Selects the Multiple Speed oscillator (MSI) clock range .*/
__HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);
- 80026b4: 4bc6 ldr r3, [pc, #792] ; (80029d0 <HAL_RCC_OscConfig+0x680>)
- 80026b6: 685b ldr r3, [r3, #4]
- 80026b8: 4ac6 ldr r2, [pc, #792] ; (80029d4 <HAL_RCC_OscConfig+0x684>)
- 80026ba: 4013 ands r3, r2
- 80026bc: 0019 movs r1, r3
- 80026be: 687b ldr r3, [r7, #4]
- 80026c0: 6a1a ldr r2, [r3, #32]
- 80026c2: 4bc3 ldr r3, [pc, #780] ; (80029d0 <HAL_RCC_OscConfig+0x680>)
- 80026c4: 430a orrs r2, r1
- 80026c6: 605a str r2, [r3, #4]
+ 80026c4: 4bc6 ldr r3, [pc, #792] ; (80029e0 <HAL_RCC_OscConfig+0x680>)
+ 80026c6: 685b ldr r3, [r3, #4]
+ 80026c8: 4ac6 ldr r2, [pc, #792] ; (80029e4 <HAL_RCC_OscConfig+0x684>)
+ 80026ca: 4013 ands r3, r2
+ 80026cc: 0019 movs r1, r3
+ 80026ce: 687b ldr r3, [r7, #4]
+ 80026d0: 6a1a ldr r2, [r3, #32]
+ 80026d2: 4bc3 ldr r3, [pc, #780] ; (80029e0 <HAL_RCC_OscConfig+0x680>)
+ 80026d4: 430a orrs r2, r1
+ 80026d6: 605a str r2, [r3, #4]
/* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/
__HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);
- 80026c8: 4bc1 ldr r3, [pc, #772] ; (80029d0 <HAL_RCC_OscConfig+0x680>)
- 80026ca: 685b ldr r3, [r3, #4]
- 80026cc: 021b lsls r3, r3, #8
- 80026ce: 0a19 lsrs r1, r3, #8
- 80026d0: 687b ldr r3, [r7, #4]
- 80026d2: 69db ldr r3, [r3, #28]
- 80026d4: 061a lsls r2, r3, #24
- 80026d6: 4bbe ldr r3, [pc, #760] ; (80029d0 <HAL_RCC_OscConfig+0x680>)
- 80026d8: 430a orrs r2, r1
- 80026da: 605a str r2, [r3, #4]
- 80026dc: e019 b.n 8002712 <HAL_RCC_OscConfig+0x3c2>
+ 80026d8: 4bc1 ldr r3, [pc, #772] ; (80029e0 <HAL_RCC_OscConfig+0x680>)
+ 80026da: 685b ldr r3, [r3, #4]
+ 80026dc: 021b lsls r3, r3, #8
+ 80026de: 0a19 lsrs r1, r3, #8
+ 80026e0: 687b ldr r3, [r7, #4]
+ 80026e2: 69db ldr r3, [r3, #28]
+ 80026e4: 061a lsls r2, r3, #24
+ 80026e6: 4bbe ldr r3, [pc, #760] ; (80029e0 <HAL_RCC_OscConfig+0x680>)
+ 80026e8: 430a orrs r2, r1
+ 80026ea: 605a str r2, [r3, #4]
+ 80026ec: e019 b.n 8002722 <HAL_RCC_OscConfig+0x3c2>
}
else
{
/* Disable the Multi Speed oscillator (MSI). */
__HAL_RCC_MSI_DISABLE();
- 80026de: 4bbc ldr r3, [pc, #752] ; (80029d0 <HAL_RCC_OscConfig+0x680>)
- 80026e0: 681a ldr r2, [r3, #0]
- 80026e2: 4bbb ldr r3, [pc, #748] ; (80029d0 <HAL_RCC_OscConfig+0x680>)
- 80026e4: 49bc ldr r1, [pc, #752] ; (80029d8 <HAL_RCC_OscConfig+0x688>)
- 80026e6: 400a ands r2, r1
- 80026e8: 601a str r2, [r3, #0]
+ 80026ee: 4bbc ldr r3, [pc, #752] ; (80029e0 <HAL_RCC_OscConfig+0x680>)
+ 80026f0: 681a ldr r2, [r3, #0]
+ 80026f2: 4bbb ldr r3, [pc, #748] ; (80029e0 <HAL_RCC_OscConfig+0x680>)
+ 80026f4: 49bc ldr r1, [pc, #752] ; (80029e8 <HAL_RCC_OscConfig+0x688>)
+ 80026f6: 400a ands r2, r1
+ 80026f8: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
- 80026ea: f7fe fd15 bl 8001118 <HAL_GetTick>
- 80026ee: 0003 movs r3, r0
- 80026f0: 617b str r3, [r7, #20]
+ 80026fa: f7fe fd15 bl 8001128 <HAL_GetTick>
+ 80026fe: 0003 movs r3, r0
+ 8002700: 617b str r3, [r7, #20]
/* Wait till MSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) != 0U)
- 80026f2: e008 b.n 8002706 <HAL_RCC_OscConfig+0x3b6>
+ 8002702: e008 b.n 8002716 <HAL_RCC_OscConfig+0x3b6>
{
if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE)
- 80026f4: f7fe fd10 bl 8001118 <HAL_GetTick>
- 80026f8: 0002 movs r2, r0
- 80026fa: 697b ldr r3, [r7, #20]
- 80026fc: 1ad3 subs r3, r2, r3
- 80026fe: 2b02 cmp r3, #2
- 8002700: d901 bls.n 8002706 <HAL_RCC_OscConfig+0x3b6>
+ 8002704: f7fe fd10 bl 8001128 <HAL_GetTick>
+ 8002708: 0002 movs r2, r0
+ 800270a: 697b ldr r3, [r7, #20]
+ 800270c: 1ad3 subs r3, r2, r3
+ 800270e: 2b02 cmp r3, #2
+ 8002710: d901 bls.n 8002716 <HAL_RCC_OscConfig+0x3b6>
{
return HAL_TIMEOUT;
- 8002702: 2303 movs r3, #3
- 8002704: e19a b.n 8002a3c <HAL_RCC_OscConfig+0x6ec>
+ 8002712: 2303 movs r3, #3
+ 8002714: e19a b.n 8002a4c <HAL_RCC_OscConfig+0x6ec>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) != 0U)
- 8002706: 4bb2 ldr r3, [pc, #712] ; (80029d0 <HAL_RCC_OscConfig+0x680>)
- 8002708: 681a ldr r2, [r3, #0]
- 800270a: 2380 movs r3, #128 ; 0x80
- 800270c: 009b lsls r3, r3, #2
- 800270e: 4013 ands r3, r2
- 8002710: d1f0 bne.n 80026f4 <HAL_RCC_OscConfig+0x3a4>
+ 8002716: 4bb2 ldr r3, [pc, #712] ; (80029e0 <HAL_RCC_OscConfig+0x680>)
+ 8002718: 681a ldr r2, [r3, #0]
+ 800271a: 2380 movs r3, #128 ; 0x80
+ 800271c: 009b lsls r3, r3, #2
+ 800271e: 4013 ands r3, r2
+ 8002720: d1f0 bne.n 8002704 <HAL_RCC_OscConfig+0x3a4>
}
}
}
}
/*------------------------------ LSI Configuration -------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
- 8002712: 687b ldr r3, [r7, #4]
- 8002714: 681b ldr r3, [r3, #0]
- 8002716: 2208 movs r2, #8
- 8002718: 4013 ands r3, r2
- 800271a: d036 beq.n 800278a <HAL_RCC_OscConfig+0x43a>
+ 8002722: 687b ldr r3, [r7, #4]
+ 8002724: 681b ldr r3, [r3, #0]
+ 8002726: 2208 movs r2, #8
+ 8002728: 4013 ands r3, r2
+ 800272a: d036 beq.n 800279a <HAL_RCC_OscConfig+0x43a>
{
/* Check the parameters */
assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
/* Check the LSI State */
if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
- 800271c: 687b ldr r3, [r7, #4]
- 800271e: 695b ldr r3, [r3, #20]
- 8002720: 2b00 cmp r3, #0
- 8002722: d019 beq.n 8002758 <HAL_RCC_OscConfig+0x408>
+ 800272c: 687b ldr r3, [r7, #4]
+ 800272e: 695b ldr r3, [r3, #20]
+ 8002730: 2b00 cmp r3, #0
+ 8002732: d019 beq.n 8002768 <HAL_RCC_OscConfig+0x408>
{
/* Enable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_ENABLE();
- 8002724: 4baa ldr r3, [pc, #680] ; (80029d0 <HAL_RCC_OscConfig+0x680>)
- 8002726: 6d1a ldr r2, [r3, #80] ; 0x50
- 8002728: 4ba9 ldr r3, [pc, #676] ; (80029d0 <HAL_RCC_OscConfig+0x680>)
- 800272a: 2101 movs r1, #1
- 800272c: 430a orrs r2, r1
- 800272e: 651a str r2, [r3, #80] ; 0x50
+ 8002734: 4baa ldr r3, [pc, #680] ; (80029e0 <HAL_RCC_OscConfig+0x680>)
+ 8002736: 6d1a ldr r2, [r3, #80] ; 0x50
+ 8002738: 4ba9 ldr r3, [pc, #676] ; (80029e0 <HAL_RCC_OscConfig+0x680>)
+ 800273a: 2101 movs r1, #1
+ 800273c: 430a orrs r2, r1
+ 800273e: 651a str r2, [r3, #80] ; 0x50
/* Get Start Tick */
tickstart = HAL_GetTick();
- 8002730: f7fe fcf2 bl 8001118 <HAL_GetTick>
- 8002734: 0003 movs r3, r0
- 8002736: 617b str r3, [r7, #20]
+ 8002740: f7fe fcf2 bl 8001128 <HAL_GetTick>
+ 8002744: 0003 movs r3, r0
+ 8002746: 617b str r3, [r7, #20]
/* Wait till LSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == 0U)
- 8002738: e008 b.n 800274c <HAL_RCC_OscConfig+0x3fc>
+ 8002748: e008 b.n 800275c <HAL_RCC_OscConfig+0x3fc>
{
if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
- 800273a: f7fe fced bl 8001118 <HAL_GetTick>
- 800273e: 0002 movs r2, r0
- 8002740: 697b ldr r3, [r7, #20]
- 8002742: 1ad3 subs r3, r2, r3
- 8002744: 2b02 cmp r3, #2
- 8002746: d901 bls.n 800274c <HAL_RCC_OscConfig+0x3fc>
+ 800274a: f7fe fced bl 8001128 <HAL_GetTick>
+ 800274e: 0002 movs r2, r0
+ 8002750: 697b ldr r3, [r7, #20]
+ 8002752: 1ad3 subs r3, r2, r3
+ 8002754: 2b02 cmp r3, #2
+ 8002756: d901 bls.n 800275c <HAL_RCC_OscConfig+0x3fc>
{
return HAL_TIMEOUT;
- 8002748: 2303 movs r3, #3
- 800274a: e177 b.n 8002a3c <HAL_RCC_OscConfig+0x6ec>
+ 8002758: 2303 movs r3, #3
+ 800275a: e177 b.n 8002a4c <HAL_RCC_OscConfig+0x6ec>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == 0U)
- 800274c: 4ba0 ldr r3, [pc, #640] ; (80029d0 <HAL_RCC_OscConfig+0x680>)
- 800274e: 6d1b ldr r3, [r3, #80] ; 0x50
- 8002750: 2202 movs r2, #2
- 8002752: 4013 ands r3, r2
- 8002754: d0f1 beq.n 800273a <HAL_RCC_OscConfig+0x3ea>
- 8002756: e018 b.n 800278a <HAL_RCC_OscConfig+0x43a>
+ 800275c: 4ba0 ldr r3, [pc, #640] ; (80029e0 <HAL_RCC_OscConfig+0x680>)
+ 800275e: 6d1b ldr r3, [r3, #80] ; 0x50
+ 8002760: 2202 movs r2, #2
+ 8002762: 4013 ands r3, r2
+ 8002764: d0f1 beq.n 800274a <HAL_RCC_OscConfig+0x3ea>
+ 8002766: e018 b.n 800279a <HAL_RCC_OscConfig+0x43a>
}
}
else
{
/* Disable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_DISABLE();
- 8002758: 4b9d ldr r3, [pc, #628] ; (80029d0 <HAL_RCC_OscConfig+0x680>)
- 800275a: 6d1a ldr r2, [r3, #80] ; 0x50
- 800275c: 4b9c ldr r3, [pc, #624] ; (80029d0 <HAL_RCC_OscConfig+0x680>)
- 800275e: 2101 movs r1, #1
- 8002760: 438a bics r2, r1
- 8002762: 651a str r2, [r3, #80] ; 0x50
+ 8002768: 4b9d ldr r3, [pc, #628] ; (80029e0 <HAL_RCC_OscConfig+0x680>)
+ 800276a: 6d1a ldr r2, [r3, #80] ; 0x50
+ 800276c: 4b9c ldr r3, [pc, #624] ; (80029e0 <HAL_RCC_OscConfig+0x680>)
+ 800276e: 2101 movs r1, #1
+ 8002770: 438a bics r2, r1
+ 8002772: 651a str r2, [r3, #80] ; 0x50
/* Get Start Tick */
tickstart = HAL_GetTick();
- 8002764: f7fe fcd8 bl 8001118 <HAL_GetTick>
- 8002768: 0003 movs r3, r0
- 800276a: 617b str r3, [r7, #20]
+ 8002774: f7fe fcd8 bl 8001128 <HAL_GetTick>
+ 8002778: 0003 movs r3, r0
+ 800277a: 617b str r3, [r7, #20]
/* Wait till LSI is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != 0U)
- 800276c: e008 b.n 8002780 <HAL_RCC_OscConfig+0x430>
+ 800277c: e008 b.n 8002790 <HAL_RCC_OscConfig+0x430>
{
if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
- 800276e: f7fe fcd3 bl 8001118 <HAL_GetTick>
- 8002772: 0002 movs r2, r0
- 8002774: 697b ldr r3, [r7, #20]
- 8002776: 1ad3 subs r3, r2, r3
- 8002778: 2b02 cmp r3, #2
- 800277a: d901 bls.n 8002780 <HAL_RCC_OscConfig+0x430>
+ 800277e: f7fe fcd3 bl 8001128 <HAL_GetTick>
+ 8002782: 0002 movs r2, r0
+ 8002784: 697b ldr r3, [r7, #20]
+ 8002786: 1ad3 subs r3, r2, r3
+ 8002788: 2b02 cmp r3, #2
+ 800278a: d901 bls.n 8002790 <HAL_RCC_OscConfig+0x430>
{
return HAL_TIMEOUT;
- 800277c: 2303 movs r3, #3
- 800277e: e15d b.n 8002a3c <HAL_RCC_OscConfig+0x6ec>
+ 800278c: 2303 movs r3, #3
+ 800278e: e15d b.n 8002a4c <HAL_RCC_OscConfig+0x6ec>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != 0U)
- 8002780: 4b93 ldr r3, [pc, #588] ; (80029d0 <HAL_RCC_OscConfig+0x680>)
- 8002782: 6d1b ldr r3, [r3, #80] ; 0x50
- 8002784: 2202 movs r2, #2
- 8002786: 4013 ands r3, r2
- 8002788: d1f1 bne.n 800276e <HAL_RCC_OscConfig+0x41e>
+ 8002790: 4b93 ldr r3, [pc, #588] ; (80029e0 <HAL_RCC_OscConfig+0x680>)
+ 8002792: 6d1b ldr r3, [r3, #80] ; 0x50
+ 8002794: 2202 movs r2, #2
+ 8002796: 4013 ands r3, r2
+ 8002798: d1f1 bne.n 800277e <HAL_RCC_OscConfig+0x41e>
}
}
}
}
/*------------------------------ LSE Configuration -------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
- 800278a: 687b ldr r3, [r7, #4]
- 800278c: 681b ldr r3, [r3, #0]
- 800278e: 2204 movs r2, #4
- 8002790: 4013 ands r3, r2
- 8002792: d100 bne.n 8002796 <HAL_RCC_OscConfig+0x446>
- 8002794: e0ae b.n 80028f4 <HAL_RCC_OscConfig+0x5a4>
+ 800279a: 687b ldr r3, [r7, #4]
+ 800279c: 681b ldr r3, [r3, #0]
+ 800279e: 2204 movs r2, #4
+ 80027a0: 4013 ands r3, r2
+ 80027a2: d100 bne.n 80027a6 <HAL_RCC_OscConfig+0x446>
+ 80027a4: e0ae b.n 8002904 <HAL_RCC_OscConfig+0x5a4>
{
FlagStatus pwrclkchanged = RESET;
- 8002796: 2023 movs r0, #35 ; 0x23
- 8002798: 183b adds r3, r7, r0
- 800279a: 2200 movs r2, #0
- 800279c: 701a strb r2, [r3, #0]
+ 80027a6: 2023 movs r0, #35 ; 0x23
+ 80027a8: 183b adds r3, r7, r0
+ 80027aa: 2200 movs r2, #0
+ 80027ac: 701a strb r2, [r3, #0]
/* Check the parameters */
assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
/* Update LSE configuration in Backup Domain control register */
/* Requires to enable write access to Backup Domain of necessary */
if(__HAL_RCC_PWR_IS_CLK_DISABLED())
- 800279e: 4b8c ldr r3, [pc, #560] ; (80029d0 <HAL_RCC_OscConfig+0x680>)
- 80027a0: 6b9a ldr r2, [r3, #56] ; 0x38
- 80027a2: 2380 movs r3, #128 ; 0x80
- 80027a4: 055b lsls r3, r3, #21
- 80027a6: 4013 ands r3, r2
- 80027a8: d109 bne.n 80027be <HAL_RCC_OscConfig+0x46e>
+ 80027ae: 4b8c ldr r3, [pc, #560] ; (80029e0 <HAL_RCC_OscConfig+0x680>)
+ 80027b0: 6b9a ldr r2, [r3, #56] ; 0x38
+ 80027b2: 2380 movs r3, #128 ; 0x80
+ 80027b4: 055b lsls r3, r3, #21
+ 80027b6: 4013 ands r3, r2
+ 80027b8: d109 bne.n 80027ce <HAL_RCC_OscConfig+0x46e>
{
__HAL_RCC_PWR_CLK_ENABLE();
- 80027aa: 4b89 ldr r3, [pc, #548] ; (80029d0 <HAL_RCC_OscConfig+0x680>)
- 80027ac: 6b9a ldr r2, [r3, #56] ; 0x38
- 80027ae: 4b88 ldr r3, [pc, #544] ; (80029d0 <HAL_RCC_OscConfig+0x680>)
- 80027b0: 2180 movs r1, #128 ; 0x80
- 80027b2: 0549 lsls r1, r1, #21
- 80027b4: 430a orrs r2, r1
- 80027b6: 639a str r2, [r3, #56] ; 0x38
+ 80027ba: 4b89 ldr r3, [pc, #548] ; (80029e0 <HAL_RCC_OscConfig+0x680>)
+ 80027bc: 6b9a ldr r2, [r3, #56] ; 0x38
+ 80027be: 4b88 ldr r3, [pc, #544] ; (80029e0 <HAL_RCC_OscConfig+0x680>)
+ 80027c0: 2180 movs r1, #128 ; 0x80
+ 80027c2: 0549 lsls r1, r1, #21
+ 80027c4: 430a orrs r2, r1
+ 80027c6: 639a str r2, [r3, #56] ; 0x38
pwrclkchanged = SET;
- 80027b8: 183b adds r3, r7, r0
- 80027ba: 2201 movs r2, #1
- 80027bc: 701a strb r2, [r3, #0]
+ 80027c8: 183b adds r3, r7, r0
+ 80027ca: 2201 movs r2, #1
+ 80027cc: 701a strb r2, [r3, #0]
}
if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
- 80027be: 4b87 ldr r3, [pc, #540] ; (80029dc <HAL_RCC_OscConfig+0x68c>)
- 80027c0: 681a ldr r2, [r3, #0]
- 80027c2: 2380 movs r3, #128 ; 0x80
- 80027c4: 005b lsls r3, r3, #1
- 80027c6: 4013 ands r3, r2
- 80027c8: d11a bne.n 8002800 <HAL_RCC_OscConfig+0x4b0>
+ 80027ce: 4b87 ldr r3, [pc, #540] ; (80029ec <HAL_RCC_OscConfig+0x68c>)
+ 80027d0: 681a ldr r2, [r3, #0]
+ 80027d2: 2380 movs r3, #128 ; 0x80
+ 80027d4: 005b lsls r3, r3, #1
+ 80027d6: 4013 ands r3, r2
+ 80027d8: d11a bne.n 8002810 <HAL_RCC_OscConfig+0x4b0>
{
/* Enable write access to Backup domain */
SET_BIT(PWR->CR, PWR_CR_DBP);
- 80027ca: 4b84 ldr r3, [pc, #528] ; (80029dc <HAL_RCC_OscConfig+0x68c>)
- 80027cc: 681a ldr r2, [r3, #0]
- 80027ce: 4b83 ldr r3, [pc, #524] ; (80029dc <HAL_RCC_OscConfig+0x68c>)
- 80027d0: 2180 movs r1, #128 ; 0x80
- 80027d2: 0049 lsls r1, r1, #1
- 80027d4: 430a orrs r2, r1
- 80027d6: 601a str r2, [r3, #0]
+ 80027da: 4b84 ldr r3, [pc, #528] ; (80029ec <HAL_RCC_OscConfig+0x68c>)
+ 80027dc: 681a ldr r2, [r3, #0]
+ 80027de: 4b83 ldr r3, [pc, #524] ; (80029ec <HAL_RCC_OscConfig+0x68c>)
+ 80027e0: 2180 movs r1, #128 ; 0x80
+ 80027e2: 0049 lsls r1, r1, #1
+ 80027e4: 430a orrs r2, r1
+ 80027e6: 601a str r2, [r3, #0]
/* Wait for Backup domain Write protection disable */
tickstart = HAL_GetTick();
- 80027d8: f7fe fc9e bl 8001118 <HAL_GetTick>
- 80027dc: 0003 movs r3, r0
- 80027de: 617b str r3, [r7, #20]
+ 80027e8: f7fe fc9e bl 8001128 <HAL_GetTick>
+ 80027ec: 0003 movs r3, r0
+ 80027ee: 617b str r3, [r7, #20]
while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
- 80027e0: e008 b.n 80027f4 <HAL_RCC_OscConfig+0x4a4>
+ 80027f0: e008 b.n 8002804 <HAL_RCC_OscConfig+0x4a4>
{
if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
- 80027e2: f7fe fc99 bl 8001118 <HAL_GetTick>
- 80027e6: 0002 movs r2, r0
- 80027e8: 697b ldr r3, [r7, #20]
- 80027ea: 1ad3 subs r3, r2, r3
- 80027ec: 2b64 cmp r3, #100 ; 0x64
- 80027ee: d901 bls.n 80027f4 <HAL_RCC_OscConfig+0x4a4>
+ 80027f2: f7fe fc99 bl 8001128 <HAL_GetTick>
+ 80027f6: 0002 movs r2, r0
+ 80027f8: 697b ldr r3, [r7, #20]
+ 80027fa: 1ad3 subs r3, r2, r3
+ 80027fc: 2b64 cmp r3, #100 ; 0x64
+ 80027fe: d901 bls.n 8002804 <HAL_RCC_OscConfig+0x4a4>
{
return HAL_TIMEOUT;
- 80027f0: 2303 movs r3, #3
- 80027f2: e123 b.n 8002a3c <HAL_RCC_OscConfig+0x6ec>
+ 8002800: 2303 movs r3, #3
+ 8002802: e123 b.n 8002a4c <HAL_RCC_OscConfig+0x6ec>
while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
- 80027f4: 4b79 ldr r3, [pc, #484] ; (80029dc <HAL_RCC_OscConfig+0x68c>)
- 80027f6: 681a ldr r2, [r3, #0]
- 80027f8: 2380 movs r3, #128 ; 0x80
- 80027fa: 005b lsls r3, r3, #1
- 80027fc: 4013 ands r3, r2
- 80027fe: d0f0 beq.n 80027e2 <HAL_RCC_OscConfig+0x492>
+ 8002804: 4b79 ldr r3, [pc, #484] ; (80029ec <HAL_RCC_OscConfig+0x68c>)
+ 8002806: 681a ldr r2, [r3, #0]
+ 8002808: 2380 movs r3, #128 ; 0x80
+ 800280a: 005b lsls r3, r3, #1
+ 800280c: 4013 ands r3, r2
+ 800280e: d0f0 beq.n 80027f2 <HAL_RCC_OscConfig+0x492>
}
}
}
/* Set the new LSE configuration -----------------------------------------*/
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
- 8002800: 687b ldr r3, [r7, #4]
- 8002802: 689a ldr r2, [r3, #8]
- 8002804: 2380 movs r3, #128 ; 0x80
- 8002806: 005b lsls r3, r3, #1
- 8002808: 429a cmp r2, r3
- 800280a: d107 bne.n 800281c <HAL_RCC_OscConfig+0x4cc>
- 800280c: 4b70 ldr r3, [pc, #448] ; (80029d0 <HAL_RCC_OscConfig+0x680>)
- 800280e: 6d1a ldr r2, [r3, #80] ; 0x50
- 8002810: 4b6f ldr r3, [pc, #444] ; (80029d0 <HAL_RCC_OscConfig+0x680>)
- 8002812: 2180 movs r1, #128 ; 0x80
- 8002814: 0049 lsls r1, r1, #1
- 8002816: 430a orrs r2, r1
- 8002818: 651a str r2, [r3, #80] ; 0x50
- 800281a: e031 b.n 8002880 <HAL_RCC_OscConfig+0x530>
- 800281c: 687b ldr r3, [r7, #4]
- 800281e: 689b ldr r3, [r3, #8]
- 8002820: 2b00 cmp r3, #0
- 8002822: d10c bne.n 800283e <HAL_RCC_OscConfig+0x4ee>
- 8002824: 4b6a ldr r3, [pc, #424] ; (80029d0 <HAL_RCC_OscConfig+0x680>)
- 8002826: 6d1a ldr r2, [r3, #80] ; 0x50
- 8002828: 4b69 ldr r3, [pc, #420] ; (80029d0 <HAL_RCC_OscConfig+0x680>)
- 800282a: 496b ldr r1, [pc, #428] ; (80029d8 <HAL_RCC_OscConfig+0x688>)
- 800282c: 400a ands r2, r1
- 800282e: 651a str r2, [r3, #80] ; 0x50
- 8002830: 4b67 ldr r3, [pc, #412] ; (80029d0 <HAL_RCC_OscConfig+0x680>)
- 8002832: 6d1a ldr r2, [r3, #80] ; 0x50
- 8002834: 4b66 ldr r3, [pc, #408] ; (80029d0 <HAL_RCC_OscConfig+0x680>)
- 8002836: 496a ldr r1, [pc, #424] ; (80029e0 <HAL_RCC_OscConfig+0x690>)
- 8002838: 400a ands r2, r1
- 800283a: 651a str r2, [r3, #80] ; 0x50
- 800283c: e020 b.n 8002880 <HAL_RCC_OscConfig+0x530>
- 800283e: 687b ldr r3, [r7, #4]
- 8002840: 689a ldr r2, [r3, #8]
- 8002842: 23a0 movs r3, #160 ; 0xa0
- 8002844: 00db lsls r3, r3, #3
- 8002846: 429a cmp r2, r3
- 8002848: d10e bne.n 8002868 <HAL_RCC_OscConfig+0x518>
- 800284a: 4b61 ldr r3, [pc, #388] ; (80029d0 <HAL_RCC_OscConfig+0x680>)
- 800284c: 6d1a ldr r2, [r3, #80] ; 0x50
- 800284e: 4b60 ldr r3, [pc, #384] ; (80029d0 <HAL_RCC_OscConfig+0x680>)
- 8002850: 2180 movs r1, #128 ; 0x80
- 8002852: 00c9 lsls r1, r1, #3
- 8002854: 430a orrs r2, r1
- 8002856: 651a str r2, [r3, #80] ; 0x50
- 8002858: 4b5d ldr r3, [pc, #372] ; (80029d0 <HAL_RCC_OscConfig+0x680>)
- 800285a: 6d1a ldr r2, [r3, #80] ; 0x50
- 800285c: 4b5c ldr r3, [pc, #368] ; (80029d0 <HAL_RCC_OscConfig+0x680>)
- 800285e: 2180 movs r1, #128 ; 0x80
- 8002860: 0049 lsls r1, r1, #1
- 8002862: 430a orrs r2, r1
- 8002864: 651a str r2, [r3, #80] ; 0x50
- 8002866: e00b b.n 8002880 <HAL_RCC_OscConfig+0x530>
- 8002868: 4b59 ldr r3, [pc, #356] ; (80029d0 <HAL_RCC_OscConfig+0x680>)
+ 8002810: 687b ldr r3, [r7, #4]
+ 8002812: 689a ldr r2, [r3, #8]
+ 8002814: 2380 movs r3, #128 ; 0x80
+ 8002816: 005b lsls r3, r3, #1
+ 8002818: 429a cmp r2, r3
+ 800281a: d107 bne.n 800282c <HAL_RCC_OscConfig+0x4cc>
+ 800281c: 4b70 ldr r3, [pc, #448] ; (80029e0 <HAL_RCC_OscConfig+0x680>)
+ 800281e: 6d1a ldr r2, [r3, #80] ; 0x50
+ 8002820: 4b6f ldr r3, [pc, #444] ; (80029e0 <HAL_RCC_OscConfig+0x680>)
+ 8002822: 2180 movs r1, #128 ; 0x80
+ 8002824: 0049 lsls r1, r1, #1
+ 8002826: 430a orrs r2, r1
+ 8002828: 651a str r2, [r3, #80] ; 0x50
+ 800282a: e031 b.n 8002890 <HAL_RCC_OscConfig+0x530>
+ 800282c: 687b ldr r3, [r7, #4]
+ 800282e: 689b ldr r3, [r3, #8]
+ 8002830: 2b00 cmp r3, #0
+ 8002832: d10c bne.n 800284e <HAL_RCC_OscConfig+0x4ee>
+ 8002834: 4b6a ldr r3, [pc, #424] ; (80029e0 <HAL_RCC_OscConfig+0x680>)
+ 8002836: 6d1a ldr r2, [r3, #80] ; 0x50
+ 8002838: 4b69 ldr r3, [pc, #420] ; (80029e0 <HAL_RCC_OscConfig+0x680>)
+ 800283a: 496b ldr r1, [pc, #428] ; (80029e8 <HAL_RCC_OscConfig+0x688>)
+ 800283c: 400a ands r2, r1
+ 800283e: 651a str r2, [r3, #80] ; 0x50
+ 8002840: 4b67 ldr r3, [pc, #412] ; (80029e0 <HAL_RCC_OscConfig+0x680>)
+ 8002842: 6d1a ldr r2, [r3, #80] ; 0x50
+ 8002844: 4b66 ldr r3, [pc, #408] ; (80029e0 <HAL_RCC_OscConfig+0x680>)
+ 8002846: 496a ldr r1, [pc, #424] ; (80029f0 <HAL_RCC_OscConfig+0x690>)
+ 8002848: 400a ands r2, r1
+ 800284a: 651a str r2, [r3, #80] ; 0x50
+ 800284c: e020 b.n 8002890 <HAL_RCC_OscConfig+0x530>
+ 800284e: 687b ldr r3, [r7, #4]
+ 8002850: 689a ldr r2, [r3, #8]
+ 8002852: 23a0 movs r3, #160 ; 0xa0
+ 8002854: 00db lsls r3, r3, #3
+ 8002856: 429a cmp r2, r3
+ 8002858: d10e bne.n 8002878 <HAL_RCC_OscConfig+0x518>
+ 800285a: 4b61 ldr r3, [pc, #388] ; (80029e0 <HAL_RCC_OscConfig+0x680>)
+ 800285c: 6d1a ldr r2, [r3, #80] ; 0x50
+ 800285e: 4b60 ldr r3, [pc, #384] ; (80029e0 <HAL_RCC_OscConfig+0x680>)
+ 8002860: 2180 movs r1, #128 ; 0x80
+ 8002862: 00c9 lsls r1, r1, #3
+ 8002864: 430a orrs r2, r1
+ 8002866: 651a str r2, [r3, #80] ; 0x50
+ 8002868: 4b5d ldr r3, [pc, #372] ; (80029e0 <HAL_RCC_OscConfig+0x680>)
800286a: 6d1a ldr r2, [r3, #80] ; 0x50
- 800286c: 4b58 ldr r3, [pc, #352] ; (80029d0 <HAL_RCC_OscConfig+0x680>)
- 800286e: 495a ldr r1, [pc, #360] ; (80029d8 <HAL_RCC_OscConfig+0x688>)
- 8002870: 400a ands r2, r1
- 8002872: 651a str r2, [r3, #80] ; 0x50
- 8002874: 4b56 ldr r3, [pc, #344] ; (80029d0 <HAL_RCC_OscConfig+0x680>)
- 8002876: 6d1a ldr r2, [r3, #80] ; 0x50
- 8002878: 4b55 ldr r3, [pc, #340] ; (80029d0 <HAL_RCC_OscConfig+0x680>)
- 800287a: 4959 ldr r1, [pc, #356] ; (80029e0 <HAL_RCC_OscConfig+0x690>)
- 800287c: 400a ands r2, r1
- 800287e: 651a str r2, [r3, #80] ; 0x50
+ 800286c: 4b5c ldr r3, [pc, #368] ; (80029e0 <HAL_RCC_OscConfig+0x680>)
+ 800286e: 2180 movs r1, #128 ; 0x80
+ 8002870: 0049 lsls r1, r1, #1
+ 8002872: 430a orrs r2, r1
+ 8002874: 651a str r2, [r3, #80] ; 0x50
+ 8002876: e00b b.n 8002890 <HAL_RCC_OscConfig+0x530>
+ 8002878: 4b59 ldr r3, [pc, #356] ; (80029e0 <HAL_RCC_OscConfig+0x680>)
+ 800287a: 6d1a ldr r2, [r3, #80] ; 0x50
+ 800287c: 4b58 ldr r3, [pc, #352] ; (80029e0 <HAL_RCC_OscConfig+0x680>)
+ 800287e: 495a ldr r1, [pc, #360] ; (80029e8 <HAL_RCC_OscConfig+0x688>)
+ 8002880: 400a ands r2, r1
+ 8002882: 651a str r2, [r3, #80] ; 0x50
+ 8002884: 4b56 ldr r3, [pc, #344] ; (80029e0 <HAL_RCC_OscConfig+0x680>)
+ 8002886: 6d1a ldr r2, [r3, #80] ; 0x50
+ 8002888: 4b55 ldr r3, [pc, #340] ; (80029e0 <HAL_RCC_OscConfig+0x680>)
+ 800288a: 4959 ldr r1, [pc, #356] ; (80029f0 <HAL_RCC_OscConfig+0x690>)
+ 800288c: 400a ands r2, r1
+ 800288e: 651a str r2, [r3, #80] ; 0x50
/* Check the LSE State */
if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
- 8002880: 687b ldr r3, [r7, #4]
- 8002882: 689b ldr r3, [r3, #8]
- 8002884: 2b00 cmp r3, #0
- 8002886: d015 beq.n 80028b4 <HAL_RCC_OscConfig+0x564>
+ 8002890: 687b ldr r3, [r7, #4]
+ 8002892: 689b ldr r3, [r3, #8]
+ 8002894: 2b00 cmp r3, #0
+ 8002896: d015 beq.n 80028c4 <HAL_RCC_OscConfig+0x564>
{
/* Get Start Tick */
tickstart = HAL_GetTick();
- 8002888: f7fe fc46 bl 8001118 <HAL_GetTick>
- 800288c: 0003 movs r3, r0
- 800288e: 617b str r3, [r7, #20]
+ 8002898: f7fe fc46 bl 8001128 <HAL_GetTick>
+ 800289c: 0003 movs r3, r0
+ 800289e: 617b str r3, [r7, #20]
/* Wait till LSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U)
- 8002890: e009 b.n 80028a6 <HAL_RCC_OscConfig+0x556>
+ 80028a0: e009 b.n 80028b6 <HAL_RCC_OscConfig+0x556>
{
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
- 8002892: f7fe fc41 bl 8001118 <HAL_GetTick>
- 8002896: 0002 movs r2, r0
- 8002898: 697b ldr r3, [r7, #20]
- 800289a: 1ad3 subs r3, r2, r3
- 800289c: 4a51 ldr r2, [pc, #324] ; (80029e4 <HAL_RCC_OscConfig+0x694>)
- 800289e: 4293 cmp r3, r2
- 80028a0: d901 bls.n 80028a6 <HAL_RCC_OscConfig+0x556>
+ 80028a2: f7fe fc41 bl 8001128 <HAL_GetTick>
+ 80028a6: 0002 movs r2, r0
+ 80028a8: 697b ldr r3, [r7, #20]
+ 80028aa: 1ad3 subs r3, r2, r3
+ 80028ac: 4a51 ldr r2, [pc, #324] ; (80029f4 <HAL_RCC_OscConfig+0x694>)
+ 80028ae: 4293 cmp r3, r2
+ 80028b0: d901 bls.n 80028b6 <HAL_RCC_OscConfig+0x556>
{
return HAL_TIMEOUT;
- 80028a2: 2303 movs r3, #3
- 80028a4: e0ca b.n 8002a3c <HAL_RCC_OscConfig+0x6ec>
+ 80028b2: 2303 movs r3, #3
+ 80028b4: e0ca b.n 8002a4c <HAL_RCC_OscConfig+0x6ec>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U)
- 80028a6: 4b4a ldr r3, [pc, #296] ; (80029d0 <HAL_RCC_OscConfig+0x680>)
- 80028a8: 6d1a ldr r2, [r3, #80] ; 0x50
- 80028aa: 2380 movs r3, #128 ; 0x80
- 80028ac: 009b lsls r3, r3, #2
- 80028ae: 4013 ands r3, r2
- 80028b0: d0ef beq.n 8002892 <HAL_RCC_OscConfig+0x542>
- 80028b2: e014 b.n 80028de <HAL_RCC_OscConfig+0x58e>
+ 80028b6: 4b4a ldr r3, [pc, #296] ; (80029e0 <HAL_RCC_OscConfig+0x680>)
+ 80028b8: 6d1a ldr r2, [r3, #80] ; 0x50
+ 80028ba: 2380 movs r3, #128 ; 0x80
+ 80028bc: 009b lsls r3, r3, #2
+ 80028be: 4013 ands r3, r2
+ 80028c0: d0ef beq.n 80028a2 <HAL_RCC_OscConfig+0x542>
+ 80028c2: e014 b.n 80028ee <HAL_RCC_OscConfig+0x58e>
}
}
else
{
/* Get Start Tick */
tickstart = HAL_GetTick();
- 80028b4: f7fe fc30 bl 8001118 <HAL_GetTick>
- 80028b8: 0003 movs r3, r0
- 80028ba: 617b str r3, [r7, #20]
+ 80028c4: f7fe fc30 bl 8001128 <HAL_GetTick>
+ 80028c8: 0003 movs r3, r0
+ 80028ca: 617b str r3, [r7, #20]
/* Wait till LSE is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != 0U)
- 80028bc: e009 b.n 80028d2 <HAL_RCC_OscConfig+0x582>
+ 80028cc: e009 b.n 80028e2 <HAL_RCC_OscConfig+0x582>
{
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
- 80028be: f7fe fc2b bl 8001118 <HAL_GetTick>
- 80028c2: 0002 movs r2, r0
- 80028c4: 697b ldr r3, [r7, #20]
- 80028c6: 1ad3 subs r3, r2, r3
- 80028c8: 4a46 ldr r2, [pc, #280] ; (80029e4 <HAL_RCC_OscConfig+0x694>)
- 80028ca: 4293 cmp r3, r2
- 80028cc: d901 bls.n 80028d2 <HAL_RCC_OscConfig+0x582>
+ 80028ce: f7fe fc2b bl 8001128 <HAL_GetTick>
+ 80028d2: 0002 movs r2, r0
+ 80028d4: 697b ldr r3, [r7, #20]
+ 80028d6: 1ad3 subs r3, r2, r3
+ 80028d8: 4a46 ldr r2, [pc, #280] ; (80029f4 <HAL_RCC_OscConfig+0x694>)
+ 80028da: 4293 cmp r3, r2
+ 80028dc: d901 bls.n 80028e2 <HAL_RCC_OscConfig+0x582>
{
return HAL_TIMEOUT;
- 80028ce: 2303 movs r3, #3
- 80028d0: e0b4 b.n 8002a3c <HAL_RCC_OscConfig+0x6ec>
+ 80028de: 2303 movs r3, #3
+ 80028e0: e0b4 b.n 8002a4c <HAL_RCC_OscConfig+0x6ec>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != 0U)
- 80028d2: 4b3f ldr r3, [pc, #252] ; (80029d0 <HAL_RCC_OscConfig+0x680>)
- 80028d4: 6d1a ldr r2, [r3, #80] ; 0x50
- 80028d6: 2380 movs r3, #128 ; 0x80
- 80028d8: 009b lsls r3, r3, #2
- 80028da: 4013 ands r3, r2
- 80028dc: d1ef bne.n 80028be <HAL_RCC_OscConfig+0x56e>
+ 80028e2: 4b3f ldr r3, [pc, #252] ; (80029e0 <HAL_RCC_OscConfig+0x680>)
+ 80028e4: 6d1a ldr r2, [r3, #80] ; 0x50
+ 80028e6: 2380 movs r3, #128 ; 0x80
+ 80028e8: 009b lsls r3, r3, #2
+ 80028ea: 4013 ands r3, r2
+ 80028ec: d1ef bne.n 80028ce <HAL_RCC_OscConfig+0x56e>
}
}
}
/* Require to disable power clock if necessary */
if(pwrclkchanged == SET)
- 80028de: 2323 movs r3, #35 ; 0x23
- 80028e0: 18fb adds r3, r7, r3
- 80028e2: 781b ldrb r3, [r3, #0]
- 80028e4: 2b01 cmp r3, #1
- 80028e6: d105 bne.n 80028f4 <HAL_RCC_OscConfig+0x5a4>
+ 80028ee: 2323 movs r3, #35 ; 0x23
+ 80028f0: 18fb adds r3, r7, r3
+ 80028f2: 781b ldrb r3, [r3, #0]
+ 80028f4: 2b01 cmp r3, #1
+ 80028f6: d105 bne.n 8002904 <HAL_RCC_OscConfig+0x5a4>
{
__HAL_RCC_PWR_CLK_DISABLE();
- 80028e8: 4b39 ldr r3, [pc, #228] ; (80029d0 <HAL_RCC_OscConfig+0x680>)
- 80028ea: 6b9a ldr r2, [r3, #56] ; 0x38
- 80028ec: 4b38 ldr r3, [pc, #224] ; (80029d0 <HAL_RCC_OscConfig+0x680>)
- 80028ee: 493e ldr r1, [pc, #248] ; (80029e8 <HAL_RCC_OscConfig+0x698>)
- 80028f0: 400a ands r2, r1
- 80028f2: 639a str r2, [r3, #56] ; 0x38
+ 80028f8: 4b39 ldr r3, [pc, #228] ; (80029e0 <HAL_RCC_OscConfig+0x680>)
+ 80028fa: 6b9a ldr r2, [r3, #56] ; 0x38
+ 80028fc: 4b38 ldr r3, [pc, #224] ; (80029e0 <HAL_RCC_OscConfig+0x680>)
+ 80028fe: 493e ldr r1, [pc, #248] ; (80029f8 <HAL_RCC_OscConfig+0x698>)
+ 8002900: 400a ands r2, r1
+ 8002902: 639a str r2, [r3, #56] ; 0x38
#endif /* RCC_HSI48_SUPPORT */
/*-------------------------------- PLL Configuration -----------------------*/
/* Check the parameters */
assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
- 80028f4: 687b ldr r3, [r7, #4]
- 80028f6: 6a5b ldr r3, [r3, #36] ; 0x24
- 80028f8: 2b00 cmp r3, #0
- 80028fa: d100 bne.n 80028fe <HAL_RCC_OscConfig+0x5ae>
- 80028fc: e09d b.n 8002a3a <HAL_RCC_OscConfig+0x6ea>
+ 8002904: 687b ldr r3, [r7, #4]
+ 8002906: 6a5b ldr r3, [r3, #36] ; 0x24
+ 8002908: 2b00 cmp r3, #0
+ 800290a: d100 bne.n 800290e <HAL_RCC_OscConfig+0x5ae>
+ 800290c: e09d b.n 8002a4a <HAL_RCC_OscConfig+0x6ea>
{
/* Check if the PLL is used as system clock or not */
if(sysclk_source != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
- 80028fe: 69fb ldr r3, [r7, #28]
- 8002900: 2b0c cmp r3, #12
- 8002902: d100 bne.n 8002906 <HAL_RCC_OscConfig+0x5b6>
- 8002904: e076 b.n 80029f4 <HAL_RCC_OscConfig+0x6a4>
+ 800290e: 69fb ldr r3, [r7, #28]
+ 8002910: 2b0c cmp r3, #12
+ 8002912: d100 bne.n 8002916 <HAL_RCC_OscConfig+0x5b6>
+ 8002914: e076 b.n 8002a04 <HAL_RCC_OscConfig+0x6a4>
{
if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
- 8002906: 687b ldr r3, [r7, #4]
- 8002908: 6a5b ldr r3, [r3, #36] ; 0x24
- 800290a: 2b02 cmp r3, #2
- 800290c: d145 bne.n 800299a <HAL_RCC_OscConfig+0x64a>
+ 8002916: 687b ldr r3, [r7, #4]
+ 8002918: 6a5b ldr r3, [r3, #36] ; 0x24
+ 800291a: 2b02 cmp r3, #2
+ 800291c: d145 bne.n 80029aa <HAL_RCC_OscConfig+0x64a>
assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL));
assert_param(IS_RCC_PLL_DIV(RCC_OscInitStruct->PLL.PLLDIV));
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
- 800290e: 4b30 ldr r3, [pc, #192] ; (80029d0 <HAL_RCC_OscConfig+0x680>)
- 8002910: 681a ldr r2, [r3, #0]
- 8002912: 4b2f ldr r3, [pc, #188] ; (80029d0 <HAL_RCC_OscConfig+0x680>)
- 8002914: 4935 ldr r1, [pc, #212] ; (80029ec <HAL_RCC_OscConfig+0x69c>)
- 8002916: 400a ands r2, r1
- 8002918: 601a str r2, [r3, #0]
+ 800291e: 4b30 ldr r3, [pc, #192] ; (80029e0 <HAL_RCC_OscConfig+0x680>)
+ 8002920: 681a ldr r2, [r3, #0]
+ 8002922: 4b2f ldr r3, [pc, #188] ; (80029e0 <HAL_RCC_OscConfig+0x680>)
+ 8002924: 4935 ldr r1, [pc, #212] ; (80029fc <HAL_RCC_OscConfig+0x69c>)
+ 8002926: 400a ands r2, r1
+ 8002928: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
- 800291a: f7fe fbfd bl 8001118 <HAL_GetTick>
- 800291e: 0003 movs r3, r0
- 8002920: 617b str r3, [r7, #20]
+ 800292a: f7fe fbfd bl 8001128 <HAL_GetTick>
+ 800292e: 0003 movs r3, r0
+ 8002930: 617b str r3, [r7, #20]
/* Wait till PLL is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U)
- 8002922: e008 b.n 8002936 <HAL_RCC_OscConfig+0x5e6>
+ 8002932: e008 b.n 8002946 <HAL_RCC_OscConfig+0x5e6>
{
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
- 8002924: f7fe fbf8 bl 8001118 <HAL_GetTick>
- 8002928: 0002 movs r2, r0
- 800292a: 697b ldr r3, [r7, #20]
- 800292c: 1ad3 subs r3, r2, r3
- 800292e: 2b02 cmp r3, #2
- 8002930: d901 bls.n 8002936 <HAL_RCC_OscConfig+0x5e6>
+ 8002934: f7fe fbf8 bl 8001128 <HAL_GetTick>
+ 8002938: 0002 movs r2, r0
+ 800293a: 697b ldr r3, [r7, #20]
+ 800293c: 1ad3 subs r3, r2, r3
+ 800293e: 2b02 cmp r3, #2
+ 8002940: d901 bls.n 8002946 <HAL_RCC_OscConfig+0x5e6>
{
return HAL_TIMEOUT;
- 8002932: 2303 movs r3, #3
- 8002934: e082 b.n 8002a3c <HAL_RCC_OscConfig+0x6ec>
+ 8002942: 2303 movs r3, #3
+ 8002944: e082 b.n 8002a4c <HAL_RCC_OscConfig+0x6ec>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U)
- 8002936: 4b26 ldr r3, [pc, #152] ; (80029d0 <HAL_RCC_OscConfig+0x680>)
- 8002938: 681a ldr r2, [r3, #0]
- 800293a: 2380 movs r3, #128 ; 0x80
- 800293c: 049b lsls r3, r3, #18
- 800293e: 4013 ands r3, r2
- 8002940: d1f0 bne.n 8002924 <HAL_RCC_OscConfig+0x5d4>
+ 8002946: 4b26 ldr r3, [pc, #152] ; (80029e0 <HAL_RCC_OscConfig+0x680>)
+ 8002948: 681a ldr r2, [r3, #0]
+ 800294a: 2380 movs r3, #128 ; 0x80
+ 800294c: 049b lsls r3, r3, #18
+ 800294e: 4013 ands r3, r2
+ 8002950: d1f0 bne.n 8002934 <HAL_RCC_OscConfig+0x5d4>
}
}
/* Configure the main PLL clock source, multiplication and division factors. */
__HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
- 8002942: 4b23 ldr r3, [pc, #140] ; (80029d0 <HAL_RCC_OscConfig+0x680>)
- 8002944: 68db ldr r3, [r3, #12]
- 8002946: 4a2a ldr r2, [pc, #168] ; (80029f0 <HAL_RCC_OscConfig+0x6a0>)
- 8002948: 4013 ands r3, r2
- 800294a: 0019 movs r1, r3
- 800294c: 687b ldr r3, [r7, #4]
- 800294e: 6a9a ldr r2, [r3, #40] ; 0x28
- 8002950: 687b ldr r3, [r7, #4]
- 8002952: 6adb ldr r3, [r3, #44] ; 0x2c
- 8002954: 431a orrs r2, r3
- 8002956: 687b ldr r3, [r7, #4]
- 8002958: 6b1b ldr r3, [r3, #48] ; 0x30
- 800295a: 431a orrs r2, r3
- 800295c: 4b1c ldr r3, [pc, #112] ; (80029d0 <HAL_RCC_OscConfig+0x680>)
- 800295e: 430a orrs r2, r1
- 8002960: 60da str r2, [r3, #12]
+ 8002952: 4b23 ldr r3, [pc, #140] ; (80029e0 <HAL_RCC_OscConfig+0x680>)
+ 8002954: 68db ldr r3, [r3, #12]
+ 8002956: 4a2a ldr r2, [pc, #168] ; (8002a00 <HAL_RCC_OscConfig+0x6a0>)
+ 8002958: 4013 ands r3, r2
+ 800295a: 0019 movs r1, r3
+ 800295c: 687b ldr r3, [r7, #4]
+ 800295e: 6a9a ldr r2, [r3, #40] ; 0x28
+ 8002960: 687b ldr r3, [r7, #4]
+ 8002962: 6adb ldr r3, [r3, #44] ; 0x2c
+ 8002964: 431a orrs r2, r3
+ 8002966: 687b ldr r3, [r7, #4]
+ 8002968: 6b1b ldr r3, [r3, #48] ; 0x30
+ 800296a: 431a orrs r2, r3
+ 800296c: 4b1c ldr r3, [pc, #112] ; (80029e0 <HAL_RCC_OscConfig+0x680>)
+ 800296e: 430a orrs r2, r1
+ 8002970: 60da str r2, [r3, #12]
RCC_OscInitStruct->PLL.PLLMUL,
RCC_OscInitStruct->PLL.PLLDIV);
/* Enable the main PLL. */
__HAL_RCC_PLL_ENABLE();
- 8002962: 4b1b ldr r3, [pc, #108] ; (80029d0 <HAL_RCC_OscConfig+0x680>)
- 8002964: 681a ldr r2, [r3, #0]
- 8002966: 4b1a ldr r3, [pc, #104] ; (80029d0 <HAL_RCC_OscConfig+0x680>)
- 8002968: 2180 movs r1, #128 ; 0x80
- 800296a: 0449 lsls r1, r1, #17
- 800296c: 430a orrs r2, r1
- 800296e: 601a str r2, [r3, #0]
+ 8002972: 4b1b ldr r3, [pc, #108] ; (80029e0 <HAL_RCC_OscConfig+0x680>)
+ 8002974: 681a ldr r2, [r3, #0]
+ 8002976: 4b1a ldr r3, [pc, #104] ; (80029e0 <HAL_RCC_OscConfig+0x680>)
+ 8002978: 2180 movs r1, #128 ; 0x80
+ 800297a: 0449 lsls r1, r1, #17
+ 800297c: 430a orrs r2, r1
+ 800297e: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
- 8002970: f7fe fbd2 bl 8001118 <HAL_GetTick>
- 8002974: 0003 movs r3, r0
- 8002976: 617b str r3, [r7, #20]
+ 8002980: f7fe fbd2 bl 8001128 <HAL_GetTick>
+ 8002984: 0003 movs r3, r0
+ 8002986: 617b str r3, [r7, #20]
/* Wait till PLL is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U)
- 8002978: e008 b.n 800298c <HAL_RCC_OscConfig+0x63c>
+ 8002988: e008 b.n 800299c <HAL_RCC_OscConfig+0x63c>
{
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
- 800297a: f7fe fbcd bl 8001118 <HAL_GetTick>
- 800297e: 0002 movs r2, r0
- 8002980: 697b ldr r3, [r7, #20]
- 8002982: 1ad3 subs r3, r2, r3
- 8002984: 2b02 cmp r3, #2
- 8002986: d901 bls.n 800298c <HAL_RCC_OscConfig+0x63c>
+ 800298a: f7fe fbcd bl 8001128 <HAL_GetTick>
+ 800298e: 0002 movs r2, r0
+ 8002990: 697b ldr r3, [r7, #20]
+ 8002992: 1ad3 subs r3, r2, r3
+ 8002994: 2b02 cmp r3, #2
+ 8002996: d901 bls.n 800299c <HAL_RCC_OscConfig+0x63c>
{
return HAL_TIMEOUT;
- 8002988: 2303 movs r3, #3
- 800298a: e057 b.n 8002a3c <HAL_RCC_OscConfig+0x6ec>
+ 8002998: 2303 movs r3, #3
+ 800299a: e057 b.n 8002a4c <HAL_RCC_OscConfig+0x6ec>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U)
- 800298c: 4b10 ldr r3, [pc, #64] ; (80029d0 <HAL_RCC_OscConfig+0x680>)
- 800298e: 681a ldr r2, [r3, #0]
- 8002990: 2380 movs r3, #128 ; 0x80
- 8002992: 049b lsls r3, r3, #18
- 8002994: 4013 ands r3, r2
- 8002996: d0f0 beq.n 800297a <HAL_RCC_OscConfig+0x62a>
- 8002998: e04f b.n 8002a3a <HAL_RCC_OscConfig+0x6ea>
+ 800299c: 4b10 ldr r3, [pc, #64] ; (80029e0 <HAL_RCC_OscConfig+0x680>)
+ 800299e: 681a ldr r2, [r3, #0]
+ 80029a0: 2380 movs r3, #128 ; 0x80
+ 80029a2: 049b lsls r3, r3, #18
+ 80029a4: 4013 ands r3, r2
+ 80029a6: d0f0 beq.n 800298a <HAL_RCC_OscConfig+0x62a>
+ 80029a8: e04f b.n 8002a4a <HAL_RCC_OscConfig+0x6ea>
}
}
else
{
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
- 800299a: 4b0d ldr r3, [pc, #52] ; (80029d0 <HAL_RCC_OscConfig+0x680>)
- 800299c: 681a ldr r2, [r3, #0]
- 800299e: 4b0c ldr r3, [pc, #48] ; (80029d0 <HAL_RCC_OscConfig+0x680>)
- 80029a0: 4912 ldr r1, [pc, #72] ; (80029ec <HAL_RCC_OscConfig+0x69c>)
- 80029a2: 400a ands r2, r1
- 80029a4: 601a str r2, [r3, #0]
+ 80029aa: 4b0d ldr r3, [pc, #52] ; (80029e0 <HAL_RCC_OscConfig+0x680>)
+ 80029ac: 681a ldr r2, [r3, #0]
+ 80029ae: 4b0c ldr r3, [pc, #48] ; (80029e0 <HAL_RCC_OscConfig+0x680>)
+ 80029b0: 4912 ldr r1, [pc, #72] ; (80029fc <HAL_RCC_OscConfig+0x69c>)
+ 80029b2: 400a ands r2, r1
+ 80029b4: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
- 80029a6: f7fe fbb7 bl 8001118 <HAL_GetTick>
- 80029aa: 0003 movs r3, r0
- 80029ac: 617b str r3, [r7, #20]
+ 80029b6: f7fe fbb7 bl 8001128 <HAL_GetTick>
+ 80029ba: 0003 movs r3, r0
+ 80029bc: 617b str r3, [r7, #20]
/* Wait till PLL is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U)
- 80029ae: e008 b.n 80029c2 <HAL_RCC_OscConfig+0x672>
+ 80029be: e008 b.n 80029d2 <HAL_RCC_OscConfig+0x672>
{
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
- 80029b0: f7fe fbb2 bl 8001118 <HAL_GetTick>
- 80029b4: 0002 movs r2, r0
- 80029b6: 697b ldr r3, [r7, #20]
- 80029b8: 1ad3 subs r3, r2, r3
- 80029ba: 2b02 cmp r3, #2
- 80029bc: d901 bls.n 80029c2 <HAL_RCC_OscConfig+0x672>
+ 80029c0: f7fe fbb2 bl 8001128 <HAL_GetTick>
+ 80029c4: 0002 movs r2, r0
+ 80029c6: 697b ldr r3, [r7, #20]
+ 80029c8: 1ad3 subs r3, r2, r3
+ 80029ca: 2b02 cmp r3, #2
+ 80029cc: d901 bls.n 80029d2 <HAL_RCC_OscConfig+0x672>
{
return HAL_TIMEOUT;
- 80029be: 2303 movs r3, #3
- 80029c0: e03c b.n 8002a3c <HAL_RCC_OscConfig+0x6ec>
+ 80029ce: 2303 movs r3, #3
+ 80029d0: e03c b.n 8002a4c <HAL_RCC_OscConfig+0x6ec>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U)
- 80029c2: 4b03 ldr r3, [pc, #12] ; (80029d0 <HAL_RCC_OscConfig+0x680>)
- 80029c4: 681a ldr r2, [r3, #0]
- 80029c6: 2380 movs r3, #128 ; 0x80
- 80029c8: 049b lsls r3, r3, #18
- 80029ca: 4013 ands r3, r2
- 80029cc: d1f0 bne.n 80029b0 <HAL_RCC_OscConfig+0x660>
- 80029ce: e034 b.n 8002a3a <HAL_RCC_OscConfig+0x6ea>
- 80029d0: 40021000 .word 0x40021000
- 80029d4: ffff1fff .word 0xffff1fff
- 80029d8: fffffeff .word 0xfffffeff
- 80029dc: 40007000 .word 0x40007000
- 80029e0: fffffbff .word 0xfffffbff
- 80029e4: 00001388 .word 0x00001388
- 80029e8: efffffff .word 0xefffffff
- 80029ec: feffffff .word 0xfeffffff
- 80029f0: ff02ffff .word 0xff02ffff
+ 80029d2: 4b03 ldr r3, [pc, #12] ; (80029e0 <HAL_RCC_OscConfig+0x680>)
+ 80029d4: 681a ldr r2, [r3, #0]
+ 80029d6: 2380 movs r3, #128 ; 0x80
+ 80029d8: 049b lsls r3, r3, #18
+ 80029da: 4013 ands r3, r2
+ 80029dc: d1f0 bne.n 80029c0 <HAL_RCC_OscConfig+0x660>
+ 80029de: e034 b.n 8002a4a <HAL_RCC_OscConfig+0x6ea>
+ 80029e0: 40021000 .word 0x40021000
+ 80029e4: ffff1fff .word 0xffff1fff
+ 80029e8: fffffeff .word 0xfffffeff
+ 80029ec: 40007000 .word 0x40007000
+ 80029f0: fffffbff .word 0xfffffbff
+ 80029f4: 00001388 .word 0x00001388
+ 80029f8: efffffff .word 0xefffffff
+ 80029fc: feffffff .word 0xfeffffff
+ 8002a00: ff02ffff .word 0xff02ffff
}
}
else
{
/* Check if there is a request to disable the PLL used as System clock source */
if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
- 80029f4: 687b ldr r3, [r7, #4]
- 80029f6: 6a5b ldr r3, [r3, #36] ; 0x24
- 80029f8: 2b01 cmp r3, #1
- 80029fa: d101 bne.n 8002a00 <HAL_RCC_OscConfig+0x6b0>
+ 8002a04: 687b ldr r3, [r7, #4]
+ 8002a06: 6a5b ldr r3, [r3, #36] ; 0x24
+ 8002a08: 2b01 cmp r3, #1
+ 8002a0a: d101 bne.n 8002a10 <HAL_RCC_OscConfig+0x6b0>
{
return HAL_ERROR;
- 80029fc: 2301 movs r3, #1
- 80029fe: e01d b.n 8002a3c <HAL_RCC_OscConfig+0x6ec>
+ 8002a0c: 2301 movs r3, #1
+ 8002a0e: e01d b.n 8002a4c <HAL_RCC_OscConfig+0x6ec>
}
else
{
/* Do not return HAL_ERROR if request repeats the current configuration */
pll_config = RCC->CFGR;
- 8002a00: 4b10 ldr r3, [pc, #64] ; (8002a44 <HAL_RCC_OscConfig+0x6f4>)
- 8002a02: 68db ldr r3, [r3, #12]
- 8002a04: 61bb str r3, [r7, #24]
+ 8002a10: 4b10 ldr r3, [pc, #64] ; (8002a54 <HAL_RCC_OscConfig+0x6f4>)
+ 8002a12: 68db ldr r3, [r3, #12]
+ 8002a14: 61bb str r3, [r7, #24]
if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
- 8002a06: 69ba ldr r2, [r7, #24]
- 8002a08: 2380 movs r3, #128 ; 0x80
- 8002a0a: 025b lsls r3, r3, #9
- 8002a0c: 401a ands r2, r3
- 8002a0e: 687b ldr r3, [r7, #4]
- 8002a10: 6a9b ldr r3, [r3, #40] ; 0x28
- 8002a12: 429a cmp r2, r3
- 8002a14: d10f bne.n 8002a36 <HAL_RCC_OscConfig+0x6e6>
- (READ_BIT(pll_config, RCC_CFGR_PLLMUL) != RCC_OscInitStruct->PLL.PLLMUL) ||
8002a16: 69ba ldr r2, [r7, #24]
- 8002a18: 23f0 movs r3, #240 ; 0xf0
- 8002a1a: 039b lsls r3, r3, #14
+ 8002a18: 2380 movs r3, #128 ; 0x80
+ 8002a1a: 025b lsls r3, r3, #9
8002a1c: 401a ands r2, r3
8002a1e: 687b ldr r3, [r7, #4]
- 8002a20: 6adb ldr r3, [r3, #44] ; 0x2c
- if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
+ 8002a20: 6a9b ldr r3, [r3, #40] ; 0x28
8002a22: 429a cmp r2, r3
- 8002a24: d107 bne.n 8002a36 <HAL_RCC_OscConfig+0x6e6>
- (READ_BIT(pll_config, RCC_CFGR_PLLDIV) != RCC_OscInitStruct->PLL.PLLDIV))
+ 8002a24: d10f bne.n 8002a46 <HAL_RCC_OscConfig+0x6e6>
+ (READ_BIT(pll_config, RCC_CFGR_PLLMUL) != RCC_OscInitStruct->PLL.PLLMUL) ||
8002a26: 69ba ldr r2, [r7, #24]
- 8002a28: 23c0 movs r3, #192 ; 0xc0
- 8002a2a: 041b lsls r3, r3, #16
+ 8002a28: 23f0 movs r3, #240 ; 0xf0
+ 8002a2a: 039b lsls r3, r3, #14
8002a2c: 401a ands r2, r3
8002a2e: 687b ldr r3, [r7, #4]
- 8002a30: 6b1b ldr r3, [r3, #48] ; 0x30
- (READ_BIT(pll_config, RCC_CFGR_PLLMUL) != RCC_OscInitStruct->PLL.PLLMUL) ||
+ 8002a30: 6adb ldr r3, [r3, #44] ; 0x2c
+ if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
8002a32: 429a cmp r2, r3
- 8002a34: d001 beq.n 8002a3a <HAL_RCC_OscConfig+0x6ea>
+ 8002a34: d107 bne.n 8002a46 <HAL_RCC_OscConfig+0x6e6>
+ (READ_BIT(pll_config, RCC_CFGR_PLLDIV) != RCC_OscInitStruct->PLL.PLLDIV))
+ 8002a36: 69ba ldr r2, [r7, #24]
+ 8002a38: 23c0 movs r3, #192 ; 0xc0
+ 8002a3a: 041b lsls r3, r3, #16
+ 8002a3c: 401a ands r2, r3
+ 8002a3e: 687b ldr r3, [r7, #4]
+ 8002a40: 6b1b ldr r3, [r3, #48] ; 0x30
+ (READ_BIT(pll_config, RCC_CFGR_PLLMUL) != RCC_OscInitStruct->PLL.PLLMUL) ||
+ 8002a42: 429a cmp r2, r3
+ 8002a44: d001 beq.n 8002a4a <HAL_RCC_OscConfig+0x6ea>
{
return HAL_ERROR;
- 8002a36: 2301 movs r3, #1
- 8002a38: e000 b.n 8002a3c <HAL_RCC_OscConfig+0x6ec>
+ 8002a46: 2301 movs r3, #1
+ 8002a48: e000 b.n 8002a4c <HAL_RCC_OscConfig+0x6ec>
}
}
}
}
return HAL_OK;
- 8002a3a: 2300 movs r3, #0
+ 8002a4a: 2300 movs r3, #0
}
- 8002a3c: 0018 movs r0, r3
- 8002a3e: 46bd mov sp, r7
- 8002a40: b00a add sp, #40 ; 0x28
- 8002a42: bdb0 pop {r4, r5, r7, pc}
- 8002a44: 40021000 .word 0x40021000
+ 8002a4c: 0018 movs r0, r3
+ 8002a4e: 46bd mov sp, r7
+ 8002a50: b00a add sp, #40 ; 0x28
+ 8002a52: bdb0 pop {r4, r5, r7, pc}
+ 8002a54: 40021000 .word 0x40021000
-08002a48 <HAL_RCC_ClockConfig>:
+08002a58 <HAL_RCC_ClockConfig>:
* HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
* (for more details refer to section above "Initialization/de-initialization functions")
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
{
- 8002a48: b5b0 push {r4, r5, r7, lr}
- 8002a4a: b084 sub sp, #16
- 8002a4c: af00 add r7, sp, #0
- 8002a4e: 6078 str r0, [r7, #4]
- 8002a50: 6039 str r1, [r7, #0]
+ 8002a58: b5b0 push {r4, r5, r7, lr}
+ 8002a5a: b084 sub sp, #16
+ 8002a5c: af00 add r7, sp, #0
+ 8002a5e: 6078 str r0, [r7, #4]
+ 8002a60: 6039 str r1, [r7, #0]
uint32_t tickstart;
HAL_StatusTypeDef status;
/* Check Null pointer */
if(RCC_ClkInitStruct == NULL)
- 8002a52: 687b ldr r3, [r7, #4]
- 8002a54: 2b00 cmp r3, #0
- 8002a56: d101 bne.n 8002a5c <HAL_RCC_ClockConfig+0x14>
+ 8002a62: 687b ldr r3, [r7, #4]
+ 8002a64: 2b00 cmp r3, #0
+ 8002a66: d101 bne.n 8002a6c <HAL_RCC_ClockConfig+0x14>
{
return HAL_ERROR;
- 8002a58: 2301 movs r3, #1
- 8002a5a: e128 b.n 8002cae <HAL_RCC_ClockConfig+0x266>
+ 8002a68: 2301 movs r3, #1
+ 8002a6a: e128 b.n 8002cbe <HAL_RCC_ClockConfig+0x266>
/* To correctly read data from FLASH memory, the number of wait states (LATENCY)
must be correctly programmed according to the frequency of the CPU clock
(HCLK) and the supply voltage of the device. */
/* Increasing the number of wait states because of higher CPU frequency */
if(FLatency > __HAL_FLASH_GET_LATENCY())
- 8002a5c: 4b96 ldr r3, [pc, #600] ; (8002cb8 <HAL_RCC_ClockConfig+0x270>)
- 8002a5e: 681b ldr r3, [r3, #0]
- 8002a60: 2201 movs r2, #1
- 8002a62: 4013 ands r3, r2
- 8002a64: 683a ldr r2, [r7, #0]
- 8002a66: 429a cmp r2, r3
- 8002a68: d91e bls.n 8002aa8 <HAL_RCC_ClockConfig+0x60>
+ 8002a6c: 4b96 ldr r3, [pc, #600] ; (8002cc8 <HAL_RCC_ClockConfig+0x270>)
+ 8002a6e: 681b ldr r3, [r3, #0]
+ 8002a70: 2201 movs r2, #1
+ 8002a72: 4013 ands r3, r2
+ 8002a74: 683a ldr r2, [r7, #0]
+ 8002a76: 429a cmp r2, r3
+ 8002a78: d91e bls.n 8002ab8 <HAL_RCC_ClockConfig+0x60>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
- 8002a6a: 4b93 ldr r3, [pc, #588] ; (8002cb8 <HAL_RCC_ClockConfig+0x270>)
- 8002a6c: 681b ldr r3, [r3, #0]
- 8002a6e: 2201 movs r2, #1
- 8002a70: 4393 bics r3, r2
- 8002a72: 0019 movs r1, r3
- 8002a74: 4b90 ldr r3, [pc, #576] ; (8002cb8 <HAL_RCC_ClockConfig+0x270>)
- 8002a76: 683a ldr r2, [r7, #0]
- 8002a78: 430a orrs r2, r1
- 8002a7a: 601a str r2, [r3, #0]
+ 8002a7a: 4b93 ldr r3, [pc, #588] ; (8002cc8 <HAL_RCC_ClockConfig+0x270>)
+ 8002a7c: 681b ldr r3, [r3, #0]
+ 8002a7e: 2201 movs r2, #1
+ 8002a80: 4393 bics r3, r2
+ 8002a82: 0019 movs r1, r3
+ 8002a84: 4b90 ldr r3, [pc, #576] ; (8002cc8 <HAL_RCC_ClockConfig+0x270>)
+ 8002a86: 683a ldr r2, [r7, #0]
+ 8002a88: 430a orrs r2, r1
+ 8002a8a: 601a str r2, [r3, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by polling the FLASH_ACR register */
tickstart = HAL_GetTick();
- 8002a7c: f7fe fb4c bl 8001118 <HAL_GetTick>
- 8002a80: 0003 movs r3, r0
- 8002a82: 60fb str r3, [r7, #12]
+ 8002a8c: f7fe fb4c bl 8001128 <HAL_GetTick>
+ 8002a90: 0003 movs r3, r0
+ 8002a92: 60fb str r3, [r7, #12]
while (__HAL_FLASH_GET_LATENCY() != FLatency)
- 8002a84: e009 b.n 8002a9a <HAL_RCC_ClockConfig+0x52>
+ 8002a94: e009 b.n 8002aaa <HAL_RCC_ClockConfig+0x52>
{
if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
- 8002a86: f7fe fb47 bl 8001118 <HAL_GetTick>
- 8002a8a: 0002 movs r2, r0
- 8002a8c: 68fb ldr r3, [r7, #12]
- 8002a8e: 1ad3 subs r3, r2, r3
- 8002a90: 4a8a ldr r2, [pc, #552] ; (8002cbc <HAL_RCC_ClockConfig+0x274>)
- 8002a92: 4293 cmp r3, r2
- 8002a94: d901 bls.n 8002a9a <HAL_RCC_ClockConfig+0x52>
+ 8002a96: f7fe fb47 bl 8001128 <HAL_GetTick>
+ 8002a9a: 0002 movs r2, r0
+ 8002a9c: 68fb ldr r3, [r7, #12]
+ 8002a9e: 1ad3 subs r3, r2, r3
+ 8002aa0: 4a8a ldr r2, [pc, #552] ; (8002ccc <HAL_RCC_ClockConfig+0x274>)
+ 8002aa2: 4293 cmp r3, r2
+ 8002aa4: d901 bls.n 8002aaa <HAL_RCC_ClockConfig+0x52>
{
return HAL_TIMEOUT;
- 8002a96: 2303 movs r3, #3
- 8002a98: e109 b.n 8002cae <HAL_RCC_ClockConfig+0x266>
+ 8002aa6: 2303 movs r3, #3
+ 8002aa8: e109 b.n 8002cbe <HAL_RCC_ClockConfig+0x266>
while (__HAL_FLASH_GET_LATENCY() != FLatency)
- 8002a9a: 4b87 ldr r3, [pc, #540] ; (8002cb8 <HAL_RCC_ClockConfig+0x270>)
- 8002a9c: 681b ldr r3, [r3, #0]
- 8002a9e: 2201 movs r2, #1
- 8002aa0: 4013 ands r3, r2
- 8002aa2: 683a ldr r2, [r7, #0]
- 8002aa4: 429a cmp r2, r3
- 8002aa6: d1ee bne.n 8002a86 <HAL_RCC_ClockConfig+0x3e>
+ 8002aaa: 4b87 ldr r3, [pc, #540] ; (8002cc8 <HAL_RCC_ClockConfig+0x270>)
+ 8002aac: 681b ldr r3, [r3, #0]
+ 8002aae: 2201 movs r2, #1
+ 8002ab0: 4013 ands r3, r2
+ 8002ab2: 683a ldr r2, [r7, #0]
+ 8002ab4: 429a cmp r2, r3
+ 8002ab6: d1ee bne.n 8002a96 <HAL_RCC_ClockConfig+0x3e>
}
}
}
/*-------------------------- HCLK Configuration --------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
- 8002aa8: 687b ldr r3, [r7, #4]
- 8002aaa: 681b ldr r3, [r3, #0]
- 8002aac: 2202 movs r2, #2
- 8002aae: 4013 ands r3, r2
- 8002ab0: d009 beq.n 8002ac6 <HAL_RCC_ClockConfig+0x7e>
+ 8002ab8: 687b ldr r3, [r7, #4]
+ 8002aba: 681b ldr r3, [r3, #0]
+ 8002abc: 2202 movs r2, #2
+ 8002abe: 4013 ands r3, r2
+ 8002ac0: d009 beq.n 8002ad6 <HAL_RCC_ClockConfig+0x7e>
{
assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
- 8002ab2: 4b83 ldr r3, [pc, #524] ; (8002cc0 <HAL_RCC_ClockConfig+0x278>)
- 8002ab4: 68db ldr r3, [r3, #12]
- 8002ab6: 22f0 movs r2, #240 ; 0xf0
- 8002ab8: 4393 bics r3, r2
- 8002aba: 0019 movs r1, r3
- 8002abc: 687b ldr r3, [r7, #4]
- 8002abe: 689a ldr r2, [r3, #8]
- 8002ac0: 4b7f ldr r3, [pc, #508] ; (8002cc0 <HAL_RCC_ClockConfig+0x278>)
- 8002ac2: 430a orrs r2, r1
- 8002ac4: 60da str r2, [r3, #12]
+ 8002ac2: 4b83 ldr r3, [pc, #524] ; (8002cd0 <HAL_RCC_ClockConfig+0x278>)
+ 8002ac4: 68db ldr r3, [r3, #12]
+ 8002ac6: 22f0 movs r2, #240 ; 0xf0
+ 8002ac8: 4393 bics r3, r2
+ 8002aca: 0019 movs r1, r3
+ 8002acc: 687b ldr r3, [r7, #4]
+ 8002ace: 689a ldr r2, [r3, #8]
+ 8002ad0: 4b7f ldr r3, [pc, #508] ; (8002cd0 <HAL_RCC_ClockConfig+0x278>)
+ 8002ad2: 430a orrs r2, r1
+ 8002ad4: 60da str r2, [r3, #12]
}
/*------------------------- SYSCLK Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
- 8002ac6: 687b ldr r3, [r7, #4]
- 8002ac8: 681b ldr r3, [r3, #0]
- 8002aca: 2201 movs r2, #1
- 8002acc: 4013 ands r3, r2
- 8002ace: d100 bne.n 8002ad2 <HAL_RCC_ClockConfig+0x8a>
- 8002ad0: e089 b.n 8002be6 <HAL_RCC_ClockConfig+0x19e>
+ 8002ad6: 687b ldr r3, [r7, #4]
+ 8002ad8: 681b ldr r3, [r3, #0]
+ 8002ada: 2201 movs r2, #1
+ 8002adc: 4013 ands r3, r2
+ 8002ade: d100 bne.n 8002ae2 <HAL_RCC_ClockConfig+0x8a>
+ 8002ae0: e089 b.n 8002bf6 <HAL_RCC_ClockConfig+0x19e>
{
assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
/* HSE is selected as System Clock Source */
if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
- 8002ad2: 687b ldr r3, [r7, #4]
- 8002ad4: 685b ldr r3, [r3, #4]
- 8002ad6: 2b02 cmp r3, #2
- 8002ad8: d107 bne.n 8002aea <HAL_RCC_ClockConfig+0xa2>
+ 8002ae2: 687b ldr r3, [r7, #4]
+ 8002ae4: 685b ldr r3, [r3, #4]
+ 8002ae6: 2b02 cmp r3, #2
+ 8002ae8: d107 bne.n 8002afa <HAL_RCC_ClockConfig+0xa2>
{
/* Check the HSE ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U)
- 8002ada: 4b79 ldr r3, [pc, #484] ; (8002cc0 <HAL_RCC_ClockConfig+0x278>)
- 8002adc: 681a ldr r2, [r3, #0]
- 8002ade: 2380 movs r3, #128 ; 0x80
- 8002ae0: 029b lsls r3, r3, #10
- 8002ae2: 4013 ands r3, r2
- 8002ae4: d120 bne.n 8002b28 <HAL_RCC_ClockConfig+0xe0>
+ 8002aea: 4b79 ldr r3, [pc, #484] ; (8002cd0 <HAL_RCC_ClockConfig+0x278>)
+ 8002aec: 681a ldr r2, [r3, #0]
+ 8002aee: 2380 movs r3, #128 ; 0x80
+ 8002af0: 029b lsls r3, r3, #10
+ 8002af2: 4013 ands r3, r2
+ 8002af4: d120 bne.n 8002b38 <HAL_RCC_ClockConfig+0xe0>
{
return HAL_ERROR;
- 8002ae6: 2301 movs r3, #1
- 8002ae8: e0e1 b.n 8002cae <HAL_RCC_ClockConfig+0x266>
+ 8002af6: 2301 movs r3, #1
+ 8002af8: e0e1 b.n 8002cbe <HAL_RCC_ClockConfig+0x266>
}
}
/* PLL is selected as System Clock Source */
else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
- 8002aea: 687b ldr r3, [r7, #4]
- 8002aec: 685b ldr r3, [r3, #4]
- 8002aee: 2b03 cmp r3, #3
- 8002af0: d107 bne.n 8002b02 <HAL_RCC_ClockConfig+0xba>
+ 8002afa: 687b ldr r3, [r7, #4]
+ 8002afc: 685b ldr r3, [r3, #4]
+ 8002afe: 2b03 cmp r3, #3
+ 8002b00: d107 bne.n 8002b12 <HAL_RCC_ClockConfig+0xba>
{
/* Check the PLL ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U)
- 8002af2: 4b73 ldr r3, [pc, #460] ; (8002cc0 <HAL_RCC_ClockConfig+0x278>)
- 8002af4: 681a ldr r2, [r3, #0]
- 8002af6: 2380 movs r3, #128 ; 0x80
- 8002af8: 049b lsls r3, r3, #18
- 8002afa: 4013 ands r3, r2
- 8002afc: d114 bne.n 8002b28 <HAL_RCC_ClockConfig+0xe0>
+ 8002b02: 4b73 ldr r3, [pc, #460] ; (8002cd0 <HAL_RCC_ClockConfig+0x278>)
+ 8002b04: 681a ldr r2, [r3, #0]
+ 8002b06: 2380 movs r3, #128 ; 0x80
+ 8002b08: 049b lsls r3, r3, #18
+ 8002b0a: 4013 ands r3, r2
+ 8002b0c: d114 bne.n 8002b38 <HAL_RCC_ClockConfig+0xe0>
{
return HAL_ERROR;
- 8002afe: 2301 movs r3, #1
- 8002b00: e0d5 b.n 8002cae <HAL_RCC_ClockConfig+0x266>
+ 8002b0e: 2301 movs r3, #1
+ 8002b10: e0d5 b.n 8002cbe <HAL_RCC_ClockConfig+0x266>
}
}
/* HSI is selected as System Clock Source */
else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI)
- 8002b02: 687b ldr r3, [r7, #4]
- 8002b04: 685b ldr r3, [r3, #4]
- 8002b06: 2b01 cmp r3, #1
- 8002b08: d106 bne.n 8002b18 <HAL_RCC_ClockConfig+0xd0>
+ 8002b12: 687b ldr r3, [r7, #4]
+ 8002b14: 685b ldr r3, [r3, #4]
+ 8002b16: 2b01 cmp r3, #1
+ 8002b18: d106 bne.n 8002b28 <HAL_RCC_ClockConfig+0xd0>
{
/* Check the HSI ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U)
- 8002b0a: 4b6d ldr r3, [pc, #436] ; (8002cc0 <HAL_RCC_ClockConfig+0x278>)
- 8002b0c: 681b ldr r3, [r3, #0]
- 8002b0e: 2204 movs r2, #4
- 8002b10: 4013 ands r3, r2
- 8002b12: d109 bne.n 8002b28 <HAL_RCC_ClockConfig+0xe0>
+ 8002b1a: 4b6d ldr r3, [pc, #436] ; (8002cd0 <HAL_RCC_ClockConfig+0x278>)
+ 8002b1c: 681b ldr r3, [r3, #0]
+ 8002b1e: 2204 movs r2, #4
+ 8002b20: 4013 ands r3, r2
+ 8002b22: d109 bne.n 8002b38 <HAL_RCC_ClockConfig+0xe0>
{
return HAL_ERROR;
- 8002b14: 2301 movs r3, #1
- 8002b16: e0ca b.n 8002cae <HAL_RCC_ClockConfig+0x266>
+ 8002b24: 2301 movs r3, #1
+ 8002b26: e0ca b.n 8002cbe <HAL_RCC_ClockConfig+0x266>
}
/* MSI is selected as System Clock Source */
else
{
/* Check the MSI ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) == 0U)
- 8002b18: 4b69 ldr r3, [pc, #420] ; (8002cc0 <HAL_RCC_ClockConfig+0x278>)
- 8002b1a: 681a ldr r2, [r3, #0]
- 8002b1c: 2380 movs r3, #128 ; 0x80
- 8002b1e: 009b lsls r3, r3, #2
- 8002b20: 4013 ands r3, r2
- 8002b22: d101 bne.n 8002b28 <HAL_RCC_ClockConfig+0xe0>
+ 8002b28: 4b69 ldr r3, [pc, #420] ; (8002cd0 <HAL_RCC_ClockConfig+0x278>)
+ 8002b2a: 681a ldr r2, [r3, #0]
+ 8002b2c: 2380 movs r3, #128 ; 0x80
+ 8002b2e: 009b lsls r3, r3, #2
+ 8002b30: 4013 ands r3, r2
+ 8002b32: d101 bne.n 8002b38 <HAL_RCC_ClockConfig+0xe0>
{
return HAL_ERROR;
- 8002b24: 2301 movs r3, #1
- 8002b26: e0c2 b.n 8002cae <HAL_RCC_ClockConfig+0x266>
+ 8002b34: 2301 movs r3, #1
+ 8002b36: e0c2 b.n 8002cbe <HAL_RCC_ClockConfig+0x266>
}
}
__HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
- 8002b28: 4b65 ldr r3, [pc, #404] ; (8002cc0 <HAL_RCC_ClockConfig+0x278>)
- 8002b2a: 68db ldr r3, [r3, #12]
- 8002b2c: 2203 movs r2, #3
- 8002b2e: 4393 bics r3, r2
- 8002b30: 0019 movs r1, r3
- 8002b32: 687b ldr r3, [r7, #4]
- 8002b34: 685a ldr r2, [r3, #4]
- 8002b36: 4b62 ldr r3, [pc, #392] ; (8002cc0 <HAL_RCC_ClockConfig+0x278>)
- 8002b38: 430a orrs r2, r1
- 8002b3a: 60da str r2, [r3, #12]
+ 8002b38: 4b65 ldr r3, [pc, #404] ; (8002cd0 <HAL_RCC_ClockConfig+0x278>)
+ 8002b3a: 68db ldr r3, [r3, #12]
+ 8002b3c: 2203 movs r2, #3
+ 8002b3e: 4393 bics r3, r2
+ 8002b40: 0019 movs r1, r3
+ 8002b42: 687b ldr r3, [r7, #4]
+ 8002b44: 685a ldr r2, [r3, #4]
+ 8002b46: 4b62 ldr r3, [pc, #392] ; (8002cd0 <HAL_RCC_ClockConfig+0x278>)
+ 8002b48: 430a orrs r2, r1
+ 8002b4a: 60da str r2, [r3, #12]
/* Get Start Tick */
tickstart = HAL_GetTick();
- 8002b3c: f7fe faec bl 8001118 <HAL_GetTick>
- 8002b40: 0003 movs r3, r0
- 8002b42: 60fb str r3, [r7, #12]
+ 8002b4c: f7fe faec bl 8001128 <HAL_GetTick>
+ 8002b50: 0003 movs r3, r0
+ 8002b52: 60fb str r3, [r7, #12]
if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
- 8002b44: 687b ldr r3, [r7, #4]
- 8002b46: 685b ldr r3, [r3, #4]
- 8002b48: 2b02 cmp r3, #2
- 8002b4a: d111 bne.n 8002b70 <HAL_RCC_ClockConfig+0x128>
+ 8002b54: 687b ldr r3, [r7, #4]
+ 8002b56: 685b ldr r3, [r3, #4]
+ 8002b58: 2b02 cmp r3, #2
+ 8002b5a: d111 bne.n 8002b80 <HAL_RCC_ClockConfig+0x128>
{
while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)
- 8002b4c: e009 b.n 8002b62 <HAL_RCC_ClockConfig+0x11a>
+ 8002b5c: e009 b.n 8002b72 <HAL_RCC_ClockConfig+0x11a>
{
if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
- 8002b4e: f7fe fae3 bl 8001118 <HAL_GetTick>
- 8002b52: 0002 movs r2, r0
- 8002b54: 68fb ldr r3, [r7, #12]
- 8002b56: 1ad3 subs r3, r2, r3
- 8002b58: 4a58 ldr r2, [pc, #352] ; (8002cbc <HAL_RCC_ClockConfig+0x274>)
- 8002b5a: 4293 cmp r3, r2
- 8002b5c: d901 bls.n 8002b62 <HAL_RCC_ClockConfig+0x11a>
+ 8002b5e: f7fe fae3 bl 8001128 <HAL_GetTick>
+ 8002b62: 0002 movs r2, r0
+ 8002b64: 68fb ldr r3, [r7, #12]
+ 8002b66: 1ad3 subs r3, r2, r3
+ 8002b68: 4a58 ldr r2, [pc, #352] ; (8002ccc <HAL_RCC_ClockConfig+0x274>)
+ 8002b6a: 4293 cmp r3, r2
+ 8002b6c: d901 bls.n 8002b72 <HAL_RCC_ClockConfig+0x11a>
{
return HAL_TIMEOUT;
- 8002b5e: 2303 movs r3, #3
- 8002b60: e0a5 b.n 8002cae <HAL_RCC_ClockConfig+0x266>
+ 8002b6e: 2303 movs r3, #3
+ 8002b70: e0a5 b.n 8002cbe <HAL_RCC_ClockConfig+0x266>
while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)
- 8002b62: 4b57 ldr r3, [pc, #348] ; (8002cc0 <HAL_RCC_ClockConfig+0x278>)
- 8002b64: 68db ldr r3, [r3, #12]
- 8002b66: 220c movs r2, #12
- 8002b68: 4013 ands r3, r2
- 8002b6a: 2b08 cmp r3, #8
- 8002b6c: d1ef bne.n 8002b4e <HAL_RCC_ClockConfig+0x106>
- 8002b6e: e03a b.n 8002be6 <HAL_RCC_ClockConfig+0x19e>
+ 8002b72: 4b57 ldr r3, [pc, #348] ; (8002cd0 <HAL_RCC_ClockConfig+0x278>)
+ 8002b74: 68db ldr r3, [r3, #12]
+ 8002b76: 220c movs r2, #12
+ 8002b78: 4013 ands r3, r2
+ 8002b7a: 2b08 cmp r3, #8
+ 8002b7c: d1ef bne.n 8002b5e <HAL_RCC_ClockConfig+0x106>
+ 8002b7e: e03a b.n 8002bf6 <HAL_RCC_ClockConfig+0x19e>
}
}
}
else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
- 8002b70: 687b ldr r3, [r7, #4]
- 8002b72: 685b ldr r3, [r3, #4]
- 8002b74: 2b03 cmp r3, #3
- 8002b76: d111 bne.n 8002b9c <HAL_RCC_ClockConfig+0x154>
+ 8002b80: 687b ldr r3, [r7, #4]
+ 8002b82: 685b ldr r3, [r3, #4]
+ 8002b84: 2b03 cmp r3, #3
+ 8002b86: d111 bne.n 8002bac <HAL_RCC_ClockConfig+0x154>
{
while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
- 8002b78: e009 b.n 8002b8e <HAL_RCC_ClockConfig+0x146>
+ 8002b88: e009 b.n 8002b9e <HAL_RCC_ClockConfig+0x146>
{
if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
- 8002b7a: f7fe facd bl 8001118 <HAL_GetTick>
- 8002b7e: 0002 movs r2, r0
- 8002b80: 68fb ldr r3, [r7, #12]
- 8002b82: 1ad3 subs r3, r2, r3
- 8002b84: 4a4d ldr r2, [pc, #308] ; (8002cbc <HAL_RCC_ClockConfig+0x274>)
- 8002b86: 4293 cmp r3, r2
- 8002b88: d901 bls.n 8002b8e <HAL_RCC_ClockConfig+0x146>
+ 8002b8a: f7fe facd bl 8001128 <HAL_GetTick>
+ 8002b8e: 0002 movs r2, r0
+ 8002b90: 68fb ldr r3, [r7, #12]
+ 8002b92: 1ad3 subs r3, r2, r3
+ 8002b94: 4a4d ldr r2, [pc, #308] ; (8002ccc <HAL_RCC_ClockConfig+0x274>)
+ 8002b96: 4293 cmp r3, r2
+ 8002b98: d901 bls.n 8002b9e <HAL_RCC_ClockConfig+0x146>
{
return HAL_TIMEOUT;
- 8002b8a: 2303 movs r3, #3
- 8002b8c: e08f b.n 8002cae <HAL_RCC_ClockConfig+0x266>
+ 8002b9a: 2303 movs r3, #3
+ 8002b9c: e08f b.n 8002cbe <HAL_RCC_ClockConfig+0x266>
while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
- 8002b8e: 4b4c ldr r3, [pc, #304] ; (8002cc0 <HAL_RCC_ClockConfig+0x278>)
- 8002b90: 68db ldr r3, [r3, #12]
- 8002b92: 220c movs r2, #12
- 8002b94: 4013 ands r3, r2
- 8002b96: 2b0c cmp r3, #12
- 8002b98: d1ef bne.n 8002b7a <HAL_RCC_ClockConfig+0x132>
- 8002b9a: e024 b.n 8002be6 <HAL_RCC_ClockConfig+0x19e>
+ 8002b9e: 4b4c ldr r3, [pc, #304] ; (8002cd0 <HAL_RCC_ClockConfig+0x278>)
+ 8002ba0: 68db ldr r3, [r3, #12]
+ 8002ba2: 220c movs r2, #12
+ 8002ba4: 4013 ands r3, r2
+ 8002ba6: 2b0c cmp r3, #12
+ 8002ba8: d1ef bne.n 8002b8a <HAL_RCC_ClockConfig+0x132>
+ 8002baa: e024 b.n 8002bf6 <HAL_RCC_ClockConfig+0x19e>
}
}
}
else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI)
- 8002b9c: 687b ldr r3, [r7, #4]
- 8002b9e: 685b ldr r3, [r3, #4]
- 8002ba0: 2b01 cmp r3, #1
- 8002ba2: d11b bne.n 8002bdc <HAL_RCC_ClockConfig+0x194>
+ 8002bac: 687b ldr r3, [r7, #4]
+ 8002bae: 685b ldr r3, [r3, #4]
+ 8002bb0: 2b01 cmp r3, #1
+ 8002bb2: d11b bne.n 8002bec <HAL_RCC_ClockConfig+0x194>
{
while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)
- 8002ba4: e009 b.n 8002bba <HAL_RCC_ClockConfig+0x172>
+ 8002bb4: e009 b.n 8002bca <HAL_RCC_ClockConfig+0x172>
{
if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
- 8002ba6: f7fe fab7 bl 8001118 <HAL_GetTick>
- 8002baa: 0002 movs r2, r0
- 8002bac: 68fb ldr r3, [r7, #12]
- 8002bae: 1ad3 subs r3, r2, r3
- 8002bb0: 4a42 ldr r2, [pc, #264] ; (8002cbc <HAL_RCC_ClockConfig+0x274>)
- 8002bb2: 4293 cmp r3, r2
- 8002bb4: d901 bls.n 8002bba <HAL_RCC_ClockConfig+0x172>
+ 8002bb6: f7fe fab7 bl 8001128 <HAL_GetTick>
+ 8002bba: 0002 movs r2, r0
+ 8002bbc: 68fb ldr r3, [r7, #12]
+ 8002bbe: 1ad3 subs r3, r2, r3
+ 8002bc0: 4a42 ldr r2, [pc, #264] ; (8002ccc <HAL_RCC_ClockConfig+0x274>)
+ 8002bc2: 4293 cmp r3, r2
+ 8002bc4: d901 bls.n 8002bca <HAL_RCC_ClockConfig+0x172>
{
return HAL_TIMEOUT;
- 8002bb6: 2303 movs r3, #3
- 8002bb8: e079 b.n 8002cae <HAL_RCC_ClockConfig+0x266>
+ 8002bc6: 2303 movs r3, #3
+ 8002bc8: e079 b.n 8002cbe <HAL_RCC_ClockConfig+0x266>
while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)
- 8002bba: 4b41 ldr r3, [pc, #260] ; (8002cc0 <HAL_RCC_ClockConfig+0x278>)
- 8002bbc: 68db ldr r3, [r3, #12]
- 8002bbe: 220c movs r2, #12
- 8002bc0: 4013 ands r3, r2
- 8002bc2: 2b04 cmp r3, #4
- 8002bc4: d1ef bne.n 8002ba6 <HAL_RCC_ClockConfig+0x15e>
- 8002bc6: e00e b.n 8002be6 <HAL_RCC_ClockConfig+0x19e>
+ 8002bca: 4b41 ldr r3, [pc, #260] ; (8002cd0 <HAL_RCC_ClockConfig+0x278>)
+ 8002bcc: 68db ldr r3, [r3, #12]
+ 8002bce: 220c movs r2, #12
+ 8002bd0: 4013 ands r3, r2
+ 8002bd2: 2b04 cmp r3, #4
+ 8002bd4: d1ef bne.n 8002bb6 <HAL_RCC_ClockConfig+0x15e>
+ 8002bd6: e00e b.n 8002bf6 <HAL_RCC_ClockConfig+0x19e>
}
else
{
while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_MSI)
{
if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
- 8002bc8: f7fe faa6 bl 8001118 <HAL_GetTick>
- 8002bcc: 0002 movs r2, r0
- 8002bce: 68fb ldr r3, [r7, #12]
- 8002bd0: 1ad3 subs r3, r2, r3
- 8002bd2: 4a3a ldr r2, [pc, #232] ; (8002cbc <HAL_RCC_ClockConfig+0x274>)
- 8002bd4: 4293 cmp r3, r2
- 8002bd6: d901 bls.n 8002bdc <HAL_RCC_ClockConfig+0x194>
+ 8002bd8: f7fe faa6 bl 8001128 <HAL_GetTick>
+ 8002bdc: 0002 movs r2, r0
+ 8002bde: 68fb ldr r3, [r7, #12]
+ 8002be0: 1ad3 subs r3, r2, r3
+ 8002be2: 4a3a ldr r2, [pc, #232] ; (8002ccc <HAL_RCC_ClockConfig+0x274>)
+ 8002be4: 4293 cmp r3, r2
+ 8002be6: d901 bls.n 8002bec <HAL_RCC_ClockConfig+0x194>
{
return HAL_TIMEOUT;
- 8002bd8: 2303 movs r3, #3
- 8002bda: e068 b.n 8002cae <HAL_RCC_ClockConfig+0x266>
+ 8002be8: 2303 movs r3, #3
+ 8002bea: e068 b.n 8002cbe <HAL_RCC_ClockConfig+0x266>
while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_MSI)
- 8002bdc: 4b38 ldr r3, [pc, #224] ; (8002cc0 <HAL_RCC_ClockConfig+0x278>)
- 8002bde: 68db ldr r3, [r3, #12]
- 8002be0: 220c movs r2, #12
- 8002be2: 4013 ands r3, r2
- 8002be4: d1f0 bne.n 8002bc8 <HAL_RCC_ClockConfig+0x180>
+ 8002bec: 4b38 ldr r3, [pc, #224] ; (8002cd0 <HAL_RCC_ClockConfig+0x278>)
+ 8002bee: 68db ldr r3, [r3, #12]
+ 8002bf0: 220c movs r2, #12
+ 8002bf2: 4013 ands r3, r2
+ 8002bf4: d1f0 bne.n 8002bd8 <HAL_RCC_ClockConfig+0x180>
}
}
}
}
/* Decreasing the number of wait states because of lower CPU frequency */
if(FLatency < __HAL_FLASH_GET_LATENCY())
- 8002be6: 4b34 ldr r3, [pc, #208] ; (8002cb8 <HAL_RCC_ClockConfig+0x270>)
- 8002be8: 681b ldr r3, [r3, #0]
- 8002bea: 2201 movs r2, #1
- 8002bec: 4013 ands r3, r2
- 8002bee: 683a ldr r2, [r7, #0]
- 8002bf0: 429a cmp r2, r3
- 8002bf2: d21e bcs.n 8002c32 <HAL_RCC_ClockConfig+0x1ea>
+ 8002bf6: 4b34 ldr r3, [pc, #208] ; (8002cc8 <HAL_RCC_ClockConfig+0x270>)
+ 8002bf8: 681b ldr r3, [r3, #0]
+ 8002bfa: 2201 movs r2, #1
+ 8002bfc: 4013 ands r3, r2
+ 8002bfe: 683a ldr r2, [r7, #0]
+ 8002c00: 429a cmp r2, r3
+ 8002c02: d21e bcs.n 8002c42 <HAL_RCC_ClockConfig+0x1ea>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
- 8002bf4: 4b30 ldr r3, [pc, #192] ; (8002cb8 <HAL_RCC_ClockConfig+0x270>)
- 8002bf6: 681b ldr r3, [r3, #0]
- 8002bf8: 2201 movs r2, #1
- 8002bfa: 4393 bics r3, r2
- 8002bfc: 0019 movs r1, r3
- 8002bfe: 4b2e ldr r3, [pc, #184] ; (8002cb8 <HAL_RCC_ClockConfig+0x270>)
- 8002c00: 683a ldr r2, [r7, #0]
- 8002c02: 430a orrs r2, r1
- 8002c04: 601a str r2, [r3, #0]
+ 8002c04: 4b30 ldr r3, [pc, #192] ; (8002cc8 <HAL_RCC_ClockConfig+0x270>)
+ 8002c06: 681b ldr r3, [r3, #0]
+ 8002c08: 2201 movs r2, #1
+ 8002c0a: 4393 bics r3, r2
+ 8002c0c: 0019 movs r1, r3
+ 8002c0e: 4b2e ldr r3, [pc, #184] ; (8002cc8 <HAL_RCC_ClockConfig+0x270>)
+ 8002c10: 683a ldr r2, [r7, #0]
+ 8002c12: 430a orrs r2, r1
+ 8002c14: 601a str r2, [r3, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by polling the FLASH_ACR register */
tickstart = HAL_GetTick();
- 8002c06: f7fe fa87 bl 8001118 <HAL_GetTick>
- 8002c0a: 0003 movs r3, r0
- 8002c0c: 60fb str r3, [r7, #12]
+ 8002c16: f7fe fa87 bl 8001128 <HAL_GetTick>
+ 8002c1a: 0003 movs r3, r0
+ 8002c1c: 60fb str r3, [r7, #12]
while (__HAL_FLASH_GET_LATENCY() != FLatency)
- 8002c0e: e009 b.n 8002c24 <HAL_RCC_ClockConfig+0x1dc>
+ 8002c1e: e009 b.n 8002c34 <HAL_RCC_ClockConfig+0x1dc>
{
if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
- 8002c10: f7fe fa82 bl 8001118 <HAL_GetTick>
- 8002c14: 0002 movs r2, r0
- 8002c16: 68fb ldr r3, [r7, #12]
- 8002c18: 1ad3 subs r3, r2, r3
- 8002c1a: 4a28 ldr r2, [pc, #160] ; (8002cbc <HAL_RCC_ClockConfig+0x274>)
- 8002c1c: 4293 cmp r3, r2
- 8002c1e: d901 bls.n 8002c24 <HAL_RCC_ClockConfig+0x1dc>
+ 8002c20: f7fe fa82 bl 8001128 <HAL_GetTick>
+ 8002c24: 0002 movs r2, r0
+ 8002c26: 68fb ldr r3, [r7, #12]
+ 8002c28: 1ad3 subs r3, r2, r3
+ 8002c2a: 4a28 ldr r2, [pc, #160] ; (8002ccc <HAL_RCC_ClockConfig+0x274>)
+ 8002c2c: 4293 cmp r3, r2
+ 8002c2e: d901 bls.n 8002c34 <HAL_RCC_ClockConfig+0x1dc>
{
return HAL_TIMEOUT;
- 8002c20: 2303 movs r3, #3
- 8002c22: e044 b.n 8002cae <HAL_RCC_ClockConfig+0x266>
+ 8002c30: 2303 movs r3, #3
+ 8002c32: e044 b.n 8002cbe <HAL_RCC_ClockConfig+0x266>
while (__HAL_FLASH_GET_LATENCY() != FLatency)
- 8002c24: 4b24 ldr r3, [pc, #144] ; (8002cb8 <HAL_RCC_ClockConfig+0x270>)
- 8002c26: 681b ldr r3, [r3, #0]
- 8002c28: 2201 movs r2, #1
- 8002c2a: 4013 ands r3, r2
- 8002c2c: 683a ldr r2, [r7, #0]
- 8002c2e: 429a cmp r2, r3
- 8002c30: d1ee bne.n 8002c10 <HAL_RCC_ClockConfig+0x1c8>
+ 8002c34: 4b24 ldr r3, [pc, #144] ; (8002cc8 <HAL_RCC_ClockConfig+0x270>)
+ 8002c36: 681b ldr r3, [r3, #0]
+ 8002c38: 2201 movs r2, #1
+ 8002c3a: 4013 ands r3, r2
+ 8002c3c: 683a ldr r2, [r7, #0]
+ 8002c3e: 429a cmp r2, r3
+ 8002c40: d1ee bne.n 8002c20 <HAL_RCC_ClockConfig+0x1c8>
}
}
}
/*-------------------------- PCLK1 Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
- 8002c32: 687b ldr r3, [r7, #4]
- 8002c34: 681b ldr r3, [r3, #0]
- 8002c36: 2204 movs r2, #4
- 8002c38: 4013 ands r3, r2
- 8002c3a: d009 beq.n 8002c50 <HAL_RCC_ClockConfig+0x208>
+ 8002c42: 687b ldr r3, [r7, #4]
+ 8002c44: 681b ldr r3, [r3, #0]
+ 8002c46: 2204 movs r2, #4
+ 8002c48: 4013 ands r3, r2
+ 8002c4a: d009 beq.n 8002c60 <HAL_RCC_ClockConfig+0x208>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
- 8002c3c: 4b20 ldr r3, [pc, #128] ; (8002cc0 <HAL_RCC_ClockConfig+0x278>)
- 8002c3e: 68db ldr r3, [r3, #12]
- 8002c40: 4a20 ldr r2, [pc, #128] ; (8002cc4 <HAL_RCC_ClockConfig+0x27c>)
- 8002c42: 4013 ands r3, r2
- 8002c44: 0019 movs r1, r3
- 8002c46: 687b ldr r3, [r7, #4]
- 8002c48: 68da ldr r2, [r3, #12]
- 8002c4a: 4b1d ldr r3, [pc, #116] ; (8002cc0 <HAL_RCC_ClockConfig+0x278>)
- 8002c4c: 430a orrs r2, r1
- 8002c4e: 60da str r2, [r3, #12]
+ 8002c4c: 4b20 ldr r3, [pc, #128] ; (8002cd0 <HAL_RCC_ClockConfig+0x278>)
+ 8002c4e: 68db ldr r3, [r3, #12]
+ 8002c50: 4a20 ldr r2, [pc, #128] ; (8002cd4 <HAL_RCC_ClockConfig+0x27c>)
+ 8002c52: 4013 ands r3, r2
+ 8002c54: 0019 movs r1, r3
+ 8002c56: 687b ldr r3, [r7, #4]
+ 8002c58: 68da ldr r2, [r3, #12]
+ 8002c5a: 4b1d ldr r3, [pc, #116] ; (8002cd0 <HAL_RCC_ClockConfig+0x278>)
+ 8002c5c: 430a orrs r2, r1
+ 8002c5e: 60da str r2, [r3, #12]
}
/*-------------------------- PCLK2 Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
- 8002c50: 687b ldr r3, [r7, #4]
- 8002c52: 681b ldr r3, [r3, #0]
- 8002c54: 2208 movs r2, #8
- 8002c56: 4013 ands r3, r2
- 8002c58: d00a beq.n 8002c70 <HAL_RCC_ClockConfig+0x228>
+ 8002c60: 687b ldr r3, [r7, #4]
+ 8002c62: 681b ldr r3, [r3, #0]
+ 8002c64: 2208 movs r2, #8
+ 8002c66: 4013 ands r3, r2
+ 8002c68: d00a beq.n 8002c80 <HAL_RCC_ClockConfig+0x228>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3));
- 8002c5a: 4b19 ldr r3, [pc, #100] ; (8002cc0 <HAL_RCC_ClockConfig+0x278>)
- 8002c5c: 68db ldr r3, [r3, #12]
- 8002c5e: 4a1a ldr r2, [pc, #104] ; (8002cc8 <HAL_RCC_ClockConfig+0x280>)
- 8002c60: 4013 ands r3, r2
- 8002c62: 0019 movs r1, r3
- 8002c64: 687b ldr r3, [r7, #4]
- 8002c66: 691b ldr r3, [r3, #16]
- 8002c68: 00da lsls r2, r3, #3
- 8002c6a: 4b15 ldr r3, [pc, #84] ; (8002cc0 <HAL_RCC_ClockConfig+0x278>)
- 8002c6c: 430a orrs r2, r1
- 8002c6e: 60da str r2, [r3, #12]
+ 8002c6a: 4b19 ldr r3, [pc, #100] ; (8002cd0 <HAL_RCC_ClockConfig+0x278>)
+ 8002c6c: 68db ldr r3, [r3, #12]
+ 8002c6e: 4a1a ldr r2, [pc, #104] ; (8002cd8 <HAL_RCC_ClockConfig+0x280>)
+ 8002c70: 4013 ands r3, r2
+ 8002c72: 0019 movs r1, r3
+ 8002c74: 687b ldr r3, [r7, #4]
+ 8002c76: 691b ldr r3, [r3, #16]
+ 8002c78: 00da lsls r2, r3, #3
+ 8002c7a: 4b15 ldr r3, [pc, #84] ; (8002cd0 <HAL_RCC_ClockConfig+0x278>)
+ 8002c7c: 430a orrs r2, r1
+ 8002c7e: 60da str r2, [r3, #12]
}
/* Update the SystemCoreClock global variable */
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_Pos];
- 8002c70: f000 f832 bl 8002cd8 <HAL_RCC_GetSysClockFreq>
- 8002c74: 0001 movs r1, r0
- 8002c76: 4b12 ldr r3, [pc, #72] ; (8002cc0 <HAL_RCC_ClockConfig+0x278>)
- 8002c78: 68db ldr r3, [r3, #12]
- 8002c7a: 091b lsrs r3, r3, #4
- 8002c7c: 220f movs r2, #15
- 8002c7e: 4013 ands r3, r2
- 8002c80: 4a12 ldr r2, [pc, #72] ; (8002ccc <HAL_RCC_ClockConfig+0x284>)
- 8002c82: 5cd3 ldrb r3, [r2, r3]
- 8002c84: 000a movs r2, r1
- 8002c86: 40da lsrs r2, r3
- 8002c88: 4b11 ldr r3, [pc, #68] ; (8002cd0 <HAL_RCC_ClockConfig+0x288>)
- 8002c8a: 601a str r2, [r3, #0]
+ 8002c80: f000 f832 bl 8002ce8 <HAL_RCC_GetSysClockFreq>
+ 8002c84: 0001 movs r1, r0
+ 8002c86: 4b12 ldr r3, [pc, #72] ; (8002cd0 <HAL_RCC_ClockConfig+0x278>)
+ 8002c88: 68db ldr r3, [r3, #12]
+ 8002c8a: 091b lsrs r3, r3, #4
+ 8002c8c: 220f movs r2, #15
+ 8002c8e: 4013 ands r3, r2
+ 8002c90: 4a12 ldr r2, [pc, #72] ; (8002cdc <HAL_RCC_ClockConfig+0x284>)
+ 8002c92: 5cd3 ldrb r3, [r2, r3]
+ 8002c94: 000a movs r2, r1
+ 8002c96: 40da lsrs r2, r3
+ 8002c98: 4b11 ldr r3, [pc, #68] ; (8002ce0 <HAL_RCC_ClockConfig+0x288>)
+ 8002c9a: 601a str r2, [r3, #0]
/* Configure the source of time base considering new system clocks settings*/
status = HAL_InitTick(uwTickPrio);
- 8002c8c: 4b11 ldr r3, [pc, #68] ; (8002cd4 <HAL_RCC_ClockConfig+0x28c>)
- 8002c8e: 681b ldr r3, [r3, #0]
- 8002c90: 250b movs r5, #11
- 8002c92: 197c adds r4, r7, r5
- 8002c94: 0018 movs r0, r3
- 8002c96: f7fe f9f9 bl 800108c <HAL_InitTick>
- 8002c9a: 0003 movs r3, r0
- 8002c9c: 7023 strb r3, [r4, #0]
+ 8002c9c: 4b11 ldr r3, [pc, #68] ; (8002ce4 <HAL_RCC_ClockConfig+0x28c>)
+ 8002c9e: 681b ldr r3, [r3, #0]
+ 8002ca0: 250b movs r5, #11
+ 8002ca2: 197c adds r4, r7, r5
+ 8002ca4: 0018 movs r0, r3
+ 8002ca6: f7fe f9f9 bl 800109c <HAL_InitTick>
+ 8002caa: 0003 movs r3, r0
+ 8002cac: 7023 strb r3, [r4, #0]
if(status != HAL_OK)
- 8002c9e: 197b adds r3, r7, r5
- 8002ca0: 781b ldrb r3, [r3, #0]
- 8002ca2: 2b00 cmp r3, #0
- 8002ca4: d002 beq.n 8002cac <HAL_RCC_ClockConfig+0x264>
+ 8002cae: 197b adds r3, r7, r5
+ 8002cb0: 781b ldrb r3, [r3, #0]
+ 8002cb2: 2b00 cmp r3, #0
+ 8002cb4: d002 beq.n 8002cbc <HAL_RCC_ClockConfig+0x264>
{
return status;
- 8002ca6: 197b adds r3, r7, r5
- 8002ca8: 781b ldrb r3, [r3, #0]
- 8002caa: e000 b.n 8002cae <HAL_RCC_ClockConfig+0x266>
+ 8002cb6: 197b adds r3, r7, r5
+ 8002cb8: 781b ldrb r3, [r3, #0]
+ 8002cba: e000 b.n 8002cbe <HAL_RCC_ClockConfig+0x266>
}
return HAL_OK;
- 8002cac: 2300 movs r3, #0
+ 8002cbc: 2300 movs r3, #0
}
- 8002cae: 0018 movs r0, r3
- 8002cb0: 46bd mov sp, r7
- 8002cb2: b004 add sp, #16
- 8002cb4: bdb0 pop {r4, r5, r7, pc}
- 8002cb6: 46c0 nop ; (mov r8, r8)
- 8002cb8: 40022000 .word 0x40022000
- 8002cbc: 00001388 .word 0x00001388
- 8002cc0: 40021000 .word 0x40021000
- 8002cc4: fffff8ff .word 0xfffff8ff
- 8002cc8: ffffc7ff .word 0xffffc7ff
- 8002ccc: 08004348 .word 0x08004348
- 8002cd0: 20000000 .word 0x20000000
- 8002cd4: 20000004 .word 0x20000004
+ 8002cbe: 0018 movs r0, r3
+ 8002cc0: 46bd mov sp, r7
+ 8002cc2: b004 add sp, #16
+ 8002cc4: bdb0 pop {r4, r5, r7, pc}
+ 8002cc6: 46c0 nop ; (mov r8, r8)
+ 8002cc8: 40022000 .word 0x40022000
+ 8002ccc: 00001388 .word 0x00001388
+ 8002cd0: 40021000 .word 0x40021000
+ 8002cd4: fffff8ff .word 0xfffff8ff
+ 8002cd8: ffffc7ff .word 0xffffc7ff
+ 8002cdc: 08004358 .word 0x08004358
+ 8002ce0: 20000000 .word 0x20000000
+ 8002ce4: 20000004 .word 0x20000004
-08002cd8 <HAL_RCC_GetSysClockFreq>:
+08002ce8 <HAL_RCC_GetSysClockFreq>:
* right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
*
* @retval SYSCLK frequency
*/
uint32_t HAL_RCC_GetSysClockFreq(void)
{
- 8002cd8: b5b0 push {r4, r5, r7, lr}
- 8002cda: b08e sub sp, #56 ; 0x38
- 8002cdc: af00 add r7, sp, #0
+ 8002ce8: b5b0 push {r4, r5, r7, lr}
+ 8002cea: b08e sub sp, #56 ; 0x38
+ 8002cec: af00 add r7, sp, #0
uint32_t tmpreg, pllm, plld, pllvco, msiclkrange; /* no init needed */
uint32_t sysclockfreq;
tmpreg = RCC->CFGR;
- 8002cde: 4b4c ldr r3, [pc, #304] ; (8002e10 <HAL_RCC_GetSysClockFreq+0x138>)
- 8002ce0: 68db ldr r3, [r3, #12]
- 8002ce2: 62fb str r3, [r7, #44] ; 0x2c
+ 8002cee: 4b4c ldr r3, [pc, #304] ; (8002e20 <HAL_RCC_GetSysClockFreq+0x138>)
+ 8002cf0: 68db ldr r3, [r3, #12]
+ 8002cf2: 62fb str r3, [r7, #44] ; 0x2c
/* Get SYSCLK source -------------------------------------------------------*/
switch (tmpreg & RCC_CFGR_SWS)
- 8002ce4: 6afa ldr r2, [r7, #44] ; 0x2c
- 8002ce6: 230c movs r3, #12
- 8002ce8: 4013 ands r3, r2
- 8002cea: 2b0c cmp r3, #12
- 8002cec: d014 beq.n 8002d18 <HAL_RCC_GetSysClockFreq+0x40>
- 8002cee: d900 bls.n 8002cf2 <HAL_RCC_GetSysClockFreq+0x1a>
- 8002cf0: e07b b.n 8002dea <HAL_RCC_GetSysClockFreq+0x112>
- 8002cf2: 2b04 cmp r3, #4
- 8002cf4: d002 beq.n 8002cfc <HAL_RCC_GetSysClockFreq+0x24>
- 8002cf6: 2b08 cmp r3, #8
- 8002cf8: d00b beq.n 8002d12 <HAL_RCC_GetSysClockFreq+0x3a>
- 8002cfa: e076 b.n 8002dea <HAL_RCC_GetSysClockFreq+0x112>
+ 8002cf4: 6afa ldr r2, [r7, #44] ; 0x2c
+ 8002cf6: 230c movs r3, #12
+ 8002cf8: 4013 ands r3, r2
+ 8002cfa: 2b0c cmp r3, #12
+ 8002cfc: d014 beq.n 8002d28 <HAL_RCC_GetSysClockFreq+0x40>
+ 8002cfe: d900 bls.n 8002d02 <HAL_RCC_GetSysClockFreq+0x1a>
+ 8002d00: e07b b.n 8002dfa <HAL_RCC_GetSysClockFreq+0x112>
+ 8002d02: 2b04 cmp r3, #4
+ 8002d04: d002 beq.n 8002d0c <HAL_RCC_GetSysClockFreq+0x24>
+ 8002d06: 2b08 cmp r3, #8
+ 8002d08: d00b beq.n 8002d22 <HAL_RCC_GetSysClockFreq+0x3a>
+ 8002d0a: e076 b.n 8002dfa <HAL_RCC_GetSysClockFreq+0x112>
{
case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
{
if ((RCC->CR & RCC_CR_HSIDIVF) != 0U)
- 8002cfc: 4b44 ldr r3, [pc, #272] ; (8002e10 <HAL_RCC_GetSysClockFreq+0x138>)
- 8002cfe: 681b ldr r3, [r3, #0]
- 8002d00: 2210 movs r2, #16
- 8002d02: 4013 ands r3, r2
- 8002d04: d002 beq.n 8002d0c <HAL_RCC_GetSysClockFreq+0x34>
+ 8002d0c: 4b44 ldr r3, [pc, #272] ; (8002e20 <HAL_RCC_GetSysClockFreq+0x138>)
+ 8002d0e: 681b ldr r3, [r3, #0]
+ 8002d10: 2210 movs r2, #16
+ 8002d12: 4013 ands r3, r2
+ 8002d14: d002 beq.n 8002d1c <HAL_RCC_GetSysClockFreq+0x34>
{
sysclockfreq = (HSI_VALUE >> 2);
- 8002d06: 4b43 ldr r3, [pc, #268] ; (8002e14 <HAL_RCC_GetSysClockFreq+0x13c>)
- 8002d08: 633b str r3, [r7, #48] ; 0x30
+ 8002d16: 4b43 ldr r3, [pc, #268] ; (8002e24 <HAL_RCC_GetSysClockFreq+0x13c>)
+ 8002d18: 633b str r3, [r7, #48] ; 0x30
}
else
{
sysclockfreq = HSI_VALUE;
}
break;
- 8002d0a: e07c b.n 8002e06 <HAL_RCC_GetSysClockFreq+0x12e>
+ 8002d1a: e07c b.n 8002e16 <HAL_RCC_GetSysClockFreq+0x12e>
sysclockfreq = HSI_VALUE;
- 8002d0c: 4b42 ldr r3, [pc, #264] ; (8002e18 <HAL_RCC_GetSysClockFreq+0x140>)
- 8002d0e: 633b str r3, [r7, #48] ; 0x30
+ 8002d1c: 4b42 ldr r3, [pc, #264] ; (8002e28 <HAL_RCC_GetSysClockFreq+0x140>)
+ 8002d1e: 633b str r3, [r7, #48] ; 0x30
break;
- 8002d10: e079 b.n 8002e06 <HAL_RCC_GetSysClockFreq+0x12e>
+ 8002d20: e079 b.n 8002e16 <HAL_RCC_GetSysClockFreq+0x12e>
}
case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */
{
sysclockfreq = HSE_VALUE;
- 8002d12: 4b42 ldr r3, [pc, #264] ; (8002e1c <HAL_RCC_GetSysClockFreq+0x144>)
- 8002d14: 633b str r3, [r7, #48] ; 0x30
+ 8002d22: 4b42 ldr r3, [pc, #264] ; (8002e2c <HAL_RCC_GetSysClockFreq+0x144>)
+ 8002d24: 633b str r3, [r7, #48] ; 0x30
break;
- 8002d16: e076 b.n 8002e06 <HAL_RCC_GetSysClockFreq+0x12e>
+ 8002d26: e076 b.n 8002e16 <HAL_RCC_GetSysClockFreq+0x12e>
}
case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */
{
pllm = PLLMulTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMUL) >> RCC_CFGR_PLLMUL_Pos];
- 8002d18: 6afb ldr r3, [r7, #44] ; 0x2c
- 8002d1a: 0c9a lsrs r2, r3, #18
- 8002d1c: 230f movs r3, #15
- 8002d1e: 401a ands r2, r3
- 8002d20: 4b3f ldr r3, [pc, #252] ; (8002e20 <HAL_RCC_GetSysClockFreq+0x148>)
- 8002d22: 5c9b ldrb r3, [r3, r2]
- 8002d24: 62bb str r3, [r7, #40] ; 0x28
+ 8002d28: 6afb ldr r3, [r7, #44] ; 0x2c
+ 8002d2a: 0c9a lsrs r2, r3, #18
+ 8002d2c: 230f movs r3, #15
+ 8002d2e: 401a ands r2, r3
+ 8002d30: 4b3f ldr r3, [pc, #252] ; (8002e30 <HAL_RCC_GetSysClockFreq+0x148>)
+ 8002d32: 5c9b ldrb r3, [r3, r2]
+ 8002d34: 62bb str r3, [r7, #40] ; 0x28
plld = ((uint32_t)(tmpreg & RCC_CFGR_PLLDIV) >> RCC_CFGR_PLLDIV_Pos) + 1U;
- 8002d26: 6afb ldr r3, [r7, #44] ; 0x2c
- 8002d28: 0d9a lsrs r2, r3, #22
- 8002d2a: 2303 movs r3, #3
- 8002d2c: 4013 ands r3, r2
- 8002d2e: 3301 adds r3, #1
- 8002d30: 627b str r3, [r7, #36] ; 0x24
+ 8002d36: 6afb ldr r3, [r7, #44] ; 0x2c
+ 8002d38: 0d9a lsrs r2, r3, #22
+ 8002d3a: 2303 movs r3, #3
+ 8002d3c: 4013 ands r3, r2
+ 8002d3e: 3301 adds r3, #1
+ 8002d40: 627b str r3, [r7, #36] ; 0x24
if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI)
- 8002d32: 4b37 ldr r3, [pc, #220] ; (8002e10 <HAL_RCC_GetSysClockFreq+0x138>)
- 8002d34: 68da ldr r2, [r3, #12]
- 8002d36: 2380 movs r3, #128 ; 0x80
- 8002d38: 025b lsls r3, r3, #9
- 8002d3a: 4013 ands r3, r2
- 8002d3c: d01a beq.n 8002d74 <HAL_RCC_GetSysClockFreq+0x9c>
+ 8002d42: 4b37 ldr r3, [pc, #220] ; (8002e20 <HAL_RCC_GetSysClockFreq+0x138>)
+ 8002d44: 68da ldr r2, [r3, #12]
+ 8002d46: 2380 movs r3, #128 ; 0x80
+ 8002d48: 025b lsls r3, r3, #9
+ 8002d4a: 4013 ands r3, r2
+ 8002d4c: d01a beq.n 8002d84 <HAL_RCC_GetSysClockFreq+0x9c>
{
/* HSE used as PLL clock source */
pllvco = (uint32_t)(((uint64_t)HSE_VALUE * (uint64_t)pllm) / (uint64_t)plld);
- 8002d3e: 6abb ldr r3, [r7, #40] ; 0x28
- 8002d40: 61bb str r3, [r7, #24]
- 8002d42: 2300 movs r3, #0
- 8002d44: 61fb str r3, [r7, #28]
- 8002d46: 4a35 ldr r2, [pc, #212] ; (8002e1c <HAL_RCC_GetSysClockFreq+0x144>)
- 8002d48: 2300 movs r3, #0
- 8002d4a: 69b8 ldr r0, [r7, #24]
- 8002d4c: 69f9 ldr r1, [r7, #28]
- 8002d4e: f7fd fa87 bl 8000260 <__aeabi_lmul>
- 8002d52: 0002 movs r2, r0
- 8002d54: 000b movs r3, r1
- 8002d56: 0010 movs r0, r2
- 8002d58: 0019 movs r1, r3
- 8002d5a: 6a7b ldr r3, [r7, #36] ; 0x24
- 8002d5c: 613b str r3, [r7, #16]
- 8002d5e: 2300 movs r3, #0
- 8002d60: 617b str r3, [r7, #20]
- 8002d62: 693a ldr r2, [r7, #16]
- 8002d64: 697b ldr r3, [r7, #20]
- 8002d66: f7fd fa5b bl 8000220 <__aeabi_uldivmod>
- 8002d6a: 0002 movs r2, r0
- 8002d6c: 000b movs r3, r1
- 8002d6e: 0013 movs r3, r2
- 8002d70: 637b str r3, [r7, #52] ; 0x34
- 8002d72: e037 b.n 8002de4 <HAL_RCC_GetSysClockFreq+0x10c>
+ 8002d4e: 6abb ldr r3, [r7, #40] ; 0x28
+ 8002d50: 61bb str r3, [r7, #24]
+ 8002d52: 2300 movs r3, #0
+ 8002d54: 61fb str r3, [r7, #28]
+ 8002d56: 4a35 ldr r2, [pc, #212] ; (8002e2c <HAL_RCC_GetSysClockFreq+0x144>)
+ 8002d58: 2300 movs r3, #0
+ 8002d5a: 69b8 ldr r0, [r7, #24]
+ 8002d5c: 69f9 ldr r1, [r7, #28]
+ 8002d5e: f7fd fa7f bl 8000260 <__aeabi_lmul>
+ 8002d62: 0002 movs r2, r0
+ 8002d64: 000b movs r3, r1
+ 8002d66: 0010 movs r0, r2
+ 8002d68: 0019 movs r1, r3
+ 8002d6a: 6a7b ldr r3, [r7, #36] ; 0x24
+ 8002d6c: 613b str r3, [r7, #16]
+ 8002d6e: 2300 movs r3, #0
+ 8002d70: 617b str r3, [r7, #20]
+ 8002d72: 693a ldr r2, [r7, #16]
+ 8002d74: 697b ldr r3, [r7, #20]
+ 8002d76: f7fd fa53 bl 8000220 <__aeabi_uldivmod>
+ 8002d7a: 0002 movs r2, r0
+ 8002d7c: 000b movs r3, r1
+ 8002d7e: 0013 movs r3, r2
+ 8002d80: 637b str r3, [r7, #52] ; 0x34
+ 8002d82: e037 b.n 8002df4 <HAL_RCC_GetSysClockFreq+0x10c>
}
else
{
if ((RCC->CR & RCC_CR_HSIDIVF) != 0U)
- 8002d74: 4b26 ldr r3, [pc, #152] ; (8002e10 <HAL_RCC_GetSysClockFreq+0x138>)
- 8002d76: 681b ldr r3, [r3, #0]
- 8002d78: 2210 movs r2, #16
- 8002d7a: 4013 ands r3, r2
- 8002d7c: d01a beq.n 8002db4 <HAL_RCC_GetSysClockFreq+0xdc>
+ 8002d84: 4b26 ldr r3, [pc, #152] ; (8002e20 <HAL_RCC_GetSysClockFreq+0x138>)
+ 8002d86: 681b ldr r3, [r3, #0]
+ 8002d88: 2210 movs r2, #16
+ 8002d8a: 4013 ands r3, r2
+ 8002d8c: d01a beq.n 8002dc4 <HAL_RCC_GetSysClockFreq+0xdc>
{
pllvco = (uint32_t)((((uint64_t)(HSI_VALUE >> 2)) * (uint64_t)pllm) / (uint64_t)plld);
- 8002d7e: 6abb ldr r3, [r7, #40] ; 0x28
- 8002d80: 60bb str r3, [r7, #8]
- 8002d82: 2300 movs r3, #0
- 8002d84: 60fb str r3, [r7, #12]
- 8002d86: 4a23 ldr r2, [pc, #140] ; (8002e14 <HAL_RCC_GetSysClockFreq+0x13c>)
- 8002d88: 2300 movs r3, #0
- 8002d8a: 68b8 ldr r0, [r7, #8]
- 8002d8c: 68f9 ldr r1, [r7, #12]
- 8002d8e: f7fd fa67 bl 8000260 <__aeabi_lmul>
- 8002d92: 0002 movs r2, r0
- 8002d94: 000b movs r3, r1
- 8002d96: 0010 movs r0, r2
- 8002d98: 0019 movs r1, r3
- 8002d9a: 6a7b ldr r3, [r7, #36] ; 0x24
- 8002d9c: 603b str r3, [r7, #0]
- 8002d9e: 2300 movs r3, #0
- 8002da0: 607b str r3, [r7, #4]
- 8002da2: 683a ldr r2, [r7, #0]
- 8002da4: 687b ldr r3, [r7, #4]
- 8002da6: f7fd fa3b bl 8000220 <__aeabi_uldivmod>
- 8002daa: 0002 movs r2, r0
- 8002dac: 000b movs r3, r1
- 8002dae: 0013 movs r3, r2
- 8002db0: 637b str r3, [r7, #52] ; 0x34
- 8002db2: e017 b.n 8002de4 <HAL_RCC_GetSysClockFreq+0x10c>
+ 8002d8e: 6abb ldr r3, [r7, #40] ; 0x28
+ 8002d90: 60bb str r3, [r7, #8]
+ 8002d92: 2300 movs r3, #0
+ 8002d94: 60fb str r3, [r7, #12]
+ 8002d96: 4a23 ldr r2, [pc, #140] ; (8002e24 <HAL_RCC_GetSysClockFreq+0x13c>)
+ 8002d98: 2300 movs r3, #0
+ 8002d9a: 68b8 ldr r0, [r7, #8]
+ 8002d9c: 68f9 ldr r1, [r7, #12]
+ 8002d9e: f7fd fa5f bl 8000260 <__aeabi_lmul>
+ 8002da2: 0002 movs r2, r0
+ 8002da4: 000b movs r3, r1
+ 8002da6: 0010 movs r0, r2
+ 8002da8: 0019 movs r1, r3
+ 8002daa: 6a7b ldr r3, [r7, #36] ; 0x24
+ 8002dac: 603b str r3, [r7, #0]
+ 8002dae: 2300 movs r3, #0
+ 8002db0: 607b str r3, [r7, #4]
+ 8002db2: 683a ldr r2, [r7, #0]
+ 8002db4: 687b ldr r3, [r7, #4]
+ 8002db6: f7fd fa33 bl 8000220 <__aeabi_uldivmod>
+ 8002dba: 0002 movs r2, r0
+ 8002dbc: 000b movs r3, r1
+ 8002dbe: 0013 movs r3, r2
+ 8002dc0: 637b str r3, [r7, #52] ; 0x34
+ 8002dc2: e017 b.n 8002df4 <HAL_RCC_GetSysClockFreq+0x10c>
}
else
{
pllvco = (uint32_t)(((uint64_t)HSI_VALUE * (uint64_t)pllm) / (uint64_t)plld);
- 8002db4: 6abb ldr r3, [r7, #40] ; 0x28
- 8002db6: 0018 movs r0, r3
- 8002db8: 2300 movs r3, #0
- 8002dba: 0019 movs r1, r3
- 8002dbc: 4a16 ldr r2, [pc, #88] ; (8002e18 <HAL_RCC_GetSysClockFreq+0x140>)
- 8002dbe: 2300 movs r3, #0
- 8002dc0: f7fd fa4e bl 8000260 <__aeabi_lmul>
- 8002dc4: 0002 movs r2, r0
- 8002dc6: 000b movs r3, r1
- 8002dc8: 0010 movs r0, r2
+ 8002dc4: 6abb ldr r3, [r7, #40] ; 0x28
+ 8002dc6: 0018 movs r0, r3
+ 8002dc8: 2300 movs r3, #0
8002dca: 0019 movs r1, r3
- 8002dcc: 6a7b ldr r3, [r7, #36] ; 0x24
- 8002dce: 001c movs r4, r3
- 8002dd0: 2300 movs r3, #0
- 8002dd2: 001d movs r5, r3
- 8002dd4: 0022 movs r2, r4
- 8002dd6: 002b movs r3, r5
- 8002dd8: f7fd fa22 bl 8000220 <__aeabi_uldivmod>
- 8002ddc: 0002 movs r2, r0
- 8002dde: 000b movs r3, r1
- 8002de0: 0013 movs r3, r2
- 8002de2: 637b str r3, [r7, #52] ; 0x34
+ 8002dcc: 4a16 ldr r2, [pc, #88] ; (8002e28 <HAL_RCC_GetSysClockFreq+0x140>)
+ 8002dce: 2300 movs r3, #0
+ 8002dd0: f7fd fa46 bl 8000260 <__aeabi_lmul>
+ 8002dd4: 0002 movs r2, r0
+ 8002dd6: 000b movs r3, r1
+ 8002dd8: 0010 movs r0, r2
+ 8002dda: 0019 movs r1, r3
+ 8002ddc: 6a7b ldr r3, [r7, #36] ; 0x24
+ 8002dde: 001c movs r4, r3
+ 8002de0: 2300 movs r3, #0
+ 8002de2: 001d movs r5, r3
+ 8002de4: 0022 movs r2, r4
+ 8002de6: 002b movs r3, r5
+ 8002de8: f7fd fa1a bl 8000220 <__aeabi_uldivmod>
+ 8002dec: 0002 movs r2, r0
+ 8002dee: 000b movs r3, r1
+ 8002df0: 0013 movs r3, r2
+ 8002df2: 637b str r3, [r7, #52] ; 0x34
}
}
sysclockfreq = pllvco;
- 8002de4: 6b7b ldr r3, [r7, #52] ; 0x34
- 8002de6: 633b str r3, [r7, #48] ; 0x30
+ 8002df4: 6b7b ldr r3, [r7, #52] ; 0x34
+ 8002df6: 633b str r3, [r7, #48] ; 0x30
break;
- 8002de8: e00d b.n 8002e06 <HAL_RCC_GetSysClockFreq+0x12e>
+ 8002df8: e00d b.n 8002e16 <HAL_RCC_GetSysClockFreq+0x12e>
}
case RCC_SYSCLKSOURCE_STATUS_MSI: /* MSI used as system clock source */
default: /* MSI used as system clock */
{
msiclkrange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE ) >> RCC_ICSCR_MSIRANGE_Pos;
- 8002dea: 4b09 ldr r3, [pc, #36] ; (8002e10 <HAL_RCC_GetSysClockFreq+0x138>)
- 8002dec: 685b ldr r3, [r3, #4]
- 8002dee: 0b5b lsrs r3, r3, #13
- 8002df0: 2207 movs r2, #7
- 8002df2: 4013 ands r3, r2
- 8002df4: 623b str r3, [r7, #32]
+ 8002dfa: 4b09 ldr r3, [pc, #36] ; (8002e20 <HAL_RCC_GetSysClockFreq+0x138>)
+ 8002dfc: 685b ldr r3, [r3, #4]
+ 8002dfe: 0b5b lsrs r3, r3, #13
+ 8002e00: 2207 movs r2, #7
+ 8002e02: 4013 ands r3, r2
+ 8002e04: 623b str r3, [r7, #32]
sysclockfreq = (32768U * (1UL << (msiclkrange + 1U)));
- 8002df6: 6a3b ldr r3, [r7, #32]
- 8002df8: 3301 adds r3, #1
- 8002dfa: 2280 movs r2, #128 ; 0x80
- 8002dfc: 0212 lsls r2, r2, #8
- 8002dfe: 409a lsls r2, r3
- 8002e00: 0013 movs r3, r2
- 8002e02: 633b str r3, [r7, #48] ; 0x30
+ 8002e06: 6a3b ldr r3, [r7, #32]
+ 8002e08: 3301 adds r3, #1
+ 8002e0a: 2280 movs r2, #128 ; 0x80
+ 8002e0c: 0212 lsls r2, r2, #8
+ 8002e0e: 409a lsls r2, r3
+ 8002e10: 0013 movs r3, r2
+ 8002e12: 633b str r3, [r7, #48] ; 0x30
break;
- 8002e04: 46c0 nop ; (mov r8, r8)
+ 8002e14: 46c0 nop ; (mov r8, r8)
}
}
return sysclockfreq;
- 8002e06: 6b3b ldr r3, [r7, #48] ; 0x30
+ 8002e16: 6b3b ldr r3, [r7, #48] ; 0x30
}
- 8002e08: 0018 movs r0, r3
- 8002e0a: 46bd mov sp, r7
- 8002e0c: b00e add sp, #56 ; 0x38
- 8002e0e: bdb0 pop {r4, r5, r7, pc}
- 8002e10: 40021000 .word 0x40021000
- 8002e14: 003d0900 .word 0x003d0900
- 8002e18: 00f42400 .word 0x00f42400
- 8002e1c: 007a1200 .word 0x007a1200
- 8002e20: 08004360 .word 0x08004360
+ 8002e18: 0018 movs r0, r3
+ 8002e1a: 46bd mov sp, r7
+ 8002e1c: b00e add sp, #56 ; 0x38
+ 8002e1e: bdb0 pop {r4, r5, r7, pc}
+ 8002e20: 40021000 .word 0x40021000
+ 8002e24: 003d0900 .word 0x003d0900
+ 8002e28: 00f42400 .word 0x00f42400
+ 8002e2c: 007a1200 .word 0x007a1200
+ 8002e30: 08004370 .word 0x08004370
-08002e24 <HAL_RCC_GetHCLKFreq>:
+08002e34 <HAL_RCC_GetHCLKFreq>:
* @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
* and updated within this function
* @retval HCLK frequency
*/
uint32_t HAL_RCC_GetHCLKFreq(void)
{
- 8002e24: b580 push {r7, lr}
- 8002e26: af00 add r7, sp, #0
+ 8002e34: b580 push {r7, lr}
+ 8002e36: af00 add r7, sp, #0
return SystemCoreClock;
- 8002e28: 4b02 ldr r3, [pc, #8] ; (8002e34 <HAL_RCC_GetHCLKFreq+0x10>)
- 8002e2a: 681b ldr r3, [r3, #0]
+ 8002e38: 4b02 ldr r3, [pc, #8] ; (8002e44 <HAL_RCC_GetHCLKFreq+0x10>)
+ 8002e3a: 681b ldr r3, [r3, #0]
}
- 8002e2c: 0018 movs r0, r3
- 8002e2e: 46bd mov sp, r7
- 8002e30: bd80 pop {r7, pc}
- 8002e32: 46c0 nop ; (mov r8, r8)
- 8002e34: 20000000 .word 0x20000000
+ 8002e3c: 0018 movs r0, r3
+ 8002e3e: 46bd mov sp, r7
+ 8002e40: bd80 pop {r7, pc}
+ 8002e42: 46c0 nop ; (mov r8, r8)
+ 8002e44: 20000000 .word 0x20000000
-08002e38 <HAL_RCC_GetPCLK1Freq>:
+08002e48 <HAL_RCC_GetPCLK1Freq>:
* @note Each time PCLK1 changes, this function must be called to update the
* right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
* @retval PCLK1 frequency
*/
uint32_t HAL_RCC_GetPCLK1Freq(void)
{
- 8002e38: b580 push {r7, lr}
- 8002e3a: af00 add r7, sp, #0
+ 8002e48: b580 push {r7, lr}
+ 8002e4a: af00 add r7, sp, #0
/* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]);
- 8002e3c: f7ff fff2 bl 8002e24 <HAL_RCC_GetHCLKFreq>
- 8002e40: 0001 movs r1, r0
- 8002e42: 4b06 ldr r3, [pc, #24] ; (8002e5c <HAL_RCC_GetPCLK1Freq+0x24>)
- 8002e44: 68db ldr r3, [r3, #12]
- 8002e46: 0a1b lsrs r3, r3, #8
- 8002e48: 2207 movs r2, #7
- 8002e4a: 4013 ands r3, r2
- 8002e4c: 4a04 ldr r2, [pc, #16] ; (8002e60 <HAL_RCC_GetPCLK1Freq+0x28>)
- 8002e4e: 5cd3 ldrb r3, [r2, r3]
- 8002e50: 40d9 lsrs r1, r3
- 8002e52: 000b movs r3, r1
+ 8002e4c: f7ff fff2 bl 8002e34 <HAL_RCC_GetHCLKFreq>
+ 8002e50: 0001 movs r1, r0
+ 8002e52: 4b06 ldr r3, [pc, #24] ; (8002e6c <HAL_RCC_GetPCLK1Freq+0x24>)
+ 8002e54: 68db ldr r3, [r3, #12]
+ 8002e56: 0a1b lsrs r3, r3, #8
+ 8002e58: 2207 movs r2, #7
+ 8002e5a: 4013 ands r3, r2
+ 8002e5c: 4a04 ldr r2, [pc, #16] ; (8002e70 <HAL_RCC_GetPCLK1Freq+0x28>)
+ 8002e5e: 5cd3 ldrb r3, [r2, r3]
+ 8002e60: 40d9 lsrs r1, r3
+ 8002e62: 000b movs r3, r1
}
- 8002e54: 0018 movs r0, r3
- 8002e56: 46bd mov sp, r7
- 8002e58: bd80 pop {r7, pc}
- 8002e5a: 46c0 nop ; (mov r8, r8)
- 8002e5c: 40021000 .word 0x40021000
- 8002e60: 08004358 .word 0x08004358
+ 8002e64: 0018 movs r0, r3
+ 8002e66: 46bd mov sp, r7
+ 8002e68: bd80 pop {r7, pc}
+ 8002e6a: 46c0 nop ; (mov r8, r8)
+ 8002e6c: 40021000 .word 0x40021000
+ 8002e70: 08004368 .word 0x08004368
-08002e64 <HAL_RCC_GetPCLK2Freq>:
+08002e74 <HAL_RCC_GetPCLK2Freq>:
* @note Each time PCLK2 changes, this function must be called to update the
* right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
* @retval PCLK2 frequency
*/
uint32_t HAL_RCC_GetPCLK2Freq(void)
{
- 8002e64: b580 push {r7, lr}
- 8002e66: af00 add r7, sp, #0
+ 8002e74: b580 push {r7, lr}
+ 8002e76: af00 add r7, sp, #0
/* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]);
- 8002e68: f7ff ffdc bl 8002e24 <HAL_RCC_GetHCLKFreq>
- 8002e6c: 0001 movs r1, r0
- 8002e6e: 4b06 ldr r3, [pc, #24] ; (8002e88 <HAL_RCC_GetPCLK2Freq+0x24>)
- 8002e70: 68db ldr r3, [r3, #12]
- 8002e72: 0adb lsrs r3, r3, #11
- 8002e74: 2207 movs r2, #7
- 8002e76: 4013 ands r3, r2
- 8002e78: 4a04 ldr r2, [pc, #16] ; (8002e8c <HAL_RCC_GetPCLK2Freq+0x28>)
- 8002e7a: 5cd3 ldrb r3, [r2, r3]
- 8002e7c: 40d9 lsrs r1, r3
- 8002e7e: 000b movs r3, r1
+ 8002e78: f7ff ffdc bl 8002e34 <HAL_RCC_GetHCLKFreq>
+ 8002e7c: 0001 movs r1, r0
+ 8002e7e: 4b06 ldr r3, [pc, #24] ; (8002e98 <HAL_RCC_GetPCLK2Freq+0x24>)
+ 8002e80: 68db ldr r3, [r3, #12]
+ 8002e82: 0adb lsrs r3, r3, #11
+ 8002e84: 2207 movs r2, #7
+ 8002e86: 4013 ands r3, r2
+ 8002e88: 4a04 ldr r2, [pc, #16] ; (8002e9c <HAL_RCC_GetPCLK2Freq+0x28>)
+ 8002e8a: 5cd3 ldrb r3, [r2, r3]
+ 8002e8c: 40d9 lsrs r1, r3
+ 8002e8e: 000b movs r3, r1
}
- 8002e80: 0018 movs r0, r3
- 8002e82: 46bd mov sp, r7
- 8002e84: bd80 pop {r7, pc}
- 8002e86: 46c0 nop ; (mov r8, r8)
- 8002e88: 40021000 .word 0x40021000
- 8002e8c: 08004358 .word 0x08004358
+ 8002e90: 0018 movs r0, r3
+ 8002e92: 46bd mov sp, r7
+ 8002e94: bd80 pop {r7, pc}
+ 8002e96: 46c0 nop ; (mov r8, r8)
+ 8002e98: 40021000 .word 0x40021000
+ 8002e9c: 08004368 .word 0x08004368
-08002e90 <HAL_RCCEx_PeriphCLKConfig>:
+08002ea0 <HAL_RCCEx_PeriphCLKConfig>:
* @retval HAL status
* @note If HAL_ERROR returned, first switch-OFF HSE clock oscillator with @ref HAL_RCC_OscConfig()
* to possibly update HSE divider.
*/
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
{
- 8002e90: b580 push {r7, lr}
- 8002e92: b086 sub sp, #24
- 8002e94: af00 add r7, sp, #0
- 8002e96: 6078 str r0, [r7, #4]
+ 8002ea0: b580 push {r7, lr}
+ 8002ea2: b086 sub sp, #24
+ 8002ea4: af00 add r7, sp, #0
+ 8002ea6: 6078 str r0, [r7, #4]
uint32_t tickstart;
uint32_t temp_reg;
FlagStatus pwrclkchanged = RESET;
- 8002e98: 2017 movs r0, #23
- 8002e9a: 183b adds r3, r7, r0
- 8002e9c: 2200 movs r2, #0
- 8002e9e: 701a strb r2, [r3, #0]
+ 8002ea8: 2017 movs r0, #23
+ 8002eaa: 183b adds r3, r7, r0
+ 8002eac: 2200 movs r2, #0
+ 8002eae: 701a strb r2, [r3, #0]
/* Check the parameters */
assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
/*------------------------------- RTC/LCD Configuration ------------------------*/
if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)
- 8002ea0: 687b ldr r3, [r7, #4]
- 8002ea2: 681b ldr r3, [r3, #0]
- 8002ea4: 2220 movs r2, #32
- 8002ea6: 4013 ands r3, r2
- 8002ea8: d100 bne.n 8002eac <HAL_RCCEx_PeriphCLKConfig+0x1c>
- 8002eaa: e0c2 b.n 8003032 <HAL_RCCEx_PeriphCLKConfig+0x1a2>
+ 8002eb0: 687b ldr r3, [r7, #4]
+ 8002eb2: 681b ldr r3, [r3, #0]
+ 8002eb4: 2220 movs r2, #32
+ 8002eb6: 4013 ands r3, r2
+ 8002eb8: d100 bne.n 8002ebc <HAL_RCCEx_PeriphCLKConfig+0x1c>
+ 8002eba: e0c2 b.n 8003042 <HAL_RCCEx_PeriphCLKConfig+0x1a2>
#endif /* LCD */
/* As soon as function is called to change RTC clock source, activation of the
power domain is done. */
/* Requires to enable write access to Backup Domain of necessary */
if(__HAL_RCC_PWR_IS_CLK_DISABLED())
- 8002eac: 4b81 ldr r3, [pc, #516] ; (80030b4 <HAL_RCCEx_PeriphCLKConfig+0x224>)
- 8002eae: 6b9a ldr r2, [r3, #56] ; 0x38
- 8002eb0: 2380 movs r3, #128 ; 0x80
- 8002eb2: 055b lsls r3, r3, #21
- 8002eb4: 4013 ands r3, r2
- 8002eb6: d109 bne.n 8002ecc <HAL_RCCEx_PeriphCLKConfig+0x3c>
+ 8002ebc: 4b81 ldr r3, [pc, #516] ; (80030c4 <HAL_RCCEx_PeriphCLKConfig+0x224>)
+ 8002ebe: 6b9a ldr r2, [r3, #56] ; 0x38
+ 8002ec0: 2380 movs r3, #128 ; 0x80
+ 8002ec2: 055b lsls r3, r3, #21
+ 8002ec4: 4013 ands r3, r2
+ 8002ec6: d109 bne.n 8002edc <HAL_RCCEx_PeriphCLKConfig+0x3c>
{
__HAL_RCC_PWR_CLK_ENABLE();
- 8002eb8: 4b7e ldr r3, [pc, #504] ; (80030b4 <HAL_RCCEx_PeriphCLKConfig+0x224>)
- 8002eba: 6b9a ldr r2, [r3, #56] ; 0x38
- 8002ebc: 4b7d ldr r3, [pc, #500] ; (80030b4 <HAL_RCCEx_PeriphCLKConfig+0x224>)
- 8002ebe: 2180 movs r1, #128 ; 0x80
- 8002ec0: 0549 lsls r1, r1, #21
- 8002ec2: 430a orrs r2, r1
- 8002ec4: 639a str r2, [r3, #56] ; 0x38
+ 8002ec8: 4b7e ldr r3, [pc, #504] ; (80030c4 <HAL_RCCEx_PeriphCLKConfig+0x224>)
+ 8002eca: 6b9a ldr r2, [r3, #56] ; 0x38
+ 8002ecc: 4b7d ldr r3, [pc, #500] ; (80030c4 <HAL_RCCEx_PeriphCLKConfig+0x224>)
+ 8002ece: 2180 movs r1, #128 ; 0x80
+ 8002ed0: 0549 lsls r1, r1, #21
+ 8002ed2: 430a orrs r2, r1
+ 8002ed4: 639a str r2, [r3, #56] ; 0x38
pwrclkchanged = SET;
- 8002ec6: 183b adds r3, r7, r0
- 8002ec8: 2201 movs r2, #1
- 8002eca: 701a strb r2, [r3, #0]
+ 8002ed6: 183b adds r3, r7, r0
+ 8002ed8: 2201 movs r2, #1
+ 8002eda: 701a strb r2, [r3, #0]
}
if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
- 8002ecc: 4b7a ldr r3, [pc, #488] ; (80030b8 <HAL_RCCEx_PeriphCLKConfig+0x228>)
- 8002ece: 681a ldr r2, [r3, #0]
- 8002ed0: 2380 movs r3, #128 ; 0x80
- 8002ed2: 005b lsls r3, r3, #1
- 8002ed4: 4013 ands r3, r2
- 8002ed6: d11a bne.n 8002f0e <HAL_RCCEx_PeriphCLKConfig+0x7e>
+ 8002edc: 4b7a ldr r3, [pc, #488] ; (80030c8 <HAL_RCCEx_PeriphCLKConfig+0x228>)
+ 8002ede: 681a ldr r2, [r3, #0]
+ 8002ee0: 2380 movs r3, #128 ; 0x80
+ 8002ee2: 005b lsls r3, r3, #1
+ 8002ee4: 4013 ands r3, r2
+ 8002ee6: d11a bne.n 8002f1e <HAL_RCCEx_PeriphCLKConfig+0x7e>
{
/* Enable write access to Backup domain */
SET_BIT(PWR->CR, PWR_CR_DBP);
- 8002ed8: 4b77 ldr r3, [pc, #476] ; (80030b8 <HAL_RCCEx_PeriphCLKConfig+0x228>)
- 8002eda: 681a ldr r2, [r3, #0]
- 8002edc: 4b76 ldr r3, [pc, #472] ; (80030b8 <HAL_RCCEx_PeriphCLKConfig+0x228>)
- 8002ede: 2180 movs r1, #128 ; 0x80
- 8002ee0: 0049 lsls r1, r1, #1
- 8002ee2: 430a orrs r2, r1
- 8002ee4: 601a str r2, [r3, #0]
+ 8002ee8: 4b77 ldr r3, [pc, #476] ; (80030c8 <HAL_RCCEx_PeriphCLKConfig+0x228>)
+ 8002eea: 681a ldr r2, [r3, #0]
+ 8002eec: 4b76 ldr r3, [pc, #472] ; (80030c8 <HAL_RCCEx_PeriphCLKConfig+0x228>)
+ 8002eee: 2180 movs r1, #128 ; 0x80
+ 8002ef0: 0049 lsls r1, r1, #1
+ 8002ef2: 430a orrs r2, r1
+ 8002ef4: 601a str r2, [r3, #0]
/* Wait for Backup domain Write protection disable */
tickstart = HAL_GetTick();
- 8002ee6: f7fe f917 bl 8001118 <HAL_GetTick>
- 8002eea: 0003 movs r3, r0
- 8002eec: 613b str r3, [r7, #16]
+ 8002ef6: f7fe f917 bl 8001128 <HAL_GetTick>
+ 8002efa: 0003 movs r3, r0
+ 8002efc: 613b str r3, [r7, #16]
while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
- 8002eee: e008 b.n 8002f02 <HAL_RCCEx_PeriphCLKConfig+0x72>
+ 8002efe: e008 b.n 8002f12 <HAL_RCCEx_PeriphCLKConfig+0x72>
{
if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
- 8002ef0: f7fe f912 bl 8001118 <HAL_GetTick>
- 8002ef4: 0002 movs r2, r0
- 8002ef6: 693b ldr r3, [r7, #16]
- 8002ef8: 1ad3 subs r3, r2, r3
- 8002efa: 2b64 cmp r3, #100 ; 0x64
- 8002efc: d901 bls.n 8002f02 <HAL_RCCEx_PeriphCLKConfig+0x72>
+ 8002f00: f7fe f912 bl 8001128 <HAL_GetTick>
+ 8002f04: 0002 movs r2, r0
+ 8002f06: 693b ldr r3, [r7, #16]
+ 8002f08: 1ad3 subs r3, r2, r3
+ 8002f0a: 2b64 cmp r3, #100 ; 0x64
+ 8002f0c: d901 bls.n 8002f12 <HAL_RCCEx_PeriphCLKConfig+0x72>
{
return HAL_TIMEOUT;
- 8002efe: 2303 movs r3, #3
- 8002f00: e0d4 b.n 80030ac <HAL_RCCEx_PeriphCLKConfig+0x21c>
+ 8002f0e: 2303 movs r3, #3
+ 8002f10: e0d4 b.n 80030bc <HAL_RCCEx_PeriphCLKConfig+0x21c>
while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
- 8002f02: 4b6d ldr r3, [pc, #436] ; (80030b8 <HAL_RCCEx_PeriphCLKConfig+0x228>)
- 8002f04: 681a ldr r2, [r3, #0]
- 8002f06: 2380 movs r3, #128 ; 0x80
- 8002f08: 005b lsls r3, r3, #1
- 8002f0a: 4013 ands r3, r2
- 8002f0c: d0f0 beq.n 8002ef0 <HAL_RCCEx_PeriphCLKConfig+0x60>
+ 8002f12: 4b6d ldr r3, [pc, #436] ; (80030c8 <HAL_RCCEx_PeriphCLKConfig+0x228>)
+ 8002f14: 681a ldr r2, [r3, #0]
+ 8002f16: 2380 movs r3, #128 ; 0x80
+ 8002f18: 005b lsls r3, r3, #1
+ 8002f1a: 4013 ands r3, r2
+ 8002f1c: d0f0 beq.n 8002f00 <HAL_RCCEx_PeriphCLKConfig+0x60>
}
}
}
/* Check if user wants to change HSE RTC prescaler whereas HSE is enabled */
temp_reg = (RCC->CR & RCC_CR_RTCPRE);
- 8002f0e: 4b69 ldr r3, [pc, #420] ; (80030b4 <HAL_RCCEx_PeriphCLKConfig+0x224>)
- 8002f10: 681a ldr r2, [r3, #0]
- 8002f12: 23c0 movs r3, #192 ; 0xc0
- 8002f14: 039b lsls r3, r3, #14
- 8002f16: 4013 ands r3, r2
- 8002f18: 60fb str r3, [r7, #12]
+ 8002f1e: 4b69 ldr r3, [pc, #420] ; (80030c4 <HAL_RCCEx_PeriphCLKConfig+0x224>)
+ 8002f20: 681a ldr r2, [r3, #0]
+ 8002f22: 23c0 movs r3, #192 ; 0xc0
+ 8002f24: 039b lsls r3, r3, #14
+ 8002f26: 4013 ands r3, r2
+ 8002f28: 60fb str r3, [r7, #12]
if ((temp_reg != (PeriphClkInit->RTCClockSelection & RCC_CR_RTCPRE))
- 8002f1a: 687b ldr r3, [r7, #4]
- 8002f1c: 685a ldr r2, [r3, #4]
- 8002f1e: 23c0 movs r3, #192 ; 0xc0
- 8002f20: 039b lsls r3, r3, #14
- 8002f22: 4013 ands r3, r2
- 8002f24: 68fa ldr r2, [r7, #12]
- 8002f26: 429a cmp r2, r3
- 8002f28: d013 beq.n 8002f52 <HAL_RCCEx_PeriphCLKConfig+0xc2>
+ 8002f2a: 687b ldr r3, [r7, #4]
+ 8002f2c: 685a ldr r2, [r3, #4]
+ 8002f2e: 23c0 movs r3, #192 ; 0xc0
+ 8002f30: 039b lsls r3, r3, #14
+ 8002f32: 4013 ands r3, r2
+ 8002f34: 68fa ldr r2, [r7, #12]
+ 8002f36: 429a cmp r2, r3
+ 8002f38: d013 beq.n 8002f62 <HAL_RCCEx_PeriphCLKConfig+0xc2>
#if defined (LCD)
|| (temp_reg != (PeriphClkInit->LCDClockSelection & RCC_CR_RTCPRE))
#endif /* LCD */
)
{ /* Check HSE State */
if ((PeriphClkInit->RTCClockSelection & RCC_CSR_RTCSEL) == RCC_CSR_RTCSEL_HSE)
- 8002f2a: 687b ldr r3, [r7, #4]
- 8002f2c: 685a ldr r2, [r3, #4]
- 8002f2e: 23c0 movs r3, #192 ; 0xc0
- 8002f30: 029b lsls r3, r3, #10
- 8002f32: 401a ands r2, r3
- 8002f34: 23c0 movs r3, #192 ; 0xc0
- 8002f36: 029b lsls r3, r3, #10
- 8002f38: 429a cmp r2, r3
- 8002f3a: d10a bne.n 8002f52 <HAL_RCCEx_PeriphCLKConfig+0xc2>
+ 8002f3a: 687b ldr r3, [r7, #4]
+ 8002f3c: 685a ldr r2, [r3, #4]
+ 8002f3e: 23c0 movs r3, #192 ; 0xc0
+ 8002f40: 029b lsls r3, r3, #10
+ 8002f42: 401a ands r2, r3
+ 8002f44: 23c0 movs r3, #192 ; 0xc0
+ 8002f46: 029b lsls r3, r3, #10
+ 8002f48: 429a cmp r2, r3
+ 8002f4a: d10a bne.n 8002f62 <HAL_RCCEx_PeriphCLKConfig+0xc2>
{
if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY))
- 8002f3c: 4b5d ldr r3, [pc, #372] ; (80030b4 <HAL_RCCEx_PeriphCLKConfig+0x224>)
- 8002f3e: 681a ldr r2, [r3, #0]
- 8002f40: 2380 movs r3, #128 ; 0x80
- 8002f42: 029b lsls r3, r3, #10
- 8002f44: 401a ands r2, r3
- 8002f46: 2380 movs r3, #128 ; 0x80
- 8002f48: 029b lsls r3, r3, #10
- 8002f4a: 429a cmp r2, r3
- 8002f4c: d101 bne.n 8002f52 <HAL_RCCEx_PeriphCLKConfig+0xc2>
+ 8002f4c: 4b5d ldr r3, [pc, #372] ; (80030c4 <HAL_RCCEx_PeriphCLKConfig+0x224>)
+ 8002f4e: 681a ldr r2, [r3, #0]
+ 8002f50: 2380 movs r3, #128 ; 0x80
+ 8002f52: 029b lsls r3, r3, #10
+ 8002f54: 401a ands r2, r3
+ 8002f56: 2380 movs r3, #128 ; 0x80
+ 8002f58: 029b lsls r3, r3, #10
+ 8002f5a: 429a cmp r2, r3
+ 8002f5c: d101 bne.n 8002f62 <HAL_RCCEx_PeriphCLKConfig+0xc2>
{
/* To update HSE divider, first switch-OFF HSE clock oscillator*/
return HAL_ERROR;
- 8002f4e: 2301 movs r3, #1
- 8002f50: e0ac b.n 80030ac <HAL_RCCEx_PeriphCLKConfig+0x21c>
+ 8002f5e: 2301 movs r3, #1
+ 8002f60: e0ac b.n 80030bc <HAL_RCCEx_PeriphCLKConfig+0x21c>
}
}
}
/* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */
temp_reg = (RCC->CSR & RCC_CSR_RTCSEL);
- 8002f52: 4b58 ldr r3, [pc, #352] ; (80030b4 <HAL_RCCEx_PeriphCLKConfig+0x224>)
- 8002f54: 6d1a ldr r2, [r3, #80] ; 0x50
- 8002f56: 23c0 movs r3, #192 ; 0xc0
- 8002f58: 029b lsls r3, r3, #10
- 8002f5a: 4013 ands r3, r2
- 8002f5c: 60fb str r3, [r7, #12]
+ 8002f62: 4b58 ldr r3, [pc, #352] ; (80030c4 <HAL_RCCEx_PeriphCLKConfig+0x224>)
+ 8002f64: 6d1a ldr r2, [r3, #80] ; 0x50
+ 8002f66: 23c0 movs r3, #192 ; 0xc0
+ 8002f68: 029b lsls r3, r3, #10
+ 8002f6a: 4013 ands r3, r2
+ 8002f6c: 60fb str r3, [r7, #12]
if((temp_reg != 0x00000000U) && (((temp_reg != (PeriphClkInit->RTCClockSelection & RCC_CSR_RTCSEL)) \
- 8002f5e: 68fb ldr r3, [r7, #12]
- 8002f60: 2b00 cmp r3, #0
- 8002f62: d03b beq.n 8002fdc <HAL_RCCEx_PeriphCLKConfig+0x14c>
- 8002f64: 687b ldr r3, [r7, #4]
- 8002f66: 685a ldr r2, [r3, #4]
- 8002f68: 23c0 movs r3, #192 ; 0xc0
- 8002f6a: 029b lsls r3, r3, #10
- 8002f6c: 4013 ands r3, r2
- 8002f6e: 68fa ldr r2, [r7, #12]
- 8002f70: 429a cmp r2, r3
- 8002f72: d033 beq.n 8002fdc <HAL_RCCEx_PeriphCLKConfig+0x14c>
- && (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
+ 8002f6e: 68fb ldr r3, [r7, #12]
+ 8002f70: 2b00 cmp r3, #0
+ 8002f72: d03b beq.n 8002fec <HAL_RCCEx_PeriphCLKConfig+0x14c>
8002f74: 687b ldr r3, [r7, #4]
- 8002f76: 681b ldr r3, [r3, #0]
- 8002f78: 2220 movs r2, #32
- 8002f7a: 4013 ands r3, r2
- 8002f7c: d02e beq.n 8002fdc <HAL_RCCEx_PeriphCLKConfig+0x14c>
+ 8002f76: 685a ldr r2, [r3, #4]
+ 8002f78: 23c0 movs r3, #192 ; 0xc0
+ 8002f7a: 029b lsls r3, r3, #10
+ 8002f7c: 4013 ands r3, r2
+ 8002f7e: 68fa ldr r2, [r7, #12]
+ 8002f80: 429a cmp r2, r3
+ 8002f82: d033 beq.n 8002fec <HAL_RCCEx_PeriphCLKConfig+0x14c>
+ && (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
+ 8002f84: 687b ldr r3, [r7, #4]
+ 8002f86: 681b ldr r3, [r3, #0]
+ 8002f88: 2220 movs r2, #32
+ 8002f8a: 4013 ands r3, r2
+ 8002f8c: d02e beq.n 8002fec <HAL_RCCEx_PeriphCLKConfig+0x14c>
&& (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LCD) == RCC_PERIPHCLK_LCD))
#endif /* LCD */
))
{
/* Store the content of CSR register before the reset of Backup Domain */
temp_reg = (RCC->CSR & ~(RCC_CSR_RTCSEL));
- 8002f7e: 4b4d ldr r3, [pc, #308] ; (80030b4 <HAL_RCCEx_PeriphCLKConfig+0x224>)
- 8002f80: 6d1b ldr r3, [r3, #80] ; 0x50
- 8002f82: 4a4e ldr r2, [pc, #312] ; (80030bc <HAL_RCCEx_PeriphCLKConfig+0x22c>)
- 8002f84: 4013 ands r3, r2
- 8002f86: 60fb str r3, [r7, #12]
+ 8002f8e: 4b4d ldr r3, [pc, #308] ; (80030c4 <HAL_RCCEx_PeriphCLKConfig+0x224>)
+ 8002f90: 6d1b ldr r3, [r3, #80] ; 0x50
+ 8002f92: 4a4e ldr r2, [pc, #312] ; (80030cc <HAL_RCCEx_PeriphCLKConfig+0x22c>)
+ 8002f94: 4013 ands r3, r2
+ 8002f96: 60fb str r3, [r7, #12]
/* RTC Clock selection can be changed only if the Backup Domain is reset */
__HAL_RCC_BACKUPRESET_FORCE();
- 8002f88: 4b4a ldr r3, [pc, #296] ; (80030b4 <HAL_RCCEx_PeriphCLKConfig+0x224>)
- 8002f8a: 6d1a ldr r2, [r3, #80] ; 0x50
- 8002f8c: 4b49 ldr r3, [pc, #292] ; (80030b4 <HAL_RCCEx_PeriphCLKConfig+0x224>)
- 8002f8e: 2180 movs r1, #128 ; 0x80
- 8002f90: 0309 lsls r1, r1, #12
- 8002f92: 430a orrs r2, r1
- 8002f94: 651a str r2, [r3, #80] ; 0x50
+ 8002f98: 4b4a ldr r3, [pc, #296] ; (80030c4 <HAL_RCCEx_PeriphCLKConfig+0x224>)
+ 8002f9a: 6d1a ldr r2, [r3, #80] ; 0x50
+ 8002f9c: 4b49 ldr r3, [pc, #292] ; (80030c4 <HAL_RCCEx_PeriphCLKConfig+0x224>)
+ 8002f9e: 2180 movs r1, #128 ; 0x80
+ 8002fa0: 0309 lsls r1, r1, #12
+ 8002fa2: 430a orrs r2, r1
+ 8002fa4: 651a str r2, [r3, #80] ; 0x50
__HAL_RCC_BACKUPRESET_RELEASE();
- 8002f96: 4b47 ldr r3, [pc, #284] ; (80030b4 <HAL_RCCEx_PeriphCLKConfig+0x224>)
- 8002f98: 6d1a ldr r2, [r3, #80] ; 0x50
- 8002f9a: 4b46 ldr r3, [pc, #280] ; (80030b4 <HAL_RCCEx_PeriphCLKConfig+0x224>)
- 8002f9c: 4948 ldr r1, [pc, #288] ; (80030c0 <HAL_RCCEx_PeriphCLKConfig+0x230>)
- 8002f9e: 400a ands r2, r1
- 8002fa0: 651a str r2, [r3, #80] ; 0x50
+ 8002fa6: 4b47 ldr r3, [pc, #284] ; (80030c4 <HAL_RCCEx_PeriphCLKConfig+0x224>)
+ 8002fa8: 6d1a ldr r2, [r3, #80] ; 0x50
+ 8002faa: 4b46 ldr r3, [pc, #280] ; (80030c4 <HAL_RCCEx_PeriphCLKConfig+0x224>)
+ 8002fac: 4948 ldr r1, [pc, #288] ; (80030d0 <HAL_RCCEx_PeriphCLKConfig+0x230>)
+ 8002fae: 400a ands r2, r1
+ 8002fb0: 651a str r2, [r3, #80] ; 0x50
/* Restore the Content of CSR register */
RCC->CSR = temp_reg;
- 8002fa2: 4b44 ldr r3, [pc, #272] ; (80030b4 <HAL_RCCEx_PeriphCLKConfig+0x224>)
- 8002fa4: 68fa ldr r2, [r7, #12]
- 8002fa6: 651a str r2, [r3, #80] ; 0x50
+ 8002fb2: 4b44 ldr r3, [pc, #272] ; (80030c4 <HAL_RCCEx_PeriphCLKConfig+0x224>)
+ 8002fb4: 68fa ldr r2, [r7, #12]
+ 8002fb6: 651a str r2, [r3, #80] ; 0x50
/* Wait for LSERDY if LSE was enabled */
if (HAL_IS_BIT_SET(temp_reg, RCC_CSR_LSEON))
- 8002fa8: 68fa ldr r2, [r7, #12]
- 8002faa: 2380 movs r3, #128 ; 0x80
- 8002fac: 005b lsls r3, r3, #1
- 8002fae: 4013 ands r3, r2
- 8002fb0: d014 beq.n 8002fdc <HAL_RCCEx_PeriphCLKConfig+0x14c>
+ 8002fb8: 68fa ldr r2, [r7, #12]
+ 8002fba: 2380 movs r3, #128 ; 0x80
+ 8002fbc: 005b lsls r3, r3, #1
+ 8002fbe: 4013 ands r3, r2
+ 8002fc0: d014 beq.n 8002fec <HAL_RCCEx_PeriphCLKConfig+0x14c>
{
/* Get Start Tick */
tickstart = HAL_GetTick();
- 8002fb2: f7fe f8b1 bl 8001118 <HAL_GetTick>
- 8002fb6: 0003 movs r3, r0
- 8002fb8: 613b str r3, [r7, #16]
+ 8002fc2: f7fe f8b1 bl 8001128 <HAL_GetTick>
+ 8002fc6: 0003 movs r3, r0
+ 8002fc8: 613b str r3, [r7, #16]
/* Wait till LSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U)
- 8002fba: e009 b.n 8002fd0 <HAL_RCCEx_PeriphCLKConfig+0x140>
+ 8002fca: e009 b.n 8002fe0 <HAL_RCCEx_PeriphCLKConfig+0x140>
{
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
- 8002fbc: f7fe f8ac bl 8001118 <HAL_GetTick>
- 8002fc0: 0002 movs r2, r0
- 8002fc2: 693b ldr r3, [r7, #16]
- 8002fc4: 1ad3 subs r3, r2, r3
- 8002fc6: 4a3f ldr r2, [pc, #252] ; (80030c4 <HAL_RCCEx_PeriphCLKConfig+0x234>)
- 8002fc8: 4293 cmp r3, r2
- 8002fca: d901 bls.n 8002fd0 <HAL_RCCEx_PeriphCLKConfig+0x140>
+ 8002fcc: f7fe f8ac bl 8001128 <HAL_GetTick>
+ 8002fd0: 0002 movs r2, r0
+ 8002fd2: 693b ldr r3, [r7, #16]
+ 8002fd4: 1ad3 subs r3, r2, r3
+ 8002fd6: 4a3f ldr r2, [pc, #252] ; (80030d4 <HAL_RCCEx_PeriphCLKConfig+0x234>)
+ 8002fd8: 4293 cmp r3, r2
+ 8002fda: d901 bls.n 8002fe0 <HAL_RCCEx_PeriphCLKConfig+0x140>
{
return HAL_TIMEOUT;
- 8002fcc: 2303 movs r3, #3
- 8002fce: e06d b.n 80030ac <HAL_RCCEx_PeriphCLKConfig+0x21c>
+ 8002fdc: 2303 movs r3, #3
+ 8002fde: e06d b.n 80030bc <HAL_RCCEx_PeriphCLKConfig+0x21c>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U)
- 8002fd0: 4b38 ldr r3, [pc, #224] ; (80030b4 <HAL_RCCEx_PeriphCLKConfig+0x224>)
- 8002fd2: 6d1a ldr r2, [r3, #80] ; 0x50
- 8002fd4: 2380 movs r3, #128 ; 0x80
- 8002fd6: 009b lsls r3, r3, #2
- 8002fd8: 4013 ands r3, r2
- 8002fda: d0ef beq.n 8002fbc <HAL_RCCEx_PeriphCLKConfig+0x12c>
+ 8002fe0: 4b38 ldr r3, [pc, #224] ; (80030c4 <HAL_RCCEx_PeriphCLKConfig+0x224>)
+ 8002fe2: 6d1a ldr r2, [r3, #80] ; 0x50
+ 8002fe4: 2380 movs r3, #128 ; 0x80
+ 8002fe6: 009b lsls r3, r3, #2
+ 8002fe8: 4013 ands r3, r2
+ 8002fea: d0ef beq.n 8002fcc <HAL_RCCEx_PeriphCLKConfig+0x12c>
}
}
}
}
__HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
- 8002fdc: 687b ldr r3, [r7, #4]
- 8002fde: 685a ldr r2, [r3, #4]
- 8002fe0: 23c0 movs r3, #192 ; 0xc0
- 8002fe2: 029b lsls r3, r3, #10
- 8002fe4: 401a ands r2, r3
- 8002fe6: 23c0 movs r3, #192 ; 0xc0
- 8002fe8: 029b lsls r3, r3, #10
- 8002fea: 429a cmp r2, r3
- 8002fec: d10c bne.n 8003008 <HAL_RCCEx_PeriphCLKConfig+0x178>
- 8002fee: 4b31 ldr r3, [pc, #196] ; (80030b4 <HAL_RCCEx_PeriphCLKConfig+0x224>)
- 8002ff0: 681b ldr r3, [r3, #0]
- 8002ff2: 4a35 ldr r2, [pc, #212] ; (80030c8 <HAL_RCCEx_PeriphCLKConfig+0x238>)
- 8002ff4: 4013 ands r3, r2
- 8002ff6: 0019 movs r1, r3
- 8002ff8: 687b ldr r3, [r7, #4]
- 8002ffa: 685a ldr r2, [r3, #4]
- 8002ffc: 23c0 movs r3, #192 ; 0xc0
- 8002ffe: 039b lsls r3, r3, #14
- 8003000: 401a ands r2, r3
- 8003002: 4b2c ldr r3, [pc, #176] ; (80030b4 <HAL_RCCEx_PeriphCLKConfig+0x224>)
- 8003004: 430a orrs r2, r1
- 8003006: 601a str r2, [r3, #0]
- 8003008: 4b2a ldr r3, [pc, #168] ; (80030b4 <HAL_RCCEx_PeriphCLKConfig+0x224>)
- 800300a: 6d19 ldr r1, [r3, #80] ; 0x50
- 800300c: 687b ldr r3, [r7, #4]
- 800300e: 685a ldr r2, [r3, #4]
- 8003010: 23c0 movs r3, #192 ; 0xc0
- 8003012: 029b lsls r3, r3, #10
- 8003014: 401a ands r2, r3
- 8003016: 4b27 ldr r3, [pc, #156] ; (80030b4 <HAL_RCCEx_PeriphCLKConfig+0x224>)
- 8003018: 430a orrs r2, r1
- 800301a: 651a str r2, [r3, #80] ; 0x50
+ 8002fec: 687b ldr r3, [r7, #4]
+ 8002fee: 685a ldr r2, [r3, #4]
+ 8002ff0: 23c0 movs r3, #192 ; 0xc0
+ 8002ff2: 029b lsls r3, r3, #10
+ 8002ff4: 401a ands r2, r3
+ 8002ff6: 23c0 movs r3, #192 ; 0xc0
+ 8002ff8: 029b lsls r3, r3, #10
+ 8002ffa: 429a cmp r2, r3
+ 8002ffc: d10c bne.n 8003018 <HAL_RCCEx_PeriphCLKConfig+0x178>
+ 8002ffe: 4b31 ldr r3, [pc, #196] ; (80030c4 <HAL_RCCEx_PeriphCLKConfig+0x224>)
+ 8003000: 681b ldr r3, [r3, #0]
+ 8003002: 4a35 ldr r2, [pc, #212] ; (80030d8 <HAL_RCCEx_PeriphCLKConfig+0x238>)
+ 8003004: 4013 ands r3, r2
+ 8003006: 0019 movs r1, r3
+ 8003008: 687b ldr r3, [r7, #4]
+ 800300a: 685a ldr r2, [r3, #4]
+ 800300c: 23c0 movs r3, #192 ; 0xc0
+ 800300e: 039b lsls r3, r3, #14
+ 8003010: 401a ands r2, r3
+ 8003012: 4b2c ldr r3, [pc, #176] ; (80030c4 <HAL_RCCEx_PeriphCLKConfig+0x224>)
+ 8003014: 430a orrs r2, r1
+ 8003016: 601a str r2, [r3, #0]
+ 8003018: 4b2a ldr r3, [pc, #168] ; (80030c4 <HAL_RCCEx_PeriphCLKConfig+0x224>)
+ 800301a: 6d19 ldr r1, [r3, #80] ; 0x50
+ 800301c: 687b ldr r3, [r7, #4]
+ 800301e: 685a ldr r2, [r3, #4]
+ 8003020: 23c0 movs r3, #192 ; 0xc0
+ 8003022: 029b lsls r3, r3, #10
+ 8003024: 401a ands r2, r3
+ 8003026: 4b27 ldr r3, [pc, #156] ; (80030c4 <HAL_RCCEx_PeriphCLKConfig+0x224>)
+ 8003028: 430a orrs r2, r1
+ 800302a: 651a str r2, [r3, #80] ; 0x50
/* Require to disable power clock if necessary */
if(pwrclkchanged == SET)
- 800301c: 2317 movs r3, #23
- 800301e: 18fb adds r3, r7, r3
- 8003020: 781b ldrb r3, [r3, #0]
- 8003022: 2b01 cmp r3, #1
- 8003024: d105 bne.n 8003032 <HAL_RCCEx_PeriphCLKConfig+0x1a2>
+ 800302c: 2317 movs r3, #23
+ 800302e: 18fb adds r3, r7, r3
+ 8003030: 781b ldrb r3, [r3, #0]
+ 8003032: 2b01 cmp r3, #1
+ 8003034: d105 bne.n 8003042 <HAL_RCCEx_PeriphCLKConfig+0x1a2>
{
__HAL_RCC_PWR_CLK_DISABLE();
- 8003026: 4b23 ldr r3, [pc, #140] ; (80030b4 <HAL_RCCEx_PeriphCLKConfig+0x224>)
- 8003028: 6b9a ldr r2, [r3, #56] ; 0x38
- 800302a: 4b22 ldr r3, [pc, #136] ; (80030b4 <HAL_RCCEx_PeriphCLKConfig+0x224>)
- 800302c: 4927 ldr r1, [pc, #156] ; (80030cc <HAL_RCCEx_PeriphCLKConfig+0x23c>)
- 800302e: 400a ands r2, r1
- 8003030: 639a str r2, [r3, #56] ; 0x38
+ 8003036: 4b23 ldr r3, [pc, #140] ; (80030c4 <HAL_RCCEx_PeriphCLKConfig+0x224>)
+ 8003038: 6b9a ldr r2, [r3, #56] ; 0x38
+ 800303a: 4b22 ldr r3, [pc, #136] ; (80030c4 <HAL_RCCEx_PeriphCLKConfig+0x224>)
+ 800303c: 4927 ldr r1, [pc, #156] ; (80030dc <HAL_RCCEx_PeriphCLKConfig+0x23c>)
+ 800303e: 400a ands r2, r1
+ 8003040: 639a str r2, [r3, #56] ; 0x38
__HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection);
}
#endif /* RCC_CCIPR_USART1SEL */
/*----------------------------- USART2 Configuration --------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2)
- 8003032: 687b ldr r3, [r7, #4]
- 8003034: 681b ldr r3, [r3, #0]
- 8003036: 2202 movs r2, #2
- 8003038: 4013 ands r3, r2
- 800303a: d009 beq.n 8003050 <HAL_RCCEx_PeriphCLKConfig+0x1c0>
+ 8003042: 687b ldr r3, [r7, #4]
+ 8003044: 681b ldr r3, [r3, #0]
+ 8003046: 2202 movs r2, #2
+ 8003048: 4013 ands r3, r2
+ 800304a: d009 beq.n 8003060 <HAL_RCCEx_PeriphCLKConfig+0x1c0>
{
/* Check the parameters */
assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection));
/* Configure the USART2 clock source */
__HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection);
- 800303c: 4b1d ldr r3, [pc, #116] ; (80030b4 <HAL_RCCEx_PeriphCLKConfig+0x224>)
- 800303e: 6cdb ldr r3, [r3, #76] ; 0x4c
- 8003040: 220c movs r2, #12
- 8003042: 4393 bics r3, r2
- 8003044: 0019 movs r1, r3
- 8003046: 687b ldr r3, [r7, #4]
- 8003048: 689a ldr r2, [r3, #8]
- 800304a: 4b1a ldr r3, [pc, #104] ; (80030b4 <HAL_RCCEx_PeriphCLKConfig+0x224>)
- 800304c: 430a orrs r2, r1
- 800304e: 64da str r2, [r3, #76] ; 0x4c
+ 800304c: 4b1d ldr r3, [pc, #116] ; (80030c4 <HAL_RCCEx_PeriphCLKConfig+0x224>)
+ 800304e: 6cdb ldr r3, [r3, #76] ; 0x4c
+ 8003050: 220c movs r2, #12
+ 8003052: 4393 bics r3, r2
+ 8003054: 0019 movs r1, r3
+ 8003056: 687b ldr r3, [r7, #4]
+ 8003058: 689a ldr r2, [r3, #8]
+ 800305a: 4b1a ldr r3, [pc, #104] ; (80030c4 <HAL_RCCEx_PeriphCLKConfig+0x224>)
+ 800305c: 430a orrs r2, r1
+ 800305e: 64da str r2, [r3, #76] ; 0x4c
}
/*------------------------------ LPUART1 Configuration ------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1)
- 8003050: 687b ldr r3, [r7, #4]
- 8003052: 681b ldr r3, [r3, #0]
- 8003054: 2204 movs r2, #4
- 8003056: 4013 ands r3, r2
- 8003058: d009 beq.n 800306e <HAL_RCCEx_PeriphCLKConfig+0x1de>
+ 8003060: 687b ldr r3, [r7, #4]
+ 8003062: 681b ldr r3, [r3, #0]
+ 8003064: 2204 movs r2, #4
+ 8003066: 4013 ands r3, r2
+ 8003068: d009 beq.n 800307e <HAL_RCCEx_PeriphCLKConfig+0x1de>
{
/* Check the parameters */
assert_param(IS_RCC_LPUART1CLKSOURCE(PeriphClkInit->Lpuart1ClockSelection));
/* Configure the LPUAR1 clock source */
__HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection);
- 800305a: 4b16 ldr r3, [pc, #88] ; (80030b4 <HAL_RCCEx_PeriphCLKConfig+0x224>)
- 800305c: 6cdb ldr r3, [r3, #76] ; 0x4c
- 800305e: 4a1c ldr r2, [pc, #112] ; (80030d0 <HAL_RCCEx_PeriphCLKConfig+0x240>)
- 8003060: 4013 ands r3, r2
- 8003062: 0019 movs r1, r3
- 8003064: 687b ldr r3, [r7, #4]
- 8003066: 68da ldr r2, [r3, #12]
- 8003068: 4b12 ldr r3, [pc, #72] ; (80030b4 <HAL_RCCEx_PeriphCLKConfig+0x224>)
- 800306a: 430a orrs r2, r1
- 800306c: 64da str r2, [r3, #76] ; 0x4c
+ 800306a: 4b16 ldr r3, [pc, #88] ; (80030c4 <HAL_RCCEx_PeriphCLKConfig+0x224>)
+ 800306c: 6cdb ldr r3, [r3, #76] ; 0x4c
+ 800306e: 4a1c ldr r2, [pc, #112] ; (80030e0 <HAL_RCCEx_PeriphCLKConfig+0x240>)
+ 8003070: 4013 ands r3, r2
+ 8003072: 0019 movs r1, r3
+ 8003074: 687b ldr r3, [r7, #4]
+ 8003076: 68da ldr r2, [r3, #12]
+ 8003078: 4b12 ldr r3, [pc, #72] ; (80030c4 <HAL_RCCEx_PeriphCLKConfig+0x224>)
+ 800307a: 430a orrs r2, r1
+ 800307c: 64da str r2, [r3, #76] ; 0x4c
}
/*------------------------------ I2C1 Configuration ------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1)
- 800306e: 687b ldr r3, [r7, #4]
- 8003070: 681b ldr r3, [r3, #0]
- 8003072: 2208 movs r2, #8
- 8003074: 4013 ands r3, r2
- 8003076: d009 beq.n 800308c <HAL_RCCEx_PeriphCLKConfig+0x1fc>
+ 800307e: 687b ldr r3, [r7, #4]
+ 8003080: 681b ldr r3, [r3, #0]
+ 8003082: 2208 movs r2, #8
+ 8003084: 4013 ands r3, r2
+ 8003086: d009 beq.n 800309c <HAL_RCCEx_PeriphCLKConfig+0x1fc>
{
/* Check the parameters */
assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection));
/* Configure the I2C1 clock source */
__HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection);
- 8003078: 4b0e ldr r3, [pc, #56] ; (80030b4 <HAL_RCCEx_PeriphCLKConfig+0x224>)
- 800307a: 6cdb ldr r3, [r3, #76] ; 0x4c
- 800307c: 4a15 ldr r2, [pc, #84] ; (80030d4 <HAL_RCCEx_PeriphCLKConfig+0x244>)
- 800307e: 4013 ands r3, r2
- 8003080: 0019 movs r1, r3
- 8003082: 687b ldr r3, [r7, #4]
- 8003084: 691a ldr r2, [r3, #16]
- 8003086: 4b0b ldr r3, [pc, #44] ; (80030b4 <HAL_RCCEx_PeriphCLKConfig+0x224>)
- 8003088: 430a orrs r2, r1
- 800308a: 64da str r2, [r3, #76] ; 0x4c
+ 8003088: 4b0e ldr r3, [pc, #56] ; (80030c4 <HAL_RCCEx_PeriphCLKConfig+0x224>)
+ 800308a: 6cdb ldr r3, [r3, #76] ; 0x4c
+ 800308c: 4a15 ldr r2, [pc, #84] ; (80030e4 <HAL_RCCEx_PeriphCLKConfig+0x244>)
+ 800308e: 4013 ands r3, r2
+ 8003090: 0019 movs r1, r3
+ 8003092: 687b ldr r3, [r7, #4]
+ 8003094: 691a ldr r2, [r3, #16]
+ 8003096: 4b0b ldr r3, [pc, #44] ; (80030c4 <HAL_RCCEx_PeriphCLKConfig+0x224>)
+ 8003098: 430a orrs r2, r1
+ 800309a: 64da str r2, [r3, #76] ; 0x4c
__HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection);
}
#endif /* USB */
/*---------------------------- LPTIM1 configuration ------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == (RCC_PERIPHCLK_LPTIM1))
- 800308c: 687b ldr r3, [r7, #4]
- 800308e: 681b ldr r3, [r3, #0]
- 8003090: 2280 movs r2, #128 ; 0x80
- 8003092: 4013 ands r3, r2
- 8003094: d009 beq.n 80030aa <HAL_RCCEx_PeriphCLKConfig+0x21a>
+ 800309c: 687b ldr r3, [r7, #4]
+ 800309e: 681b ldr r3, [r3, #0]
+ 80030a0: 2280 movs r2, #128 ; 0x80
+ 80030a2: 4013 ands r3, r2
+ 80030a4: d009 beq.n 80030ba <HAL_RCCEx_PeriphCLKConfig+0x21a>
{
assert_param(IS_RCC_LPTIMCLK(PeriphClkInit->LptimClockSelection));
__HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->LptimClockSelection);
- 8003096: 4b07 ldr r3, [pc, #28] ; (80030b4 <HAL_RCCEx_PeriphCLKConfig+0x224>)
- 8003098: 6cdb ldr r3, [r3, #76] ; 0x4c
- 800309a: 4a0f ldr r2, [pc, #60] ; (80030d8 <HAL_RCCEx_PeriphCLKConfig+0x248>)
- 800309c: 4013 ands r3, r2
- 800309e: 0019 movs r1, r3
- 80030a0: 687b ldr r3, [r7, #4]
- 80030a2: 695a ldr r2, [r3, #20]
- 80030a4: 4b03 ldr r3, [pc, #12] ; (80030b4 <HAL_RCCEx_PeriphCLKConfig+0x224>)
- 80030a6: 430a orrs r2, r1
- 80030a8: 64da str r2, [r3, #76] ; 0x4c
+ 80030a6: 4b07 ldr r3, [pc, #28] ; (80030c4 <HAL_RCCEx_PeriphCLKConfig+0x224>)
+ 80030a8: 6cdb ldr r3, [r3, #76] ; 0x4c
+ 80030aa: 4a0f ldr r2, [pc, #60] ; (80030e8 <HAL_RCCEx_PeriphCLKConfig+0x248>)
+ 80030ac: 4013 ands r3, r2
+ 80030ae: 0019 movs r1, r3
+ 80030b0: 687b ldr r3, [r7, #4]
+ 80030b2: 695a ldr r2, [r3, #20]
+ 80030b4: 4b03 ldr r3, [pc, #12] ; (80030c4 <HAL_RCCEx_PeriphCLKConfig+0x224>)
+ 80030b6: 430a orrs r2, r1
+ 80030b8: 64da str r2, [r3, #76] ; 0x4c
}
return HAL_OK;
- 80030aa: 2300 movs r3, #0
+ 80030ba: 2300 movs r3, #0
}
- 80030ac: 0018 movs r0, r3
- 80030ae: 46bd mov sp, r7
- 80030b0: b006 add sp, #24
- 80030b2: bd80 pop {r7, pc}
- 80030b4: 40021000 .word 0x40021000
- 80030b8: 40007000 .word 0x40007000
- 80030bc: fffcffff .word 0xfffcffff
- 80030c0: fff7ffff .word 0xfff7ffff
- 80030c4: 00001388 .word 0x00001388
- 80030c8: ffcfffff .word 0xffcfffff
- 80030cc: efffffff .word 0xefffffff
- 80030d0: fffff3ff .word 0xfffff3ff
- 80030d4: ffffcfff .word 0xffffcfff
- 80030d8: fff3ffff .word 0xfff3ffff
+ 80030bc: 0018 movs r0, r3
+ 80030be: 46bd mov sp, r7
+ 80030c0: b006 add sp, #24
+ 80030c2: bd80 pop {r7, pc}
+ 80030c4: 40021000 .word 0x40021000
+ 80030c8: 40007000 .word 0x40007000
+ 80030cc: fffcffff .word 0xfffcffff
+ 80030d0: fff7ffff .word 0xfff7ffff
+ 80030d4: 00001388 .word 0x00001388
+ 80030d8: ffcfffff .word 0xffcfffff
+ 80030dc: efffffff .word 0xefffffff
+ 80030e0: fffff3ff .word 0xfffff3ff
+ 80030e4: ffffcfff .word 0xffffcfff
+ 80030e8: fff3ffff .word 0xfff3ffff
-080030dc <HAL_TIM_Base_Init>:
+080030ec <HAL_TIM_Base_Init>:
* Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()
* @param htim TIM Base handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
{
- 80030dc: b580 push {r7, lr}
- 80030de: b082 sub sp, #8
- 80030e0: af00 add r7, sp, #0
- 80030e2: 6078 str r0, [r7, #4]
+ 80030ec: b580 push {r7, lr}
+ 80030ee: b082 sub sp, #8
+ 80030f0: af00 add r7, sp, #0
+ 80030f2: 6078 str r0, [r7, #4]
/* Check the TIM handle allocation */
if (htim == NULL)
- 80030e4: 687b ldr r3, [r7, #4]
- 80030e6: 2b00 cmp r3, #0
- 80030e8: d101 bne.n 80030ee <HAL_TIM_Base_Init+0x12>
+ 80030f4: 687b ldr r3, [r7, #4]
+ 80030f6: 2b00 cmp r3, #0
+ 80030f8: d101 bne.n 80030fe <HAL_TIM_Base_Init+0x12>
{
return HAL_ERROR;
- 80030ea: 2301 movs r3, #1
- 80030ec: e032 b.n 8003154 <HAL_TIM_Base_Init+0x78>
+ 80030fa: 2301 movs r3, #1
+ 80030fc: e032 b.n 8003164 <HAL_TIM_Base_Init+0x78>
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
assert_param(IS_TIM_PERIOD(htim->Init.Period));
assert_param(IS_TIM_PRESCALER(htim->Init.Prescaler));
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
if (htim->State == HAL_TIM_STATE_RESET)
- 80030ee: 687b ldr r3, [r7, #4]
- 80030f0: 2239 movs r2, #57 ; 0x39
- 80030f2: 5c9b ldrb r3, [r3, r2]
- 80030f4: b2db uxtb r3, r3
- 80030f6: 2b00 cmp r3, #0
- 80030f8: d107 bne.n 800310a <HAL_TIM_Base_Init+0x2e>
+ 80030fe: 687b ldr r3, [r7, #4]
+ 8003100: 2239 movs r2, #57 ; 0x39
+ 8003102: 5c9b ldrb r3, [r3, r2]
+ 8003104: b2db uxtb r3, r3
+ 8003106: 2b00 cmp r3, #0
+ 8003108: d107 bne.n 800311a <HAL_TIM_Base_Init+0x2e>
{
/* Allocate lock resource and initialize it */
htim->Lock = HAL_UNLOCKED;
- 80030fa: 687b ldr r3, [r7, #4]
- 80030fc: 2238 movs r2, #56 ; 0x38
- 80030fe: 2100 movs r1, #0
- 8003100: 5499 strb r1, [r3, r2]
+ 800310a: 687b ldr r3, [r7, #4]
+ 800310c: 2238 movs r2, #56 ; 0x38
+ 800310e: 2100 movs r1, #0
+ 8003110: 5499 strb r1, [r3, r2]
}
/* Init the low level hardware : GPIO, CLOCK, NVIC */
htim->Base_MspInitCallback(htim);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC */
HAL_TIM_Base_MspInit(htim);
- 8003102: 687b ldr r3, [r7, #4]
- 8003104: 0018 movs r0, r3
- 8003106: f7fd fe7f bl 8000e08 <HAL_TIM_Base_MspInit>
+ 8003112: 687b ldr r3, [r7, #4]
+ 8003114: 0018 movs r0, r3
+ 8003116: f7fd fe7f bl 8000e18 <HAL_TIM_Base_MspInit>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
/* Set the TIM state */
htim->State = HAL_TIM_STATE_BUSY;
- 800310a: 687b ldr r3, [r7, #4]
- 800310c: 2239 movs r2, #57 ; 0x39
- 800310e: 2102 movs r1, #2
- 8003110: 5499 strb r1, [r3, r2]
+ 800311a: 687b ldr r3, [r7, #4]
+ 800311c: 2239 movs r2, #57 ; 0x39
+ 800311e: 2102 movs r1, #2
+ 8003120: 5499 strb r1, [r3, r2]
/* Set the Time Base configuration */
TIM_Base_SetConfig(htim->Instance, &htim->Init);
- 8003112: 687b ldr r3, [r7, #4]
- 8003114: 681a ldr r2, [r3, #0]
- 8003116: 687b ldr r3, [r7, #4]
- 8003118: 3304 adds r3, #4
- 800311a: 0019 movs r1, r3
- 800311c: 0010 movs r0, r2
- 800311e: f000 f9ff bl 8003520 <TIM_Base_SetConfig>
+ 8003122: 687b ldr r3, [r7, #4]
+ 8003124: 681a ldr r2, [r3, #0]
+ 8003126: 687b ldr r3, [r7, #4]
+ 8003128: 3304 adds r3, #4
+ 800312a: 0019 movs r1, r3
+ 800312c: 0010 movs r0, r2
+ 800312e: f000 f9ff bl 8003530 <TIM_Base_SetConfig>
/* Initialize the DMA burst operation state */
htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
- 8003122: 687b ldr r3, [r7, #4]
- 8003124: 223e movs r2, #62 ; 0x3e
- 8003126: 2101 movs r1, #1
- 8003128: 5499 strb r1, [r3, r2]
+ 8003132: 687b ldr r3, [r7, #4]
+ 8003134: 223e movs r2, #62 ; 0x3e
+ 8003136: 2101 movs r1, #1
+ 8003138: 5499 strb r1, [r3, r2]
/* Initialize the TIM channels state */
TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
- 800312a: 687b ldr r3, [r7, #4]
- 800312c: 223a movs r2, #58 ; 0x3a
- 800312e: 2101 movs r1, #1
- 8003130: 5499 strb r1, [r3, r2]
- 8003132: 687b ldr r3, [r7, #4]
- 8003134: 223b movs r2, #59 ; 0x3b
- 8003136: 2101 movs r1, #1
- 8003138: 5499 strb r1, [r3, r2]
800313a: 687b ldr r3, [r7, #4]
- 800313c: 223c movs r2, #60 ; 0x3c
+ 800313c: 223a movs r2, #58 ; 0x3a
800313e: 2101 movs r1, #1
8003140: 5499 strb r1, [r3, r2]
8003142: 687b ldr r3, [r7, #4]
- 8003144: 223d movs r2, #61 ; 0x3d
+ 8003144: 223b movs r2, #59 ; 0x3b
8003146: 2101 movs r1, #1
8003148: 5499 strb r1, [r3, r2]
+ 800314a: 687b ldr r3, [r7, #4]
+ 800314c: 223c movs r2, #60 ; 0x3c
+ 800314e: 2101 movs r1, #1
+ 8003150: 5499 strb r1, [r3, r2]
+ 8003152: 687b ldr r3, [r7, #4]
+ 8003154: 223d movs r2, #61 ; 0x3d
+ 8003156: 2101 movs r1, #1
+ 8003158: 5499 strb r1, [r3, r2]
/* Initialize the TIM state*/
htim->State = HAL_TIM_STATE_READY;
- 800314a: 687b ldr r3, [r7, #4]
- 800314c: 2239 movs r2, #57 ; 0x39
- 800314e: 2101 movs r1, #1
- 8003150: 5499 strb r1, [r3, r2]
+ 800315a: 687b ldr r3, [r7, #4]
+ 800315c: 2239 movs r2, #57 ; 0x39
+ 800315e: 2101 movs r1, #1
+ 8003160: 5499 strb r1, [r3, r2]
return HAL_OK;
- 8003152: 2300 movs r3, #0
+ 8003162: 2300 movs r3, #0
}
- 8003154: 0018 movs r0, r3
- 8003156: 46bd mov sp, r7
- 8003158: b002 add sp, #8
- 800315a: bd80 pop {r7, pc}
+ 8003164: 0018 movs r0, r3
+ 8003166: 46bd mov sp, r7
+ 8003168: b002 add sp, #8
+ 800316a: bd80 pop {r7, pc}
-0800315c <HAL_TIM_PWM_Init>:
+0800316c <HAL_TIM_PWM_Init>:
* Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init()
* @param htim TIM PWM handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
{
- 800315c: b580 push {r7, lr}
- 800315e: b082 sub sp, #8
- 8003160: af00 add r7, sp, #0
- 8003162: 6078 str r0, [r7, #4]
+ 800316c: b580 push {r7, lr}
+ 800316e: b082 sub sp, #8
+ 8003170: af00 add r7, sp, #0
+ 8003172: 6078 str r0, [r7, #4]
/* Check the TIM handle allocation */
if (htim == NULL)
- 8003164: 687b ldr r3, [r7, #4]
- 8003166: 2b00 cmp r3, #0
- 8003168: d101 bne.n 800316e <HAL_TIM_PWM_Init+0x12>
+ 8003174: 687b ldr r3, [r7, #4]
+ 8003176: 2b00 cmp r3, #0
+ 8003178: d101 bne.n 800317e <HAL_TIM_PWM_Init+0x12>
{
return HAL_ERROR;
- 800316a: 2301 movs r3, #1
- 800316c: e032 b.n 80031d4 <HAL_TIM_PWM_Init+0x78>
+ 800317a: 2301 movs r3, #1
+ 800317c: e032 b.n 80031e4 <HAL_TIM_PWM_Init+0x78>
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
assert_param(IS_TIM_PERIOD(htim->Init.Period));
assert_param(IS_TIM_PRESCALER(htim->Init.Prescaler));
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
if (htim->State == HAL_TIM_STATE_RESET)
- 800316e: 687b ldr r3, [r7, #4]
- 8003170: 2239 movs r2, #57 ; 0x39
- 8003172: 5c9b ldrb r3, [r3, r2]
- 8003174: b2db uxtb r3, r3
- 8003176: 2b00 cmp r3, #0
- 8003178: d107 bne.n 800318a <HAL_TIM_PWM_Init+0x2e>
+ 800317e: 687b ldr r3, [r7, #4]
+ 8003180: 2239 movs r2, #57 ; 0x39
+ 8003182: 5c9b ldrb r3, [r3, r2]
+ 8003184: b2db uxtb r3, r3
+ 8003186: 2b00 cmp r3, #0
+ 8003188: d107 bne.n 800319a <HAL_TIM_PWM_Init+0x2e>
{
/* Allocate lock resource and initialize it */
htim->Lock = HAL_UNLOCKED;
- 800317a: 687b ldr r3, [r7, #4]
- 800317c: 2238 movs r2, #56 ; 0x38
- 800317e: 2100 movs r1, #0
- 8003180: 5499 strb r1, [r3, r2]
+ 800318a: 687b ldr r3, [r7, #4]
+ 800318c: 2238 movs r2, #56 ; 0x38
+ 800318e: 2100 movs r1, #0
+ 8003190: 5499 strb r1, [r3, r2]
}
/* Init the low level hardware : GPIO, CLOCK, NVIC */
htim->PWM_MspInitCallback(htim);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
HAL_TIM_PWM_MspInit(htim);
- 8003182: 687b ldr r3, [r7, #4]
- 8003184: 0018 movs r0, r3
- 8003186: f000 f829 bl 80031dc <HAL_TIM_PWM_MspInit>
+ 8003192: 687b ldr r3, [r7, #4]
+ 8003194: 0018 movs r0, r3
+ 8003196: f000 f829 bl 80031ec <HAL_TIM_PWM_MspInit>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
/* Set the TIM state */
htim->State = HAL_TIM_STATE_BUSY;
- 800318a: 687b ldr r3, [r7, #4]
- 800318c: 2239 movs r2, #57 ; 0x39
- 800318e: 2102 movs r1, #2
- 8003190: 5499 strb r1, [r3, r2]
+ 800319a: 687b ldr r3, [r7, #4]
+ 800319c: 2239 movs r2, #57 ; 0x39
+ 800319e: 2102 movs r1, #2
+ 80031a0: 5499 strb r1, [r3, r2]
/* Init the base time for the PWM */
TIM_Base_SetConfig(htim->Instance, &htim->Init);
- 8003192: 687b ldr r3, [r7, #4]
- 8003194: 681a ldr r2, [r3, #0]
- 8003196: 687b ldr r3, [r7, #4]
- 8003198: 3304 adds r3, #4
- 800319a: 0019 movs r1, r3
- 800319c: 0010 movs r0, r2
- 800319e: f000 f9bf bl 8003520 <TIM_Base_SetConfig>
+ 80031a2: 687b ldr r3, [r7, #4]
+ 80031a4: 681a ldr r2, [r3, #0]
+ 80031a6: 687b ldr r3, [r7, #4]
+ 80031a8: 3304 adds r3, #4
+ 80031aa: 0019 movs r1, r3
+ 80031ac: 0010 movs r0, r2
+ 80031ae: f000 f9bf bl 8003530 <TIM_Base_SetConfig>
/* Initialize the DMA burst operation state */
htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
- 80031a2: 687b ldr r3, [r7, #4]
- 80031a4: 223e movs r2, #62 ; 0x3e
- 80031a6: 2101 movs r1, #1
- 80031a8: 5499 strb r1, [r3, r2]
+ 80031b2: 687b ldr r3, [r7, #4]
+ 80031b4: 223e movs r2, #62 ; 0x3e
+ 80031b6: 2101 movs r1, #1
+ 80031b8: 5499 strb r1, [r3, r2]
/* Initialize the TIM channels state */
TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
- 80031aa: 687b ldr r3, [r7, #4]
- 80031ac: 223a movs r2, #58 ; 0x3a
- 80031ae: 2101 movs r1, #1
- 80031b0: 5499 strb r1, [r3, r2]
- 80031b2: 687b ldr r3, [r7, #4]
- 80031b4: 223b movs r2, #59 ; 0x3b
- 80031b6: 2101 movs r1, #1
- 80031b8: 5499 strb r1, [r3, r2]
80031ba: 687b ldr r3, [r7, #4]
- 80031bc: 223c movs r2, #60 ; 0x3c
+ 80031bc: 223a movs r2, #58 ; 0x3a
80031be: 2101 movs r1, #1
80031c0: 5499 strb r1, [r3, r2]
80031c2: 687b ldr r3, [r7, #4]
- 80031c4: 223d movs r2, #61 ; 0x3d
+ 80031c4: 223b movs r2, #59 ; 0x3b
80031c6: 2101 movs r1, #1
80031c8: 5499 strb r1, [r3, r2]
+ 80031ca: 687b ldr r3, [r7, #4]
+ 80031cc: 223c movs r2, #60 ; 0x3c
+ 80031ce: 2101 movs r1, #1
+ 80031d0: 5499 strb r1, [r3, r2]
+ 80031d2: 687b ldr r3, [r7, #4]
+ 80031d4: 223d movs r2, #61 ; 0x3d
+ 80031d6: 2101 movs r1, #1
+ 80031d8: 5499 strb r1, [r3, r2]
/* Initialize the TIM state*/
htim->State = HAL_TIM_STATE_READY;
- 80031ca: 687b ldr r3, [r7, #4]
- 80031cc: 2239 movs r2, #57 ; 0x39
- 80031ce: 2101 movs r1, #1
- 80031d0: 5499 strb r1, [r3, r2]
+ 80031da: 687b ldr r3, [r7, #4]
+ 80031dc: 2239 movs r2, #57 ; 0x39
+ 80031de: 2101 movs r1, #1
+ 80031e0: 5499 strb r1, [r3, r2]
return HAL_OK;
- 80031d2: 2300 movs r3, #0
+ 80031e2: 2300 movs r3, #0
}
- 80031d4: 0018 movs r0, r3
- 80031d6: 46bd mov sp, r7
- 80031d8: b002 add sp, #8
- 80031da: bd80 pop {r7, pc}
+ 80031e4: 0018 movs r0, r3
+ 80031e6: 46bd mov sp, r7
+ 80031e8: b002 add sp, #8
+ 80031ea: bd80 pop {r7, pc}
-080031dc <HAL_TIM_PWM_MspInit>:
+080031ec <HAL_TIM_PWM_MspInit>:
* @brief Initializes the TIM PWM MSP.
* @param htim TIM PWM handle
* @retval None
*/
__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
{
- 80031dc: b580 push {r7, lr}
- 80031de: b082 sub sp, #8
- 80031e0: af00 add r7, sp, #0
- 80031e2: 6078 str r0, [r7, #4]
+ 80031ec: b580 push {r7, lr}
+ 80031ee: b082 sub sp, #8
+ 80031f0: af00 add r7, sp, #0
+ 80031f2: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_PWM_MspInit could be implemented in the user file
*/
}
- 80031e4: 46c0 nop ; (mov r8, r8)
- 80031e6: 46bd mov sp, r7
- 80031e8: b002 add sp, #8
- 80031ea: bd80 pop {r7, pc}
+ 80031f4: 46c0 nop ; (mov r8, r8)
+ 80031f6: 46bd mov sp, r7
+ 80031f8: b002 add sp, #8
+ 80031fa: bd80 pop {r7, pc}
-080031ec <HAL_TIM_PWM_ConfigChannel>:
+080031fc <HAL_TIM_PWM_ConfigChannel>:
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
TIM_OC_InitTypeDef *sConfig,
uint32_t Channel)
{
- 80031ec: b580 push {r7, lr}
- 80031ee: b086 sub sp, #24
- 80031f0: af00 add r7, sp, #0
- 80031f2: 60f8 str r0, [r7, #12]
- 80031f4: 60b9 str r1, [r7, #8]
- 80031f6: 607a str r2, [r7, #4]
+ 80031fc: b580 push {r7, lr}
+ 80031fe: b086 sub sp, #24
+ 8003200: af00 add r7, sp, #0
+ 8003202: 60f8 str r0, [r7, #12]
+ 8003204: 60b9 str r1, [r7, #8]
+ 8003206: 607a str r2, [r7, #4]
HAL_StatusTypeDef status = HAL_OK;
- 80031f8: 2317 movs r3, #23
- 80031fa: 18fb adds r3, r7, r3
- 80031fc: 2200 movs r2, #0
- 80031fe: 701a strb r2, [r3, #0]
+ 8003208: 2317 movs r3, #23
+ 800320a: 18fb adds r3, r7, r3
+ 800320c: 2200 movs r2, #0
+ 800320e: 701a strb r2, [r3, #0]
assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
/* Process Locked */
__HAL_LOCK(htim);
- 8003200: 68fb ldr r3, [r7, #12]
- 8003202: 2238 movs r2, #56 ; 0x38
- 8003204: 5c9b ldrb r3, [r3, r2]
- 8003206: 2b01 cmp r3, #1
- 8003208: d101 bne.n 800320e <HAL_TIM_PWM_ConfigChannel+0x22>
- 800320a: 2302 movs r3, #2
- 800320c: e0ad b.n 800336a <HAL_TIM_PWM_ConfigChannel+0x17e>
- 800320e: 68fb ldr r3, [r7, #12]
- 8003210: 2238 movs r2, #56 ; 0x38
- 8003212: 2101 movs r1, #1
- 8003214: 5499 strb r1, [r3, r2]
+ 8003210: 68fb ldr r3, [r7, #12]
+ 8003212: 2238 movs r2, #56 ; 0x38
+ 8003214: 5c9b ldrb r3, [r3, r2]
+ 8003216: 2b01 cmp r3, #1
+ 8003218: d101 bne.n 800321e <HAL_TIM_PWM_ConfigChannel+0x22>
+ 800321a: 2302 movs r3, #2
+ 800321c: e0ad b.n 800337a <HAL_TIM_PWM_ConfigChannel+0x17e>
+ 800321e: 68fb ldr r3, [r7, #12]
+ 8003220: 2238 movs r2, #56 ; 0x38
+ 8003222: 2101 movs r1, #1
+ 8003224: 5499 strb r1, [r3, r2]
switch (Channel)
- 8003216: 687b ldr r3, [r7, #4]
- 8003218: 2b0c cmp r3, #12
- 800321a: d100 bne.n 800321e <HAL_TIM_PWM_ConfigChannel+0x32>
- 800321c: e076 b.n 800330c <HAL_TIM_PWM_ConfigChannel+0x120>
- 800321e: 687b ldr r3, [r7, #4]
- 8003220: 2b0c cmp r3, #12
- 8003222: d900 bls.n 8003226 <HAL_TIM_PWM_ConfigChannel+0x3a>
- 8003224: e095 b.n 8003352 <HAL_TIM_PWM_ConfigChannel+0x166>
8003226: 687b ldr r3, [r7, #4]
- 8003228: 2b08 cmp r3, #8
- 800322a: d04e beq.n 80032ca <HAL_TIM_PWM_ConfigChannel+0xde>
- 800322c: 687b ldr r3, [r7, #4]
- 800322e: 2b08 cmp r3, #8
- 8003230: d900 bls.n 8003234 <HAL_TIM_PWM_ConfigChannel+0x48>
- 8003232: e08e b.n 8003352 <HAL_TIM_PWM_ConfigChannel+0x166>
- 8003234: 687b ldr r3, [r7, #4]
- 8003236: 2b00 cmp r3, #0
- 8003238: d003 beq.n 8003242 <HAL_TIM_PWM_ConfigChannel+0x56>
- 800323a: 687b ldr r3, [r7, #4]
- 800323c: 2b04 cmp r3, #4
- 800323e: d021 beq.n 8003284 <HAL_TIM_PWM_ConfigChannel+0x98>
- 8003240: e087 b.n 8003352 <HAL_TIM_PWM_ConfigChannel+0x166>
+ 8003228: 2b0c cmp r3, #12
+ 800322a: d100 bne.n 800322e <HAL_TIM_PWM_ConfigChannel+0x32>
+ 800322c: e076 b.n 800331c <HAL_TIM_PWM_ConfigChannel+0x120>
+ 800322e: 687b ldr r3, [r7, #4]
+ 8003230: 2b0c cmp r3, #12
+ 8003232: d900 bls.n 8003236 <HAL_TIM_PWM_ConfigChannel+0x3a>
+ 8003234: e095 b.n 8003362 <HAL_TIM_PWM_ConfigChannel+0x166>
+ 8003236: 687b ldr r3, [r7, #4]
+ 8003238: 2b08 cmp r3, #8
+ 800323a: d04e beq.n 80032da <HAL_TIM_PWM_ConfigChannel+0xde>
+ 800323c: 687b ldr r3, [r7, #4]
+ 800323e: 2b08 cmp r3, #8
+ 8003240: d900 bls.n 8003244 <HAL_TIM_PWM_ConfigChannel+0x48>
+ 8003242: e08e b.n 8003362 <HAL_TIM_PWM_ConfigChannel+0x166>
+ 8003244: 687b ldr r3, [r7, #4]
+ 8003246: 2b00 cmp r3, #0
+ 8003248: d003 beq.n 8003252 <HAL_TIM_PWM_ConfigChannel+0x56>
+ 800324a: 687b ldr r3, [r7, #4]
+ 800324c: 2b04 cmp r3, #4
+ 800324e: d021 beq.n 8003294 <HAL_TIM_PWM_ConfigChannel+0x98>
+ 8003250: e087 b.n 8003362 <HAL_TIM_PWM_ConfigChannel+0x166>
{
/* Check the parameters */
assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
/* Configure the Channel 1 in PWM mode */
TIM_OC1_SetConfig(htim->Instance, sConfig);
- 8003242: 68fb ldr r3, [r7, #12]
- 8003244: 681b ldr r3, [r3, #0]
- 8003246: 68ba ldr r2, [r7, #8]
- 8003248: 0011 movs r1, r2
- 800324a: 0018 movs r0, r3
- 800324c: f000 f9bc bl 80035c8 <TIM_OC1_SetConfig>
+ 8003252: 68fb ldr r3, [r7, #12]
+ 8003254: 681b ldr r3, [r3, #0]
+ 8003256: 68ba ldr r2, [r7, #8]
+ 8003258: 0011 movs r1, r2
+ 800325a: 0018 movs r0, r3
+ 800325c: f000 f9bc bl 80035d8 <TIM_OC1_SetConfig>
/* Set the Preload enable bit for channel1 */
htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
- 8003250: 68fb ldr r3, [r7, #12]
- 8003252: 681b ldr r3, [r3, #0]
- 8003254: 699a ldr r2, [r3, #24]
- 8003256: 68fb ldr r3, [r7, #12]
- 8003258: 681b ldr r3, [r3, #0]
- 800325a: 2108 movs r1, #8
- 800325c: 430a orrs r2, r1
- 800325e: 619a str r2, [r3, #24]
-
- /* Configure the Output Fast mode */
- htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
8003260: 68fb ldr r3, [r7, #12]
8003262: 681b ldr r3, [r3, #0]
8003264: 699a ldr r2, [r3, #24]
8003266: 68fb ldr r3, [r7, #12]
8003268: 681b ldr r3, [r3, #0]
- 800326a: 2104 movs r1, #4
- 800326c: 438a bics r2, r1
+ 800326a: 2108 movs r1, #8
+ 800326c: 430a orrs r2, r1
800326e: 619a str r2, [r3, #24]
- htim->Instance->CCMR1 |= sConfig->OCFastMode;
+
+ /* Configure the Output Fast mode */
+ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
8003270: 68fb ldr r3, [r7, #12]
8003272: 681b ldr r3, [r3, #0]
- 8003274: 6999 ldr r1, [r3, #24]
- 8003276: 68bb ldr r3, [r7, #8]
- 8003278: 68da ldr r2, [r3, #12]
- 800327a: 68fb ldr r3, [r7, #12]
- 800327c: 681b ldr r3, [r3, #0]
- 800327e: 430a orrs r2, r1
- 8003280: 619a str r2, [r3, #24]
+ 8003274: 699a ldr r2, [r3, #24]
+ 8003276: 68fb ldr r3, [r7, #12]
+ 8003278: 681b ldr r3, [r3, #0]
+ 800327a: 2104 movs r1, #4
+ 800327c: 438a bics r2, r1
+ 800327e: 619a str r2, [r3, #24]
+ htim->Instance->CCMR1 |= sConfig->OCFastMode;
+ 8003280: 68fb ldr r3, [r7, #12]
+ 8003282: 681b ldr r3, [r3, #0]
+ 8003284: 6999 ldr r1, [r3, #24]
+ 8003286: 68bb ldr r3, [r7, #8]
+ 8003288: 68da ldr r2, [r3, #12]
+ 800328a: 68fb ldr r3, [r7, #12]
+ 800328c: 681b ldr r3, [r3, #0]
+ 800328e: 430a orrs r2, r1
+ 8003290: 619a str r2, [r3, #24]
break;
- 8003282: e06b b.n 800335c <HAL_TIM_PWM_ConfigChannel+0x170>
+ 8003292: e06b b.n 800336c <HAL_TIM_PWM_ConfigChannel+0x170>
{
/* Check the parameters */
assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
/* Configure the Channel 2 in PWM mode */
TIM_OC2_SetConfig(htim->Instance, sConfig);
- 8003284: 68fb ldr r3, [r7, #12]
- 8003286: 681b ldr r3, [r3, #0]
- 8003288: 68ba ldr r2, [r7, #8]
- 800328a: 0011 movs r1, r2
- 800328c: 0018 movs r0, r3
- 800328e: f000 f9d7 bl 8003640 <TIM_OC2_SetConfig>
+ 8003294: 68fb ldr r3, [r7, #12]
+ 8003296: 681b ldr r3, [r3, #0]
+ 8003298: 68ba ldr r2, [r7, #8]
+ 800329a: 0011 movs r1, r2
+ 800329c: 0018 movs r0, r3
+ 800329e: f000 f9d7 bl 8003650 <TIM_OC2_SetConfig>
/* Set the Preload enable bit for channel2 */
htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
- 8003292: 68fb ldr r3, [r7, #12]
- 8003294: 681b ldr r3, [r3, #0]
- 8003296: 699a ldr r2, [r3, #24]
- 8003298: 68fb ldr r3, [r7, #12]
- 800329a: 681b ldr r3, [r3, #0]
- 800329c: 2180 movs r1, #128 ; 0x80
- 800329e: 0109 lsls r1, r1, #4
- 80032a0: 430a orrs r2, r1
- 80032a2: 619a str r2, [r3, #24]
+ 80032a2: 68fb ldr r3, [r7, #12]
+ 80032a4: 681b ldr r3, [r3, #0]
+ 80032a6: 699a ldr r2, [r3, #24]
+ 80032a8: 68fb ldr r3, [r7, #12]
+ 80032aa: 681b ldr r3, [r3, #0]
+ 80032ac: 2180 movs r1, #128 ; 0x80
+ 80032ae: 0109 lsls r1, r1, #4
+ 80032b0: 430a orrs r2, r1
+ 80032b2: 619a str r2, [r3, #24]
/* Configure the Output Fast mode */
htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
- 80032a4: 68fb ldr r3, [r7, #12]
- 80032a6: 681b ldr r3, [r3, #0]
- 80032a8: 699a ldr r2, [r3, #24]
- 80032aa: 68fb ldr r3, [r7, #12]
- 80032ac: 681b ldr r3, [r3, #0]
- 80032ae: 4931 ldr r1, [pc, #196] ; (8003374 <HAL_TIM_PWM_ConfigChannel+0x188>)
- 80032b0: 400a ands r2, r1
- 80032b2: 619a str r2, [r3, #24]
- htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
80032b4: 68fb ldr r3, [r7, #12]
80032b6: 681b ldr r3, [r3, #0]
- 80032b8: 6999 ldr r1, [r3, #24]
- 80032ba: 68bb ldr r3, [r7, #8]
- 80032bc: 68db ldr r3, [r3, #12]
- 80032be: 021a lsls r2, r3, #8
- 80032c0: 68fb ldr r3, [r7, #12]
- 80032c2: 681b ldr r3, [r3, #0]
- 80032c4: 430a orrs r2, r1
- 80032c6: 619a str r2, [r3, #24]
+ 80032b8: 699a ldr r2, [r3, #24]
+ 80032ba: 68fb ldr r3, [r7, #12]
+ 80032bc: 681b ldr r3, [r3, #0]
+ 80032be: 4931 ldr r1, [pc, #196] ; (8003384 <HAL_TIM_PWM_ConfigChannel+0x188>)
+ 80032c0: 400a ands r2, r1
+ 80032c2: 619a str r2, [r3, #24]
+ htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
+ 80032c4: 68fb ldr r3, [r7, #12]
+ 80032c6: 681b ldr r3, [r3, #0]
+ 80032c8: 6999 ldr r1, [r3, #24]
+ 80032ca: 68bb ldr r3, [r7, #8]
+ 80032cc: 68db ldr r3, [r3, #12]
+ 80032ce: 021a lsls r2, r3, #8
+ 80032d0: 68fb ldr r3, [r7, #12]
+ 80032d2: 681b ldr r3, [r3, #0]
+ 80032d4: 430a orrs r2, r1
+ 80032d6: 619a str r2, [r3, #24]
break;
- 80032c8: e048 b.n 800335c <HAL_TIM_PWM_ConfigChannel+0x170>
+ 80032d8: e048 b.n 800336c <HAL_TIM_PWM_ConfigChannel+0x170>
{
/* Check the parameters */
assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
/* Configure the Channel 3 in PWM mode */
TIM_OC3_SetConfig(htim->Instance, sConfig);
- 80032ca: 68fb ldr r3, [r7, #12]
- 80032cc: 681b ldr r3, [r3, #0]
- 80032ce: 68ba ldr r2, [r7, #8]
- 80032d0: 0011 movs r1, r2
- 80032d2: 0018 movs r0, r3
- 80032d4: f000 f9f6 bl 80036c4 <TIM_OC3_SetConfig>
+ 80032da: 68fb ldr r3, [r7, #12]
+ 80032dc: 681b ldr r3, [r3, #0]
+ 80032de: 68ba ldr r2, [r7, #8]
+ 80032e0: 0011 movs r1, r2
+ 80032e2: 0018 movs r0, r3
+ 80032e4: f000 f9f6 bl 80036d4 <TIM_OC3_SetConfig>
/* Set the Preload enable bit for channel3 */
htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
- 80032d8: 68fb ldr r3, [r7, #12]
- 80032da: 681b ldr r3, [r3, #0]
- 80032dc: 69da ldr r2, [r3, #28]
- 80032de: 68fb ldr r3, [r7, #12]
- 80032e0: 681b ldr r3, [r3, #0]
- 80032e2: 2108 movs r1, #8
- 80032e4: 430a orrs r2, r1
- 80032e6: 61da str r2, [r3, #28]
-
- /* Configure the Output Fast mode */
- htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
80032e8: 68fb ldr r3, [r7, #12]
80032ea: 681b ldr r3, [r3, #0]
80032ec: 69da ldr r2, [r3, #28]
80032ee: 68fb ldr r3, [r7, #12]
80032f0: 681b ldr r3, [r3, #0]
- 80032f2: 2104 movs r1, #4
- 80032f4: 438a bics r2, r1
+ 80032f2: 2108 movs r1, #8
+ 80032f4: 430a orrs r2, r1
80032f6: 61da str r2, [r3, #28]
- htim->Instance->CCMR2 |= sConfig->OCFastMode;
+
+ /* Configure the Output Fast mode */
+ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
80032f8: 68fb ldr r3, [r7, #12]
80032fa: 681b ldr r3, [r3, #0]
- 80032fc: 69d9 ldr r1, [r3, #28]
- 80032fe: 68bb ldr r3, [r7, #8]
- 8003300: 68da ldr r2, [r3, #12]
- 8003302: 68fb ldr r3, [r7, #12]
- 8003304: 681b ldr r3, [r3, #0]
- 8003306: 430a orrs r2, r1
- 8003308: 61da str r2, [r3, #28]
+ 80032fc: 69da ldr r2, [r3, #28]
+ 80032fe: 68fb ldr r3, [r7, #12]
+ 8003300: 681b ldr r3, [r3, #0]
+ 8003302: 2104 movs r1, #4
+ 8003304: 438a bics r2, r1
+ 8003306: 61da str r2, [r3, #28]
+ htim->Instance->CCMR2 |= sConfig->OCFastMode;
+ 8003308: 68fb ldr r3, [r7, #12]
+ 800330a: 681b ldr r3, [r3, #0]
+ 800330c: 69d9 ldr r1, [r3, #28]
+ 800330e: 68bb ldr r3, [r7, #8]
+ 8003310: 68da ldr r2, [r3, #12]
+ 8003312: 68fb ldr r3, [r7, #12]
+ 8003314: 681b ldr r3, [r3, #0]
+ 8003316: 430a orrs r2, r1
+ 8003318: 61da str r2, [r3, #28]
break;
- 800330a: e027 b.n 800335c <HAL_TIM_PWM_ConfigChannel+0x170>
+ 800331a: e027 b.n 800336c <HAL_TIM_PWM_ConfigChannel+0x170>
{
/* Check the parameters */
assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
/* Configure the Channel 4 in PWM mode */
TIM_OC4_SetConfig(htim->Instance, sConfig);
- 800330c: 68fb ldr r3, [r7, #12]
- 800330e: 681b ldr r3, [r3, #0]
- 8003310: 68ba ldr r2, [r7, #8]
- 8003312: 0011 movs r1, r2
- 8003314: 0018 movs r0, r3
- 8003316: f000 fa15 bl 8003744 <TIM_OC4_SetConfig>
+ 800331c: 68fb ldr r3, [r7, #12]
+ 800331e: 681b ldr r3, [r3, #0]
+ 8003320: 68ba ldr r2, [r7, #8]
+ 8003322: 0011 movs r1, r2
+ 8003324: 0018 movs r0, r3
+ 8003326: f000 fa15 bl 8003754 <TIM_OC4_SetConfig>
/* Set the Preload enable bit for channel4 */
htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
- 800331a: 68fb ldr r3, [r7, #12]
- 800331c: 681b ldr r3, [r3, #0]
- 800331e: 69da ldr r2, [r3, #28]
- 8003320: 68fb ldr r3, [r7, #12]
- 8003322: 681b ldr r3, [r3, #0]
- 8003324: 2180 movs r1, #128 ; 0x80
- 8003326: 0109 lsls r1, r1, #4
- 8003328: 430a orrs r2, r1
- 800332a: 61da str r2, [r3, #28]
+ 800332a: 68fb ldr r3, [r7, #12]
+ 800332c: 681b ldr r3, [r3, #0]
+ 800332e: 69da ldr r2, [r3, #28]
+ 8003330: 68fb ldr r3, [r7, #12]
+ 8003332: 681b ldr r3, [r3, #0]
+ 8003334: 2180 movs r1, #128 ; 0x80
+ 8003336: 0109 lsls r1, r1, #4
+ 8003338: 430a orrs r2, r1
+ 800333a: 61da str r2, [r3, #28]
/* Configure the Output Fast mode */
htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
- 800332c: 68fb ldr r3, [r7, #12]
- 800332e: 681b ldr r3, [r3, #0]
- 8003330: 69da ldr r2, [r3, #28]
- 8003332: 68fb ldr r3, [r7, #12]
- 8003334: 681b ldr r3, [r3, #0]
- 8003336: 490f ldr r1, [pc, #60] ; (8003374 <HAL_TIM_PWM_ConfigChannel+0x188>)
- 8003338: 400a ands r2, r1
- 800333a: 61da str r2, [r3, #28]
- htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;
800333c: 68fb ldr r3, [r7, #12]
800333e: 681b ldr r3, [r3, #0]
- 8003340: 69d9 ldr r1, [r3, #28]
- 8003342: 68bb ldr r3, [r7, #8]
- 8003344: 68db ldr r3, [r3, #12]
- 8003346: 021a lsls r2, r3, #8
- 8003348: 68fb ldr r3, [r7, #12]
- 800334a: 681b ldr r3, [r3, #0]
- 800334c: 430a orrs r2, r1
- 800334e: 61da str r2, [r3, #28]
+ 8003340: 69da ldr r2, [r3, #28]
+ 8003342: 68fb ldr r3, [r7, #12]
+ 8003344: 681b ldr r3, [r3, #0]
+ 8003346: 490f ldr r1, [pc, #60] ; (8003384 <HAL_TIM_PWM_ConfigChannel+0x188>)
+ 8003348: 400a ands r2, r1
+ 800334a: 61da str r2, [r3, #28]
+ htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;
+ 800334c: 68fb ldr r3, [r7, #12]
+ 800334e: 681b ldr r3, [r3, #0]
+ 8003350: 69d9 ldr r1, [r3, #28]
+ 8003352: 68bb ldr r3, [r7, #8]
+ 8003354: 68db ldr r3, [r3, #12]
+ 8003356: 021a lsls r2, r3, #8
+ 8003358: 68fb ldr r3, [r7, #12]
+ 800335a: 681b ldr r3, [r3, #0]
+ 800335c: 430a orrs r2, r1
+ 800335e: 61da str r2, [r3, #28]
break;
- 8003350: e004 b.n 800335c <HAL_TIM_PWM_ConfigChannel+0x170>
+ 8003360: e004 b.n 800336c <HAL_TIM_PWM_ConfigChannel+0x170>
}
default:
status = HAL_ERROR;
- 8003352: 2317 movs r3, #23
- 8003354: 18fb adds r3, r7, r3
- 8003356: 2201 movs r2, #1
- 8003358: 701a strb r2, [r3, #0]
+ 8003362: 2317 movs r3, #23
+ 8003364: 18fb adds r3, r7, r3
+ 8003366: 2201 movs r2, #1
+ 8003368: 701a strb r2, [r3, #0]
break;
- 800335a: 46c0 nop ; (mov r8, r8)
+ 800336a: 46c0 nop ; (mov r8, r8)
}
__HAL_UNLOCK(htim);
- 800335c: 68fb ldr r3, [r7, #12]
- 800335e: 2238 movs r2, #56 ; 0x38
- 8003360: 2100 movs r1, #0
- 8003362: 5499 strb r1, [r3, r2]
+ 800336c: 68fb ldr r3, [r7, #12]
+ 800336e: 2238 movs r2, #56 ; 0x38
+ 8003370: 2100 movs r1, #0
+ 8003372: 5499 strb r1, [r3, r2]
return status;
- 8003364: 2317 movs r3, #23
- 8003366: 18fb adds r3, r7, r3
- 8003368: 781b ldrb r3, [r3, #0]
+ 8003374: 2317 movs r3, #23
+ 8003376: 18fb adds r3, r7, r3
+ 8003378: 781b ldrb r3, [r3, #0]
}
- 800336a: 0018 movs r0, r3
- 800336c: 46bd mov sp, r7
- 800336e: b006 add sp, #24
- 8003370: bd80 pop {r7, pc}
- 8003372: 46c0 nop ; (mov r8, r8)
- 8003374: fffffbff .word 0xfffffbff
+ 800337a: 0018 movs r0, r3
+ 800337c: 46bd mov sp, r7
+ 800337e: b006 add sp, #24
+ 8003380: bd80 pop {r7, pc}
+ 8003382: 46c0 nop ; (mov r8, r8)
+ 8003384: fffffbff .word 0xfffffbff
-08003378 <HAL_TIM_ConfigClockSource>:
+08003388 <HAL_TIM_ConfigClockSource>:
* @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that
* contains the clock source information for the TIM peripheral.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig)
{
- 8003378: b580 push {r7, lr}
- 800337a: b084 sub sp, #16
- 800337c: af00 add r7, sp, #0
- 800337e: 6078 str r0, [r7, #4]
- 8003380: 6039 str r1, [r7, #0]
+ 8003388: b580 push {r7, lr}
+ 800338a: b084 sub sp, #16
+ 800338c: af00 add r7, sp, #0
+ 800338e: 6078 str r0, [r7, #4]
+ 8003390: 6039 str r1, [r7, #0]
HAL_StatusTypeDef status = HAL_OK;
- 8003382: 230f movs r3, #15
- 8003384: 18fb adds r3, r7, r3
- 8003386: 2200 movs r2, #0
- 8003388: 701a strb r2, [r3, #0]
+ 8003392: 230f movs r3, #15
+ 8003394: 18fb adds r3, r7, r3
+ 8003396: 2200 movs r2, #0
+ 8003398: 701a strb r2, [r3, #0]
uint32_t tmpsmcr;
/* Process Locked */
__HAL_LOCK(htim);
- 800338a: 687b ldr r3, [r7, #4]
- 800338c: 2238 movs r2, #56 ; 0x38
- 800338e: 5c9b ldrb r3, [r3, r2]
- 8003390: 2b01 cmp r3, #1
- 8003392: d101 bne.n 8003398 <HAL_TIM_ConfigClockSource+0x20>
- 8003394: 2302 movs r3, #2
- 8003396: e0bc b.n 8003512 <HAL_TIM_ConfigClockSource+0x19a>
- 8003398: 687b ldr r3, [r7, #4]
- 800339a: 2238 movs r2, #56 ; 0x38
- 800339c: 2101 movs r1, #1
- 800339e: 5499 strb r1, [r3, r2]
+ 800339a: 687b ldr r3, [r7, #4]
+ 800339c: 2238 movs r2, #56 ; 0x38
+ 800339e: 5c9b ldrb r3, [r3, r2]
+ 80033a0: 2b01 cmp r3, #1
+ 80033a2: d101 bne.n 80033a8 <HAL_TIM_ConfigClockSource+0x20>
+ 80033a4: 2302 movs r3, #2
+ 80033a6: e0bc b.n 8003522 <HAL_TIM_ConfigClockSource+0x19a>
+ 80033a8: 687b ldr r3, [r7, #4]
+ 80033aa: 2238 movs r2, #56 ; 0x38
+ 80033ac: 2101 movs r1, #1
+ 80033ae: 5499 strb r1, [r3, r2]
htim->State = HAL_TIM_STATE_BUSY;
- 80033a0: 687b ldr r3, [r7, #4]
- 80033a2: 2239 movs r2, #57 ; 0x39
- 80033a4: 2102 movs r1, #2
- 80033a6: 5499 strb r1, [r3, r2]
+ 80033b0: 687b ldr r3, [r7, #4]
+ 80033b2: 2239 movs r2, #57 ; 0x39
+ 80033b4: 2102 movs r1, #2
+ 80033b6: 5499 strb r1, [r3, r2]
/* Check the parameters */
assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
/* Reset the SMS, TS, ECE, ETPS and ETRF bits */
tmpsmcr = htim->Instance->SMCR;
- 80033a8: 687b ldr r3, [r7, #4]
- 80033aa: 681b ldr r3, [r3, #0]
- 80033ac: 689b ldr r3, [r3, #8]
- 80033ae: 60bb str r3, [r7, #8]
- tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
- 80033b0: 68bb ldr r3, [r7, #8]
- 80033b2: 2277 movs r2, #119 ; 0x77
- 80033b4: 4393 bics r3, r2
- 80033b6: 60bb str r3, [r7, #8]
- tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
- 80033b8: 68bb ldr r3, [r7, #8]
- 80033ba: 4a58 ldr r2, [pc, #352] ; (800351c <HAL_TIM_ConfigClockSource+0x1a4>)
- 80033bc: 4013 ands r3, r2
+ 80033b8: 687b ldr r3, [r7, #4]
+ 80033ba: 681b ldr r3, [r3, #0]
+ 80033bc: 689b ldr r3, [r3, #8]
80033be: 60bb str r3, [r7, #8]
+ tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
+ 80033c0: 68bb ldr r3, [r7, #8]
+ 80033c2: 2277 movs r2, #119 ; 0x77
+ 80033c4: 4393 bics r3, r2
+ 80033c6: 60bb str r3, [r7, #8]
+ tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
+ 80033c8: 68bb ldr r3, [r7, #8]
+ 80033ca: 4a58 ldr r2, [pc, #352] ; (800352c <HAL_TIM_ConfigClockSource+0x1a4>)
+ 80033cc: 4013 ands r3, r2
+ 80033ce: 60bb str r3, [r7, #8]
htim->Instance->SMCR = tmpsmcr;
- 80033c0: 687b ldr r3, [r7, #4]
- 80033c2: 681b ldr r3, [r3, #0]
- 80033c4: 68ba ldr r2, [r7, #8]
- 80033c6: 609a str r2, [r3, #8]
+ 80033d0: 687b ldr r3, [r7, #4]
+ 80033d2: 681b ldr r3, [r3, #0]
+ 80033d4: 68ba ldr r2, [r7, #8]
+ 80033d6: 609a str r2, [r3, #8]
switch (sClockSourceConfig->ClockSource)
- 80033c8: 683b ldr r3, [r7, #0]
- 80033ca: 681b ldr r3, [r3, #0]
- 80033cc: 2280 movs r2, #128 ; 0x80
- 80033ce: 0192 lsls r2, r2, #6
- 80033d0: 4293 cmp r3, r2
- 80033d2: d040 beq.n 8003456 <HAL_TIM_ConfigClockSource+0xde>
- 80033d4: 2280 movs r2, #128 ; 0x80
- 80033d6: 0192 lsls r2, r2, #6
- 80033d8: 4293 cmp r3, r2
- 80033da: d900 bls.n 80033de <HAL_TIM_ConfigClockSource+0x66>
- 80033dc: e088 b.n 80034f0 <HAL_TIM_ConfigClockSource+0x178>
- 80033de: 2280 movs r2, #128 ; 0x80
- 80033e0: 0152 lsls r2, r2, #5
- 80033e2: 4293 cmp r3, r2
- 80033e4: d100 bne.n 80033e8 <HAL_TIM_ConfigClockSource+0x70>
- 80033e6: e088 b.n 80034fa <HAL_TIM_ConfigClockSource+0x182>
- 80033e8: 2280 movs r2, #128 ; 0x80
- 80033ea: 0152 lsls r2, r2, #5
- 80033ec: 4293 cmp r3, r2
- 80033ee: d900 bls.n 80033f2 <HAL_TIM_ConfigClockSource+0x7a>
- 80033f0: e07e b.n 80034f0 <HAL_TIM_ConfigClockSource+0x178>
- 80033f2: 2b70 cmp r3, #112 ; 0x70
- 80033f4: d018 beq.n 8003428 <HAL_TIM_ConfigClockSource+0xb0>
- 80033f6: d900 bls.n 80033fa <HAL_TIM_ConfigClockSource+0x82>
- 80033f8: e07a b.n 80034f0 <HAL_TIM_ConfigClockSource+0x178>
- 80033fa: 2b60 cmp r3, #96 ; 0x60
- 80033fc: d04f beq.n 800349e <HAL_TIM_ConfigClockSource+0x126>
- 80033fe: d900 bls.n 8003402 <HAL_TIM_ConfigClockSource+0x8a>
- 8003400: e076 b.n 80034f0 <HAL_TIM_ConfigClockSource+0x178>
- 8003402: 2b50 cmp r3, #80 ; 0x50
- 8003404: d03b beq.n 800347e <HAL_TIM_ConfigClockSource+0x106>
- 8003406: d900 bls.n 800340a <HAL_TIM_ConfigClockSource+0x92>
- 8003408: e072 b.n 80034f0 <HAL_TIM_ConfigClockSource+0x178>
- 800340a: 2b40 cmp r3, #64 ; 0x40
- 800340c: d057 beq.n 80034be <HAL_TIM_ConfigClockSource+0x146>
- 800340e: d900 bls.n 8003412 <HAL_TIM_ConfigClockSource+0x9a>
- 8003410: e06e b.n 80034f0 <HAL_TIM_ConfigClockSource+0x178>
- 8003412: 2b30 cmp r3, #48 ; 0x30
- 8003414: d063 beq.n 80034de <HAL_TIM_ConfigClockSource+0x166>
- 8003416: d86b bhi.n 80034f0 <HAL_TIM_ConfigClockSource+0x178>
- 8003418: 2b20 cmp r3, #32
- 800341a: d060 beq.n 80034de <HAL_TIM_ConfigClockSource+0x166>
- 800341c: d868 bhi.n 80034f0 <HAL_TIM_ConfigClockSource+0x178>
- 800341e: 2b00 cmp r3, #0
- 8003420: d05d beq.n 80034de <HAL_TIM_ConfigClockSource+0x166>
- 8003422: 2b10 cmp r3, #16
- 8003424: d05b beq.n 80034de <HAL_TIM_ConfigClockSource+0x166>
- 8003426: e063 b.n 80034f0 <HAL_TIM_ConfigClockSource+0x178>
+ 80033d8: 683b ldr r3, [r7, #0]
+ 80033da: 681b ldr r3, [r3, #0]
+ 80033dc: 2280 movs r2, #128 ; 0x80
+ 80033de: 0192 lsls r2, r2, #6
+ 80033e0: 4293 cmp r3, r2
+ 80033e2: d040 beq.n 8003466 <HAL_TIM_ConfigClockSource+0xde>
+ 80033e4: 2280 movs r2, #128 ; 0x80
+ 80033e6: 0192 lsls r2, r2, #6
+ 80033e8: 4293 cmp r3, r2
+ 80033ea: d900 bls.n 80033ee <HAL_TIM_ConfigClockSource+0x66>
+ 80033ec: e088 b.n 8003500 <HAL_TIM_ConfigClockSource+0x178>
+ 80033ee: 2280 movs r2, #128 ; 0x80
+ 80033f0: 0152 lsls r2, r2, #5
+ 80033f2: 4293 cmp r3, r2
+ 80033f4: d100 bne.n 80033f8 <HAL_TIM_ConfigClockSource+0x70>
+ 80033f6: e088 b.n 800350a <HAL_TIM_ConfigClockSource+0x182>
+ 80033f8: 2280 movs r2, #128 ; 0x80
+ 80033fa: 0152 lsls r2, r2, #5
+ 80033fc: 4293 cmp r3, r2
+ 80033fe: d900 bls.n 8003402 <HAL_TIM_ConfigClockSource+0x7a>
+ 8003400: e07e b.n 8003500 <HAL_TIM_ConfigClockSource+0x178>
+ 8003402: 2b70 cmp r3, #112 ; 0x70
+ 8003404: d018 beq.n 8003438 <HAL_TIM_ConfigClockSource+0xb0>
+ 8003406: d900 bls.n 800340a <HAL_TIM_ConfigClockSource+0x82>
+ 8003408: e07a b.n 8003500 <HAL_TIM_ConfigClockSource+0x178>
+ 800340a: 2b60 cmp r3, #96 ; 0x60
+ 800340c: d04f beq.n 80034ae <HAL_TIM_ConfigClockSource+0x126>
+ 800340e: d900 bls.n 8003412 <HAL_TIM_ConfigClockSource+0x8a>
+ 8003410: e076 b.n 8003500 <HAL_TIM_ConfigClockSource+0x178>
+ 8003412: 2b50 cmp r3, #80 ; 0x50
+ 8003414: d03b beq.n 800348e <HAL_TIM_ConfigClockSource+0x106>
+ 8003416: d900 bls.n 800341a <HAL_TIM_ConfigClockSource+0x92>
+ 8003418: e072 b.n 8003500 <HAL_TIM_ConfigClockSource+0x178>
+ 800341a: 2b40 cmp r3, #64 ; 0x40
+ 800341c: d057 beq.n 80034ce <HAL_TIM_ConfigClockSource+0x146>
+ 800341e: d900 bls.n 8003422 <HAL_TIM_ConfigClockSource+0x9a>
+ 8003420: e06e b.n 8003500 <HAL_TIM_ConfigClockSource+0x178>
+ 8003422: 2b30 cmp r3, #48 ; 0x30
+ 8003424: d063 beq.n 80034ee <HAL_TIM_ConfigClockSource+0x166>
+ 8003426: d86b bhi.n 8003500 <HAL_TIM_ConfigClockSource+0x178>
+ 8003428: 2b20 cmp r3, #32
+ 800342a: d060 beq.n 80034ee <HAL_TIM_ConfigClockSource+0x166>
+ 800342c: d868 bhi.n 8003500 <HAL_TIM_ConfigClockSource+0x178>
+ 800342e: 2b00 cmp r3, #0
+ 8003430: d05d beq.n 80034ee <HAL_TIM_ConfigClockSource+0x166>
+ 8003432: 2b10 cmp r3, #16
+ 8003434: d05b beq.n 80034ee <HAL_TIM_ConfigClockSource+0x166>
+ 8003436: e063 b.n 8003500 <HAL_TIM_ConfigClockSource+0x178>
assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
/* Configure the ETR Clock source */
TIM_ETR_SetConfig(htim->Instance,
- 8003428: 687b ldr r3, [r7, #4]
- 800342a: 6818 ldr r0, [r3, #0]
- 800342c: 683b ldr r3, [r7, #0]
- 800342e: 6899 ldr r1, [r3, #8]
- 8003430: 683b ldr r3, [r7, #0]
- 8003432: 685a ldr r2, [r3, #4]
- 8003434: 683b ldr r3, [r7, #0]
- 8003436: 68db ldr r3, [r3, #12]
- 8003438: f000 fa44 bl 80038c4 <TIM_ETR_SetConfig>
+ 8003438: 687b ldr r3, [r7, #4]
+ 800343a: 6818 ldr r0, [r3, #0]
+ 800343c: 683b ldr r3, [r7, #0]
+ 800343e: 6899 ldr r1, [r3, #8]
+ 8003440: 683b ldr r3, [r7, #0]
+ 8003442: 685a ldr r2, [r3, #4]
+ 8003444: 683b ldr r3, [r7, #0]
+ 8003446: 68db ldr r3, [r3, #12]
+ 8003448: f000 fa44 bl 80038d4 <TIM_ETR_SetConfig>
sClockSourceConfig->ClockPrescaler,
sClockSourceConfig->ClockPolarity,
sClockSourceConfig->ClockFilter);
/* Select the External clock mode1 and the ETRF trigger */
tmpsmcr = htim->Instance->SMCR;
- 800343c: 687b ldr r3, [r7, #4]
- 800343e: 681b ldr r3, [r3, #0]
- 8003440: 689b ldr r3, [r3, #8]
- 8003442: 60bb str r3, [r7, #8]
- tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
- 8003444: 68bb ldr r3, [r7, #8]
- 8003446: 2277 movs r2, #119 ; 0x77
- 8003448: 4313 orrs r3, r2
- 800344a: 60bb str r3, [r7, #8]
- /* Write to TIMx SMCR */
- htim->Instance->SMCR = tmpsmcr;
800344c: 687b ldr r3, [r7, #4]
800344e: 681b ldr r3, [r3, #0]
- 8003450: 68ba ldr r2, [r7, #8]
- 8003452: 609a str r2, [r3, #8]
+ 8003450: 689b ldr r3, [r3, #8]
+ 8003452: 60bb str r3, [r7, #8]
+ tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
+ 8003454: 68bb ldr r3, [r7, #8]
+ 8003456: 2277 movs r2, #119 ; 0x77
+ 8003458: 4313 orrs r3, r2
+ 800345a: 60bb str r3, [r7, #8]
+ /* Write to TIMx SMCR */
+ htim->Instance->SMCR = tmpsmcr;
+ 800345c: 687b ldr r3, [r7, #4]
+ 800345e: 681b ldr r3, [r3, #0]
+ 8003460: 68ba ldr r2, [r7, #8]
+ 8003462: 609a str r2, [r3, #8]
break;
- 8003454: e052 b.n 80034fc <HAL_TIM_ConfigClockSource+0x184>
+ 8003464: e052 b.n 800350c <HAL_TIM_ConfigClockSource+0x184>
assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
/* Configure the ETR Clock source */
TIM_ETR_SetConfig(htim->Instance,
- 8003456: 687b ldr r3, [r7, #4]
- 8003458: 6818 ldr r0, [r3, #0]
- 800345a: 683b ldr r3, [r7, #0]
- 800345c: 6899 ldr r1, [r3, #8]
- 800345e: 683b ldr r3, [r7, #0]
- 8003460: 685a ldr r2, [r3, #4]
- 8003462: 683b ldr r3, [r7, #0]
- 8003464: 68db ldr r3, [r3, #12]
- 8003466: f000 fa2d bl 80038c4 <TIM_ETR_SetConfig>
+ 8003466: 687b ldr r3, [r7, #4]
+ 8003468: 6818 ldr r0, [r3, #0]
+ 800346a: 683b ldr r3, [r7, #0]
+ 800346c: 6899 ldr r1, [r3, #8]
+ 800346e: 683b ldr r3, [r7, #0]
+ 8003470: 685a ldr r2, [r3, #4]
+ 8003472: 683b ldr r3, [r7, #0]
+ 8003474: 68db ldr r3, [r3, #12]
+ 8003476: f000 fa2d bl 80038d4 <TIM_ETR_SetConfig>
sClockSourceConfig->ClockPrescaler,
sClockSourceConfig->ClockPolarity,
sClockSourceConfig->ClockFilter);
/* Enable the External clock mode2 */
htim->Instance->SMCR |= TIM_SMCR_ECE;
- 800346a: 687b ldr r3, [r7, #4]
- 800346c: 681b ldr r3, [r3, #0]
- 800346e: 689a ldr r2, [r3, #8]
- 8003470: 687b ldr r3, [r7, #4]
- 8003472: 681b ldr r3, [r3, #0]
- 8003474: 2180 movs r1, #128 ; 0x80
- 8003476: 01c9 lsls r1, r1, #7
- 8003478: 430a orrs r2, r1
- 800347a: 609a str r2, [r3, #8]
+ 800347a: 687b ldr r3, [r7, #4]
+ 800347c: 681b ldr r3, [r3, #0]
+ 800347e: 689a ldr r2, [r3, #8]
+ 8003480: 687b ldr r3, [r7, #4]
+ 8003482: 681b ldr r3, [r3, #0]
+ 8003484: 2180 movs r1, #128 ; 0x80
+ 8003486: 01c9 lsls r1, r1, #7
+ 8003488: 430a orrs r2, r1
+ 800348a: 609a str r2, [r3, #8]
break;
- 800347c: e03e b.n 80034fc <HAL_TIM_ConfigClockSource+0x184>
+ 800348c: e03e b.n 800350c <HAL_TIM_ConfigClockSource+0x184>
/* Check TI1 input conditioning related parameters */
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
TIM_TI1_ConfigInputStage(htim->Instance,
- 800347e: 687b ldr r3, [r7, #4]
- 8003480: 6818 ldr r0, [r3, #0]
- 8003482: 683b ldr r3, [r7, #0]
- 8003484: 6859 ldr r1, [r3, #4]
- 8003486: 683b ldr r3, [r7, #0]
- 8003488: 68db ldr r3, [r3, #12]
- 800348a: 001a movs r2, r3
- 800348c: f000 f9a0 bl 80037d0 <TIM_TI1_ConfigInputStage>
+ 800348e: 687b ldr r3, [r7, #4]
+ 8003490: 6818 ldr r0, [r3, #0]
+ 8003492: 683b ldr r3, [r7, #0]
+ 8003494: 6859 ldr r1, [r3, #4]
+ 8003496: 683b ldr r3, [r7, #0]
+ 8003498: 68db ldr r3, [r3, #12]
+ 800349a: 001a movs r2, r3
+ 800349c: f000 f9a0 bl 80037e0 <TIM_TI1_ConfigInputStage>
sClockSourceConfig->ClockPolarity,
sClockSourceConfig->ClockFilter);
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
- 8003490: 687b ldr r3, [r7, #4]
- 8003492: 681b ldr r3, [r3, #0]
- 8003494: 2150 movs r1, #80 ; 0x50
- 8003496: 0018 movs r0, r3
- 8003498: f000 f9fa bl 8003890 <TIM_ITRx_SetConfig>
+ 80034a0: 687b ldr r3, [r7, #4]
+ 80034a2: 681b ldr r3, [r3, #0]
+ 80034a4: 2150 movs r1, #80 ; 0x50
+ 80034a6: 0018 movs r0, r3
+ 80034a8: f000 f9fa bl 80038a0 <TIM_ITRx_SetConfig>
break;
- 800349c: e02e b.n 80034fc <HAL_TIM_ConfigClockSource+0x184>
+ 80034ac: e02e b.n 800350c <HAL_TIM_ConfigClockSource+0x184>
/* Check TI2 input conditioning related parameters */
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
TIM_TI2_ConfigInputStage(htim->Instance,
- 800349e: 687b ldr r3, [r7, #4]
- 80034a0: 6818 ldr r0, [r3, #0]
- 80034a2: 683b ldr r3, [r7, #0]
- 80034a4: 6859 ldr r1, [r3, #4]
- 80034a6: 683b ldr r3, [r7, #0]
- 80034a8: 68db ldr r3, [r3, #12]
- 80034aa: 001a movs r2, r3
- 80034ac: f000 f9be bl 800382c <TIM_TI2_ConfigInputStage>
+ 80034ae: 687b ldr r3, [r7, #4]
+ 80034b0: 6818 ldr r0, [r3, #0]
+ 80034b2: 683b ldr r3, [r7, #0]
+ 80034b4: 6859 ldr r1, [r3, #4]
+ 80034b6: 683b ldr r3, [r7, #0]
+ 80034b8: 68db ldr r3, [r3, #12]
+ 80034ba: 001a movs r2, r3
+ 80034bc: f000 f9be bl 800383c <TIM_TI2_ConfigInputStage>
sClockSourceConfig->ClockPolarity,
sClockSourceConfig->ClockFilter);
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
- 80034b0: 687b ldr r3, [r7, #4]
- 80034b2: 681b ldr r3, [r3, #0]
- 80034b4: 2160 movs r1, #96 ; 0x60
- 80034b6: 0018 movs r0, r3
- 80034b8: f000 f9ea bl 8003890 <TIM_ITRx_SetConfig>
+ 80034c0: 687b ldr r3, [r7, #4]
+ 80034c2: 681b ldr r3, [r3, #0]
+ 80034c4: 2160 movs r1, #96 ; 0x60
+ 80034c6: 0018 movs r0, r3
+ 80034c8: f000 f9ea bl 80038a0 <TIM_ITRx_SetConfig>
break;
- 80034bc: e01e b.n 80034fc <HAL_TIM_ConfigClockSource+0x184>
+ 80034cc: e01e b.n 800350c <HAL_TIM_ConfigClockSource+0x184>
/* Check TI1 input conditioning related parameters */
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
TIM_TI1_ConfigInputStage(htim->Instance,
- 80034be: 687b ldr r3, [r7, #4]
- 80034c0: 6818 ldr r0, [r3, #0]
- 80034c2: 683b ldr r3, [r7, #0]
- 80034c4: 6859 ldr r1, [r3, #4]
- 80034c6: 683b ldr r3, [r7, #0]
- 80034c8: 68db ldr r3, [r3, #12]
- 80034ca: 001a movs r2, r3
- 80034cc: f000 f980 bl 80037d0 <TIM_TI1_ConfigInputStage>
+ 80034ce: 687b ldr r3, [r7, #4]
+ 80034d0: 6818 ldr r0, [r3, #0]
+ 80034d2: 683b ldr r3, [r7, #0]
+ 80034d4: 6859 ldr r1, [r3, #4]
+ 80034d6: 683b ldr r3, [r7, #0]
+ 80034d8: 68db ldr r3, [r3, #12]
+ 80034da: 001a movs r2, r3
+ 80034dc: f000 f980 bl 80037e0 <TIM_TI1_ConfigInputStage>
sClockSourceConfig->ClockPolarity,
sClockSourceConfig->ClockFilter);
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
- 80034d0: 687b ldr r3, [r7, #4]
- 80034d2: 681b ldr r3, [r3, #0]
- 80034d4: 2140 movs r1, #64 ; 0x40
- 80034d6: 0018 movs r0, r3
- 80034d8: f000 f9da bl 8003890 <TIM_ITRx_SetConfig>
+ 80034e0: 687b ldr r3, [r7, #4]
+ 80034e2: 681b ldr r3, [r3, #0]
+ 80034e4: 2140 movs r1, #64 ; 0x40
+ 80034e6: 0018 movs r0, r3
+ 80034e8: f000 f9da bl 80038a0 <TIM_ITRx_SetConfig>
break;
- 80034dc: e00e b.n 80034fc <HAL_TIM_ConfigClockSource+0x184>
+ 80034ec: e00e b.n 800350c <HAL_TIM_ConfigClockSource+0x184>
case TIM_CLOCKSOURCE_ITR3:
{
/* Check whether or not the timer instance supports internal trigger input */
assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
- 80034de: 687b ldr r3, [r7, #4]
- 80034e0: 681a ldr r2, [r3, #0]
- 80034e2: 683b ldr r3, [r7, #0]
- 80034e4: 681b ldr r3, [r3, #0]
- 80034e6: 0019 movs r1, r3
- 80034e8: 0010 movs r0, r2
- 80034ea: f000 f9d1 bl 8003890 <TIM_ITRx_SetConfig>
+ 80034ee: 687b ldr r3, [r7, #4]
+ 80034f0: 681a ldr r2, [r3, #0]
+ 80034f2: 683b ldr r3, [r7, #0]
+ 80034f4: 681b ldr r3, [r3, #0]
+ 80034f6: 0019 movs r1, r3
+ 80034f8: 0010 movs r0, r2
+ 80034fa: f000 f9d1 bl 80038a0 <TIM_ITRx_SetConfig>
break;
- 80034ee: e005 b.n 80034fc <HAL_TIM_ConfigClockSource+0x184>
+ 80034fe: e005 b.n 800350c <HAL_TIM_ConfigClockSource+0x184>
}
default:
status = HAL_ERROR;
- 80034f0: 230f movs r3, #15
- 80034f2: 18fb adds r3, r7, r3
- 80034f4: 2201 movs r2, #1
- 80034f6: 701a strb r2, [r3, #0]
+ 8003500: 230f movs r3, #15
+ 8003502: 18fb adds r3, r7, r3
+ 8003504: 2201 movs r2, #1
+ 8003506: 701a strb r2, [r3, #0]
break;
- 80034f8: e000 b.n 80034fc <HAL_TIM_ConfigClockSource+0x184>
+ 8003508: e000 b.n 800350c <HAL_TIM_ConfigClockSource+0x184>
break;
- 80034fa: 46c0 nop ; (mov r8, r8)
+ 800350a: 46c0 nop ; (mov r8, r8)
}
htim->State = HAL_TIM_STATE_READY;
- 80034fc: 687b ldr r3, [r7, #4]
- 80034fe: 2239 movs r2, #57 ; 0x39
- 8003500: 2101 movs r1, #1
- 8003502: 5499 strb r1, [r3, r2]
+ 800350c: 687b ldr r3, [r7, #4]
+ 800350e: 2239 movs r2, #57 ; 0x39
+ 8003510: 2101 movs r1, #1
+ 8003512: 5499 strb r1, [r3, r2]
__HAL_UNLOCK(htim);
- 8003504: 687b ldr r3, [r7, #4]
- 8003506: 2238 movs r2, #56 ; 0x38
- 8003508: 2100 movs r1, #0
- 800350a: 5499 strb r1, [r3, r2]
+ 8003514: 687b ldr r3, [r7, #4]
+ 8003516: 2238 movs r2, #56 ; 0x38
+ 8003518: 2100 movs r1, #0
+ 800351a: 5499 strb r1, [r3, r2]
return status;
- 800350c: 230f movs r3, #15
- 800350e: 18fb adds r3, r7, r3
- 8003510: 781b ldrb r3, [r3, #0]
+ 800351c: 230f movs r3, #15
+ 800351e: 18fb adds r3, r7, r3
+ 8003520: 781b ldrb r3, [r3, #0]
}
- 8003512: 0018 movs r0, r3
- 8003514: 46bd mov sp, r7
- 8003516: b004 add sp, #16
- 8003518: bd80 pop {r7, pc}
- 800351a: 46c0 nop ; (mov r8, r8)
- 800351c: ffff00ff .word 0xffff00ff
+ 8003522: 0018 movs r0, r3
+ 8003524: 46bd mov sp, r7
+ 8003526: b004 add sp, #16
+ 8003528: bd80 pop {r7, pc}
+ 800352a: 46c0 nop ; (mov r8, r8)
+ 800352c: ffff00ff .word 0xffff00ff
-08003520 <TIM_Base_SetConfig>:
+08003530 <TIM_Base_SetConfig>:
* @param TIMx TIM peripheral
* @param Structure TIM Base configuration structure
* @retval None
*/
static void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
{
- 8003520: b580 push {r7, lr}
- 8003522: b084 sub sp, #16
- 8003524: af00 add r7, sp, #0
- 8003526: 6078 str r0, [r7, #4]
- 8003528: 6039 str r1, [r7, #0]
+ 8003530: b580 push {r7, lr}
+ 8003532: b084 sub sp, #16
+ 8003534: af00 add r7, sp, #0
+ 8003536: 6078 str r0, [r7, #4]
+ 8003538: 6039 str r1, [r7, #0]
uint32_t tmpcr1;
tmpcr1 = TIMx->CR1;
- 800352a: 687b ldr r3, [r7, #4]
- 800352c: 681b ldr r3, [r3, #0]
- 800352e: 60fb str r3, [r7, #12]
+ 800353a: 687b ldr r3, [r7, #4]
+ 800353c: 681b ldr r3, [r3, #0]
+ 800353e: 60fb str r3, [r7, #12]
/* Set TIM Time Base Unit parameters ---------------------------------------*/
if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
- 8003530: 687a ldr r2, [r7, #4]
- 8003532: 2380 movs r3, #128 ; 0x80
- 8003534: 05db lsls r3, r3, #23
- 8003536: 429a cmp r2, r3
- 8003538: d007 beq.n 800354a <TIM_Base_SetConfig+0x2a>
- 800353a: 687b ldr r3, [r7, #4]
- 800353c: 4a1f ldr r2, [pc, #124] ; (80035bc <TIM_Base_SetConfig+0x9c>)
- 800353e: 4293 cmp r3, r2
- 8003540: d003 beq.n 800354a <TIM_Base_SetConfig+0x2a>
- 8003542: 687b ldr r3, [r7, #4]
- 8003544: 4a1e ldr r2, [pc, #120] ; (80035c0 <TIM_Base_SetConfig+0xa0>)
- 8003546: 4293 cmp r3, r2
- 8003548: d108 bne.n 800355c <TIM_Base_SetConfig+0x3c>
+ 8003540: 687a ldr r2, [r7, #4]
+ 8003542: 2380 movs r3, #128 ; 0x80
+ 8003544: 05db lsls r3, r3, #23
+ 8003546: 429a cmp r2, r3
+ 8003548: d007 beq.n 800355a <TIM_Base_SetConfig+0x2a>
+ 800354a: 687b ldr r3, [r7, #4]
+ 800354c: 4a1f ldr r2, [pc, #124] ; (80035cc <TIM_Base_SetConfig+0x9c>)
+ 800354e: 4293 cmp r3, r2
+ 8003550: d003 beq.n 800355a <TIM_Base_SetConfig+0x2a>
+ 8003552: 687b ldr r3, [r7, #4]
+ 8003554: 4a1e ldr r2, [pc, #120] ; (80035d0 <TIM_Base_SetConfig+0xa0>)
+ 8003556: 4293 cmp r3, r2
+ 8003558: d108 bne.n 800356c <TIM_Base_SetConfig+0x3c>
{
/* Select the Counter Mode */
tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
- 800354a: 68fb ldr r3, [r7, #12]
- 800354c: 2270 movs r2, #112 ; 0x70
- 800354e: 4393 bics r3, r2
- 8003550: 60fb str r3, [r7, #12]
+ 800355a: 68fb ldr r3, [r7, #12]
+ 800355c: 2270 movs r2, #112 ; 0x70
+ 800355e: 4393 bics r3, r2
+ 8003560: 60fb str r3, [r7, #12]
tmpcr1 |= Structure->CounterMode;
- 8003552: 683b ldr r3, [r7, #0]
- 8003554: 685b ldr r3, [r3, #4]
- 8003556: 68fa ldr r2, [r7, #12]
- 8003558: 4313 orrs r3, r2
- 800355a: 60fb str r3, [r7, #12]
+ 8003562: 683b ldr r3, [r7, #0]
+ 8003564: 685b ldr r3, [r3, #4]
+ 8003566: 68fa ldr r2, [r7, #12]
+ 8003568: 4313 orrs r3, r2
+ 800356a: 60fb str r3, [r7, #12]
}
if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
- 800355c: 687a ldr r2, [r7, #4]
- 800355e: 2380 movs r3, #128 ; 0x80
- 8003560: 05db lsls r3, r3, #23
- 8003562: 429a cmp r2, r3
- 8003564: d007 beq.n 8003576 <TIM_Base_SetConfig+0x56>
- 8003566: 687b ldr r3, [r7, #4]
- 8003568: 4a14 ldr r2, [pc, #80] ; (80035bc <TIM_Base_SetConfig+0x9c>)
- 800356a: 4293 cmp r3, r2
- 800356c: d003 beq.n 8003576 <TIM_Base_SetConfig+0x56>
- 800356e: 687b ldr r3, [r7, #4]
- 8003570: 4a13 ldr r2, [pc, #76] ; (80035c0 <TIM_Base_SetConfig+0xa0>)
- 8003572: 4293 cmp r3, r2
- 8003574: d108 bne.n 8003588 <TIM_Base_SetConfig+0x68>
+ 800356c: 687a ldr r2, [r7, #4]
+ 800356e: 2380 movs r3, #128 ; 0x80
+ 8003570: 05db lsls r3, r3, #23
+ 8003572: 429a cmp r2, r3
+ 8003574: d007 beq.n 8003586 <TIM_Base_SetConfig+0x56>
+ 8003576: 687b ldr r3, [r7, #4]
+ 8003578: 4a14 ldr r2, [pc, #80] ; (80035cc <TIM_Base_SetConfig+0x9c>)
+ 800357a: 4293 cmp r3, r2
+ 800357c: d003 beq.n 8003586 <TIM_Base_SetConfig+0x56>
+ 800357e: 687b ldr r3, [r7, #4]
+ 8003580: 4a13 ldr r2, [pc, #76] ; (80035d0 <TIM_Base_SetConfig+0xa0>)
+ 8003582: 4293 cmp r3, r2
+ 8003584: d108 bne.n 8003598 <TIM_Base_SetConfig+0x68>
{
/* Set the clock division */
tmpcr1 &= ~TIM_CR1_CKD;
- 8003576: 68fb ldr r3, [r7, #12]
- 8003578: 4a12 ldr r2, [pc, #72] ; (80035c4 <TIM_Base_SetConfig+0xa4>)
- 800357a: 4013 ands r3, r2
- 800357c: 60fb str r3, [r7, #12]
+ 8003586: 68fb ldr r3, [r7, #12]
+ 8003588: 4a12 ldr r2, [pc, #72] ; (80035d4 <TIM_Base_SetConfig+0xa4>)
+ 800358a: 4013 ands r3, r2
+ 800358c: 60fb str r3, [r7, #12]
tmpcr1 |= (uint32_t)Structure->ClockDivision;
- 800357e: 683b ldr r3, [r7, #0]
- 8003580: 68db ldr r3, [r3, #12]
- 8003582: 68fa ldr r2, [r7, #12]
- 8003584: 4313 orrs r3, r2
- 8003586: 60fb str r3, [r7, #12]
+ 800358e: 683b ldr r3, [r7, #0]
+ 8003590: 68db ldr r3, [r3, #12]
+ 8003592: 68fa ldr r2, [r7, #12]
+ 8003594: 4313 orrs r3, r2
+ 8003596: 60fb str r3, [r7, #12]
}
/* Set the auto-reload preload */
MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
- 8003588: 68fb ldr r3, [r7, #12]
- 800358a: 2280 movs r2, #128 ; 0x80
- 800358c: 4393 bics r3, r2
- 800358e: 001a movs r2, r3
- 8003590: 683b ldr r3, [r7, #0]
- 8003592: 691b ldr r3, [r3, #16]
- 8003594: 4313 orrs r3, r2
- 8003596: 60fb str r3, [r7, #12]
+ 8003598: 68fb ldr r3, [r7, #12]
+ 800359a: 2280 movs r2, #128 ; 0x80
+ 800359c: 4393 bics r3, r2
+ 800359e: 001a movs r2, r3
+ 80035a0: 683b ldr r3, [r7, #0]
+ 80035a2: 691b ldr r3, [r3, #16]
+ 80035a4: 4313 orrs r3, r2
+ 80035a6: 60fb str r3, [r7, #12]
TIMx->CR1 = tmpcr1;
- 8003598: 687b ldr r3, [r7, #4]
- 800359a: 68fa ldr r2, [r7, #12]
- 800359c: 601a str r2, [r3, #0]
+ 80035a8: 687b ldr r3, [r7, #4]
+ 80035aa: 68fa ldr r2, [r7, #12]
+ 80035ac: 601a str r2, [r3, #0]
/* Set the Autoreload value */
TIMx->ARR = (uint32_t)Structure->Period ;
- 800359e: 683b ldr r3, [r7, #0]
- 80035a0: 689a ldr r2, [r3, #8]
- 80035a2: 687b ldr r3, [r7, #4]
- 80035a4: 62da str r2, [r3, #44] ; 0x2c
+ 80035ae: 683b ldr r3, [r7, #0]
+ 80035b0: 689a ldr r2, [r3, #8]
+ 80035b2: 687b ldr r3, [r7, #4]
+ 80035b4: 62da str r2, [r3, #44] ; 0x2c
/* Set the Prescaler value */
TIMx->PSC = Structure->Prescaler;
- 80035a6: 683b ldr r3, [r7, #0]
- 80035a8: 681a ldr r2, [r3, #0]
- 80035aa: 687b ldr r3, [r7, #4]
- 80035ac: 629a str r2, [r3, #40] ; 0x28
+ 80035b6: 683b ldr r3, [r7, #0]
+ 80035b8: 681a ldr r2, [r3, #0]
+ 80035ba: 687b ldr r3, [r7, #4]
+ 80035bc: 629a str r2, [r3, #40] ; 0x28
/* Generate an update event to reload the Prescaler
and the repetition counter (only for advanced timer) value immediately */
TIMx->EGR = TIM_EGR_UG;
- 80035ae: 687b ldr r3, [r7, #4]
- 80035b0: 2201 movs r2, #1
- 80035b2: 615a str r2, [r3, #20]
+ 80035be: 687b ldr r3, [r7, #4]
+ 80035c0: 2201 movs r2, #1
+ 80035c2: 615a str r2, [r3, #20]
}
- 80035b4: 46c0 nop ; (mov r8, r8)
- 80035b6: 46bd mov sp, r7
- 80035b8: b004 add sp, #16
- 80035ba: bd80 pop {r7, pc}
- 80035bc: 40010800 .word 0x40010800
- 80035c0: 40011400 .word 0x40011400
- 80035c4: fffffcff .word 0xfffffcff
+ 80035c4: 46c0 nop ; (mov r8, r8)
+ 80035c6: 46bd mov sp, r7
+ 80035c8: b004 add sp, #16
+ 80035ca: bd80 pop {r7, pc}
+ 80035cc: 40010800 .word 0x40010800
+ 80035d0: 40011400 .word 0x40011400
+ 80035d4: fffffcff .word 0xfffffcff
-080035c8 <TIM_OC1_SetConfig>:
+080035d8 <TIM_OC1_SetConfig>:
* @param TIMx to select the TIM peripheral
* @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
{
- 80035c8: b580 push {r7, lr}
- 80035ca: b086 sub sp, #24
- 80035cc: af00 add r7, sp, #0
- 80035ce: 6078 str r0, [r7, #4]
- 80035d0: 6039 str r1, [r7, #0]
+ 80035d8: b580 push {r7, lr}
+ 80035da: b086 sub sp, #24
+ 80035dc: af00 add r7, sp, #0
+ 80035de: 6078 str r0, [r7, #4]
+ 80035e0: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Disable the Channel 1: Reset the CC1E Bit */
TIMx->CCER &= ~TIM_CCER_CC1E;
- 80035d2: 687b ldr r3, [r7, #4]
- 80035d4: 6a1b ldr r3, [r3, #32]
- 80035d6: 2201 movs r2, #1
- 80035d8: 4393 bics r3, r2
- 80035da: 001a movs r2, r3
- 80035dc: 687b ldr r3, [r7, #4]
- 80035de: 621a str r2, [r3, #32]
+ 80035e2: 687b ldr r3, [r7, #4]
+ 80035e4: 6a1b ldr r3, [r3, #32]
+ 80035e6: 2201 movs r2, #1
+ 80035e8: 4393 bics r3, r2
+ 80035ea: 001a movs r2, r3
+ 80035ec: 687b ldr r3, [r7, #4]
+ 80035ee: 621a str r2, [r3, #32]
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
- 80035e0: 687b ldr r3, [r7, #4]
- 80035e2: 6a1b ldr r3, [r3, #32]
- 80035e4: 617b str r3, [r7, #20]
+ 80035f0: 687b ldr r3, [r7, #4]
+ 80035f2: 6a1b ldr r3, [r3, #32]
+ 80035f4: 617b str r3, [r7, #20]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
- 80035e6: 687b ldr r3, [r7, #4]
- 80035e8: 685b ldr r3, [r3, #4]
- 80035ea: 613b str r3, [r7, #16]
+ 80035f6: 687b ldr r3, [r7, #4]
+ 80035f8: 685b ldr r3, [r3, #4]
+ 80035fa: 613b str r3, [r7, #16]
/* Get the TIMx CCMR1 register value */
tmpccmrx = TIMx->CCMR1;
- 80035ec: 687b ldr r3, [r7, #4]
- 80035ee: 699b ldr r3, [r3, #24]
- 80035f0: 60fb str r3, [r7, #12]
+ 80035fc: 687b ldr r3, [r7, #4]
+ 80035fe: 699b ldr r3, [r3, #24]
+ 8003600: 60fb str r3, [r7, #12]
/* Reset the Output Compare Mode Bits */
tmpccmrx &= ~TIM_CCMR1_OC1M;
- 80035f2: 68fb ldr r3, [r7, #12]
- 80035f4: 2270 movs r2, #112 ; 0x70
- 80035f6: 4393 bics r3, r2
- 80035f8: 60fb str r3, [r7, #12]
+ 8003602: 68fb ldr r3, [r7, #12]
+ 8003604: 2270 movs r2, #112 ; 0x70
+ 8003606: 4393 bics r3, r2
+ 8003608: 60fb str r3, [r7, #12]
tmpccmrx &= ~TIM_CCMR1_CC1S;
- 80035fa: 68fb ldr r3, [r7, #12]
- 80035fc: 2203 movs r2, #3
- 80035fe: 4393 bics r3, r2
- 8003600: 60fb str r3, [r7, #12]
+ 800360a: 68fb ldr r3, [r7, #12]
+ 800360c: 2203 movs r2, #3
+ 800360e: 4393 bics r3, r2
+ 8003610: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= OC_Config->OCMode;
- 8003602: 683b ldr r3, [r7, #0]
- 8003604: 681b ldr r3, [r3, #0]
- 8003606: 68fa ldr r2, [r7, #12]
- 8003608: 4313 orrs r3, r2
- 800360a: 60fb str r3, [r7, #12]
+ 8003612: 683b ldr r3, [r7, #0]
+ 8003614: 681b ldr r3, [r3, #0]
+ 8003616: 68fa ldr r2, [r7, #12]
+ 8003618: 4313 orrs r3, r2
+ 800361a: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC1P;
- 800360c: 697b ldr r3, [r7, #20]
- 800360e: 2202 movs r2, #2
- 8003610: 4393 bics r3, r2
- 8003612: 617b str r3, [r7, #20]
+ 800361c: 697b ldr r3, [r7, #20]
+ 800361e: 2202 movs r2, #2
+ 8003620: 4393 bics r3, r2
+ 8003622: 617b str r3, [r7, #20]
/* Set the Output Compare Polarity */
tmpccer |= OC_Config->OCPolarity;
- 8003614: 683b ldr r3, [r7, #0]
- 8003616: 689b ldr r3, [r3, #8]
- 8003618: 697a ldr r2, [r7, #20]
- 800361a: 4313 orrs r3, r2
- 800361c: 617b str r3, [r7, #20]
+ 8003624: 683b ldr r3, [r7, #0]
+ 8003626: 689b ldr r3, [r3, #8]
+ 8003628: 697a ldr r2, [r7, #20]
+ 800362a: 4313 orrs r3, r2
+ 800362c: 617b str r3, [r7, #20]
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
- 800361e: 687b ldr r3, [r7, #4]
- 8003620: 693a ldr r2, [r7, #16]
- 8003622: 605a str r2, [r3, #4]
+ 800362e: 687b ldr r3, [r7, #4]
+ 8003630: 693a ldr r2, [r7, #16]
+ 8003632: 605a str r2, [r3, #4]
/* Write to TIMx CCMR1 */
TIMx->CCMR1 = tmpccmrx;
- 8003624: 687b ldr r3, [r7, #4]
- 8003626: 68fa ldr r2, [r7, #12]
- 8003628: 619a str r2, [r3, #24]
+ 8003634: 687b ldr r3, [r7, #4]
+ 8003636: 68fa ldr r2, [r7, #12]
+ 8003638: 619a str r2, [r3, #24]
/* Set the Capture Compare Register value */
TIMx->CCR1 = OC_Config->Pulse;
- 800362a: 683b ldr r3, [r7, #0]
- 800362c: 685a ldr r2, [r3, #4]
- 800362e: 687b ldr r3, [r7, #4]
- 8003630: 635a str r2, [r3, #52] ; 0x34
+ 800363a: 683b ldr r3, [r7, #0]
+ 800363c: 685a ldr r2, [r3, #4]
+ 800363e: 687b ldr r3, [r7, #4]
+ 8003640: 635a str r2, [r3, #52] ; 0x34
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
- 8003632: 687b ldr r3, [r7, #4]
- 8003634: 697a ldr r2, [r7, #20]
- 8003636: 621a str r2, [r3, #32]
+ 8003642: 687b ldr r3, [r7, #4]
+ 8003644: 697a ldr r2, [r7, #20]
+ 8003646: 621a str r2, [r3, #32]
}
- 8003638: 46c0 nop ; (mov r8, r8)
- 800363a: 46bd mov sp, r7
- 800363c: b006 add sp, #24
- 800363e: bd80 pop {r7, pc}
+ 8003648: 46c0 nop ; (mov r8, r8)
+ 800364a: 46bd mov sp, r7
+ 800364c: b006 add sp, #24
+ 800364e: bd80 pop {r7, pc}
-08003640 <TIM_OC2_SetConfig>:
+08003650 <TIM_OC2_SetConfig>:
* @param TIMx to select the TIM peripheral
* @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
{
- 8003640: b580 push {r7, lr}
- 8003642: b086 sub sp, #24
- 8003644: af00 add r7, sp, #0
- 8003646: 6078 str r0, [r7, #4]
- 8003648: 6039 str r1, [r7, #0]
+ 8003650: b580 push {r7, lr}
+ 8003652: b086 sub sp, #24
+ 8003654: af00 add r7, sp, #0
+ 8003656: 6078 str r0, [r7, #4]
+ 8003658: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Disable the Channel 2: Reset the CC2E Bit */
TIMx->CCER &= ~TIM_CCER_CC2E;
- 800364a: 687b ldr r3, [r7, #4]
- 800364c: 6a1b ldr r3, [r3, #32]
- 800364e: 2210 movs r2, #16
- 8003650: 4393 bics r3, r2
- 8003652: 001a movs r2, r3
- 8003654: 687b ldr r3, [r7, #4]
- 8003656: 621a str r2, [r3, #32]
+ 800365a: 687b ldr r3, [r7, #4]
+ 800365c: 6a1b ldr r3, [r3, #32]
+ 800365e: 2210 movs r2, #16
+ 8003660: 4393 bics r3, r2
+ 8003662: 001a movs r2, r3
+ 8003664: 687b ldr r3, [r7, #4]
+ 8003666: 621a str r2, [r3, #32]
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
- 8003658: 687b ldr r3, [r7, #4]
- 800365a: 6a1b ldr r3, [r3, #32]
- 800365c: 617b str r3, [r7, #20]
+ 8003668: 687b ldr r3, [r7, #4]
+ 800366a: 6a1b ldr r3, [r3, #32]
+ 800366c: 617b str r3, [r7, #20]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
- 800365e: 687b ldr r3, [r7, #4]
- 8003660: 685b ldr r3, [r3, #4]
- 8003662: 613b str r3, [r7, #16]
+ 800366e: 687b ldr r3, [r7, #4]
+ 8003670: 685b ldr r3, [r3, #4]
+ 8003672: 613b str r3, [r7, #16]
/* Get the TIMx CCMR1 register value */
tmpccmrx = TIMx->CCMR1;
- 8003664: 687b ldr r3, [r7, #4]
- 8003666: 699b ldr r3, [r3, #24]
- 8003668: 60fb str r3, [r7, #12]
+ 8003674: 687b ldr r3, [r7, #4]
+ 8003676: 699b ldr r3, [r3, #24]
+ 8003678: 60fb str r3, [r7, #12]
/* Reset the Output Compare mode and Capture/Compare selection Bits */
tmpccmrx &= ~TIM_CCMR1_OC2M;
- 800366a: 68fb ldr r3, [r7, #12]
- 800366c: 4a13 ldr r2, [pc, #76] ; (80036bc <TIM_OC2_SetConfig+0x7c>)
- 800366e: 4013 ands r3, r2
- 8003670: 60fb str r3, [r7, #12]
+ 800367a: 68fb ldr r3, [r7, #12]
+ 800367c: 4a13 ldr r2, [pc, #76] ; (80036cc <TIM_OC2_SetConfig+0x7c>)
+ 800367e: 4013 ands r3, r2
+ 8003680: 60fb str r3, [r7, #12]
tmpccmrx &= ~TIM_CCMR1_CC2S;
- 8003672: 68fb ldr r3, [r7, #12]
- 8003674: 4a12 ldr r2, [pc, #72] ; (80036c0 <TIM_OC2_SetConfig+0x80>)
- 8003676: 4013 ands r3, r2
- 8003678: 60fb str r3, [r7, #12]
+ 8003682: 68fb ldr r3, [r7, #12]
+ 8003684: 4a12 ldr r2, [pc, #72] ; (80036d0 <TIM_OC2_SetConfig+0x80>)
+ 8003686: 4013 ands r3, r2
+ 8003688: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= (OC_Config->OCMode << 8U);
- 800367a: 683b ldr r3, [r7, #0]
- 800367c: 681b ldr r3, [r3, #0]
- 800367e: 021b lsls r3, r3, #8
- 8003680: 68fa ldr r2, [r7, #12]
- 8003682: 4313 orrs r3, r2
- 8003684: 60fb str r3, [r7, #12]
+ 800368a: 683b ldr r3, [r7, #0]
+ 800368c: 681b ldr r3, [r3, #0]
+ 800368e: 021b lsls r3, r3, #8
+ 8003690: 68fa ldr r2, [r7, #12]
+ 8003692: 4313 orrs r3, r2
+ 8003694: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC2P;
- 8003686: 697b ldr r3, [r7, #20]
- 8003688: 2220 movs r2, #32
- 800368a: 4393 bics r3, r2
- 800368c: 617b str r3, [r7, #20]
+ 8003696: 697b ldr r3, [r7, #20]
+ 8003698: 2220 movs r2, #32
+ 800369a: 4393 bics r3, r2
+ 800369c: 617b str r3, [r7, #20]
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 4U);
- 800368e: 683b ldr r3, [r7, #0]
- 8003690: 689b ldr r3, [r3, #8]
- 8003692: 011b lsls r3, r3, #4
- 8003694: 697a ldr r2, [r7, #20]
- 8003696: 4313 orrs r3, r2
- 8003698: 617b str r3, [r7, #20]
+ 800369e: 683b ldr r3, [r7, #0]
+ 80036a0: 689b ldr r3, [r3, #8]
+ 80036a2: 011b lsls r3, r3, #4
+ 80036a4: 697a ldr r2, [r7, #20]
+ 80036a6: 4313 orrs r3, r2
+ 80036a8: 617b str r3, [r7, #20]
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
- 800369a: 687b ldr r3, [r7, #4]
- 800369c: 693a ldr r2, [r7, #16]
- 800369e: 605a str r2, [r3, #4]
+ 80036aa: 687b ldr r3, [r7, #4]
+ 80036ac: 693a ldr r2, [r7, #16]
+ 80036ae: 605a str r2, [r3, #4]
/* Write to TIMx CCMR1 */
TIMx->CCMR1 = tmpccmrx;
- 80036a0: 687b ldr r3, [r7, #4]
- 80036a2: 68fa ldr r2, [r7, #12]
- 80036a4: 619a str r2, [r3, #24]
+ 80036b0: 687b ldr r3, [r7, #4]
+ 80036b2: 68fa ldr r2, [r7, #12]
+ 80036b4: 619a str r2, [r3, #24]
/* Set the Capture Compare Register value */
TIMx->CCR2 = OC_Config->Pulse;
- 80036a6: 683b ldr r3, [r7, #0]
- 80036a8: 685a ldr r2, [r3, #4]
- 80036aa: 687b ldr r3, [r7, #4]
- 80036ac: 639a str r2, [r3, #56] ; 0x38
+ 80036b6: 683b ldr r3, [r7, #0]
+ 80036b8: 685a ldr r2, [r3, #4]
+ 80036ba: 687b ldr r3, [r7, #4]
+ 80036bc: 639a str r2, [r3, #56] ; 0x38
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
- 80036ae: 687b ldr r3, [r7, #4]
- 80036b0: 697a ldr r2, [r7, #20]
- 80036b2: 621a str r2, [r3, #32]
+ 80036be: 687b ldr r3, [r7, #4]
+ 80036c0: 697a ldr r2, [r7, #20]
+ 80036c2: 621a str r2, [r3, #32]
}
- 80036b4: 46c0 nop ; (mov r8, r8)
- 80036b6: 46bd mov sp, r7
- 80036b8: b006 add sp, #24
- 80036ba: bd80 pop {r7, pc}
- 80036bc: ffff8fff .word 0xffff8fff
- 80036c0: fffffcff .word 0xfffffcff
+ 80036c4: 46c0 nop ; (mov r8, r8)
+ 80036c6: 46bd mov sp, r7
+ 80036c8: b006 add sp, #24
+ 80036ca: bd80 pop {r7, pc}
+ 80036cc: ffff8fff .word 0xffff8fff
+ 80036d0: fffffcff .word 0xfffffcff
-080036c4 <TIM_OC3_SetConfig>:
+080036d4 <TIM_OC3_SetConfig>:
* @param TIMx to select the TIM peripheral
* @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
{
- 80036c4: b580 push {r7, lr}
- 80036c6: b086 sub sp, #24
- 80036c8: af00 add r7, sp, #0
- 80036ca: 6078 str r0, [r7, #4]
- 80036cc: 6039 str r1, [r7, #0]
+ 80036d4: b580 push {r7, lr}
+ 80036d6: b086 sub sp, #24
+ 80036d8: af00 add r7, sp, #0
+ 80036da: 6078 str r0, [r7, #4]
+ 80036dc: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Disable the Channel 3: Reset the CC2E Bit */
TIMx->CCER &= ~TIM_CCER_CC3E;
- 80036ce: 687b ldr r3, [r7, #4]
- 80036d0: 6a1b ldr r3, [r3, #32]
- 80036d2: 4a1a ldr r2, [pc, #104] ; (800373c <TIM_OC3_SetConfig+0x78>)
- 80036d4: 401a ands r2, r3
- 80036d6: 687b ldr r3, [r7, #4]
- 80036d8: 621a str r2, [r3, #32]
+ 80036de: 687b ldr r3, [r7, #4]
+ 80036e0: 6a1b ldr r3, [r3, #32]
+ 80036e2: 4a1a ldr r2, [pc, #104] ; (800374c <TIM_OC3_SetConfig+0x78>)
+ 80036e4: 401a ands r2, r3
+ 80036e6: 687b ldr r3, [r7, #4]
+ 80036e8: 621a str r2, [r3, #32]
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
- 80036da: 687b ldr r3, [r7, #4]
- 80036dc: 6a1b ldr r3, [r3, #32]
- 80036de: 617b str r3, [r7, #20]
+ 80036ea: 687b ldr r3, [r7, #4]
+ 80036ec: 6a1b ldr r3, [r3, #32]
+ 80036ee: 617b str r3, [r7, #20]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
- 80036e0: 687b ldr r3, [r7, #4]
- 80036e2: 685b ldr r3, [r3, #4]
- 80036e4: 613b str r3, [r7, #16]
+ 80036f0: 687b ldr r3, [r7, #4]
+ 80036f2: 685b ldr r3, [r3, #4]
+ 80036f4: 613b str r3, [r7, #16]
/* Get the TIMx CCMR2 register value */
tmpccmrx = TIMx->CCMR2;
- 80036e6: 687b ldr r3, [r7, #4]
- 80036e8: 69db ldr r3, [r3, #28]
- 80036ea: 60fb str r3, [r7, #12]
+ 80036f6: 687b ldr r3, [r7, #4]
+ 80036f8: 69db ldr r3, [r3, #28]
+ 80036fa: 60fb str r3, [r7, #12]
/* Reset the Output Compare mode and Capture/Compare selection Bits */
tmpccmrx &= ~TIM_CCMR2_OC3M;
- 80036ec: 68fb ldr r3, [r7, #12]
- 80036ee: 2270 movs r2, #112 ; 0x70
- 80036f0: 4393 bics r3, r2
- 80036f2: 60fb str r3, [r7, #12]
+ 80036fc: 68fb ldr r3, [r7, #12]
+ 80036fe: 2270 movs r2, #112 ; 0x70
+ 8003700: 4393 bics r3, r2
+ 8003702: 60fb str r3, [r7, #12]
tmpccmrx &= ~TIM_CCMR2_CC3S;
- 80036f4: 68fb ldr r3, [r7, #12]
- 80036f6: 2203 movs r2, #3
- 80036f8: 4393 bics r3, r2
- 80036fa: 60fb str r3, [r7, #12]
+ 8003704: 68fb ldr r3, [r7, #12]
+ 8003706: 2203 movs r2, #3
+ 8003708: 4393 bics r3, r2
+ 800370a: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= OC_Config->OCMode;
- 80036fc: 683b ldr r3, [r7, #0]
- 80036fe: 681b ldr r3, [r3, #0]
- 8003700: 68fa ldr r2, [r7, #12]
- 8003702: 4313 orrs r3, r2
- 8003704: 60fb str r3, [r7, #12]
+ 800370c: 683b ldr r3, [r7, #0]
+ 800370e: 681b ldr r3, [r3, #0]
+ 8003710: 68fa ldr r2, [r7, #12]
+ 8003712: 4313 orrs r3, r2
+ 8003714: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC3P;
- 8003706: 697b ldr r3, [r7, #20]
- 8003708: 4a0d ldr r2, [pc, #52] ; (8003740 <TIM_OC3_SetConfig+0x7c>)
- 800370a: 4013 ands r3, r2
- 800370c: 617b str r3, [r7, #20]
+ 8003716: 697b ldr r3, [r7, #20]
+ 8003718: 4a0d ldr r2, [pc, #52] ; (8003750 <TIM_OC3_SetConfig+0x7c>)
+ 800371a: 4013 ands r3, r2
+ 800371c: 617b str r3, [r7, #20]
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 8U);
- 800370e: 683b ldr r3, [r7, #0]
- 8003710: 689b ldr r3, [r3, #8]
- 8003712: 021b lsls r3, r3, #8
- 8003714: 697a ldr r2, [r7, #20]
- 8003716: 4313 orrs r3, r2
- 8003718: 617b str r3, [r7, #20]
+ 800371e: 683b ldr r3, [r7, #0]
+ 8003720: 689b ldr r3, [r3, #8]
+ 8003722: 021b lsls r3, r3, #8
+ 8003724: 697a ldr r2, [r7, #20]
+ 8003726: 4313 orrs r3, r2
+ 8003728: 617b str r3, [r7, #20]
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
- 800371a: 687b ldr r3, [r7, #4]
- 800371c: 693a ldr r2, [r7, #16]
- 800371e: 605a str r2, [r3, #4]
+ 800372a: 687b ldr r3, [r7, #4]
+ 800372c: 693a ldr r2, [r7, #16]
+ 800372e: 605a str r2, [r3, #4]
/* Write to TIMx CCMR2 */
TIMx->CCMR2 = tmpccmrx;
- 8003720: 687b ldr r3, [r7, #4]
- 8003722: 68fa ldr r2, [r7, #12]
- 8003724: 61da str r2, [r3, #28]
+ 8003730: 687b ldr r3, [r7, #4]
+ 8003732: 68fa ldr r2, [r7, #12]
+ 8003734: 61da str r2, [r3, #28]
/* Set the Capture Compare Register value */
TIMx->CCR3 = OC_Config->Pulse;
- 8003726: 683b ldr r3, [r7, #0]
- 8003728: 685a ldr r2, [r3, #4]
- 800372a: 687b ldr r3, [r7, #4]
- 800372c: 63da str r2, [r3, #60] ; 0x3c
+ 8003736: 683b ldr r3, [r7, #0]
+ 8003738: 685a ldr r2, [r3, #4]
+ 800373a: 687b ldr r3, [r7, #4]
+ 800373c: 63da str r2, [r3, #60] ; 0x3c
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
- 800372e: 687b ldr r3, [r7, #4]
- 8003730: 697a ldr r2, [r7, #20]
- 8003732: 621a str r2, [r3, #32]
+ 800373e: 687b ldr r3, [r7, #4]
+ 8003740: 697a ldr r2, [r7, #20]
+ 8003742: 621a str r2, [r3, #32]
}
- 8003734: 46c0 nop ; (mov r8, r8)
- 8003736: 46bd mov sp, r7
- 8003738: b006 add sp, #24
- 800373a: bd80 pop {r7, pc}
- 800373c: fffffeff .word 0xfffffeff
- 8003740: fffffdff .word 0xfffffdff
+ 8003744: 46c0 nop ; (mov r8, r8)
+ 8003746: 46bd mov sp, r7
+ 8003748: b006 add sp, #24
+ 800374a: bd80 pop {r7, pc}
+ 800374c: fffffeff .word 0xfffffeff
+ 8003750: fffffdff .word 0xfffffdff
-08003744 <TIM_OC4_SetConfig>:
+08003754 <TIM_OC4_SetConfig>:
* @param TIMx to select the TIM peripheral
* @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
{
- 8003744: b580 push {r7, lr}
- 8003746: b086 sub sp, #24
- 8003748: af00 add r7, sp, #0
- 800374a: 6078 str r0, [r7, #4]
- 800374c: 6039 str r1, [r7, #0]
+ 8003754: b580 push {r7, lr}
+ 8003756: b086 sub sp, #24
+ 8003758: af00 add r7, sp, #0
+ 800375a: 6078 str r0, [r7, #4]
+ 800375c: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Disable the Channel 4: Reset the CC4E Bit */
TIMx->CCER &= ~TIM_CCER_CC4E;
- 800374e: 687b ldr r3, [r7, #4]
- 8003750: 6a1b ldr r3, [r3, #32]
- 8003752: 4a1b ldr r2, [pc, #108] ; (80037c0 <TIM_OC4_SetConfig+0x7c>)
- 8003754: 401a ands r2, r3
- 8003756: 687b ldr r3, [r7, #4]
- 8003758: 621a str r2, [r3, #32]
+ 800375e: 687b ldr r3, [r7, #4]
+ 8003760: 6a1b ldr r3, [r3, #32]
+ 8003762: 4a1b ldr r2, [pc, #108] ; (80037d0 <TIM_OC4_SetConfig+0x7c>)
+ 8003764: 401a ands r2, r3
+ 8003766: 687b ldr r3, [r7, #4]
+ 8003768: 621a str r2, [r3, #32]
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
- 800375a: 687b ldr r3, [r7, #4]
- 800375c: 6a1b ldr r3, [r3, #32]
- 800375e: 617b str r3, [r7, #20]
+ 800376a: 687b ldr r3, [r7, #4]
+ 800376c: 6a1b ldr r3, [r3, #32]
+ 800376e: 617b str r3, [r7, #20]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
- 8003760: 687b ldr r3, [r7, #4]
- 8003762: 685b ldr r3, [r3, #4]
- 8003764: 613b str r3, [r7, #16]
+ 8003770: 687b ldr r3, [r7, #4]
+ 8003772: 685b ldr r3, [r3, #4]
+ 8003774: 613b str r3, [r7, #16]
/* Get the TIMx CCMR2 register value */
tmpccmrx = TIMx->CCMR2;
- 8003766: 687b ldr r3, [r7, #4]
- 8003768: 69db ldr r3, [r3, #28]
- 800376a: 60fb str r3, [r7, #12]
+ 8003776: 687b ldr r3, [r7, #4]
+ 8003778: 69db ldr r3, [r3, #28]
+ 800377a: 60fb str r3, [r7, #12]
/* Reset the Output Compare mode and Capture/Compare selection Bits */
tmpccmrx &= ~TIM_CCMR2_OC4M;
- 800376c: 68fb ldr r3, [r7, #12]
- 800376e: 4a15 ldr r2, [pc, #84] ; (80037c4 <TIM_OC4_SetConfig+0x80>)
- 8003770: 4013 ands r3, r2
- 8003772: 60fb str r3, [r7, #12]
+ 800377c: 68fb ldr r3, [r7, #12]
+ 800377e: 4a15 ldr r2, [pc, #84] ; (80037d4 <TIM_OC4_SetConfig+0x80>)
+ 8003780: 4013 ands r3, r2
+ 8003782: 60fb str r3, [r7, #12]
tmpccmrx &= ~TIM_CCMR2_CC4S;
- 8003774: 68fb ldr r3, [r7, #12]
- 8003776: 4a14 ldr r2, [pc, #80] ; (80037c8 <TIM_OC4_SetConfig+0x84>)
- 8003778: 4013 ands r3, r2
- 800377a: 60fb str r3, [r7, #12]
+ 8003784: 68fb ldr r3, [r7, #12]
+ 8003786: 4a14 ldr r2, [pc, #80] ; (80037d8 <TIM_OC4_SetConfig+0x84>)
+ 8003788: 4013 ands r3, r2
+ 800378a: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= (OC_Config->OCMode << 8U);
- 800377c: 683b ldr r3, [r7, #0]
- 800377e: 681b ldr r3, [r3, #0]
- 8003780: 021b lsls r3, r3, #8
- 8003782: 68fa ldr r2, [r7, #12]
- 8003784: 4313 orrs r3, r2
- 8003786: 60fb str r3, [r7, #12]
+ 800378c: 683b ldr r3, [r7, #0]
+ 800378e: 681b ldr r3, [r3, #0]
+ 8003790: 021b lsls r3, r3, #8
+ 8003792: 68fa ldr r2, [r7, #12]
+ 8003794: 4313 orrs r3, r2
+ 8003796: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC4P;
- 8003788: 697b ldr r3, [r7, #20]
- 800378a: 4a10 ldr r2, [pc, #64] ; (80037cc <TIM_OC4_SetConfig+0x88>)
- 800378c: 4013 ands r3, r2
- 800378e: 617b str r3, [r7, #20]
+ 8003798: 697b ldr r3, [r7, #20]
+ 800379a: 4a10 ldr r2, [pc, #64] ; (80037dc <TIM_OC4_SetConfig+0x88>)
+ 800379c: 4013 ands r3, r2
+ 800379e: 617b str r3, [r7, #20]
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 12U);
- 8003790: 683b ldr r3, [r7, #0]
- 8003792: 689b ldr r3, [r3, #8]
- 8003794: 031b lsls r3, r3, #12
- 8003796: 697a ldr r2, [r7, #20]
- 8003798: 4313 orrs r3, r2
- 800379a: 617b str r3, [r7, #20]
+ 80037a0: 683b ldr r3, [r7, #0]
+ 80037a2: 689b ldr r3, [r3, #8]
+ 80037a4: 031b lsls r3, r3, #12
+ 80037a6: 697a ldr r2, [r7, #20]
+ 80037a8: 4313 orrs r3, r2
+ 80037aa: 617b str r3, [r7, #20]
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
- 800379c: 687b ldr r3, [r7, #4]
- 800379e: 693a ldr r2, [r7, #16]
- 80037a0: 605a str r2, [r3, #4]
+ 80037ac: 687b ldr r3, [r7, #4]
+ 80037ae: 693a ldr r2, [r7, #16]
+ 80037b0: 605a str r2, [r3, #4]
/* Write to TIMx CCMR2 */
TIMx->CCMR2 = tmpccmrx;
- 80037a2: 687b ldr r3, [r7, #4]
- 80037a4: 68fa ldr r2, [r7, #12]
- 80037a6: 61da str r2, [r3, #28]
+ 80037b2: 687b ldr r3, [r7, #4]
+ 80037b4: 68fa ldr r2, [r7, #12]
+ 80037b6: 61da str r2, [r3, #28]
/* Set the Capture Compare Register value */
TIMx->CCR4 = OC_Config->Pulse;
- 80037a8: 683b ldr r3, [r7, #0]
- 80037aa: 685a ldr r2, [r3, #4]
- 80037ac: 687b ldr r3, [r7, #4]
- 80037ae: 641a str r2, [r3, #64] ; 0x40
+ 80037b8: 683b ldr r3, [r7, #0]
+ 80037ba: 685a ldr r2, [r3, #4]
+ 80037bc: 687b ldr r3, [r7, #4]
+ 80037be: 641a str r2, [r3, #64] ; 0x40
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
- 80037b0: 687b ldr r3, [r7, #4]
- 80037b2: 697a ldr r2, [r7, #20]
- 80037b4: 621a str r2, [r3, #32]
+ 80037c0: 687b ldr r3, [r7, #4]
+ 80037c2: 697a ldr r2, [r7, #20]
+ 80037c4: 621a str r2, [r3, #32]
}
- 80037b6: 46c0 nop ; (mov r8, r8)
- 80037b8: 46bd mov sp, r7
- 80037ba: b006 add sp, #24
- 80037bc: bd80 pop {r7, pc}
- 80037be: 46c0 nop ; (mov r8, r8)
- 80037c0: ffffefff .word 0xffffefff
- 80037c4: ffff8fff .word 0xffff8fff
- 80037c8: fffffcff .word 0xfffffcff
- 80037cc: ffffdfff .word 0xffffdfff
+ 80037c6: 46c0 nop ; (mov r8, r8)
+ 80037c8: 46bd mov sp, r7
+ 80037ca: b006 add sp, #24
+ 80037cc: bd80 pop {r7, pc}
+ 80037ce: 46c0 nop ; (mov r8, r8)
+ 80037d0: ffffefff .word 0xffffefff
+ 80037d4: ffff8fff .word 0xffff8fff
+ 80037d8: fffffcff .word 0xfffffcff
+ 80037dc: ffffdfff .word 0xffffdfff
-080037d0 <TIM_TI1_ConfigInputStage>:
+080037e0 <TIM_TI1_ConfigInputStage>:
* @param TIM_ICFilter Specifies the Input Capture Filter.
* This parameter must be a value between 0x00 and 0x0F.
* @retval None
*/
static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
{
- 80037d0: b580 push {r7, lr}
- 80037d2: b086 sub sp, #24
- 80037d4: af00 add r7, sp, #0
- 80037d6: 60f8 str r0, [r7, #12]
- 80037d8: 60b9 str r1, [r7, #8]
- 80037da: 607a str r2, [r7, #4]
+ 80037e0: b580 push {r7, lr}
+ 80037e2: b086 sub sp, #24
+ 80037e4: af00 add r7, sp, #0
+ 80037e6: 60f8 str r0, [r7, #12]
+ 80037e8: 60b9 str r1, [r7, #8]
+ 80037ea: 607a str r2, [r7, #4]
uint32_t tmpccmr1;
uint32_t tmpccer;
/* Disable the Channel 1: Reset the CC1E Bit */
tmpccer = TIMx->CCER;
- 80037dc: 68fb ldr r3, [r7, #12]
- 80037de: 6a1b ldr r3, [r3, #32]
- 80037e0: 617b str r3, [r7, #20]
- TIMx->CCER &= ~TIM_CCER_CC1E;
- 80037e2: 68fb ldr r3, [r7, #12]
- 80037e4: 6a1b ldr r3, [r3, #32]
- 80037e6: 2201 movs r2, #1
- 80037e8: 4393 bics r3, r2
- 80037ea: 001a movs r2, r3
80037ec: 68fb ldr r3, [r7, #12]
- 80037ee: 621a str r2, [r3, #32]
+ 80037ee: 6a1b ldr r3, [r3, #32]
+ 80037f0: 617b str r3, [r7, #20]
+ TIMx->CCER &= ~TIM_CCER_CC1E;
+ 80037f2: 68fb ldr r3, [r7, #12]
+ 80037f4: 6a1b ldr r3, [r3, #32]
+ 80037f6: 2201 movs r2, #1
+ 80037f8: 4393 bics r3, r2
+ 80037fa: 001a movs r2, r3
+ 80037fc: 68fb ldr r3, [r7, #12]
+ 80037fe: 621a str r2, [r3, #32]
tmpccmr1 = TIMx->CCMR1;
- 80037f0: 68fb ldr r3, [r7, #12]
- 80037f2: 699b ldr r3, [r3, #24]
- 80037f4: 613b str r3, [r7, #16]
+ 8003800: 68fb ldr r3, [r7, #12]
+ 8003802: 699b ldr r3, [r3, #24]
+ 8003804: 613b str r3, [r7, #16]
/* Set the filter */
tmpccmr1 &= ~TIM_CCMR1_IC1F;
- 80037f6: 693b ldr r3, [r7, #16]
- 80037f8: 22f0 movs r2, #240 ; 0xf0
- 80037fa: 4393 bics r3, r2
- 80037fc: 613b str r3, [r7, #16]
+ 8003806: 693b ldr r3, [r7, #16]
+ 8003808: 22f0 movs r2, #240 ; 0xf0
+ 800380a: 4393 bics r3, r2
+ 800380c: 613b str r3, [r7, #16]
tmpccmr1 |= (TIM_ICFilter << 4U);
- 80037fe: 687b ldr r3, [r7, #4]
- 8003800: 011b lsls r3, r3, #4
- 8003802: 693a ldr r2, [r7, #16]
- 8003804: 4313 orrs r3, r2
- 8003806: 613b str r3, [r7, #16]
+ 800380e: 687b ldr r3, [r7, #4]
+ 8003810: 011b lsls r3, r3, #4
+ 8003812: 693a ldr r2, [r7, #16]
+ 8003814: 4313 orrs r3, r2
+ 8003816: 613b str r3, [r7, #16]
/* Select the Polarity and set the CC1E Bit */
tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
- 8003808: 697b ldr r3, [r7, #20]
- 800380a: 220a movs r2, #10
- 800380c: 4393 bics r3, r2
- 800380e: 617b str r3, [r7, #20]
+ 8003818: 697b ldr r3, [r7, #20]
+ 800381a: 220a movs r2, #10
+ 800381c: 4393 bics r3, r2
+ 800381e: 617b str r3, [r7, #20]
tmpccer |= TIM_ICPolarity;
- 8003810: 697a ldr r2, [r7, #20]
- 8003812: 68bb ldr r3, [r7, #8]
- 8003814: 4313 orrs r3, r2
- 8003816: 617b str r3, [r7, #20]
+ 8003820: 697a ldr r2, [r7, #20]
+ 8003822: 68bb ldr r3, [r7, #8]
+ 8003824: 4313 orrs r3, r2
+ 8003826: 617b str r3, [r7, #20]
/* Write to TIMx CCMR1 and CCER registers */
TIMx->CCMR1 = tmpccmr1;
- 8003818: 68fb ldr r3, [r7, #12]
- 800381a: 693a ldr r2, [r7, #16]
- 800381c: 619a str r2, [r3, #24]
+ 8003828: 68fb ldr r3, [r7, #12]
+ 800382a: 693a ldr r2, [r7, #16]
+ 800382c: 619a str r2, [r3, #24]
TIMx->CCER = tmpccer;
- 800381e: 68fb ldr r3, [r7, #12]
- 8003820: 697a ldr r2, [r7, #20]
- 8003822: 621a str r2, [r3, #32]
+ 800382e: 68fb ldr r3, [r7, #12]
+ 8003830: 697a ldr r2, [r7, #20]
+ 8003832: 621a str r2, [r3, #32]
}
- 8003824: 46c0 nop ; (mov r8, r8)
- 8003826: 46bd mov sp, r7
- 8003828: b006 add sp, #24
- 800382a: bd80 pop {r7, pc}
+ 8003834: 46c0 nop ; (mov r8, r8)
+ 8003836: 46bd mov sp, r7
+ 8003838: b006 add sp, #24
+ 800383a: bd80 pop {r7, pc}
-0800382c <TIM_TI2_ConfigInputStage>:
+0800383c <TIM_TI2_ConfigInputStage>:
* @param TIM_ICFilter Specifies the Input Capture Filter.
* This parameter must be a value between 0x00 and 0x0F.
* @retval None
*/
static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
{
- 800382c: b580 push {r7, lr}
- 800382e: b086 sub sp, #24
- 8003830: af00 add r7, sp, #0
- 8003832: 60f8 str r0, [r7, #12]
- 8003834: 60b9 str r1, [r7, #8]
- 8003836: 607a str r2, [r7, #4]
+ 800383c: b580 push {r7, lr}
+ 800383e: b086 sub sp, #24
+ 8003840: af00 add r7, sp, #0
+ 8003842: 60f8 str r0, [r7, #12]
+ 8003844: 60b9 str r1, [r7, #8]
+ 8003846: 607a str r2, [r7, #4]
uint32_t tmpccmr1;
uint32_t tmpccer;
/* Disable the Channel 2: Reset the CC2E Bit */
TIMx->CCER &= ~TIM_CCER_CC2E;
- 8003838: 68fb ldr r3, [r7, #12]
- 800383a: 6a1b ldr r3, [r3, #32]
- 800383c: 2210 movs r2, #16
- 800383e: 4393 bics r3, r2
- 8003840: 001a movs r2, r3
- 8003842: 68fb ldr r3, [r7, #12]
- 8003844: 621a str r2, [r3, #32]
+ 8003848: 68fb ldr r3, [r7, #12]
+ 800384a: 6a1b ldr r3, [r3, #32]
+ 800384c: 2210 movs r2, #16
+ 800384e: 4393 bics r3, r2
+ 8003850: 001a movs r2, r3
+ 8003852: 68fb ldr r3, [r7, #12]
+ 8003854: 621a str r2, [r3, #32]
tmpccmr1 = TIMx->CCMR1;
- 8003846: 68fb ldr r3, [r7, #12]
- 8003848: 699b ldr r3, [r3, #24]
- 800384a: 617b str r3, [r7, #20]
+ 8003856: 68fb ldr r3, [r7, #12]
+ 8003858: 699b ldr r3, [r3, #24]
+ 800385a: 617b str r3, [r7, #20]
tmpccer = TIMx->CCER;
- 800384c: 68fb ldr r3, [r7, #12]
- 800384e: 6a1b ldr r3, [r3, #32]
- 8003850: 613b str r3, [r7, #16]
+ 800385c: 68fb ldr r3, [r7, #12]
+ 800385e: 6a1b ldr r3, [r3, #32]
+ 8003860: 613b str r3, [r7, #16]
/* Set the filter */
tmpccmr1 &= ~TIM_CCMR1_IC2F;
- 8003852: 697b ldr r3, [r7, #20]
- 8003854: 4a0d ldr r2, [pc, #52] ; (800388c <TIM_TI2_ConfigInputStage+0x60>)
- 8003856: 4013 ands r3, r2
- 8003858: 617b str r3, [r7, #20]
+ 8003862: 697b ldr r3, [r7, #20]
+ 8003864: 4a0d ldr r2, [pc, #52] ; (800389c <TIM_TI2_ConfigInputStage+0x60>)
+ 8003866: 4013 ands r3, r2
+ 8003868: 617b str r3, [r7, #20]
tmpccmr1 |= (TIM_ICFilter << 12U);
- 800385a: 687b ldr r3, [r7, #4]
- 800385c: 031b lsls r3, r3, #12
- 800385e: 697a ldr r2, [r7, #20]
- 8003860: 4313 orrs r3, r2
- 8003862: 617b str r3, [r7, #20]
+ 800386a: 687b ldr r3, [r7, #4]
+ 800386c: 031b lsls r3, r3, #12
+ 800386e: 697a ldr r2, [r7, #20]
+ 8003870: 4313 orrs r3, r2
+ 8003872: 617b str r3, [r7, #20]
/* Select the Polarity and set the CC2E Bit */
tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
- 8003864: 693b ldr r3, [r7, #16]
- 8003866: 22a0 movs r2, #160 ; 0xa0
- 8003868: 4393 bics r3, r2
- 800386a: 613b str r3, [r7, #16]
+ 8003874: 693b ldr r3, [r7, #16]
+ 8003876: 22a0 movs r2, #160 ; 0xa0
+ 8003878: 4393 bics r3, r2
+ 800387a: 613b str r3, [r7, #16]
tmpccer |= (TIM_ICPolarity << 4U);
- 800386c: 68bb ldr r3, [r7, #8]
- 800386e: 011b lsls r3, r3, #4
- 8003870: 693a ldr r2, [r7, #16]
- 8003872: 4313 orrs r3, r2
- 8003874: 613b str r3, [r7, #16]
+ 800387c: 68bb ldr r3, [r7, #8]
+ 800387e: 011b lsls r3, r3, #4
+ 8003880: 693a ldr r2, [r7, #16]
+ 8003882: 4313 orrs r3, r2
+ 8003884: 613b str r3, [r7, #16]
/* Write to TIMx CCMR1 and CCER registers */
TIMx->CCMR1 = tmpccmr1 ;
- 8003876: 68fb ldr r3, [r7, #12]
- 8003878: 697a ldr r2, [r7, #20]
- 800387a: 619a str r2, [r3, #24]
+ 8003886: 68fb ldr r3, [r7, #12]
+ 8003888: 697a ldr r2, [r7, #20]
+ 800388a: 619a str r2, [r3, #24]
TIMx->CCER = tmpccer;
- 800387c: 68fb ldr r3, [r7, #12]
- 800387e: 693a ldr r2, [r7, #16]
- 8003880: 621a str r2, [r3, #32]
+ 800388c: 68fb ldr r3, [r7, #12]
+ 800388e: 693a ldr r2, [r7, #16]
+ 8003890: 621a str r2, [r3, #32]
}
- 8003882: 46c0 nop ; (mov r8, r8)
- 8003884: 46bd mov sp, r7
- 8003886: b006 add sp, #24
- 8003888: bd80 pop {r7, pc}
- 800388a: 46c0 nop ; (mov r8, r8)
- 800388c: ffff0fff .word 0xffff0fff
+ 8003892: 46c0 nop ; (mov r8, r8)
+ 8003894: 46bd mov sp, r7
+ 8003896: b006 add sp, #24
+ 8003898: bd80 pop {r7, pc}
+ 800389a: 46c0 nop ; (mov r8, r8)
+ 800389c: ffff0fff .word 0xffff0fff
-08003890 <TIM_ITRx_SetConfig>:
+080038a0 <TIM_ITRx_SetConfig>:
* @arg TIM_TS_TI2FP2: Filtered Timer Input 2
* @arg TIM_TS_ETRF: External Trigger input
* @retval None
*/
static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource)
{
- 8003890: b580 push {r7, lr}
- 8003892: b084 sub sp, #16
- 8003894: af00 add r7, sp, #0
- 8003896: 6078 str r0, [r7, #4]
- 8003898: 6039 str r1, [r7, #0]
+ 80038a0: b580 push {r7, lr}
+ 80038a2: b084 sub sp, #16
+ 80038a4: af00 add r7, sp, #0
+ 80038a6: 6078 str r0, [r7, #4]
+ 80038a8: 6039 str r1, [r7, #0]
uint32_t tmpsmcr;
/* Get the TIMx SMCR register value */
tmpsmcr = TIMx->SMCR;
- 800389a: 687b ldr r3, [r7, #4]
- 800389c: 689b ldr r3, [r3, #8]
- 800389e: 60fb str r3, [r7, #12]
+ 80038aa: 687b ldr r3, [r7, #4]
+ 80038ac: 689b ldr r3, [r3, #8]
+ 80038ae: 60fb str r3, [r7, #12]
/* Reset the TS Bits */
tmpsmcr &= ~TIM_SMCR_TS;
- 80038a0: 68fb ldr r3, [r7, #12]
- 80038a2: 2270 movs r2, #112 ; 0x70
- 80038a4: 4393 bics r3, r2
- 80038a6: 60fb str r3, [r7, #12]
+ 80038b0: 68fb ldr r3, [r7, #12]
+ 80038b2: 2270 movs r2, #112 ; 0x70
+ 80038b4: 4393 bics r3, r2
+ 80038b6: 60fb str r3, [r7, #12]
/* Set the Input Trigger source and the slave mode*/
tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1);
- 80038a8: 683a ldr r2, [r7, #0]
- 80038aa: 68fb ldr r3, [r7, #12]
- 80038ac: 4313 orrs r3, r2
- 80038ae: 2207 movs r2, #7
- 80038b0: 4313 orrs r3, r2
- 80038b2: 60fb str r3, [r7, #12]
+ 80038b8: 683a ldr r2, [r7, #0]
+ 80038ba: 68fb ldr r3, [r7, #12]
+ 80038bc: 4313 orrs r3, r2
+ 80038be: 2207 movs r2, #7
+ 80038c0: 4313 orrs r3, r2
+ 80038c2: 60fb str r3, [r7, #12]
/* Write to TIMx SMCR */
TIMx->SMCR = tmpsmcr;
- 80038b4: 687b ldr r3, [r7, #4]
- 80038b6: 68fa ldr r2, [r7, #12]
- 80038b8: 609a str r2, [r3, #8]
+ 80038c4: 687b ldr r3, [r7, #4]
+ 80038c6: 68fa ldr r2, [r7, #12]
+ 80038c8: 609a str r2, [r3, #8]
}
- 80038ba: 46c0 nop ; (mov r8, r8)
- 80038bc: 46bd mov sp, r7
- 80038be: b004 add sp, #16
- 80038c0: bd80 pop {r7, pc}
+ 80038ca: 46c0 nop ; (mov r8, r8)
+ 80038cc: 46bd mov sp, r7
+ 80038ce: b004 add sp, #16
+ 80038d0: bd80 pop {r7, pc}
...
-080038c4 <TIM_ETR_SetConfig>:
+080038d4 <TIM_ETR_SetConfig>:
* This parameter must be a value between 0x00 and 0x0F
* @retval None
*/
static void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
{
- 80038c4: b580 push {r7, lr}
- 80038c6: b086 sub sp, #24
- 80038c8: af00 add r7, sp, #0
- 80038ca: 60f8 str r0, [r7, #12]
- 80038cc: 60b9 str r1, [r7, #8]
- 80038ce: 607a str r2, [r7, #4]
- 80038d0: 603b str r3, [r7, #0]
+ 80038d4: b580 push {r7, lr}
+ 80038d6: b086 sub sp, #24
+ 80038d8: af00 add r7, sp, #0
+ 80038da: 60f8 str r0, [r7, #12]
+ 80038dc: 60b9 str r1, [r7, #8]
+ 80038de: 607a str r2, [r7, #4]
+ 80038e0: 603b str r3, [r7, #0]
uint32_t tmpsmcr;
tmpsmcr = TIMx->SMCR;
- 80038d2: 68fb ldr r3, [r7, #12]
- 80038d4: 689b ldr r3, [r3, #8]
- 80038d6: 617b str r3, [r7, #20]
+ 80038e2: 68fb ldr r3, [r7, #12]
+ 80038e4: 689b ldr r3, [r3, #8]
+ 80038e6: 617b str r3, [r7, #20]
/* Reset the ETR Bits */
tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
- 80038d8: 697b ldr r3, [r7, #20]
- 80038da: 4a09 ldr r2, [pc, #36] ; (8003900 <TIM_ETR_SetConfig+0x3c>)
- 80038dc: 4013 ands r3, r2
- 80038de: 617b str r3, [r7, #20]
+ 80038e8: 697b ldr r3, [r7, #20]
+ 80038ea: 4a09 ldr r2, [pc, #36] ; (8003910 <TIM_ETR_SetConfig+0x3c>)
+ 80038ec: 4013 ands r3, r2
+ 80038ee: 617b str r3, [r7, #20]
/* Set the Prescaler, the Filter value and the Polarity */
tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));
- 80038e0: 683b ldr r3, [r7, #0]
- 80038e2: 021a lsls r2, r3, #8
- 80038e4: 687b ldr r3, [r7, #4]
- 80038e6: 431a orrs r2, r3
- 80038e8: 68bb ldr r3, [r7, #8]
- 80038ea: 4313 orrs r3, r2
- 80038ec: 697a ldr r2, [r7, #20]
- 80038ee: 4313 orrs r3, r2
- 80038f0: 617b str r3, [r7, #20]
+ 80038f0: 683b ldr r3, [r7, #0]
+ 80038f2: 021a lsls r2, r3, #8
+ 80038f4: 687b ldr r3, [r7, #4]
+ 80038f6: 431a orrs r2, r3
+ 80038f8: 68bb ldr r3, [r7, #8]
+ 80038fa: 4313 orrs r3, r2
+ 80038fc: 697a ldr r2, [r7, #20]
+ 80038fe: 4313 orrs r3, r2
+ 8003900: 617b str r3, [r7, #20]
/* Write to TIMx SMCR */
TIMx->SMCR = tmpsmcr;
- 80038f2: 68fb ldr r3, [r7, #12]
- 80038f4: 697a ldr r2, [r7, #20]
- 80038f6: 609a str r2, [r3, #8]
+ 8003902: 68fb ldr r3, [r7, #12]
+ 8003904: 697a ldr r2, [r7, #20]
+ 8003906: 609a str r2, [r3, #8]
}
- 80038f8: 46c0 nop ; (mov r8, r8)
- 80038fa: 46bd mov sp, r7
- 80038fc: b006 add sp, #24
- 80038fe: bd80 pop {r7, pc}
- 8003900: ffff00ff .word 0xffff00ff
+ 8003908: 46c0 nop ; (mov r8, r8)
+ 800390a: 46bd mov sp, r7
+ 800390c: b006 add sp, #24
+ 800390e: bd80 pop {r7, pc}
+ 8003910: ffff00ff .word 0xffff00ff
-08003904 <HAL_TIMEx_MasterConfigSynchronization>:
+08003914 <HAL_TIMEx_MasterConfigSynchronization>:
* mode.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
TIM_MasterConfigTypeDef *sMasterConfig)
{
- 8003904: b580 push {r7, lr}
- 8003906: b084 sub sp, #16
- 8003908: af00 add r7, sp, #0
- 800390a: 6078 str r0, [r7, #4]
- 800390c: 6039 str r1, [r7, #0]
+ 8003914: b580 push {r7, lr}
+ 8003916: b084 sub sp, #16
+ 8003918: af00 add r7, sp, #0
+ 800391a: 6078 str r0, [r7, #4]
+ 800391c: 6039 str r1, [r7, #0]
assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
/* Check input state */
__HAL_LOCK(htim);
- 800390e: 687b ldr r3, [r7, #4]
- 8003910: 2238 movs r2, #56 ; 0x38
- 8003912: 5c9b ldrb r3, [r3, r2]
- 8003914: 2b01 cmp r3, #1
- 8003916: d101 bne.n 800391c <HAL_TIMEx_MasterConfigSynchronization+0x18>
- 8003918: 2302 movs r3, #2
- 800391a: e042 b.n 80039a2 <HAL_TIMEx_MasterConfigSynchronization+0x9e>
- 800391c: 687b ldr r3, [r7, #4]
- 800391e: 2238 movs r2, #56 ; 0x38
- 8003920: 2101 movs r1, #1
- 8003922: 5499 strb r1, [r3, r2]
+ 800391e: 687b ldr r3, [r7, #4]
+ 8003920: 2238 movs r2, #56 ; 0x38
+ 8003922: 5c9b ldrb r3, [r3, r2]
+ 8003924: 2b01 cmp r3, #1
+ 8003926: d101 bne.n 800392c <HAL_TIMEx_MasterConfigSynchronization+0x18>
+ 8003928: 2302 movs r3, #2
+ 800392a: e042 b.n 80039b2 <HAL_TIMEx_MasterConfigSynchronization+0x9e>
+ 800392c: 687b ldr r3, [r7, #4]
+ 800392e: 2238 movs r2, #56 ; 0x38
+ 8003930: 2101 movs r1, #1
+ 8003932: 5499 strb r1, [r3, r2]
/* Change the handler state */
htim->State = HAL_TIM_STATE_BUSY;
- 8003924: 687b ldr r3, [r7, #4]
- 8003926: 2239 movs r2, #57 ; 0x39
- 8003928: 2102 movs r1, #2
- 800392a: 5499 strb r1, [r3, r2]
+ 8003934: 687b ldr r3, [r7, #4]
+ 8003936: 2239 movs r2, #57 ; 0x39
+ 8003938: 2102 movs r1, #2
+ 800393a: 5499 strb r1, [r3, r2]
/* Get the TIMx CR2 register value */
tmpcr2 = htim->Instance->CR2;
- 800392c: 687b ldr r3, [r7, #4]
- 800392e: 681b ldr r3, [r3, #0]
- 8003930: 685b ldr r3, [r3, #4]
- 8003932: 60fb str r3, [r7, #12]
+ 800393c: 687b ldr r3, [r7, #4]
+ 800393e: 681b ldr r3, [r3, #0]
+ 8003940: 685b ldr r3, [r3, #4]
+ 8003942: 60fb str r3, [r7, #12]
/* Get the TIMx SMCR register value */
tmpsmcr = htim->Instance->SMCR;
- 8003934: 687b ldr r3, [r7, #4]
- 8003936: 681b ldr r3, [r3, #0]
- 8003938: 689b ldr r3, [r3, #8]
- 800393a: 60bb str r3, [r7, #8]
+ 8003944: 687b ldr r3, [r7, #4]
+ 8003946: 681b ldr r3, [r3, #0]
+ 8003948: 689b ldr r3, [r3, #8]
+ 800394a: 60bb str r3, [r7, #8]
/* Reset the MMS Bits */
tmpcr2 &= ~TIM_CR2_MMS;
- 800393c: 68fb ldr r3, [r7, #12]
- 800393e: 2270 movs r2, #112 ; 0x70
- 8003940: 4393 bics r3, r2
- 8003942: 60fb str r3, [r7, #12]
+ 800394c: 68fb ldr r3, [r7, #12]
+ 800394e: 2270 movs r2, #112 ; 0x70
+ 8003950: 4393 bics r3, r2
+ 8003952: 60fb str r3, [r7, #12]
/* Select the TRGO source */
tmpcr2 |= sMasterConfig->MasterOutputTrigger;
- 8003944: 683b ldr r3, [r7, #0]
- 8003946: 681b ldr r3, [r3, #0]
- 8003948: 68fa ldr r2, [r7, #12]
- 800394a: 4313 orrs r3, r2
- 800394c: 60fb str r3, [r7, #12]
+ 8003954: 683b ldr r3, [r7, #0]
+ 8003956: 681b ldr r3, [r3, #0]
+ 8003958: 68fa ldr r2, [r7, #12]
+ 800395a: 4313 orrs r3, r2
+ 800395c: 60fb str r3, [r7, #12]
/* Update TIMx CR2 */
htim->Instance->CR2 = tmpcr2;
- 800394e: 687b ldr r3, [r7, #4]
- 8003950: 681b ldr r3, [r3, #0]
- 8003952: 68fa ldr r2, [r7, #12]
- 8003954: 605a str r2, [r3, #4]
+ 800395e: 687b ldr r3, [r7, #4]
+ 8003960: 681b ldr r3, [r3, #0]
+ 8003962: 68fa ldr r2, [r7, #12]
+ 8003964: 605a str r2, [r3, #4]
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
- 8003956: 687b ldr r3, [r7, #4]
- 8003958: 681a ldr r2, [r3, #0]
- 800395a: 2380 movs r3, #128 ; 0x80
- 800395c: 05db lsls r3, r3, #23
- 800395e: 429a cmp r2, r3
- 8003960: d009 beq.n 8003976 <HAL_TIMEx_MasterConfigSynchronization+0x72>
- 8003962: 687b ldr r3, [r7, #4]
- 8003964: 681b ldr r3, [r3, #0]
- 8003966: 4a11 ldr r2, [pc, #68] ; (80039ac <HAL_TIMEx_MasterConfigSynchronization+0xa8>)
- 8003968: 4293 cmp r3, r2
- 800396a: d004 beq.n 8003976 <HAL_TIMEx_MasterConfigSynchronization+0x72>
- 800396c: 687b ldr r3, [r7, #4]
- 800396e: 681b ldr r3, [r3, #0]
- 8003970: 4a0f ldr r2, [pc, #60] ; (80039b0 <HAL_TIMEx_MasterConfigSynchronization+0xac>)
- 8003972: 4293 cmp r3, r2
- 8003974: d10c bne.n 8003990 <HAL_TIMEx_MasterConfigSynchronization+0x8c>
+ 8003966: 687b ldr r3, [r7, #4]
+ 8003968: 681a ldr r2, [r3, #0]
+ 800396a: 2380 movs r3, #128 ; 0x80
+ 800396c: 05db lsls r3, r3, #23
+ 800396e: 429a cmp r2, r3
+ 8003970: d009 beq.n 8003986 <HAL_TIMEx_MasterConfigSynchronization+0x72>
+ 8003972: 687b ldr r3, [r7, #4]
+ 8003974: 681b ldr r3, [r3, #0]
+ 8003976: 4a11 ldr r2, [pc, #68] ; (80039bc <HAL_TIMEx_MasterConfigSynchronization+0xa8>)
+ 8003978: 4293 cmp r3, r2
+ 800397a: d004 beq.n 8003986 <HAL_TIMEx_MasterConfigSynchronization+0x72>
+ 800397c: 687b ldr r3, [r7, #4]
+ 800397e: 681b ldr r3, [r3, #0]
+ 8003980: 4a0f ldr r2, [pc, #60] ; (80039c0 <HAL_TIMEx_MasterConfigSynchronization+0xac>)
+ 8003982: 4293 cmp r3, r2
+ 8003984: d10c bne.n 80039a0 <HAL_TIMEx_MasterConfigSynchronization+0x8c>
{
/* Reset the MSM Bit */
tmpsmcr &= ~TIM_SMCR_MSM;
- 8003976: 68bb ldr r3, [r7, #8]
- 8003978: 2280 movs r2, #128 ; 0x80
- 800397a: 4393 bics r3, r2
- 800397c: 60bb str r3, [r7, #8]
+ 8003986: 68bb ldr r3, [r7, #8]
+ 8003988: 2280 movs r2, #128 ; 0x80
+ 800398a: 4393 bics r3, r2
+ 800398c: 60bb str r3, [r7, #8]
/* Set master mode */
tmpsmcr |= sMasterConfig->MasterSlaveMode;
- 800397e: 683b ldr r3, [r7, #0]
- 8003980: 685b ldr r3, [r3, #4]
- 8003982: 68ba ldr r2, [r7, #8]
- 8003984: 4313 orrs r3, r2
- 8003986: 60bb str r3, [r7, #8]
+ 800398e: 683b ldr r3, [r7, #0]
+ 8003990: 685b ldr r3, [r3, #4]
+ 8003992: 68ba ldr r2, [r7, #8]
+ 8003994: 4313 orrs r3, r2
+ 8003996: 60bb str r3, [r7, #8]
/* Update TIMx SMCR */
htim->Instance->SMCR = tmpsmcr;
- 8003988: 687b ldr r3, [r7, #4]
- 800398a: 681b ldr r3, [r3, #0]
- 800398c: 68ba ldr r2, [r7, #8]
- 800398e: 609a str r2, [r3, #8]
+ 8003998: 687b ldr r3, [r7, #4]
+ 800399a: 681b ldr r3, [r3, #0]
+ 800399c: 68ba ldr r2, [r7, #8]
+ 800399e: 609a str r2, [r3, #8]
}
/* Change the htim state */
htim->State = HAL_TIM_STATE_READY;
- 8003990: 687b ldr r3, [r7, #4]
- 8003992: 2239 movs r2, #57 ; 0x39
- 8003994: 2101 movs r1, #1
- 8003996: 5499 strb r1, [r3, r2]
+ 80039a0: 687b ldr r3, [r7, #4]
+ 80039a2: 2239 movs r2, #57 ; 0x39
+ 80039a4: 2101 movs r1, #1
+ 80039a6: 5499 strb r1, [r3, r2]
__HAL_UNLOCK(htim);
- 8003998: 687b ldr r3, [r7, #4]
- 800399a: 2238 movs r2, #56 ; 0x38
- 800399c: 2100 movs r1, #0
- 800399e: 5499 strb r1, [r3, r2]
+ 80039a8: 687b ldr r3, [r7, #4]
+ 80039aa: 2238 movs r2, #56 ; 0x38
+ 80039ac: 2100 movs r1, #0
+ 80039ae: 5499 strb r1, [r3, r2]
return HAL_OK;
- 80039a0: 2300 movs r3, #0
+ 80039b0: 2300 movs r3, #0
}
- 80039a2: 0018 movs r0, r3
- 80039a4: 46bd mov sp, r7
- 80039a6: b004 add sp, #16
- 80039a8: bd80 pop {r7, pc}
- 80039aa: 46c0 nop ; (mov r8, r8)
- 80039ac: 40010800 .word 0x40010800
- 80039b0: 40011400 .word 0x40011400
+ 80039b2: 0018 movs r0, r3
+ 80039b4: 46bd mov sp, r7
+ 80039b6: b004 add sp, #16
+ 80039b8: bd80 pop {r7, pc}
+ 80039ba: 46c0 nop ; (mov r8, r8)
+ 80039bc: 40010800 .word 0x40010800
+ 80039c0: 40011400 .word 0x40011400
-080039b4 <UART_SetConfig>:
+080039c4 <UART_SetConfig>:
* @brief Configure the UART peripheral.
* @param huart UART handle.
* @retval HAL status
*/
HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart)
{
- 80039b4: b5b0 push {r4, r5, r7, lr}
- 80039b6: b08e sub sp, #56 ; 0x38
- 80039b8: af00 add r7, sp, #0
- 80039ba: 61f8 str r0, [r7, #28]
+ 80039c4: b5b0 push {r4, r5, r7, lr}
+ 80039c6: b08e sub sp, #56 ; 0x38
+ 80039c8: af00 add r7, sp, #0
+ 80039ca: 61f8 str r0, [r7, #28]
uint32_t tmpreg;
uint16_t brrtemp;
UART_ClockSourceTypeDef clocksource;
uint32_t usartdiv;
HAL_StatusTypeDef ret = HAL_OK;
- 80039bc: 231a movs r3, #26
- 80039be: 2218 movs r2, #24
- 80039c0: 4694 mov ip, r2
- 80039c2: 44bc add ip, r7
- 80039c4: 4463 add r3, ip
- 80039c6: 2200 movs r2, #0
- 80039c8: 701a strb r2, [r3, #0]
+ 80039cc: 231a movs r3, #26
+ 80039ce: 2218 movs r2, #24
+ 80039d0: 4694 mov ip, r2
+ 80039d2: 44bc add ip, r7
+ 80039d4: 4463 add r3, ip
+ 80039d6: 2200 movs r2, #0
+ 80039d8: 701a strb r2, [r3, #0]
* the UART Word Length, Parity, Mode and oversampling:
* set the M bits according to huart->Init.WordLength value
* set PCE and PS bits according to huart->Init.Parity value
* set TE and RE bits according to huart->Init.Mode value
* set OVER8 bit according to huart->Init.OverSampling value */
tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ;
- 80039ca: 69fb ldr r3, [r7, #28]
- 80039cc: 689a ldr r2, [r3, #8]
- 80039ce: 69fb ldr r3, [r7, #28]
- 80039d0: 691b ldr r3, [r3, #16]
- 80039d2: 431a orrs r2, r3
- 80039d4: 69fb ldr r3, [r7, #28]
- 80039d6: 695b ldr r3, [r3, #20]
- 80039d8: 431a orrs r2, r3
80039da: 69fb ldr r3, [r7, #28]
- 80039dc: 69db ldr r3, [r3, #28]
- 80039de: 4313 orrs r3, r2
- 80039e0: 637b str r3, [r7, #52] ; 0x34
+ 80039dc: 689a ldr r2, [r3, #8]
+ 80039de: 69fb ldr r3, [r7, #28]
+ 80039e0: 691b ldr r3, [r3, #16]
+ 80039e2: 431a orrs r2, r3
+ 80039e4: 69fb ldr r3, [r7, #28]
+ 80039e6: 695b ldr r3, [r3, #20]
+ 80039e8: 431a orrs r2, r3
+ 80039ea: 69fb ldr r3, [r7, #28]
+ 80039ec: 69db ldr r3, [r3, #28]
+ 80039ee: 4313 orrs r3, r2
+ 80039f0: 637b str r3, [r7, #52] ; 0x34
MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg);
- 80039e2: 69fb ldr r3, [r7, #28]
- 80039e4: 681b ldr r3, [r3, #0]
- 80039e6: 681b ldr r3, [r3, #0]
- 80039e8: 4abc ldr r2, [pc, #752] ; (8003cdc <UART_SetConfig+0x328>)
- 80039ea: 4013 ands r3, r2
- 80039ec: 0019 movs r1, r3
- 80039ee: 69fb ldr r3, [r7, #28]
- 80039f0: 681b ldr r3, [r3, #0]
- 80039f2: 6b7a ldr r2, [r7, #52] ; 0x34
- 80039f4: 430a orrs r2, r1
- 80039f6: 601a str r2, [r3, #0]
+ 80039f2: 69fb ldr r3, [r7, #28]
+ 80039f4: 681b ldr r3, [r3, #0]
+ 80039f6: 681b ldr r3, [r3, #0]
+ 80039f8: 4abc ldr r2, [pc, #752] ; (8003cec <UART_SetConfig+0x328>)
+ 80039fa: 4013 ands r3, r2
+ 80039fc: 0019 movs r1, r3
+ 80039fe: 69fb ldr r3, [r7, #28]
+ 8003a00: 681b ldr r3, [r3, #0]
+ 8003a02: 6b7a ldr r2, [r7, #52] ; 0x34
+ 8003a04: 430a orrs r2, r1
+ 8003a06: 601a str r2, [r3, #0]
/*-------------------------- USART CR2 Configuration -----------------------*/
/* Configure the UART Stop Bits: Set STOP[13:12] bits according
* to huart->Init.StopBits value */
MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
- 80039f8: 69fb ldr r3, [r7, #28]
- 80039fa: 681b ldr r3, [r3, #0]
- 80039fc: 685b ldr r3, [r3, #4]
- 80039fe: 4ab8 ldr r2, [pc, #736] ; (8003ce0 <UART_SetConfig+0x32c>)
- 8003a00: 4013 ands r3, r2
- 8003a02: 0019 movs r1, r3
- 8003a04: 69fb ldr r3, [r7, #28]
- 8003a06: 68da ldr r2, [r3, #12]
8003a08: 69fb ldr r3, [r7, #28]
8003a0a: 681b ldr r3, [r3, #0]
- 8003a0c: 430a orrs r2, r1
- 8003a0e: 605a str r2, [r3, #4]
+ 8003a0c: 685b ldr r3, [r3, #4]
+ 8003a0e: 4ab8 ldr r2, [pc, #736] ; (8003cf0 <UART_SetConfig+0x32c>)
+ 8003a10: 4013 ands r3, r2
+ 8003a12: 0019 movs r1, r3
+ 8003a14: 69fb ldr r3, [r7, #28]
+ 8003a16: 68da ldr r2, [r3, #12]
+ 8003a18: 69fb ldr r3, [r7, #28]
+ 8003a1a: 681b ldr r3, [r3, #0]
+ 8003a1c: 430a orrs r2, r1
+ 8003a1e: 605a str r2, [r3, #4]
/* Configure
* - UART HardWare Flow Control: set CTSE and RTSE bits according
* to huart->Init.HwFlowCtl value
* - one-bit sampling method versus three samples' majority rule according
* to huart->Init.OneBitSampling (not applicable to LPUART) */
tmpreg = (uint32_t)huart->Init.HwFlowCtl;
- 8003a10: 69fb ldr r3, [r7, #28]
- 8003a12: 699b ldr r3, [r3, #24]
- 8003a14: 637b str r3, [r7, #52] ; 0x34
+ 8003a20: 69fb ldr r3, [r7, #28]
+ 8003a22: 699b ldr r3, [r3, #24]
+ 8003a24: 637b str r3, [r7, #52] ; 0x34
if (!(UART_INSTANCE_LOWPOWER(huart)))
- 8003a16: 69fb ldr r3, [r7, #28]
- 8003a18: 681b ldr r3, [r3, #0]
- 8003a1a: 4ab2 ldr r2, [pc, #712] ; (8003ce4 <UART_SetConfig+0x330>)
- 8003a1c: 4293 cmp r3, r2
- 8003a1e: d004 beq.n 8003a2a <UART_SetConfig+0x76>
+ 8003a26: 69fb ldr r3, [r7, #28]
+ 8003a28: 681b ldr r3, [r3, #0]
+ 8003a2a: 4ab2 ldr r2, [pc, #712] ; (8003cf4 <UART_SetConfig+0x330>)
+ 8003a2c: 4293 cmp r3, r2
+ 8003a2e: d004 beq.n 8003a3a <UART_SetConfig+0x76>
{
tmpreg |= huart->Init.OneBitSampling;
- 8003a20: 69fb ldr r3, [r7, #28]
- 8003a22: 6a1b ldr r3, [r3, #32]
- 8003a24: 6b7a ldr r2, [r7, #52] ; 0x34
- 8003a26: 4313 orrs r3, r2
- 8003a28: 637b str r3, [r7, #52] ; 0x34
+ 8003a30: 69fb ldr r3, [r7, #28]
+ 8003a32: 6a1b ldr r3, [r3, #32]
+ 8003a34: 6b7a ldr r2, [r7, #52] ; 0x34
+ 8003a36: 4313 orrs r3, r2
+ 8003a38: 637b str r3, [r7, #52] ; 0x34
}
MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg);
- 8003a2a: 69fb ldr r3, [r7, #28]
- 8003a2c: 681b ldr r3, [r3, #0]
- 8003a2e: 689b ldr r3, [r3, #8]
- 8003a30: 4aad ldr r2, [pc, #692] ; (8003ce8 <UART_SetConfig+0x334>)
- 8003a32: 4013 ands r3, r2
- 8003a34: 0019 movs r1, r3
- 8003a36: 69fb ldr r3, [r7, #28]
- 8003a38: 681b ldr r3, [r3, #0]
- 8003a3a: 6b7a ldr r2, [r7, #52] ; 0x34
- 8003a3c: 430a orrs r2, r1
- 8003a3e: 609a str r2, [r3, #8]
+ 8003a3a: 69fb ldr r3, [r7, #28]
+ 8003a3c: 681b ldr r3, [r3, #0]
+ 8003a3e: 689b ldr r3, [r3, #8]
+ 8003a40: 4aad ldr r2, [pc, #692] ; (8003cf8 <UART_SetConfig+0x334>)
+ 8003a42: 4013 ands r3, r2
+ 8003a44: 0019 movs r1, r3
+ 8003a46: 69fb ldr r3, [r7, #28]
+ 8003a48: 681b ldr r3, [r3, #0]
+ 8003a4a: 6b7a ldr r2, [r7, #52] ; 0x34
+ 8003a4c: 430a orrs r2, r1
+ 8003a4e: 609a str r2, [r3, #8]
/*-------------------------- USART BRR Configuration -----------------------*/
UART_GETCLOCKSOURCE(huart, clocksource);
- 8003a40: 69fb ldr r3, [r7, #28]
- 8003a42: 681b ldr r3, [r3, #0]
- 8003a44: 4aa9 ldr r2, [pc, #676] ; (8003cec <UART_SetConfig+0x338>)
- 8003a46: 4293 cmp r3, r2
- 8003a48: d136 bne.n 8003ab8 <UART_SetConfig+0x104>
- 8003a4a: 4ba9 ldr r3, [pc, #676] ; (8003cf0 <UART_SetConfig+0x33c>)
- 8003a4c: 6cdb ldr r3, [r3, #76] ; 0x4c
- 8003a4e: 220c movs r2, #12
- 8003a50: 4013 ands r3, r2
- 8003a52: 2b0c cmp r3, #12
- 8003a54: d020 beq.n 8003a98 <UART_SetConfig+0xe4>
- 8003a56: d827 bhi.n 8003aa8 <UART_SetConfig+0xf4>
- 8003a58: 2b08 cmp r3, #8
- 8003a5a: d00d beq.n 8003a78 <UART_SetConfig+0xc4>
- 8003a5c: d824 bhi.n 8003aa8 <UART_SetConfig+0xf4>
- 8003a5e: 2b00 cmp r3, #0
- 8003a60: d002 beq.n 8003a68 <UART_SetConfig+0xb4>
- 8003a62: 2b04 cmp r3, #4
- 8003a64: d010 beq.n 8003a88 <UART_SetConfig+0xd4>
- 8003a66: e01f b.n 8003aa8 <UART_SetConfig+0xf4>
- 8003a68: 231b movs r3, #27
- 8003a6a: 2218 movs r2, #24
- 8003a6c: 4694 mov ip, r2
- 8003a6e: 44bc add ip, r7
- 8003a70: 4463 add r3, ip
- 8003a72: 2200 movs r2, #0
- 8003a74: 701a strb r2, [r3, #0]
- 8003a76: e06f b.n 8003b58 <UART_SetConfig+0x1a4>
+ 8003a50: 69fb ldr r3, [r7, #28]
+ 8003a52: 681b ldr r3, [r3, #0]
+ 8003a54: 4aa9 ldr r2, [pc, #676] ; (8003cfc <UART_SetConfig+0x338>)
+ 8003a56: 4293 cmp r3, r2
+ 8003a58: d136 bne.n 8003ac8 <UART_SetConfig+0x104>
+ 8003a5a: 4ba9 ldr r3, [pc, #676] ; (8003d00 <UART_SetConfig+0x33c>)
+ 8003a5c: 6cdb ldr r3, [r3, #76] ; 0x4c
+ 8003a5e: 220c movs r2, #12
+ 8003a60: 4013 ands r3, r2
+ 8003a62: 2b0c cmp r3, #12
+ 8003a64: d020 beq.n 8003aa8 <UART_SetConfig+0xe4>
+ 8003a66: d827 bhi.n 8003ab8 <UART_SetConfig+0xf4>
+ 8003a68: 2b08 cmp r3, #8
+ 8003a6a: d00d beq.n 8003a88 <UART_SetConfig+0xc4>
+ 8003a6c: d824 bhi.n 8003ab8 <UART_SetConfig+0xf4>
+ 8003a6e: 2b00 cmp r3, #0
+ 8003a70: d002 beq.n 8003a78 <UART_SetConfig+0xb4>
+ 8003a72: 2b04 cmp r3, #4
+ 8003a74: d010 beq.n 8003a98 <UART_SetConfig+0xd4>
+ 8003a76: e01f b.n 8003ab8 <UART_SetConfig+0xf4>
8003a78: 231b movs r3, #27
8003a7a: 2218 movs r2, #24
8003a7c: 4694 mov ip, r2
8003a7e: 44bc add ip, r7
8003a80: 4463 add r3, ip
- 8003a82: 2202 movs r2, #2
+ 8003a82: 2200 movs r2, #0
8003a84: 701a strb r2, [r3, #0]
- 8003a86: e067 b.n 8003b58 <UART_SetConfig+0x1a4>
+ 8003a86: e06f b.n 8003b68 <UART_SetConfig+0x1a4>
8003a88: 231b movs r3, #27
8003a8a: 2218 movs r2, #24
8003a8c: 4694 mov ip, r2
8003a8e: 44bc add ip, r7
8003a90: 4463 add r3, ip
- 8003a92: 2204 movs r2, #4
+ 8003a92: 2202 movs r2, #2
8003a94: 701a strb r2, [r3, #0]
- 8003a96: e05f b.n 8003b58 <UART_SetConfig+0x1a4>
+ 8003a96: e067 b.n 8003b68 <UART_SetConfig+0x1a4>
8003a98: 231b movs r3, #27
8003a9a: 2218 movs r2, #24
8003a9c: 4694 mov ip, r2
8003a9e: 44bc add ip, r7
8003aa0: 4463 add r3, ip
- 8003aa2: 2208 movs r2, #8
+ 8003aa2: 2204 movs r2, #4
8003aa4: 701a strb r2, [r3, #0]
- 8003aa6: e057 b.n 8003b58 <UART_SetConfig+0x1a4>
+ 8003aa6: e05f b.n 8003b68 <UART_SetConfig+0x1a4>
8003aa8: 231b movs r3, #27
8003aaa: 2218 movs r2, #24
8003aac: 4694 mov ip, r2
8003aae: 44bc add ip, r7
8003ab0: 4463 add r3, ip
- 8003ab2: 2210 movs r2, #16
+ 8003ab2: 2208 movs r2, #8
8003ab4: 701a strb r2, [r3, #0]
- 8003ab6: e04f b.n 8003b58 <UART_SetConfig+0x1a4>
- 8003ab8: 69fb ldr r3, [r7, #28]
- 8003aba: 681b ldr r3, [r3, #0]
- 8003abc: 4a89 ldr r2, [pc, #548] ; (8003ce4 <UART_SetConfig+0x330>)
- 8003abe: 4293 cmp r3, r2
- 8003ac0: d143 bne.n 8003b4a <UART_SetConfig+0x196>
- 8003ac2: 4b8b ldr r3, [pc, #556] ; (8003cf0 <UART_SetConfig+0x33c>)
- 8003ac4: 6cda ldr r2, [r3, #76] ; 0x4c
- 8003ac6: 23c0 movs r3, #192 ; 0xc0
- 8003ac8: 011b lsls r3, r3, #4
- 8003aca: 4013 ands r3, r2
- 8003acc: 22c0 movs r2, #192 ; 0xc0
- 8003ace: 0112 lsls r2, r2, #4
- 8003ad0: 4293 cmp r3, r2
- 8003ad2: d02a beq.n 8003b2a <UART_SetConfig+0x176>
- 8003ad4: 22c0 movs r2, #192 ; 0xc0
- 8003ad6: 0112 lsls r2, r2, #4
- 8003ad8: 4293 cmp r3, r2
- 8003ada: d82e bhi.n 8003b3a <UART_SetConfig+0x186>
- 8003adc: 2280 movs r2, #128 ; 0x80
+ 8003ab6: e057 b.n 8003b68 <UART_SetConfig+0x1a4>
+ 8003ab8: 231b movs r3, #27
+ 8003aba: 2218 movs r2, #24
+ 8003abc: 4694 mov ip, r2
+ 8003abe: 44bc add ip, r7
+ 8003ac0: 4463 add r3, ip
+ 8003ac2: 2210 movs r2, #16
+ 8003ac4: 701a strb r2, [r3, #0]
+ 8003ac6: e04f b.n 8003b68 <UART_SetConfig+0x1a4>
+ 8003ac8: 69fb ldr r3, [r7, #28]
+ 8003aca: 681b ldr r3, [r3, #0]
+ 8003acc: 4a89 ldr r2, [pc, #548] ; (8003cf4 <UART_SetConfig+0x330>)
+ 8003ace: 4293 cmp r3, r2
+ 8003ad0: d143 bne.n 8003b5a <UART_SetConfig+0x196>
+ 8003ad2: 4b8b ldr r3, [pc, #556] ; (8003d00 <UART_SetConfig+0x33c>)
+ 8003ad4: 6cda ldr r2, [r3, #76] ; 0x4c
+ 8003ad6: 23c0 movs r3, #192 ; 0xc0
+ 8003ad8: 011b lsls r3, r3, #4
+ 8003ada: 4013 ands r3, r2
+ 8003adc: 22c0 movs r2, #192 ; 0xc0
8003ade: 0112 lsls r2, r2, #4
8003ae0: 4293 cmp r3, r2
- 8003ae2: d012 beq.n 8003b0a <UART_SetConfig+0x156>
- 8003ae4: 2280 movs r2, #128 ; 0x80
+ 8003ae2: d02a beq.n 8003b3a <UART_SetConfig+0x176>
+ 8003ae4: 22c0 movs r2, #192 ; 0xc0
8003ae6: 0112 lsls r2, r2, #4
8003ae8: 4293 cmp r3, r2
- 8003aea: d826 bhi.n 8003b3a <UART_SetConfig+0x186>
- 8003aec: 2b00 cmp r3, #0
- 8003aee: d004 beq.n 8003afa <UART_SetConfig+0x146>
- 8003af0: 2280 movs r2, #128 ; 0x80
- 8003af2: 00d2 lsls r2, r2, #3
- 8003af4: 4293 cmp r3, r2
- 8003af6: d010 beq.n 8003b1a <UART_SetConfig+0x166>
- 8003af8: e01f b.n 8003b3a <UART_SetConfig+0x186>
- 8003afa: 231b movs r3, #27
- 8003afc: 2218 movs r2, #24
- 8003afe: 4694 mov ip, r2
- 8003b00: 44bc add ip, r7
- 8003b02: 4463 add r3, ip
- 8003b04: 2200 movs r2, #0
- 8003b06: 701a strb r2, [r3, #0]
- 8003b08: e026 b.n 8003b58 <UART_SetConfig+0x1a4>
+ 8003aea: d82e bhi.n 8003b4a <UART_SetConfig+0x186>
+ 8003aec: 2280 movs r2, #128 ; 0x80
+ 8003aee: 0112 lsls r2, r2, #4
+ 8003af0: 4293 cmp r3, r2
+ 8003af2: d012 beq.n 8003b1a <UART_SetConfig+0x156>
+ 8003af4: 2280 movs r2, #128 ; 0x80
+ 8003af6: 0112 lsls r2, r2, #4
+ 8003af8: 4293 cmp r3, r2
+ 8003afa: d826 bhi.n 8003b4a <UART_SetConfig+0x186>
+ 8003afc: 2b00 cmp r3, #0
+ 8003afe: d004 beq.n 8003b0a <UART_SetConfig+0x146>
+ 8003b00: 2280 movs r2, #128 ; 0x80
+ 8003b02: 00d2 lsls r2, r2, #3
+ 8003b04: 4293 cmp r3, r2
+ 8003b06: d010 beq.n 8003b2a <UART_SetConfig+0x166>
+ 8003b08: e01f b.n 8003b4a <UART_SetConfig+0x186>
8003b0a: 231b movs r3, #27
8003b0c: 2218 movs r2, #24
8003b0e: 4694 mov ip, r2
8003b10: 44bc add ip, r7
8003b12: 4463 add r3, ip
- 8003b14: 2202 movs r2, #2
+ 8003b14: 2200 movs r2, #0
8003b16: 701a strb r2, [r3, #0]
- 8003b18: e01e b.n 8003b58 <UART_SetConfig+0x1a4>
+ 8003b18: e026 b.n 8003b68 <UART_SetConfig+0x1a4>
8003b1a: 231b movs r3, #27
8003b1c: 2218 movs r2, #24
8003b1e: 4694 mov ip, r2
8003b20: 44bc add ip, r7
8003b22: 4463 add r3, ip
- 8003b24: 2204 movs r2, #4
+ 8003b24: 2202 movs r2, #2
8003b26: 701a strb r2, [r3, #0]
- 8003b28: e016 b.n 8003b58 <UART_SetConfig+0x1a4>
+ 8003b28: e01e b.n 8003b68 <UART_SetConfig+0x1a4>
8003b2a: 231b movs r3, #27
8003b2c: 2218 movs r2, #24
8003b2e: 4694 mov ip, r2
8003b30: 44bc add ip, r7
8003b32: 4463 add r3, ip
- 8003b34: 2208 movs r2, #8
+ 8003b34: 2204 movs r2, #4
8003b36: 701a strb r2, [r3, #0]
- 8003b38: e00e b.n 8003b58 <UART_SetConfig+0x1a4>
+ 8003b38: e016 b.n 8003b68 <UART_SetConfig+0x1a4>
8003b3a: 231b movs r3, #27
8003b3c: 2218 movs r2, #24
8003b3e: 4694 mov ip, r2
8003b40: 44bc add ip, r7
8003b42: 4463 add r3, ip
- 8003b44: 2210 movs r2, #16
+ 8003b44: 2208 movs r2, #8
8003b46: 701a strb r2, [r3, #0]
- 8003b48: e006 b.n 8003b58 <UART_SetConfig+0x1a4>
+ 8003b48: e00e b.n 8003b68 <UART_SetConfig+0x1a4>
8003b4a: 231b movs r3, #27
8003b4c: 2218 movs r2, #24
8003b4e: 4694 mov ip, r2
@@ -10741,1406 +10740,1414 @@ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart)
8003b52: 4463 add r3, ip
8003b54: 2210 movs r2, #16
8003b56: 701a strb r2, [r3, #0]
+ 8003b58: e006 b.n 8003b68 <UART_SetConfig+0x1a4>
+ 8003b5a: 231b movs r3, #27
+ 8003b5c: 2218 movs r2, #24
+ 8003b5e: 4694 mov ip, r2
+ 8003b60: 44bc add ip, r7
+ 8003b62: 4463 add r3, ip
+ 8003b64: 2210 movs r2, #16
+ 8003b66: 701a strb r2, [r3, #0]
/* Check LPUART instance */
if (UART_INSTANCE_LOWPOWER(huart))
- 8003b58: 69fb ldr r3, [r7, #28]
- 8003b5a: 681b ldr r3, [r3, #0]
- 8003b5c: 4a61 ldr r2, [pc, #388] ; (8003ce4 <UART_SetConfig+0x330>)
- 8003b5e: 4293 cmp r3, r2
- 8003b60: d000 beq.n 8003b64 <UART_SetConfig+0x1b0>
- 8003b62: e088 b.n 8003c76 <UART_SetConfig+0x2c2>
+ 8003b68: 69fb ldr r3, [r7, #28]
+ 8003b6a: 681b ldr r3, [r3, #0]
+ 8003b6c: 4a61 ldr r2, [pc, #388] ; (8003cf4 <UART_SetConfig+0x330>)
+ 8003b6e: 4293 cmp r3, r2
+ 8003b70: d000 beq.n 8003b74 <UART_SetConfig+0x1b0>
+ 8003b72: e088 b.n 8003c86 <UART_SetConfig+0x2c2>
{
/* Retrieve frequency clock */
switch (clocksource)
- 8003b64: 231b movs r3, #27
- 8003b66: 2218 movs r2, #24
- 8003b68: 4694 mov ip, r2
- 8003b6a: 44bc add ip, r7
- 8003b6c: 4463 add r3, ip
- 8003b6e: 781b ldrb r3, [r3, #0]
- 8003b70: 2b08 cmp r3, #8
- 8003b72: d01d beq.n 8003bb0 <UART_SetConfig+0x1fc>
- 8003b74: dc20 bgt.n 8003bb8 <UART_SetConfig+0x204>
- 8003b76: 2b04 cmp r3, #4
- 8003b78: d015 beq.n 8003ba6 <UART_SetConfig+0x1f2>
- 8003b7a: dc1d bgt.n 8003bb8 <UART_SetConfig+0x204>
- 8003b7c: 2b00 cmp r3, #0
- 8003b7e: d002 beq.n 8003b86 <UART_SetConfig+0x1d2>
- 8003b80: 2b02 cmp r3, #2
- 8003b82: d005 beq.n 8003b90 <UART_SetConfig+0x1dc>
- 8003b84: e018 b.n 8003bb8 <UART_SetConfig+0x204>
+ 8003b74: 231b movs r3, #27
+ 8003b76: 2218 movs r2, #24
+ 8003b78: 4694 mov ip, r2
+ 8003b7a: 44bc add ip, r7
+ 8003b7c: 4463 add r3, ip
+ 8003b7e: 781b ldrb r3, [r3, #0]
+ 8003b80: 2b08 cmp r3, #8
+ 8003b82: d01d beq.n 8003bc0 <UART_SetConfig+0x1fc>
+ 8003b84: dc20 bgt.n 8003bc8 <UART_SetConfig+0x204>
+ 8003b86: 2b04 cmp r3, #4
+ 8003b88: d015 beq.n 8003bb6 <UART_SetConfig+0x1f2>
+ 8003b8a: dc1d bgt.n 8003bc8 <UART_SetConfig+0x204>
+ 8003b8c: 2b00 cmp r3, #0
+ 8003b8e: d002 beq.n 8003b96 <UART_SetConfig+0x1d2>
+ 8003b90: 2b02 cmp r3, #2
+ 8003b92: d005 beq.n 8003ba0 <UART_SetConfig+0x1dc>
+ 8003b94: e018 b.n 8003bc8 <UART_SetConfig+0x204>
{
case UART_CLOCKSOURCE_PCLK1:
pclk = HAL_RCC_GetPCLK1Freq();
- 8003b86: f7ff f957 bl 8002e38 <HAL_RCC_GetPCLK1Freq>
- 8003b8a: 0003 movs r3, r0
- 8003b8c: 62fb str r3, [r7, #44] ; 0x2c
+ 8003b96: f7ff f957 bl 8002e48 <HAL_RCC_GetPCLK1Freq>
+ 8003b9a: 0003 movs r3, r0
+ 8003b9c: 62fb str r3, [r7, #44] ; 0x2c
break;
- 8003b8e: e01d b.n 8003bcc <UART_SetConfig+0x218>
+ 8003b9e: e01d b.n 8003bdc <UART_SetConfig+0x218>
case UART_CLOCKSOURCE_HSI:
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
- 8003b90: 4b57 ldr r3, [pc, #348] ; (8003cf0 <UART_SetConfig+0x33c>)
- 8003b92: 681b ldr r3, [r3, #0]
- 8003b94: 2210 movs r2, #16
- 8003b96: 4013 ands r3, r2
- 8003b98: d002 beq.n 8003ba0 <UART_SetConfig+0x1ec>
+ 8003ba0: 4b57 ldr r3, [pc, #348] ; (8003d00 <UART_SetConfig+0x33c>)
+ 8003ba2: 681b ldr r3, [r3, #0]
+ 8003ba4: 2210 movs r2, #16
+ 8003ba6: 4013 ands r3, r2
+ 8003ba8: d002 beq.n 8003bb0 <UART_SetConfig+0x1ec>
{
pclk = (uint32_t)(HSI_VALUE >> 2U);
- 8003b9a: 4b56 ldr r3, [pc, #344] ; (8003cf4 <UART_SetConfig+0x340>)
- 8003b9c: 62fb str r3, [r7, #44] ; 0x2c
+ 8003baa: 4b56 ldr r3, [pc, #344] ; (8003d04 <UART_SetConfig+0x340>)
+ 8003bac: 62fb str r3, [r7, #44] ; 0x2c
}
else
{
pclk = (uint32_t) HSI_VALUE;
}
break;
- 8003b9e: e015 b.n 8003bcc <UART_SetConfig+0x218>
+ 8003bae: e015 b.n 8003bdc <UART_SetConfig+0x218>
pclk = (uint32_t) HSI_VALUE;
- 8003ba0: 4b55 ldr r3, [pc, #340] ; (8003cf8 <UART_SetConfig+0x344>)
- 8003ba2: 62fb str r3, [r7, #44] ; 0x2c
+ 8003bb0: 4b55 ldr r3, [pc, #340] ; (8003d08 <UART_SetConfig+0x344>)
+ 8003bb2: 62fb str r3, [r7, #44] ; 0x2c
break;
- 8003ba4: e012 b.n 8003bcc <UART_SetConfig+0x218>
+ 8003bb4: e012 b.n 8003bdc <UART_SetConfig+0x218>
case UART_CLOCKSOURCE_SYSCLK:
pclk = HAL_RCC_GetSysClockFreq();
- 8003ba6: f7ff f897 bl 8002cd8 <HAL_RCC_GetSysClockFreq>
- 8003baa: 0003 movs r3, r0
- 8003bac: 62fb str r3, [r7, #44] ; 0x2c
+ 8003bb6: f7ff f897 bl 8002ce8 <HAL_RCC_GetSysClockFreq>
+ 8003bba: 0003 movs r3, r0
+ 8003bbc: 62fb str r3, [r7, #44] ; 0x2c
break;
- 8003bae: e00d b.n 8003bcc <UART_SetConfig+0x218>
+ 8003bbe: e00d b.n 8003bdc <UART_SetConfig+0x218>
case UART_CLOCKSOURCE_LSE:
pclk = (uint32_t) LSE_VALUE;
- 8003bb0: 2380 movs r3, #128 ; 0x80
- 8003bb2: 021b lsls r3, r3, #8
- 8003bb4: 62fb str r3, [r7, #44] ; 0x2c
+ 8003bc0: 2380 movs r3, #128 ; 0x80
+ 8003bc2: 021b lsls r3, r3, #8
+ 8003bc4: 62fb str r3, [r7, #44] ; 0x2c
break;
- 8003bb6: e009 b.n 8003bcc <UART_SetConfig+0x218>
+ 8003bc6: e009 b.n 8003bdc <UART_SetConfig+0x218>
default:
pclk = 0U;
- 8003bb8: 2300 movs r3, #0
- 8003bba: 62fb str r3, [r7, #44] ; 0x2c
+ 8003bc8: 2300 movs r3, #0
+ 8003bca: 62fb str r3, [r7, #44] ; 0x2c
ret = HAL_ERROR;
- 8003bbc: 231a movs r3, #26
- 8003bbe: 2218 movs r2, #24
- 8003bc0: 4694 mov ip, r2
- 8003bc2: 44bc add ip, r7
- 8003bc4: 4463 add r3, ip
- 8003bc6: 2201 movs r2, #1
- 8003bc8: 701a strb r2, [r3, #0]
+ 8003bcc: 231a movs r3, #26
+ 8003bce: 2218 movs r2, #24
+ 8003bd0: 4694 mov ip, r2
+ 8003bd2: 44bc add ip, r7
+ 8003bd4: 4463 add r3, ip
+ 8003bd6: 2201 movs r2, #1
+ 8003bd8: 701a strb r2, [r3, #0]
break;
- 8003bca: 46c0 nop ; (mov r8, r8)
+ 8003bda: 46c0 nop ; (mov r8, r8)
}
/* If proper clock source reported */
if (pclk != 0U)
- 8003bcc: 6afb ldr r3, [r7, #44] ; 0x2c
- 8003bce: 2b00 cmp r3, #0
- 8003bd0: d100 bne.n 8003bd4 <UART_SetConfig+0x220>
- 8003bd2: e139 b.n 8003e48 <UART_SetConfig+0x494>
+ 8003bdc: 6afb ldr r3, [r7, #44] ; 0x2c
+ 8003bde: 2b00 cmp r3, #0
+ 8003be0: d100 bne.n 8003be4 <UART_SetConfig+0x220>
+ 8003be2: e139 b.n 8003e58 <UART_SetConfig+0x494>
{
/* No Prescaler applicable */
/* Ensure that Frequency clock is in the range [3 * baudrate, 4096 * baudrate] */
if ((pclk < (3U * huart->Init.BaudRate)) ||
- 8003bd4: 69fb ldr r3, [r7, #28]
- 8003bd6: 685a ldr r2, [r3, #4]
- 8003bd8: 0013 movs r3, r2
- 8003bda: 005b lsls r3, r3, #1
- 8003bdc: 189b adds r3, r3, r2
- 8003bde: 6afa ldr r2, [r7, #44] ; 0x2c
- 8003be0: 429a cmp r2, r3
- 8003be2: d305 bcc.n 8003bf0 <UART_SetConfig+0x23c>
- (pclk > (4096U * huart->Init.BaudRate)))
8003be4: 69fb ldr r3, [r7, #28]
- 8003be6: 685b ldr r3, [r3, #4]
- 8003be8: 031b lsls r3, r3, #12
+ 8003be6: 685a ldr r2, [r3, #4]
+ 8003be8: 0013 movs r3, r2
+ 8003bea: 005b lsls r3, r3, #1
+ 8003bec: 189b adds r3, r3, r2
+ 8003bee: 6afa ldr r2, [r7, #44] ; 0x2c
+ 8003bf0: 429a cmp r2, r3
+ 8003bf2: d305 bcc.n 8003c00 <UART_SetConfig+0x23c>
+ (pclk > (4096U * huart->Init.BaudRate)))
+ 8003bf4: 69fb ldr r3, [r7, #28]
+ 8003bf6: 685b ldr r3, [r3, #4]
+ 8003bf8: 031b lsls r3, r3, #12
if ((pclk < (3U * huart->Init.BaudRate)) ||
- 8003bea: 6afa ldr r2, [r7, #44] ; 0x2c
- 8003bec: 429a cmp r2, r3
- 8003bee: d907 bls.n 8003c00 <UART_SetConfig+0x24c>
+ 8003bfa: 6afa ldr r2, [r7, #44] ; 0x2c
+ 8003bfc: 429a cmp r2, r3
+ 8003bfe: d907 bls.n 8003c10 <UART_SetConfig+0x24c>
{
ret = HAL_ERROR;
- 8003bf0: 231a movs r3, #26
- 8003bf2: 2218 movs r2, #24
- 8003bf4: 4694 mov ip, r2
- 8003bf6: 44bc add ip, r7
- 8003bf8: 4463 add r3, ip
- 8003bfa: 2201 movs r2, #1
- 8003bfc: 701a strb r2, [r3, #0]
- 8003bfe: e123 b.n 8003e48 <UART_SetConfig+0x494>
+ 8003c00: 231a movs r3, #26
+ 8003c02: 2218 movs r2, #24
+ 8003c04: 4694 mov ip, r2
+ 8003c06: 44bc add ip, r7
+ 8003c08: 4463 add r3, ip
+ 8003c0a: 2201 movs r2, #1
+ 8003c0c: 701a strb r2, [r3, #0]
+ 8003c0e: e123 b.n 8003e58 <UART_SetConfig+0x494>
}
else
{
usartdiv = (uint32_t)(UART_DIV_LPUART(pclk, huart->Init.BaudRate));
- 8003c00: 6afb ldr r3, [r7, #44] ; 0x2c
- 8003c02: 613b str r3, [r7, #16]
- 8003c04: 2300 movs r3, #0
- 8003c06: 617b str r3, [r7, #20]
- 8003c08: 6939 ldr r1, [r7, #16]
- 8003c0a: 697a ldr r2, [r7, #20]
- 8003c0c: 000b movs r3, r1
- 8003c0e: 0e1b lsrs r3, r3, #24
- 8003c10: 0010 movs r0, r2
- 8003c12: 0205 lsls r5, r0, #8
- 8003c14: 431d orrs r5, r3
- 8003c16: 000b movs r3, r1
- 8003c18: 021c lsls r4, r3, #8
- 8003c1a: 69fb ldr r3, [r7, #28]
- 8003c1c: 685b ldr r3, [r3, #4]
- 8003c1e: 085b lsrs r3, r3, #1
- 8003c20: 60bb str r3, [r7, #8]
- 8003c22: 2300 movs r3, #0
- 8003c24: 60fb str r3, [r7, #12]
- 8003c26: 68b8 ldr r0, [r7, #8]
- 8003c28: 68f9 ldr r1, [r7, #12]
- 8003c2a: 1900 adds r0, r0, r4
- 8003c2c: 4169 adcs r1, r5
- 8003c2e: 69fb ldr r3, [r7, #28]
- 8003c30: 685b ldr r3, [r3, #4]
- 8003c32: 603b str r3, [r7, #0]
- 8003c34: 2300 movs r3, #0
- 8003c36: 607b str r3, [r7, #4]
- 8003c38: 683a ldr r2, [r7, #0]
- 8003c3a: 687b ldr r3, [r7, #4]
- 8003c3c: f7fc faf0 bl 8000220 <__aeabi_uldivmod>
- 8003c40: 0002 movs r2, r0
- 8003c42: 000b movs r3, r1
- 8003c44: 0013 movs r3, r2
- 8003c46: 62bb str r3, [r7, #40] ; 0x28
+ 8003c10: 6afb ldr r3, [r7, #44] ; 0x2c
+ 8003c12: 613b str r3, [r7, #16]
+ 8003c14: 2300 movs r3, #0
+ 8003c16: 617b str r3, [r7, #20]
+ 8003c18: 6939 ldr r1, [r7, #16]
+ 8003c1a: 697a ldr r2, [r7, #20]
+ 8003c1c: 000b movs r3, r1
+ 8003c1e: 0e1b lsrs r3, r3, #24
+ 8003c20: 0010 movs r0, r2
+ 8003c22: 0205 lsls r5, r0, #8
+ 8003c24: 431d orrs r5, r3
+ 8003c26: 000b movs r3, r1
+ 8003c28: 021c lsls r4, r3, #8
+ 8003c2a: 69fb ldr r3, [r7, #28]
+ 8003c2c: 685b ldr r3, [r3, #4]
+ 8003c2e: 085b lsrs r3, r3, #1
+ 8003c30: 60bb str r3, [r7, #8]
+ 8003c32: 2300 movs r3, #0
+ 8003c34: 60fb str r3, [r7, #12]
+ 8003c36: 68b8 ldr r0, [r7, #8]
+ 8003c38: 68f9 ldr r1, [r7, #12]
+ 8003c3a: 1900 adds r0, r0, r4
+ 8003c3c: 4169 adcs r1, r5
+ 8003c3e: 69fb ldr r3, [r7, #28]
+ 8003c40: 685b ldr r3, [r3, #4]
+ 8003c42: 603b str r3, [r7, #0]
+ 8003c44: 2300 movs r3, #0
+ 8003c46: 607b str r3, [r7, #4]
+ 8003c48: 683a ldr r2, [r7, #0]
+ 8003c4a: 687b ldr r3, [r7, #4]
+ 8003c4c: f7fc fae8 bl 8000220 <__aeabi_uldivmod>
+ 8003c50: 0002 movs r2, r0
+ 8003c52: 000b movs r3, r1
+ 8003c54: 0013 movs r3, r2
+ 8003c56: 62bb str r3, [r7, #40] ; 0x28
if ((usartdiv >= LPUART_BRR_MIN) && (usartdiv <= LPUART_BRR_MAX))
- 8003c48: 6aba ldr r2, [r7, #40] ; 0x28
- 8003c4a: 23c0 movs r3, #192 ; 0xc0
- 8003c4c: 009b lsls r3, r3, #2
- 8003c4e: 429a cmp r2, r3
- 8003c50: d309 bcc.n 8003c66 <UART_SetConfig+0x2b2>
- 8003c52: 6aba ldr r2, [r7, #40] ; 0x28
- 8003c54: 2380 movs r3, #128 ; 0x80
- 8003c56: 035b lsls r3, r3, #13
- 8003c58: 429a cmp r2, r3
- 8003c5a: d204 bcs.n 8003c66 <UART_SetConfig+0x2b2>
+ 8003c58: 6aba ldr r2, [r7, #40] ; 0x28
+ 8003c5a: 23c0 movs r3, #192 ; 0xc0
+ 8003c5c: 009b lsls r3, r3, #2
+ 8003c5e: 429a cmp r2, r3
+ 8003c60: d309 bcc.n 8003c76 <UART_SetConfig+0x2b2>
+ 8003c62: 6aba ldr r2, [r7, #40] ; 0x28
+ 8003c64: 2380 movs r3, #128 ; 0x80
+ 8003c66: 035b lsls r3, r3, #13
+ 8003c68: 429a cmp r2, r3
+ 8003c6a: d204 bcs.n 8003c76 <UART_SetConfig+0x2b2>
{
huart->Instance->BRR = usartdiv;
- 8003c5c: 69fb ldr r3, [r7, #28]
- 8003c5e: 681b ldr r3, [r3, #0]
- 8003c60: 6aba ldr r2, [r7, #40] ; 0x28
- 8003c62: 60da str r2, [r3, #12]
- 8003c64: e0f0 b.n 8003e48 <UART_SetConfig+0x494>
+ 8003c6c: 69fb ldr r3, [r7, #28]
+ 8003c6e: 681b ldr r3, [r3, #0]
+ 8003c70: 6aba ldr r2, [r7, #40] ; 0x28
+ 8003c72: 60da str r2, [r3, #12]
+ 8003c74: e0f0 b.n 8003e58 <UART_SetConfig+0x494>
}
else
{
ret = HAL_ERROR;
- 8003c66: 231a movs r3, #26
- 8003c68: 2218 movs r2, #24
- 8003c6a: 4694 mov ip, r2
- 8003c6c: 44bc add ip, r7
- 8003c6e: 4463 add r3, ip
- 8003c70: 2201 movs r2, #1
- 8003c72: 701a strb r2, [r3, #0]
- 8003c74: e0e8 b.n 8003e48 <UART_SetConfig+0x494>
+ 8003c76: 231a movs r3, #26
+ 8003c78: 2218 movs r2, #24
+ 8003c7a: 4694 mov ip, r2
+ 8003c7c: 44bc add ip, r7
+ 8003c7e: 4463 add r3, ip
+ 8003c80: 2201 movs r2, #1
+ 8003c82: 701a strb r2, [r3, #0]
+ 8003c84: e0e8 b.n 8003e58 <UART_SetConfig+0x494>
}
} /* if ( (pclk < (3 * huart->Init.BaudRate) ) || (pclk > (4096 * huart->Init.BaudRate) )) */
} /* if (pclk != 0) */
}
/* Check UART Over Sampling to set Baud Rate Register */
else if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
- 8003c76: 69fb ldr r3, [r7, #28]
- 8003c78: 69da ldr r2, [r3, #28]
- 8003c7a: 2380 movs r3, #128 ; 0x80
- 8003c7c: 021b lsls r3, r3, #8
- 8003c7e: 429a cmp r2, r3
- 8003c80: d000 beq.n 8003c84 <UART_SetConfig+0x2d0>
- 8003c82: e087 b.n 8003d94 <UART_SetConfig+0x3e0>
+ 8003c86: 69fb ldr r3, [r7, #28]
+ 8003c88: 69da ldr r2, [r3, #28]
+ 8003c8a: 2380 movs r3, #128 ; 0x80
+ 8003c8c: 021b lsls r3, r3, #8
+ 8003c8e: 429a cmp r2, r3
+ 8003c90: d000 beq.n 8003c94 <UART_SetConfig+0x2d0>
+ 8003c92: e087 b.n 8003da4 <UART_SetConfig+0x3e0>
{
switch (clocksource)
- 8003c84: 231b movs r3, #27
- 8003c86: 2218 movs r2, #24
- 8003c88: 4694 mov ip, r2
- 8003c8a: 44bc add ip, r7
- 8003c8c: 4463 add r3, ip
- 8003c8e: 781b ldrb r3, [r3, #0]
- 8003c90: 2b08 cmp r3, #8
- 8003c92: d835 bhi.n 8003d00 <UART_SetConfig+0x34c>
- 8003c94: 009a lsls r2, r3, #2
- 8003c96: 4b19 ldr r3, [pc, #100] ; (8003cfc <UART_SetConfig+0x348>)
- 8003c98: 18d3 adds r3, r2, r3
- 8003c9a: 681b ldr r3, [r3, #0]
- 8003c9c: 469f mov pc, r3
+ 8003c94: 231b movs r3, #27
+ 8003c96: 2218 movs r2, #24
+ 8003c98: 4694 mov ip, r2
+ 8003c9a: 44bc add ip, r7
+ 8003c9c: 4463 add r3, ip
+ 8003c9e: 781b ldrb r3, [r3, #0]
+ 8003ca0: 2b08 cmp r3, #8
+ 8003ca2: d835 bhi.n 8003d10 <UART_SetConfig+0x34c>
+ 8003ca4: 009a lsls r2, r3, #2
+ 8003ca6: 4b19 ldr r3, [pc, #100] ; (8003d0c <UART_SetConfig+0x348>)
+ 8003ca8: 18d3 adds r3, r2, r3
+ 8003caa: 681b ldr r3, [r3, #0]
+ 8003cac: 469f mov pc, r3
{
case UART_CLOCKSOURCE_PCLK1:
pclk = HAL_RCC_GetPCLK1Freq();
- 8003c9e: f7ff f8cb bl 8002e38 <HAL_RCC_GetPCLK1Freq>
- 8003ca2: 0003 movs r3, r0
- 8003ca4: 62fb str r3, [r7, #44] ; 0x2c
+ 8003cae: f7ff f8cb bl 8002e48 <HAL_RCC_GetPCLK1Freq>
+ 8003cb2: 0003 movs r3, r0
+ 8003cb4: 62fb str r3, [r7, #44] ; 0x2c
break;
- 8003ca6: e035 b.n 8003d14 <UART_SetConfig+0x360>
+ 8003cb6: e035 b.n 8003d24 <UART_SetConfig+0x360>
case UART_CLOCKSOURCE_PCLK2:
pclk = HAL_RCC_GetPCLK2Freq();
- 8003ca8: f7ff f8dc bl 8002e64 <HAL_RCC_GetPCLK2Freq>
- 8003cac: 0003 movs r3, r0
- 8003cae: 62fb str r3, [r7, #44] ; 0x2c
+ 8003cb8: f7ff f8dc bl 8002e74 <HAL_RCC_GetPCLK2Freq>
+ 8003cbc: 0003 movs r3, r0
+ 8003cbe: 62fb str r3, [r7, #44] ; 0x2c
break;
- 8003cb0: e030 b.n 8003d14 <UART_SetConfig+0x360>
+ 8003cc0: e030 b.n 8003d24 <UART_SetConfig+0x360>
case UART_CLOCKSOURCE_HSI:
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
- 8003cb2: 4b0f ldr r3, [pc, #60] ; (8003cf0 <UART_SetConfig+0x33c>)
- 8003cb4: 681b ldr r3, [r3, #0]
- 8003cb6: 2210 movs r2, #16
- 8003cb8: 4013 ands r3, r2
- 8003cba: d002 beq.n 8003cc2 <UART_SetConfig+0x30e>
+ 8003cc2: 4b0f ldr r3, [pc, #60] ; (8003d00 <UART_SetConfig+0x33c>)
+ 8003cc4: 681b ldr r3, [r3, #0]
+ 8003cc6: 2210 movs r2, #16
+ 8003cc8: 4013 ands r3, r2
+ 8003cca: d002 beq.n 8003cd2 <UART_SetConfig+0x30e>
{
pclk = (uint32_t)(HSI_VALUE >> 2U);
- 8003cbc: 4b0d ldr r3, [pc, #52] ; (8003cf4 <UART_SetConfig+0x340>)
- 8003cbe: 62fb str r3, [r7, #44] ; 0x2c
+ 8003ccc: 4b0d ldr r3, [pc, #52] ; (8003d04 <UART_SetConfig+0x340>)
+ 8003cce: 62fb str r3, [r7, #44] ; 0x2c
}
else
{
pclk = (uint32_t) HSI_VALUE;
}
break;
- 8003cc0: e028 b.n 8003d14 <UART_SetConfig+0x360>
+ 8003cd0: e028 b.n 8003d24 <UART_SetConfig+0x360>
pclk = (uint32_t) HSI_VALUE;
- 8003cc2: 4b0d ldr r3, [pc, #52] ; (8003cf8 <UART_SetConfig+0x344>)
- 8003cc4: 62fb str r3, [r7, #44] ; 0x2c
+ 8003cd2: 4b0d ldr r3, [pc, #52] ; (8003d08 <UART_SetConfig+0x344>)
+ 8003cd4: 62fb str r3, [r7, #44] ; 0x2c
break;
- 8003cc6: e025 b.n 8003d14 <UART_SetConfig+0x360>
+ 8003cd6: e025 b.n 8003d24 <UART_SetConfig+0x360>
case UART_CLOCKSOURCE_SYSCLK:
pclk = HAL_RCC_GetSysClockFreq();
- 8003cc8: f7ff f806 bl 8002cd8 <HAL_RCC_GetSysClockFreq>
- 8003ccc: 0003 movs r3, r0
- 8003cce: 62fb str r3, [r7, #44] ; 0x2c
+ 8003cd8: f7ff f806 bl 8002ce8 <HAL_RCC_GetSysClockFreq>
+ 8003cdc: 0003 movs r3, r0
+ 8003cde: 62fb str r3, [r7, #44] ; 0x2c
break;
- 8003cd0: e020 b.n 8003d14 <UART_SetConfig+0x360>
+ 8003ce0: e020 b.n 8003d24 <UART_SetConfig+0x360>
case UART_CLOCKSOURCE_LSE:
pclk = (uint32_t) LSE_VALUE;
- 8003cd2: 2380 movs r3, #128 ; 0x80
- 8003cd4: 021b lsls r3, r3, #8
- 8003cd6: 62fb str r3, [r7, #44] ; 0x2c
+ 8003ce2: 2380 movs r3, #128 ; 0x80
+ 8003ce4: 021b lsls r3, r3, #8
+ 8003ce6: 62fb str r3, [r7, #44] ; 0x2c
break;
- 8003cd8: e01c b.n 8003d14 <UART_SetConfig+0x360>
- 8003cda: 46c0 nop ; (mov r8, r8)
- 8003cdc: efff69f3 .word 0xefff69f3
- 8003ce0: ffffcfff .word 0xffffcfff
- 8003ce4: 40004800 .word 0x40004800
- 8003ce8: fffff4ff .word 0xfffff4ff
- 8003cec: 40004400 .word 0x40004400
- 8003cf0: 40021000 .word 0x40021000
- 8003cf4: 003d0900 .word 0x003d0900
- 8003cf8: 00f42400 .word 0x00f42400
- 8003cfc: 0800436c .word 0x0800436c
+ 8003ce8: e01c b.n 8003d24 <UART_SetConfig+0x360>
+ 8003cea: 46c0 nop ; (mov r8, r8)
+ 8003cec: efff69f3 .word 0xefff69f3
+ 8003cf0: ffffcfff .word 0xffffcfff
+ 8003cf4: 40004800 .word 0x40004800
+ 8003cf8: fffff4ff .word 0xfffff4ff
+ 8003cfc: 40004400 .word 0x40004400
+ 8003d00: 40021000 .word 0x40021000
+ 8003d04: 003d0900 .word 0x003d0900
+ 8003d08: 00f42400 .word 0x00f42400
+ 8003d0c: 0800437c .word 0x0800437c
default:
pclk = 0U;
- 8003d00: 2300 movs r3, #0
- 8003d02: 62fb str r3, [r7, #44] ; 0x2c
+ 8003d10: 2300 movs r3, #0
+ 8003d12: 62fb str r3, [r7, #44] ; 0x2c
ret = HAL_ERROR;
- 8003d04: 231a movs r3, #26
- 8003d06: 2218 movs r2, #24
- 8003d08: 4694 mov ip, r2
- 8003d0a: 44bc add ip, r7
- 8003d0c: 4463 add r3, ip
- 8003d0e: 2201 movs r2, #1
- 8003d10: 701a strb r2, [r3, #0]
+ 8003d14: 231a movs r3, #26
+ 8003d16: 2218 movs r2, #24
+ 8003d18: 4694 mov ip, r2
+ 8003d1a: 44bc add ip, r7
+ 8003d1c: 4463 add r3, ip
+ 8003d1e: 2201 movs r2, #1
+ 8003d20: 701a strb r2, [r3, #0]
break;
- 8003d12: 46c0 nop ; (mov r8, r8)
+ 8003d22: 46c0 nop ; (mov r8, r8)
}
/* USARTDIV must be greater than or equal to 0d16 */
if (pclk != 0U)
- 8003d14: 6afb ldr r3, [r7, #44] ; 0x2c
- 8003d16: 2b00 cmp r3, #0
- 8003d18: d100 bne.n 8003d1c <UART_SetConfig+0x368>
- 8003d1a: e095 b.n 8003e48 <UART_SetConfig+0x494>
+ 8003d24: 6afb ldr r3, [r7, #44] ; 0x2c
+ 8003d26: 2b00 cmp r3, #0
+ 8003d28: d100 bne.n 8003d2c <UART_SetConfig+0x368>
+ 8003d2a: e095 b.n 8003e58 <UART_SetConfig+0x494>
{
usartdiv = (uint16_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate));
- 8003d1c: 6afb ldr r3, [r7, #44] ; 0x2c
- 8003d1e: 005a lsls r2, r3, #1
- 8003d20: 69fb ldr r3, [r7, #28]
- 8003d22: 685b ldr r3, [r3, #4]
- 8003d24: 085b lsrs r3, r3, #1
- 8003d26: 18d2 adds r2, r2, r3
- 8003d28: 69fb ldr r3, [r7, #28]
- 8003d2a: 685b ldr r3, [r3, #4]
- 8003d2c: 0019 movs r1, r3
- 8003d2e: 0010 movs r0, r2
- 8003d30: f7fc f9ea bl 8000108 <__udivsi3>
- 8003d34: 0003 movs r3, r0
- 8003d36: b29b uxth r3, r3
- 8003d38: 62bb str r3, [r7, #40] ; 0x28
+ 8003d2c: 6afb ldr r3, [r7, #44] ; 0x2c
+ 8003d2e: 005a lsls r2, r3, #1
+ 8003d30: 69fb ldr r3, [r7, #28]
+ 8003d32: 685b ldr r3, [r3, #4]
+ 8003d34: 085b lsrs r3, r3, #1
+ 8003d36: 18d2 adds r2, r2, r3
+ 8003d38: 69fb ldr r3, [r7, #28]
+ 8003d3a: 685b ldr r3, [r3, #4]
+ 8003d3c: 0019 movs r1, r3
+ 8003d3e: 0010 movs r0, r2
+ 8003d40: f7fc f9e2 bl 8000108 <__udivsi3>
+ 8003d44: 0003 movs r3, r0
+ 8003d46: b29b uxth r3, r3
+ 8003d48: 62bb str r3, [r7, #40] ; 0x28
if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
- 8003d3a: 6abb ldr r3, [r7, #40] ; 0x28
- 8003d3c: 2b0f cmp r3, #15
- 8003d3e: d921 bls.n 8003d84 <UART_SetConfig+0x3d0>
- 8003d40: 6aba ldr r2, [r7, #40] ; 0x28
- 8003d42: 2380 movs r3, #128 ; 0x80
- 8003d44: 025b lsls r3, r3, #9
- 8003d46: 429a cmp r2, r3
- 8003d48: d21c bcs.n 8003d84 <UART_SetConfig+0x3d0>
+ 8003d4a: 6abb ldr r3, [r7, #40] ; 0x28
+ 8003d4c: 2b0f cmp r3, #15
+ 8003d4e: d921 bls.n 8003d94 <UART_SetConfig+0x3d0>
+ 8003d50: 6aba ldr r2, [r7, #40] ; 0x28
+ 8003d52: 2380 movs r3, #128 ; 0x80
+ 8003d54: 025b lsls r3, r3, #9
+ 8003d56: 429a cmp r2, r3
+ 8003d58: d21c bcs.n 8003d94 <UART_SetConfig+0x3d0>
{
brrtemp = (uint16_t)(usartdiv & 0xFFF0U);
- 8003d4a: 6abb ldr r3, [r7, #40] ; 0x28
- 8003d4c: b29a uxth r2, r3
- 8003d4e: 200e movs r0, #14
- 8003d50: 2418 movs r4, #24
- 8003d52: 193b adds r3, r7, r4
- 8003d54: 181b adds r3, r3, r0
- 8003d56: 210f movs r1, #15
- 8003d58: 438a bics r2, r1
- 8003d5a: 801a strh r2, [r3, #0]
+ 8003d5a: 6abb ldr r3, [r7, #40] ; 0x28
+ 8003d5c: b29a uxth r2, r3
+ 8003d5e: 200e movs r0, #14
+ 8003d60: 2418 movs r4, #24
+ 8003d62: 193b adds r3, r7, r4
+ 8003d64: 181b adds r3, r3, r0
+ 8003d66: 210f movs r1, #15
+ 8003d68: 438a bics r2, r1
+ 8003d6a: 801a strh r2, [r3, #0]
brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
- 8003d5c: 6abb ldr r3, [r7, #40] ; 0x28
- 8003d5e: 085b lsrs r3, r3, #1
- 8003d60: b29b uxth r3, r3
- 8003d62: 2207 movs r2, #7
- 8003d64: 4013 ands r3, r2
- 8003d66: b299 uxth r1, r3
- 8003d68: 193b adds r3, r7, r4
- 8003d6a: 181b adds r3, r3, r0
- 8003d6c: 193a adds r2, r7, r4
- 8003d6e: 1812 adds r2, r2, r0
- 8003d70: 8812 ldrh r2, [r2, #0]
- 8003d72: 430a orrs r2, r1
- 8003d74: 801a strh r2, [r3, #0]
+ 8003d6c: 6abb ldr r3, [r7, #40] ; 0x28
+ 8003d6e: 085b lsrs r3, r3, #1
+ 8003d70: b29b uxth r3, r3
+ 8003d72: 2207 movs r2, #7
+ 8003d74: 4013 ands r3, r2
+ 8003d76: b299 uxth r1, r3
+ 8003d78: 193b adds r3, r7, r4
+ 8003d7a: 181b adds r3, r3, r0
+ 8003d7c: 193a adds r2, r7, r4
+ 8003d7e: 1812 adds r2, r2, r0
+ 8003d80: 8812 ldrh r2, [r2, #0]
+ 8003d82: 430a orrs r2, r1
+ 8003d84: 801a strh r2, [r3, #0]
huart->Instance->BRR = brrtemp;
- 8003d76: 69fb ldr r3, [r7, #28]
- 8003d78: 681b ldr r3, [r3, #0]
- 8003d7a: 193a adds r2, r7, r4
- 8003d7c: 1812 adds r2, r2, r0
- 8003d7e: 8812 ldrh r2, [r2, #0]
- 8003d80: 60da str r2, [r3, #12]
- 8003d82: e061 b.n 8003e48 <UART_SetConfig+0x494>
+ 8003d86: 69fb ldr r3, [r7, #28]
+ 8003d88: 681b ldr r3, [r3, #0]
+ 8003d8a: 193a adds r2, r7, r4
+ 8003d8c: 1812 adds r2, r2, r0
+ 8003d8e: 8812 ldrh r2, [r2, #0]
+ 8003d90: 60da str r2, [r3, #12]
+ 8003d92: e061 b.n 8003e58 <UART_SetConfig+0x494>
}
else
{
ret = HAL_ERROR;
- 8003d84: 231a movs r3, #26
- 8003d86: 2218 movs r2, #24
- 8003d88: 4694 mov ip, r2
- 8003d8a: 44bc add ip, r7
- 8003d8c: 4463 add r3, ip
- 8003d8e: 2201 movs r2, #1
- 8003d90: 701a strb r2, [r3, #0]
- 8003d92: e059 b.n 8003e48 <UART_SetConfig+0x494>
+ 8003d94: 231a movs r3, #26
+ 8003d96: 2218 movs r2, #24
+ 8003d98: 4694 mov ip, r2
+ 8003d9a: 44bc add ip, r7
+ 8003d9c: 4463 add r3, ip
+ 8003d9e: 2201 movs r2, #1
+ 8003da0: 701a strb r2, [r3, #0]
+ 8003da2: e059 b.n 8003e58 <UART_SetConfig+0x494>
}
}
}
else
{
switch (clocksource)
- 8003d94: 231b movs r3, #27
- 8003d96: 2218 movs r2, #24
- 8003d98: 4694 mov ip, r2
- 8003d9a: 44bc add ip, r7
- 8003d9c: 4463 add r3, ip
- 8003d9e: 781b ldrb r3, [r3, #0]
- 8003da0: 2b08 cmp r3, #8
- 8003da2: d822 bhi.n 8003dea <UART_SetConfig+0x436>
- 8003da4: 009a lsls r2, r3, #2
- 8003da6: 4b30 ldr r3, [pc, #192] ; (8003e68 <UART_SetConfig+0x4b4>)
- 8003da8: 18d3 adds r3, r2, r3
- 8003daa: 681b ldr r3, [r3, #0]
- 8003dac: 469f mov pc, r3
+ 8003da4: 231b movs r3, #27
+ 8003da6: 2218 movs r2, #24
+ 8003da8: 4694 mov ip, r2
+ 8003daa: 44bc add ip, r7
+ 8003dac: 4463 add r3, ip
+ 8003dae: 781b ldrb r3, [r3, #0]
+ 8003db0: 2b08 cmp r3, #8
+ 8003db2: d822 bhi.n 8003dfa <UART_SetConfig+0x436>
+ 8003db4: 009a lsls r2, r3, #2
+ 8003db6: 4b30 ldr r3, [pc, #192] ; (8003e78 <UART_SetConfig+0x4b4>)
+ 8003db8: 18d3 adds r3, r2, r3
+ 8003dba: 681b ldr r3, [r3, #0]
+ 8003dbc: 469f mov pc, r3
{
case UART_CLOCKSOURCE_PCLK1:
pclk = HAL_RCC_GetPCLK1Freq();
- 8003dae: f7ff f843 bl 8002e38 <HAL_RCC_GetPCLK1Freq>
- 8003db2: 0003 movs r3, r0
- 8003db4: 62fb str r3, [r7, #44] ; 0x2c
+ 8003dbe: f7ff f843 bl 8002e48 <HAL_RCC_GetPCLK1Freq>
+ 8003dc2: 0003 movs r3, r0
+ 8003dc4: 62fb str r3, [r7, #44] ; 0x2c
break;
- 8003db6: e022 b.n 8003dfe <UART_SetConfig+0x44a>
+ 8003dc6: e022 b.n 8003e0e <UART_SetConfig+0x44a>
case UART_CLOCKSOURCE_PCLK2:
pclk = HAL_RCC_GetPCLK2Freq();
- 8003db8: f7ff f854 bl 8002e64 <HAL_RCC_GetPCLK2Freq>
- 8003dbc: 0003 movs r3, r0
- 8003dbe: 62fb str r3, [r7, #44] ; 0x2c
+ 8003dc8: f7ff f854 bl 8002e74 <HAL_RCC_GetPCLK2Freq>
+ 8003dcc: 0003 movs r3, r0
+ 8003dce: 62fb str r3, [r7, #44] ; 0x2c
break;
- 8003dc0: e01d b.n 8003dfe <UART_SetConfig+0x44a>
+ 8003dd0: e01d b.n 8003e0e <UART_SetConfig+0x44a>
case UART_CLOCKSOURCE_HSI:
if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
- 8003dc2: 4b2a ldr r3, [pc, #168] ; (8003e6c <UART_SetConfig+0x4b8>)
- 8003dc4: 681b ldr r3, [r3, #0]
- 8003dc6: 2210 movs r2, #16
- 8003dc8: 4013 ands r3, r2
- 8003dca: d002 beq.n 8003dd2 <UART_SetConfig+0x41e>
+ 8003dd2: 4b2a ldr r3, [pc, #168] ; (8003e7c <UART_SetConfig+0x4b8>)
+ 8003dd4: 681b ldr r3, [r3, #0]
+ 8003dd6: 2210 movs r2, #16
+ 8003dd8: 4013 ands r3, r2
+ 8003dda: d002 beq.n 8003de2 <UART_SetConfig+0x41e>
{
pclk = (uint32_t)(HSI_VALUE >> 2U);
- 8003dcc: 4b28 ldr r3, [pc, #160] ; (8003e70 <UART_SetConfig+0x4bc>)
- 8003dce: 62fb str r3, [r7, #44] ; 0x2c
+ 8003ddc: 4b28 ldr r3, [pc, #160] ; (8003e80 <UART_SetConfig+0x4bc>)
+ 8003dde: 62fb str r3, [r7, #44] ; 0x2c
}
else
{
pclk = (uint32_t) HSI_VALUE;
}
break;
- 8003dd0: e015 b.n 8003dfe <UART_SetConfig+0x44a>
+ 8003de0: e015 b.n 8003e0e <UART_SetConfig+0x44a>
pclk = (uint32_t) HSI_VALUE;
- 8003dd2: 4b28 ldr r3, [pc, #160] ; (8003e74 <UART_SetConfig+0x4c0>)
- 8003dd4: 62fb str r3, [r7, #44] ; 0x2c
+ 8003de2: 4b28 ldr r3, [pc, #160] ; (8003e84 <UART_SetConfig+0x4c0>)
+ 8003de4: 62fb str r3, [r7, #44] ; 0x2c
break;
- 8003dd6: e012 b.n 8003dfe <UART_SetConfig+0x44a>
+ 8003de6: e012 b.n 8003e0e <UART_SetConfig+0x44a>
case UART_CLOCKSOURCE_SYSCLK:
pclk = HAL_RCC_GetSysClockFreq();
- 8003dd8: f7fe ff7e bl 8002cd8 <HAL_RCC_GetSysClockFreq>
- 8003ddc: 0003 movs r3, r0
- 8003dde: 62fb str r3, [r7, #44] ; 0x2c
+ 8003de8: f7fe ff7e bl 8002ce8 <HAL_RCC_GetSysClockFreq>
+ 8003dec: 0003 movs r3, r0
+ 8003dee: 62fb str r3, [r7, #44] ; 0x2c
break;
- 8003de0: e00d b.n 8003dfe <UART_SetConfig+0x44a>
+ 8003df0: e00d b.n 8003e0e <UART_SetConfig+0x44a>
case UART_CLOCKSOURCE_LSE:
pclk = (uint32_t) LSE_VALUE;
- 8003de2: 2380 movs r3, #128 ; 0x80
- 8003de4: 021b lsls r3, r3, #8
- 8003de6: 62fb str r3, [r7, #44] ; 0x2c
+ 8003df2: 2380 movs r3, #128 ; 0x80
+ 8003df4: 021b lsls r3, r3, #8
+ 8003df6: 62fb str r3, [r7, #44] ; 0x2c
break;
- 8003de8: e009 b.n 8003dfe <UART_SetConfig+0x44a>
+ 8003df8: e009 b.n 8003e0e <UART_SetConfig+0x44a>
default:
pclk = 0U;
- 8003dea: 2300 movs r3, #0
- 8003dec: 62fb str r3, [r7, #44] ; 0x2c
+ 8003dfa: 2300 movs r3, #0
+ 8003dfc: 62fb str r3, [r7, #44] ; 0x2c
ret = HAL_ERROR;
- 8003dee: 231a movs r3, #26
- 8003df0: 2218 movs r2, #24
- 8003df2: 4694 mov ip, r2
- 8003df4: 44bc add ip, r7
- 8003df6: 4463 add r3, ip
- 8003df8: 2201 movs r2, #1
- 8003dfa: 701a strb r2, [r3, #0]
+ 8003dfe: 231a movs r3, #26
+ 8003e00: 2218 movs r2, #24
+ 8003e02: 4694 mov ip, r2
+ 8003e04: 44bc add ip, r7
+ 8003e06: 4463 add r3, ip
+ 8003e08: 2201 movs r2, #1
+ 8003e0a: 701a strb r2, [r3, #0]
break;
- 8003dfc: 46c0 nop ; (mov r8, r8)
+ 8003e0c: 46c0 nop ; (mov r8, r8)
}
if (pclk != 0U)
- 8003dfe: 6afb ldr r3, [r7, #44] ; 0x2c
- 8003e00: 2b00 cmp r3, #0
- 8003e02: d021 beq.n 8003e48 <UART_SetConfig+0x494>
+ 8003e0e: 6afb ldr r3, [r7, #44] ; 0x2c
+ 8003e10: 2b00 cmp r3, #0
+ 8003e12: d021 beq.n 8003e58 <UART_SetConfig+0x494>
{
/* USARTDIV must be greater than or equal to 0d16 */
usartdiv = (uint16_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate));
- 8003e04: 69fb ldr r3, [r7, #28]
- 8003e06: 685b ldr r3, [r3, #4]
- 8003e08: 085a lsrs r2, r3, #1
- 8003e0a: 6afb ldr r3, [r7, #44] ; 0x2c
- 8003e0c: 18d2 adds r2, r2, r3
- 8003e0e: 69fb ldr r3, [r7, #28]
- 8003e10: 685b ldr r3, [r3, #4]
- 8003e12: 0019 movs r1, r3
- 8003e14: 0010 movs r0, r2
- 8003e16: f7fc f977 bl 8000108 <__udivsi3>
- 8003e1a: 0003 movs r3, r0
- 8003e1c: b29b uxth r3, r3
- 8003e1e: 62bb str r3, [r7, #40] ; 0x28
+ 8003e14: 69fb ldr r3, [r7, #28]
+ 8003e16: 685b ldr r3, [r3, #4]
+ 8003e18: 085a lsrs r2, r3, #1
+ 8003e1a: 6afb ldr r3, [r7, #44] ; 0x2c
+ 8003e1c: 18d2 adds r2, r2, r3
+ 8003e1e: 69fb ldr r3, [r7, #28]
+ 8003e20: 685b ldr r3, [r3, #4]
+ 8003e22: 0019 movs r1, r3
+ 8003e24: 0010 movs r0, r2
+ 8003e26: f7fc f96f bl 8000108 <__udivsi3>
+ 8003e2a: 0003 movs r3, r0
+ 8003e2c: b29b uxth r3, r3
+ 8003e2e: 62bb str r3, [r7, #40] ; 0x28
if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
- 8003e20: 6abb ldr r3, [r7, #40] ; 0x28
- 8003e22: 2b0f cmp r3, #15
- 8003e24: d909 bls.n 8003e3a <UART_SetConfig+0x486>
- 8003e26: 6aba ldr r2, [r7, #40] ; 0x28
- 8003e28: 2380 movs r3, #128 ; 0x80
- 8003e2a: 025b lsls r3, r3, #9
- 8003e2c: 429a cmp r2, r3
- 8003e2e: d204 bcs.n 8003e3a <UART_SetConfig+0x486>
+ 8003e30: 6abb ldr r3, [r7, #40] ; 0x28
+ 8003e32: 2b0f cmp r3, #15
+ 8003e34: d909 bls.n 8003e4a <UART_SetConfig+0x486>
+ 8003e36: 6aba ldr r2, [r7, #40] ; 0x28
+ 8003e38: 2380 movs r3, #128 ; 0x80
+ 8003e3a: 025b lsls r3, r3, #9
+ 8003e3c: 429a cmp r2, r3
+ 8003e3e: d204 bcs.n 8003e4a <UART_SetConfig+0x486>
{
huart->Instance->BRR = usartdiv;
- 8003e30: 69fb ldr r3, [r7, #28]
- 8003e32: 681b ldr r3, [r3, #0]
- 8003e34: 6aba ldr r2, [r7, #40] ; 0x28
- 8003e36: 60da str r2, [r3, #12]
- 8003e38: e006 b.n 8003e48 <UART_SetConfig+0x494>
+ 8003e40: 69fb ldr r3, [r7, #28]
+ 8003e42: 681b ldr r3, [r3, #0]
+ 8003e44: 6aba ldr r2, [r7, #40] ; 0x28
+ 8003e46: 60da str r2, [r3, #12]
+ 8003e48: e006 b.n 8003e58 <UART_SetConfig+0x494>
}
else
{
ret = HAL_ERROR;
- 8003e3a: 231a movs r3, #26
- 8003e3c: 2218 movs r2, #24
- 8003e3e: 4694 mov ip, r2
- 8003e40: 44bc add ip, r7
- 8003e42: 4463 add r3, ip
- 8003e44: 2201 movs r2, #1
- 8003e46: 701a strb r2, [r3, #0]
+ 8003e4a: 231a movs r3, #26
+ 8003e4c: 2218 movs r2, #24
+ 8003e4e: 4694 mov ip, r2
+ 8003e50: 44bc add ip, r7
+ 8003e52: 4463 add r3, ip
+ 8003e54: 2201 movs r2, #1
+ 8003e56: 701a strb r2, [r3, #0]
}
}
/* Clear ISR function pointers */
huart->RxISR = NULL;
- 8003e48: 69fb ldr r3, [r7, #28]
- 8003e4a: 2200 movs r2, #0
- 8003e4c: 665a str r2, [r3, #100] ; 0x64
+ 8003e58: 69fb ldr r3, [r7, #28]
+ 8003e5a: 2200 movs r2, #0
+ 8003e5c: 665a str r2, [r3, #100] ; 0x64
huart->TxISR = NULL;
- 8003e4e: 69fb ldr r3, [r7, #28]
- 8003e50: 2200 movs r2, #0
- 8003e52: 669a str r2, [r3, #104] ; 0x68
+ 8003e5e: 69fb ldr r3, [r7, #28]
+ 8003e60: 2200 movs r2, #0
+ 8003e62: 669a str r2, [r3, #104] ; 0x68
return ret;
- 8003e54: 231a movs r3, #26
- 8003e56: 2218 movs r2, #24
- 8003e58: 4694 mov ip, r2
- 8003e5a: 44bc add ip, r7
- 8003e5c: 4463 add r3, ip
- 8003e5e: 781b ldrb r3, [r3, #0]
+ 8003e64: 231a movs r3, #26
+ 8003e66: 2218 movs r2, #24
+ 8003e68: 4694 mov ip, r2
+ 8003e6a: 44bc add ip, r7
+ 8003e6c: 4463 add r3, ip
+ 8003e6e: 781b ldrb r3, [r3, #0]
}
- 8003e60: 0018 movs r0, r3
- 8003e62: 46bd mov sp, r7
- 8003e64: b00e add sp, #56 ; 0x38
- 8003e66: bdb0 pop {r4, r5, r7, pc}
- 8003e68: 08004390 .word 0x08004390
- 8003e6c: 40021000 .word 0x40021000
- 8003e70: 003d0900 .word 0x003d0900
- 8003e74: 00f42400 .word 0x00f42400
+ 8003e70: 0018 movs r0, r3
+ 8003e72: 46bd mov sp, r7
+ 8003e74: b00e add sp, #56 ; 0x38
+ 8003e76: bdb0 pop {r4, r5, r7, pc}
+ 8003e78: 080043a0 .word 0x080043a0
+ 8003e7c: 40021000 .word 0x40021000
+ 8003e80: 003d0900 .word 0x003d0900
+ 8003e84: 00f42400 .word 0x00f42400
-08003e78 <UART_AdvFeatureConfig>:
+08003e88 <UART_AdvFeatureConfig>:
* @brief Configure the UART peripheral advanced features.
* @param huart UART handle.
* @retval None
*/
void UART_AdvFeatureConfig(UART_HandleTypeDef *huart)
{
- 8003e78: b580 push {r7, lr}
- 8003e7a: b082 sub sp, #8
- 8003e7c: af00 add r7, sp, #0
- 8003e7e: 6078 str r0, [r7, #4]
+ 8003e88: b580 push {r7, lr}
+ 8003e8a: b082 sub sp, #8
+ 8003e8c: af00 add r7, sp, #0
+ 8003e8e: 6078 str r0, [r7, #4]
/* Check whether the set of advanced features to configure is properly set */
assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit));
/* if required, configure TX pin active level inversion */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT))
- 8003e80: 687b ldr r3, [r7, #4]
- 8003e82: 6a5b ldr r3, [r3, #36] ; 0x24
- 8003e84: 2201 movs r2, #1
- 8003e86: 4013 ands r3, r2
- 8003e88: d00b beq.n 8003ea2 <UART_AdvFeatureConfig+0x2a>
+ 8003e90: 687b ldr r3, [r7, #4]
+ 8003e92: 6a5b ldr r3, [r3, #36] ; 0x24
+ 8003e94: 2201 movs r2, #1
+ 8003e96: 4013 ands r3, r2
+ 8003e98: d00b beq.n 8003eb2 <UART_AdvFeatureConfig+0x2a>
{
assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert));
MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert);
- 8003e8a: 687b ldr r3, [r7, #4]
- 8003e8c: 681b ldr r3, [r3, #0]
- 8003e8e: 685b ldr r3, [r3, #4]
- 8003e90: 4a4a ldr r2, [pc, #296] ; (8003fbc <UART_AdvFeatureConfig+0x144>)
- 8003e92: 4013 ands r3, r2
- 8003e94: 0019 movs r1, r3
- 8003e96: 687b ldr r3, [r7, #4]
- 8003e98: 6a9a ldr r2, [r3, #40] ; 0x28
8003e9a: 687b ldr r3, [r7, #4]
8003e9c: 681b ldr r3, [r3, #0]
- 8003e9e: 430a orrs r2, r1
- 8003ea0: 605a str r2, [r3, #4]
+ 8003e9e: 685b ldr r3, [r3, #4]
+ 8003ea0: 4a4a ldr r2, [pc, #296] ; (8003fcc <UART_AdvFeatureConfig+0x144>)
+ 8003ea2: 4013 ands r3, r2
+ 8003ea4: 0019 movs r1, r3
+ 8003ea6: 687b ldr r3, [r7, #4]
+ 8003ea8: 6a9a ldr r2, [r3, #40] ; 0x28
+ 8003eaa: 687b ldr r3, [r7, #4]
+ 8003eac: 681b ldr r3, [r3, #0]
+ 8003eae: 430a orrs r2, r1
+ 8003eb0: 605a str r2, [r3, #4]
}
/* if required, configure RX pin active level inversion */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT))
- 8003ea2: 687b ldr r3, [r7, #4]
- 8003ea4: 6a5b ldr r3, [r3, #36] ; 0x24
- 8003ea6: 2202 movs r2, #2
- 8003ea8: 4013 ands r3, r2
- 8003eaa: d00b beq.n 8003ec4 <UART_AdvFeatureConfig+0x4c>
+ 8003eb2: 687b ldr r3, [r7, #4]
+ 8003eb4: 6a5b ldr r3, [r3, #36] ; 0x24
+ 8003eb6: 2202 movs r2, #2
+ 8003eb8: 4013 ands r3, r2
+ 8003eba: d00b beq.n 8003ed4 <UART_AdvFeatureConfig+0x4c>
{
assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert));
MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert);
- 8003eac: 687b ldr r3, [r7, #4]
- 8003eae: 681b ldr r3, [r3, #0]
- 8003eb0: 685b ldr r3, [r3, #4]
- 8003eb2: 4a43 ldr r2, [pc, #268] ; (8003fc0 <UART_AdvFeatureConfig+0x148>)
- 8003eb4: 4013 ands r3, r2
- 8003eb6: 0019 movs r1, r3
- 8003eb8: 687b ldr r3, [r7, #4]
- 8003eba: 6ada ldr r2, [r3, #44] ; 0x2c
8003ebc: 687b ldr r3, [r7, #4]
8003ebe: 681b ldr r3, [r3, #0]
- 8003ec0: 430a orrs r2, r1
- 8003ec2: 605a str r2, [r3, #4]
+ 8003ec0: 685b ldr r3, [r3, #4]
+ 8003ec2: 4a43 ldr r2, [pc, #268] ; (8003fd0 <UART_AdvFeatureConfig+0x148>)
+ 8003ec4: 4013 ands r3, r2
+ 8003ec6: 0019 movs r1, r3
+ 8003ec8: 687b ldr r3, [r7, #4]
+ 8003eca: 6ada ldr r2, [r3, #44] ; 0x2c
+ 8003ecc: 687b ldr r3, [r7, #4]
+ 8003ece: 681b ldr r3, [r3, #0]
+ 8003ed0: 430a orrs r2, r1
+ 8003ed2: 605a str r2, [r3, #4]
}
/* if required, configure data inversion */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT))
- 8003ec4: 687b ldr r3, [r7, #4]
- 8003ec6: 6a5b ldr r3, [r3, #36] ; 0x24
- 8003ec8: 2204 movs r2, #4
- 8003eca: 4013 ands r3, r2
- 8003ecc: d00b beq.n 8003ee6 <UART_AdvFeatureConfig+0x6e>
+ 8003ed4: 687b ldr r3, [r7, #4]
+ 8003ed6: 6a5b ldr r3, [r3, #36] ; 0x24
+ 8003ed8: 2204 movs r2, #4
+ 8003eda: 4013 ands r3, r2
+ 8003edc: d00b beq.n 8003ef6 <UART_AdvFeatureConfig+0x6e>
{
assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert));
MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert);
- 8003ece: 687b ldr r3, [r7, #4]
- 8003ed0: 681b ldr r3, [r3, #0]
- 8003ed2: 685b ldr r3, [r3, #4]
- 8003ed4: 4a3b ldr r2, [pc, #236] ; (8003fc4 <UART_AdvFeatureConfig+0x14c>)
- 8003ed6: 4013 ands r3, r2
- 8003ed8: 0019 movs r1, r3
- 8003eda: 687b ldr r3, [r7, #4]
- 8003edc: 6b1a ldr r2, [r3, #48] ; 0x30
8003ede: 687b ldr r3, [r7, #4]
8003ee0: 681b ldr r3, [r3, #0]
- 8003ee2: 430a orrs r2, r1
- 8003ee4: 605a str r2, [r3, #4]
+ 8003ee2: 685b ldr r3, [r3, #4]
+ 8003ee4: 4a3b ldr r2, [pc, #236] ; (8003fd4 <UART_AdvFeatureConfig+0x14c>)
+ 8003ee6: 4013 ands r3, r2
+ 8003ee8: 0019 movs r1, r3
+ 8003eea: 687b ldr r3, [r7, #4]
+ 8003eec: 6b1a ldr r2, [r3, #48] ; 0x30
+ 8003eee: 687b ldr r3, [r7, #4]
+ 8003ef0: 681b ldr r3, [r3, #0]
+ 8003ef2: 430a orrs r2, r1
+ 8003ef4: 605a str r2, [r3, #4]
}
/* if required, configure RX/TX pins swap */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT))
- 8003ee6: 687b ldr r3, [r7, #4]
- 8003ee8: 6a5b ldr r3, [r3, #36] ; 0x24
- 8003eea: 2208 movs r2, #8
- 8003eec: 4013 ands r3, r2
- 8003eee: d00b beq.n 8003f08 <UART_AdvFeatureConfig+0x90>
+ 8003ef6: 687b ldr r3, [r7, #4]
+ 8003ef8: 6a5b ldr r3, [r3, #36] ; 0x24
+ 8003efa: 2208 movs r2, #8
+ 8003efc: 4013 ands r3, r2
+ 8003efe: d00b beq.n 8003f18 <UART_AdvFeatureConfig+0x90>
{
assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap));
MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap);
- 8003ef0: 687b ldr r3, [r7, #4]
- 8003ef2: 681b ldr r3, [r3, #0]
- 8003ef4: 685b ldr r3, [r3, #4]
- 8003ef6: 4a34 ldr r2, [pc, #208] ; (8003fc8 <UART_AdvFeatureConfig+0x150>)
- 8003ef8: 4013 ands r3, r2
- 8003efa: 0019 movs r1, r3
- 8003efc: 687b ldr r3, [r7, #4]
- 8003efe: 6b5a ldr r2, [r3, #52] ; 0x34
8003f00: 687b ldr r3, [r7, #4]
8003f02: 681b ldr r3, [r3, #0]
- 8003f04: 430a orrs r2, r1
- 8003f06: 605a str r2, [r3, #4]
+ 8003f04: 685b ldr r3, [r3, #4]
+ 8003f06: 4a34 ldr r2, [pc, #208] ; (8003fd8 <UART_AdvFeatureConfig+0x150>)
+ 8003f08: 4013 ands r3, r2
+ 8003f0a: 0019 movs r1, r3
+ 8003f0c: 687b ldr r3, [r7, #4]
+ 8003f0e: 6b5a ldr r2, [r3, #52] ; 0x34
+ 8003f10: 687b ldr r3, [r7, #4]
+ 8003f12: 681b ldr r3, [r3, #0]
+ 8003f14: 430a orrs r2, r1
+ 8003f16: 605a str r2, [r3, #4]
}
/* if required, configure RX overrun detection disabling */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT))
- 8003f08: 687b ldr r3, [r7, #4]
- 8003f0a: 6a5b ldr r3, [r3, #36] ; 0x24
- 8003f0c: 2210 movs r2, #16
- 8003f0e: 4013 ands r3, r2
- 8003f10: d00b beq.n 8003f2a <UART_AdvFeatureConfig+0xb2>
+ 8003f18: 687b ldr r3, [r7, #4]
+ 8003f1a: 6a5b ldr r3, [r3, #36] ; 0x24
+ 8003f1c: 2210 movs r2, #16
+ 8003f1e: 4013 ands r3, r2
+ 8003f20: d00b beq.n 8003f3a <UART_AdvFeatureConfig+0xb2>
{
assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable));
MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable);
- 8003f12: 687b ldr r3, [r7, #4]
- 8003f14: 681b ldr r3, [r3, #0]
- 8003f16: 689b ldr r3, [r3, #8]
- 8003f18: 4a2c ldr r2, [pc, #176] ; (8003fcc <UART_AdvFeatureConfig+0x154>)
- 8003f1a: 4013 ands r3, r2
- 8003f1c: 0019 movs r1, r3
- 8003f1e: 687b ldr r3, [r7, #4]
- 8003f20: 6b9a ldr r2, [r3, #56] ; 0x38
8003f22: 687b ldr r3, [r7, #4]
8003f24: 681b ldr r3, [r3, #0]
- 8003f26: 430a orrs r2, r1
- 8003f28: 609a str r2, [r3, #8]
+ 8003f26: 689b ldr r3, [r3, #8]
+ 8003f28: 4a2c ldr r2, [pc, #176] ; (8003fdc <UART_AdvFeatureConfig+0x154>)
+ 8003f2a: 4013 ands r3, r2
+ 8003f2c: 0019 movs r1, r3
+ 8003f2e: 687b ldr r3, [r7, #4]
+ 8003f30: 6b9a ldr r2, [r3, #56] ; 0x38
+ 8003f32: 687b ldr r3, [r7, #4]
+ 8003f34: 681b ldr r3, [r3, #0]
+ 8003f36: 430a orrs r2, r1
+ 8003f38: 609a str r2, [r3, #8]
}
/* if required, configure DMA disabling on reception error */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT))
- 8003f2a: 687b ldr r3, [r7, #4]
- 8003f2c: 6a5b ldr r3, [r3, #36] ; 0x24
- 8003f2e: 2220 movs r2, #32
- 8003f30: 4013 ands r3, r2
- 8003f32: d00b beq.n 8003f4c <UART_AdvFeatureConfig+0xd4>
+ 8003f3a: 687b ldr r3, [r7, #4]
+ 8003f3c: 6a5b ldr r3, [r3, #36] ; 0x24
+ 8003f3e: 2220 movs r2, #32
+ 8003f40: 4013 ands r3, r2
+ 8003f42: d00b beq.n 8003f5c <UART_AdvFeatureConfig+0xd4>
{
assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError));
MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError);
- 8003f34: 687b ldr r3, [r7, #4]
- 8003f36: 681b ldr r3, [r3, #0]
- 8003f38: 689b ldr r3, [r3, #8]
- 8003f3a: 4a25 ldr r2, [pc, #148] ; (8003fd0 <UART_AdvFeatureConfig+0x158>)
- 8003f3c: 4013 ands r3, r2
- 8003f3e: 0019 movs r1, r3
- 8003f40: 687b ldr r3, [r7, #4]
- 8003f42: 6bda ldr r2, [r3, #60] ; 0x3c
8003f44: 687b ldr r3, [r7, #4]
8003f46: 681b ldr r3, [r3, #0]
- 8003f48: 430a orrs r2, r1
- 8003f4a: 609a str r2, [r3, #8]
+ 8003f48: 689b ldr r3, [r3, #8]
+ 8003f4a: 4a25 ldr r2, [pc, #148] ; (8003fe0 <UART_AdvFeatureConfig+0x158>)
+ 8003f4c: 4013 ands r3, r2
+ 8003f4e: 0019 movs r1, r3
+ 8003f50: 687b ldr r3, [r7, #4]
+ 8003f52: 6bda ldr r2, [r3, #60] ; 0x3c
+ 8003f54: 687b ldr r3, [r7, #4]
+ 8003f56: 681b ldr r3, [r3, #0]
+ 8003f58: 430a orrs r2, r1
+ 8003f5a: 609a str r2, [r3, #8]
}
/* if required, configure auto Baud rate detection scheme */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT))
- 8003f4c: 687b ldr r3, [r7, #4]
- 8003f4e: 6a5b ldr r3, [r3, #36] ; 0x24
- 8003f50: 2240 movs r2, #64 ; 0x40
- 8003f52: 4013 ands r3, r2
- 8003f54: d01d beq.n 8003f92 <UART_AdvFeatureConfig+0x11a>
+ 8003f5c: 687b ldr r3, [r7, #4]
+ 8003f5e: 6a5b ldr r3, [r3, #36] ; 0x24
+ 8003f60: 2240 movs r2, #64 ; 0x40
+ 8003f62: 4013 ands r3, r2
+ 8003f64: d01d beq.n 8003fa2 <UART_AdvFeatureConfig+0x11a>
{
assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance));
assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable));
MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable);
- 8003f56: 687b ldr r3, [r7, #4]
- 8003f58: 681b ldr r3, [r3, #0]
- 8003f5a: 685b ldr r3, [r3, #4]
- 8003f5c: 4a1d ldr r2, [pc, #116] ; (8003fd4 <UART_AdvFeatureConfig+0x15c>)
- 8003f5e: 4013 ands r3, r2
- 8003f60: 0019 movs r1, r3
- 8003f62: 687b ldr r3, [r7, #4]
- 8003f64: 6c1a ldr r2, [r3, #64] ; 0x40
8003f66: 687b ldr r3, [r7, #4]
8003f68: 681b ldr r3, [r3, #0]
- 8003f6a: 430a orrs r2, r1
- 8003f6c: 605a str r2, [r3, #4]
+ 8003f6a: 685b ldr r3, [r3, #4]
+ 8003f6c: 4a1d ldr r2, [pc, #116] ; (8003fe4 <UART_AdvFeatureConfig+0x15c>)
+ 8003f6e: 4013 ands r3, r2
+ 8003f70: 0019 movs r1, r3
+ 8003f72: 687b ldr r3, [r7, #4]
+ 8003f74: 6c1a ldr r2, [r3, #64] ; 0x40
+ 8003f76: 687b ldr r3, [r7, #4]
+ 8003f78: 681b ldr r3, [r3, #0]
+ 8003f7a: 430a orrs r2, r1
+ 8003f7c: 605a str r2, [r3, #4]
/* set auto Baudrate detection parameters if detection is enabled */
if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)
- 8003f6e: 687b ldr r3, [r7, #4]
- 8003f70: 6c1a ldr r2, [r3, #64] ; 0x40
- 8003f72: 2380 movs r3, #128 ; 0x80
- 8003f74: 035b lsls r3, r3, #13
- 8003f76: 429a cmp r2, r3
- 8003f78: d10b bne.n 8003f92 <UART_AdvFeatureConfig+0x11a>
+ 8003f7e: 687b ldr r3, [r7, #4]
+ 8003f80: 6c1a ldr r2, [r3, #64] ; 0x40
+ 8003f82: 2380 movs r3, #128 ; 0x80
+ 8003f84: 035b lsls r3, r3, #13
+ 8003f86: 429a cmp r2, r3
+ 8003f88: d10b bne.n 8003fa2 <UART_AdvFeatureConfig+0x11a>
{
assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode));
MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode);
- 8003f7a: 687b ldr r3, [r7, #4]
- 8003f7c: 681b ldr r3, [r3, #0]
- 8003f7e: 685b ldr r3, [r3, #4]
- 8003f80: 4a15 ldr r2, [pc, #84] ; (8003fd8 <UART_AdvFeatureConfig+0x160>)
- 8003f82: 4013 ands r3, r2
- 8003f84: 0019 movs r1, r3
- 8003f86: 687b ldr r3, [r7, #4]
- 8003f88: 6c5a ldr r2, [r3, #68] ; 0x44
8003f8a: 687b ldr r3, [r7, #4]
8003f8c: 681b ldr r3, [r3, #0]
- 8003f8e: 430a orrs r2, r1
- 8003f90: 605a str r2, [r3, #4]
+ 8003f8e: 685b ldr r3, [r3, #4]
+ 8003f90: 4a15 ldr r2, [pc, #84] ; (8003fe8 <UART_AdvFeatureConfig+0x160>)
+ 8003f92: 4013 ands r3, r2
+ 8003f94: 0019 movs r1, r3
+ 8003f96: 687b ldr r3, [r7, #4]
+ 8003f98: 6c5a ldr r2, [r3, #68] ; 0x44
+ 8003f9a: 687b ldr r3, [r7, #4]
+ 8003f9c: 681b ldr r3, [r3, #0]
+ 8003f9e: 430a orrs r2, r1
+ 8003fa0: 605a str r2, [r3, #4]
}
}
/* if required, configure MSB first on communication line */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT))
- 8003f92: 687b ldr r3, [r7, #4]
- 8003f94: 6a5b ldr r3, [r3, #36] ; 0x24
- 8003f96: 2280 movs r2, #128 ; 0x80
- 8003f98: 4013 ands r3, r2
- 8003f9a: d00b beq.n 8003fb4 <UART_AdvFeatureConfig+0x13c>
+ 8003fa2: 687b ldr r3, [r7, #4]
+ 8003fa4: 6a5b ldr r3, [r3, #36] ; 0x24
+ 8003fa6: 2280 movs r2, #128 ; 0x80
+ 8003fa8: 4013 ands r3, r2
+ 8003faa: d00b beq.n 8003fc4 <UART_AdvFeatureConfig+0x13c>
{
assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst));
MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst);
- 8003f9c: 687b ldr r3, [r7, #4]
- 8003f9e: 681b ldr r3, [r3, #0]
- 8003fa0: 685b ldr r3, [r3, #4]
- 8003fa2: 4a0e ldr r2, [pc, #56] ; (8003fdc <UART_AdvFeatureConfig+0x164>)
- 8003fa4: 4013 ands r3, r2
- 8003fa6: 0019 movs r1, r3
- 8003fa8: 687b ldr r3, [r7, #4]
- 8003faa: 6c9a ldr r2, [r3, #72] ; 0x48
8003fac: 687b ldr r3, [r7, #4]
8003fae: 681b ldr r3, [r3, #0]
- 8003fb0: 430a orrs r2, r1
- 8003fb2: 605a str r2, [r3, #4]
+ 8003fb0: 685b ldr r3, [r3, #4]
+ 8003fb2: 4a0e ldr r2, [pc, #56] ; (8003fec <UART_AdvFeatureConfig+0x164>)
+ 8003fb4: 4013 ands r3, r2
+ 8003fb6: 0019 movs r1, r3
+ 8003fb8: 687b ldr r3, [r7, #4]
+ 8003fba: 6c9a ldr r2, [r3, #72] ; 0x48
+ 8003fbc: 687b ldr r3, [r7, #4]
+ 8003fbe: 681b ldr r3, [r3, #0]
+ 8003fc0: 430a orrs r2, r1
+ 8003fc2: 605a str r2, [r3, #4]
}
}
- 8003fb4: 46c0 nop ; (mov r8, r8)
- 8003fb6: 46bd mov sp, r7
- 8003fb8: b002 add sp, #8
- 8003fba: bd80 pop {r7, pc}
- 8003fbc: fffdffff .word 0xfffdffff
- 8003fc0: fffeffff .word 0xfffeffff
- 8003fc4: fffbffff .word 0xfffbffff
- 8003fc8: ffff7fff .word 0xffff7fff
- 8003fcc: ffffefff .word 0xffffefff
- 8003fd0: ffffdfff .word 0xffffdfff
- 8003fd4: ffefffff .word 0xffefffff
- 8003fd8: ff9fffff .word 0xff9fffff
- 8003fdc: fff7ffff .word 0xfff7ffff
+ 8003fc4: 46c0 nop ; (mov r8, r8)
+ 8003fc6: 46bd mov sp, r7
+ 8003fc8: b002 add sp, #8
+ 8003fca: bd80 pop {r7, pc}
+ 8003fcc: fffdffff .word 0xfffdffff
+ 8003fd0: fffeffff .word 0xfffeffff
+ 8003fd4: fffbffff .word 0xfffbffff
+ 8003fd8: ffff7fff .word 0xffff7fff
+ 8003fdc: ffffefff .word 0xffffefff
+ 8003fe0: ffffdfff .word 0xffffdfff
+ 8003fe4: ffefffff .word 0xffefffff
+ 8003fe8: ff9fffff .word 0xff9fffff
+ 8003fec: fff7ffff .word 0xfff7ffff
-08003fe0 <UART_CheckIdleState>:
+08003ff0 <UART_CheckIdleState>:
* @brief Check the UART Idle State.
* @param huart UART handle.
* @retval HAL status
*/
HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart)
{
- 8003fe0: b580 push {r7, lr}
- 8003fe2: b086 sub sp, #24
- 8003fe4: af02 add r7, sp, #8
- 8003fe6: 6078 str r0, [r7, #4]
+ 8003ff0: b580 push {r7, lr}
+ 8003ff2: b086 sub sp, #24
+ 8003ff4: af02 add r7, sp, #8
+ 8003ff6: 6078 str r0, [r7, #4]
uint32_t tickstart;
/* Initialize the UART ErrorCode */
huart->ErrorCode = HAL_UART_ERROR_NONE;
- 8003fe8: 687b ldr r3, [r7, #4]
- 8003fea: 2280 movs r2, #128 ; 0x80
- 8003fec: 2100 movs r1, #0
- 8003fee: 5099 str r1, [r3, r2]
+ 8003ff8: 687b ldr r3, [r7, #4]
+ 8003ffa: 2280 movs r2, #128 ; 0x80
+ 8003ffc: 2100 movs r1, #0
+ 8003ffe: 5099 str r1, [r3, r2]
/* Init tickstart for timeout management */
tickstart = HAL_GetTick();
- 8003ff0: f7fd f892 bl 8001118 <HAL_GetTick>
- 8003ff4: 0003 movs r3, r0
- 8003ff6: 60fb str r3, [r7, #12]
+ 8004000: f7fd f892 bl 8001128 <HAL_GetTick>
+ 8004004: 0003 movs r3, r0
+ 8004006: 60fb str r3, [r7, #12]
/* Check if the Transmitter is enabled */
if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
- 8003ff8: 687b ldr r3, [r7, #4]
- 8003ffa: 681b ldr r3, [r3, #0]
- 8003ffc: 681b ldr r3, [r3, #0]
- 8003ffe: 2208 movs r2, #8
- 8004000: 4013 ands r3, r2
- 8004002: 2b08 cmp r3, #8
- 8004004: d10c bne.n 8004020 <UART_CheckIdleState+0x40>
+ 8004008: 687b ldr r3, [r7, #4]
+ 800400a: 681b ldr r3, [r3, #0]
+ 800400c: 681b ldr r3, [r3, #0]
+ 800400e: 2208 movs r2, #8
+ 8004010: 4013 ands r3, r2
+ 8004012: 2b08 cmp r3, #8
+ 8004014: d10c bne.n 8004030 <UART_CheckIdleState+0x40>
{
/* Wait until TEACK flag is set */
if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
- 8004006: 68fb ldr r3, [r7, #12]
- 8004008: 2280 movs r2, #128 ; 0x80
- 800400a: 0391 lsls r1, r2, #14
- 800400c: 6878 ldr r0, [r7, #4]
- 800400e: 4a17 ldr r2, [pc, #92] ; (800406c <UART_CheckIdleState+0x8c>)
- 8004010: 9200 str r2, [sp, #0]
- 8004012: 2200 movs r2, #0
- 8004014: f000 f82c bl 8004070 <UART_WaitOnFlagUntilTimeout>
- 8004018: 1e03 subs r3, r0, #0
- 800401a: d001 beq.n 8004020 <UART_CheckIdleState+0x40>
+ 8004016: 68fb ldr r3, [r7, #12]
+ 8004018: 2280 movs r2, #128 ; 0x80
+ 800401a: 0391 lsls r1, r2, #14
+ 800401c: 6878 ldr r0, [r7, #4]
+ 800401e: 4a17 ldr r2, [pc, #92] ; (800407c <UART_CheckIdleState+0x8c>)
+ 8004020: 9200 str r2, [sp, #0]
+ 8004022: 2200 movs r2, #0
+ 8004024: f000 f82c bl 8004080 <UART_WaitOnFlagUntilTimeout>
+ 8004028: 1e03 subs r3, r0, #0
+ 800402a: d001 beq.n 8004030 <UART_CheckIdleState+0x40>
{
/* Timeout occurred */
return HAL_TIMEOUT;
- 800401c: 2303 movs r3, #3
- 800401e: e021 b.n 8004064 <UART_CheckIdleState+0x84>
+ 800402c: 2303 movs r3, #3
+ 800402e: e021 b.n 8004074 <UART_CheckIdleState+0x84>
}
}
/* Check if the Receiver is enabled */
if ((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
- 8004020: 687b ldr r3, [r7, #4]
- 8004022: 681b ldr r3, [r3, #0]
- 8004024: 681b ldr r3, [r3, #0]
- 8004026: 2204 movs r2, #4
- 8004028: 4013 ands r3, r2
- 800402a: 2b04 cmp r3, #4
- 800402c: d10c bne.n 8004048 <UART_CheckIdleState+0x68>
+ 8004030: 687b ldr r3, [r7, #4]
+ 8004032: 681b ldr r3, [r3, #0]
+ 8004034: 681b ldr r3, [r3, #0]
+ 8004036: 2204 movs r2, #4
+ 8004038: 4013 ands r3, r2
+ 800403a: 2b04 cmp r3, #4
+ 800403c: d10c bne.n 8004058 <UART_CheckIdleState+0x68>
{
/* Wait until REACK flag is set */
if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
- 800402e: 68fb ldr r3, [r7, #12]
- 8004030: 2280 movs r2, #128 ; 0x80
- 8004032: 03d1 lsls r1, r2, #15
- 8004034: 6878 ldr r0, [r7, #4]
- 8004036: 4a0d ldr r2, [pc, #52] ; (800406c <UART_CheckIdleState+0x8c>)
- 8004038: 9200 str r2, [sp, #0]
- 800403a: 2200 movs r2, #0
- 800403c: f000 f818 bl 8004070 <UART_WaitOnFlagUntilTimeout>
- 8004040: 1e03 subs r3, r0, #0
- 8004042: d001 beq.n 8004048 <UART_CheckIdleState+0x68>
+ 800403e: 68fb ldr r3, [r7, #12]
+ 8004040: 2280 movs r2, #128 ; 0x80
+ 8004042: 03d1 lsls r1, r2, #15
+ 8004044: 6878 ldr r0, [r7, #4]
+ 8004046: 4a0d ldr r2, [pc, #52] ; (800407c <UART_CheckIdleState+0x8c>)
+ 8004048: 9200 str r2, [sp, #0]
+ 800404a: 2200 movs r2, #0
+ 800404c: f000 f818 bl 8004080 <UART_WaitOnFlagUntilTimeout>
+ 8004050: 1e03 subs r3, r0, #0
+ 8004052: d001 beq.n 8004058 <UART_CheckIdleState+0x68>
{
/* Timeout occurred */
return HAL_TIMEOUT;
- 8004044: 2303 movs r3, #3
- 8004046: e00d b.n 8004064 <UART_CheckIdleState+0x84>
+ 8004054: 2303 movs r3, #3
+ 8004056: e00d b.n 8004074 <UART_CheckIdleState+0x84>
}
}
/* Initialize the UART State */
huart->gState = HAL_UART_STATE_READY;
- 8004048: 687b ldr r3, [r7, #4]
- 800404a: 2220 movs r2, #32
- 800404c: 679a str r2, [r3, #120] ; 0x78
+ 8004058: 687b ldr r3, [r7, #4]
+ 800405a: 2220 movs r2, #32
+ 800405c: 679a str r2, [r3, #120] ; 0x78
huart->RxState = HAL_UART_STATE_READY;
- 800404e: 687b ldr r3, [r7, #4]
- 8004050: 2220 movs r2, #32
- 8004052: 67da str r2, [r3, #124] ; 0x7c
+ 800405e: 687b ldr r3, [r7, #4]
+ 8004060: 2220 movs r2, #32
+ 8004062: 67da str r2, [r3, #124] ; 0x7c
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
- 8004054: 687b ldr r3, [r7, #4]
- 8004056: 2200 movs r2, #0
- 8004058: 661a str r2, [r3, #96] ; 0x60
+ 8004064: 687b ldr r3, [r7, #4]
+ 8004066: 2200 movs r2, #0
+ 8004068: 661a str r2, [r3, #96] ; 0x60
__HAL_UNLOCK(huart);
- 800405a: 687b ldr r3, [r7, #4]
- 800405c: 2274 movs r2, #116 ; 0x74
- 800405e: 2100 movs r1, #0
- 8004060: 5499 strb r1, [r3, r2]
+ 800406a: 687b ldr r3, [r7, #4]
+ 800406c: 2274 movs r2, #116 ; 0x74
+ 800406e: 2100 movs r1, #0
+ 8004070: 5499 strb r1, [r3, r2]
return HAL_OK;
- 8004062: 2300 movs r3, #0
+ 8004072: 2300 movs r3, #0
}
- 8004064: 0018 movs r0, r3
- 8004066: 46bd mov sp, r7
- 8004068: b004 add sp, #16
- 800406a: bd80 pop {r7, pc}
- 800406c: 01ffffff .word 0x01ffffff
+ 8004074: 0018 movs r0, r3
+ 8004076: 46bd mov sp, r7
+ 8004078: b004 add sp, #16
+ 800407a: bd80 pop {r7, pc}
+ 800407c: 01ffffff .word 0x01ffffff
-08004070 <UART_WaitOnFlagUntilTimeout>:
+08004080 <UART_WaitOnFlagUntilTimeout>:
* @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status,
uint32_t Tickstart, uint32_t Timeout)
{
- 8004070: b580 push {r7, lr}
- 8004072: b094 sub sp, #80 ; 0x50
- 8004074: af00 add r7, sp, #0
- 8004076: 60f8 str r0, [r7, #12]
- 8004078: 60b9 str r1, [r7, #8]
- 800407a: 603b str r3, [r7, #0]
- 800407c: 1dfb adds r3, r7, #7
- 800407e: 701a strb r2, [r3, #0]
+ 8004080: b580 push {r7, lr}
+ 8004082: b094 sub sp, #80 ; 0x50
+ 8004084: af00 add r7, sp, #0
+ 8004086: 60f8 str r0, [r7, #12]
+ 8004088: 60b9 str r1, [r7, #8]
+ 800408a: 603b str r3, [r7, #0]
+ 800408c: 1dfb adds r3, r7, #7
+ 800408e: 701a strb r2, [r3, #0]
/* Wait until flag is set */
while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
- 8004080: e0a3 b.n 80041ca <UART_WaitOnFlagUntilTimeout+0x15a>
+ 8004090: e0a3 b.n 80041da <UART_WaitOnFlagUntilTimeout+0x15a>
{
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
- 8004082: 6dbb ldr r3, [r7, #88] ; 0x58
- 8004084: 3301 adds r3, #1
- 8004086: d100 bne.n 800408a <UART_WaitOnFlagUntilTimeout+0x1a>
- 8004088: e09f b.n 80041ca <UART_WaitOnFlagUntilTimeout+0x15a>
+ 8004092: 6dbb ldr r3, [r7, #88] ; 0x58
+ 8004094: 3301 adds r3, #1
+ 8004096: d100 bne.n 800409a <UART_WaitOnFlagUntilTimeout+0x1a>
+ 8004098: e09f b.n 80041da <UART_WaitOnFlagUntilTimeout+0x15a>
{
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
- 800408a: f7fd f845 bl 8001118 <HAL_GetTick>
- 800408e: 0002 movs r2, r0
- 8004090: 683b ldr r3, [r7, #0]
- 8004092: 1ad3 subs r3, r2, r3
- 8004094: 6dba ldr r2, [r7, #88] ; 0x58
- 8004096: 429a cmp r2, r3
- 8004098: d302 bcc.n 80040a0 <UART_WaitOnFlagUntilTimeout+0x30>
- 800409a: 6dbb ldr r3, [r7, #88] ; 0x58
- 800409c: 2b00 cmp r3, #0
- 800409e: d13d bne.n 800411c <UART_WaitOnFlagUntilTimeout+0xac>
+ 800409a: f7fd f845 bl 8001128 <HAL_GetTick>
+ 800409e: 0002 movs r2, r0
+ 80040a0: 683b ldr r3, [r7, #0]
+ 80040a2: 1ad3 subs r3, r2, r3
+ 80040a4: 6dba ldr r2, [r7, #88] ; 0x58
+ 80040a6: 429a cmp r2, r3
+ 80040a8: d302 bcc.n 80040b0 <UART_WaitOnFlagUntilTimeout+0x30>
+ 80040aa: 6dbb ldr r3, [r7, #88] ; 0x58
+ 80040ac: 2b00 cmp r3, #0
+ 80040ae: d13d bne.n 800412c <UART_WaitOnFlagUntilTimeout+0xac>
*/
__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
{
uint32_t result;
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
- 80040a0: f3ef 8310 mrs r3, PRIMASK
- 80040a4: 62bb str r3, [r7, #40] ; 0x28
+ 80040b0: f3ef 8310 mrs r3, PRIMASK
+ 80040b4: 62bb str r3, [r7, #40] ; 0x28
return(result);
- 80040a6: 6abb ldr r3, [r7, #40] ; 0x28
+ 80040b6: 6abb ldr r3, [r7, #40] ; 0x28
{
/* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error)
interrupts for the interrupt process */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
- 80040a8: 647b str r3, [r7, #68] ; 0x44
- 80040aa: 2301 movs r3, #1
- 80040ac: 62fb str r3, [r7, #44] ; 0x2c
+ 80040b8: 647b str r3, [r7, #68] ; 0x44
+ 80040ba: 2301 movs r3, #1
+ 80040bc: 62fb str r3, [r7, #44] ; 0x2c
\details Assigns the given value to the Priority Mask Register.
\param [in] priMask Priority Mask
*/
__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
{
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
- 80040ae: 6afb ldr r3, [r7, #44] ; 0x2c
- 80040b0: f383 8810 msr PRIMASK, r3
+ 80040be: 6afb ldr r3, [r7, #44] ; 0x2c
+ 80040c0: f383 8810 msr PRIMASK, r3
}
- 80040b4: 46c0 nop ; (mov r8, r8)
- 80040b6: 68fb ldr r3, [r7, #12]
- 80040b8: 681b ldr r3, [r3, #0]
- 80040ba: 681a ldr r2, [r3, #0]
- 80040bc: 68fb ldr r3, [r7, #12]
- 80040be: 681b ldr r3, [r3, #0]
- 80040c0: 494c ldr r1, [pc, #304] ; (80041f4 <UART_WaitOnFlagUntilTimeout+0x184>)
- 80040c2: 400a ands r2, r1
- 80040c4: 601a str r2, [r3, #0]
- 80040c6: 6c7b ldr r3, [r7, #68] ; 0x44
- 80040c8: 633b str r3, [r7, #48] ; 0x30
+ 80040c4: 46c0 nop ; (mov r8, r8)
+ 80040c6: 68fb ldr r3, [r7, #12]
+ 80040c8: 681b ldr r3, [r3, #0]
+ 80040ca: 681a ldr r2, [r3, #0]
+ 80040cc: 68fb ldr r3, [r7, #12]
+ 80040ce: 681b ldr r3, [r3, #0]
+ 80040d0: 494c ldr r1, [pc, #304] ; (8004204 <UART_WaitOnFlagUntilTimeout+0x184>)
+ 80040d2: 400a ands r2, r1
+ 80040d4: 601a str r2, [r3, #0]
+ 80040d6: 6c7b ldr r3, [r7, #68] ; 0x44
+ 80040d8: 633b str r3, [r7, #48] ; 0x30
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
- 80040ca: 6b3b ldr r3, [r7, #48] ; 0x30
- 80040cc: f383 8810 msr PRIMASK, r3
+ 80040da: 6b3b ldr r3, [r7, #48] ; 0x30
+ 80040dc: f383 8810 msr PRIMASK, r3
}
- 80040d0: 46c0 nop ; (mov r8, r8)
+ 80040e0: 46c0 nop ; (mov r8, r8)
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
- 80040d2: f3ef 8310 mrs r3, PRIMASK
- 80040d6: 637b str r3, [r7, #52] ; 0x34
+ 80040e2: f3ef 8310 mrs r3, PRIMASK
+ 80040e6: 637b str r3, [r7, #52] ; 0x34
return(result);
- 80040d8: 6b7b ldr r3, [r7, #52] ; 0x34
+ 80040e8: 6b7b ldr r3, [r7, #52] ; 0x34
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
- 80040da: 643b str r3, [r7, #64] ; 0x40
- 80040dc: 2301 movs r3, #1
- 80040de: 63bb str r3, [r7, #56] ; 0x38
+ 80040ea: 643b str r3, [r7, #64] ; 0x40
+ 80040ec: 2301 movs r3, #1
+ 80040ee: 63bb str r3, [r7, #56] ; 0x38
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
- 80040e0: 6bbb ldr r3, [r7, #56] ; 0x38
- 80040e2: f383 8810 msr PRIMASK, r3
+ 80040f0: 6bbb ldr r3, [r7, #56] ; 0x38
+ 80040f2: f383 8810 msr PRIMASK, r3
}
- 80040e6: 46c0 nop ; (mov r8, r8)
- 80040e8: 68fb ldr r3, [r7, #12]
- 80040ea: 681b ldr r3, [r3, #0]
- 80040ec: 689a ldr r2, [r3, #8]
- 80040ee: 68fb ldr r3, [r7, #12]
- 80040f0: 681b ldr r3, [r3, #0]
- 80040f2: 2101 movs r1, #1
- 80040f4: 438a bics r2, r1
- 80040f6: 609a str r2, [r3, #8]
- 80040f8: 6c3b ldr r3, [r7, #64] ; 0x40
- 80040fa: 63fb str r3, [r7, #60] ; 0x3c
+ 80040f6: 46c0 nop ; (mov r8, r8)
+ 80040f8: 68fb ldr r3, [r7, #12]
+ 80040fa: 681b ldr r3, [r3, #0]
+ 80040fc: 689a ldr r2, [r3, #8]
+ 80040fe: 68fb ldr r3, [r7, #12]
+ 8004100: 681b ldr r3, [r3, #0]
+ 8004102: 2101 movs r1, #1
+ 8004104: 438a bics r2, r1
+ 8004106: 609a str r2, [r3, #8]
+ 8004108: 6c3b ldr r3, [r7, #64] ; 0x40
+ 800410a: 63fb str r3, [r7, #60] ; 0x3c
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
- 80040fc: 6bfb ldr r3, [r7, #60] ; 0x3c
- 80040fe: f383 8810 msr PRIMASK, r3
+ 800410c: 6bfb ldr r3, [r7, #60] ; 0x3c
+ 800410e: f383 8810 msr PRIMASK, r3
}
- 8004102: 46c0 nop ; (mov r8, r8)
+ 8004112: 46c0 nop ; (mov r8, r8)
huart->gState = HAL_UART_STATE_READY;
- 8004104: 68fb ldr r3, [r7, #12]
- 8004106: 2220 movs r2, #32
- 8004108: 679a str r2, [r3, #120] ; 0x78
+ 8004114: 68fb ldr r3, [r7, #12]
+ 8004116: 2220 movs r2, #32
+ 8004118: 679a str r2, [r3, #120] ; 0x78
huart->RxState = HAL_UART_STATE_READY;
- 800410a: 68fb ldr r3, [r7, #12]
- 800410c: 2220 movs r2, #32
- 800410e: 67da str r2, [r3, #124] ; 0x7c
+ 800411a: 68fb ldr r3, [r7, #12]
+ 800411c: 2220 movs r2, #32
+ 800411e: 67da str r2, [r3, #124] ; 0x7c
__HAL_UNLOCK(huart);
- 8004110: 68fb ldr r3, [r7, #12]
- 8004112: 2274 movs r2, #116 ; 0x74
- 8004114: 2100 movs r1, #0
- 8004116: 5499 strb r1, [r3, r2]
+ 8004120: 68fb ldr r3, [r7, #12]
+ 8004122: 2274 movs r2, #116 ; 0x74
+ 8004124: 2100 movs r1, #0
+ 8004126: 5499 strb r1, [r3, r2]
return HAL_TIMEOUT;
- 8004118: 2303 movs r3, #3
- 800411a: e067 b.n 80041ec <UART_WaitOnFlagUntilTimeout+0x17c>
+ 8004128: 2303 movs r3, #3
+ 800412a: e067 b.n 80041fc <UART_WaitOnFlagUntilTimeout+0x17c>
}
if (READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U)
- 800411c: 68fb ldr r3, [r7, #12]
- 800411e: 681b ldr r3, [r3, #0]
- 8004120: 681b ldr r3, [r3, #0]
- 8004122: 2204 movs r2, #4
- 8004124: 4013 ands r3, r2
- 8004126: d050 beq.n 80041ca <UART_WaitOnFlagUntilTimeout+0x15a>
+ 800412c: 68fb ldr r3, [r7, #12]
+ 800412e: 681b ldr r3, [r3, #0]
+ 8004130: 681b ldr r3, [r3, #0]
+ 8004132: 2204 movs r2, #4
+ 8004134: 4013 ands r3, r2
+ 8004136: d050 beq.n 80041da <UART_WaitOnFlagUntilTimeout+0x15a>
{
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET)
- 8004128: 68fb ldr r3, [r7, #12]
- 800412a: 681b ldr r3, [r3, #0]
- 800412c: 69da ldr r2, [r3, #28]
- 800412e: 2380 movs r3, #128 ; 0x80
- 8004130: 011b lsls r3, r3, #4
- 8004132: 401a ands r2, r3
- 8004134: 2380 movs r3, #128 ; 0x80
- 8004136: 011b lsls r3, r3, #4
- 8004138: 429a cmp r2, r3
- 800413a: d146 bne.n 80041ca <UART_WaitOnFlagUntilTimeout+0x15a>
+ 8004138: 68fb ldr r3, [r7, #12]
+ 800413a: 681b ldr r3, [r3, #0]
+ 800413c: 69da ldr r2, [r3, #28]
+ 800413e: 2380 movs r3, #128 ; 0x80
+ 8004140: 011b lsls r3, r3, #4
+ 8004142: 401a ands r2, r3
+ 8004144: 2380 movs r3, #128 ; 0x80
+ 8004146: 011b lsls r3, r3, #4
+ 8004148: 429a cmp r2, r3
+ 800414a: d146 bne.n 80041da <UART_WaitOnFlagUntilTimeout+0x15a>
{
/* Clear Receiver Timeout flag*/
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF);
- 800413c: 68fb ldr r3, [r7, #12]
- 800413e: 681b ldr r3, [r3, #0]
- 8004140: 2280 movs r2, #128 ; 0x80
- 8004142: 0112 lsls r2, r2, #4
- 8004144: 621a str r2, [r3, #32]
+ 800414c: 68fb ldr r3, [r7, #12]
+ 800414e: 681b ldr r3, [r3, #0]
+ 8004150: 2280 movs r2, #128 ; 0x80
+ 8004152: 0112 lsls r2, r2, #4
+ 8004154: 621a str r2, [r3, #32]
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
- 8004146: f3ef 8310 mrs r3, PRIMASK
- 800414a: 613b str r3, [r7, #16]
+ 8004156: f3ef 8310 mrs r3, PRIMASK
+ 800415a: 613b str r3, [r7, #16]
return(result);
- 800414c: 693b ldr r3, [r7, #16]
+ 800415c: 693b ldr r3, [r7, #16]
/* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error)
interrupts for the interrupt process */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
- 800414e: 64fb str r3, [r7, #76] ; 0x4c
- 8004150: 2301 movs r3, #1
- 8004152: 617b str r3, [r7, #20]
+ 800415e: 64fb str r3, [r7, #76] ; 0x4c
+ 8004160: 2301 movs r3, #1
+ 8004162: 617b str r3, [r7, #20]
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
- 8004154: 697b ldr r3, [r7, #20]
- 8004156: f383 8810 msr PRIMASK, r3
+ 8004164: 697b ldr r3, [r7, #20]
+ 8004166: f383 8810 msr PRIMASK, r3
}
- 800415a: 46c0 nop ; (mov r8, r8)
- 800415c: 68fb ldr r3, [r7, #12]
- 800415e: 681b ldr r3, [r3, #0]
- 8004160: 681a ldr r2, [r3, #0]
- 8004162: 68fb ldr r3, [r7, #12]
- 8004164: 681b ldr r3, [r3, #0]
- 8004166: 4923 ldr r1, [pc, #140] ; (80041f4 <UART_WaitOnFlagUntilTimeout+0x184>)
- 8004168: 400a ands r2, r1
- 800416a: 601a str r2, [r3, #0]
- 800416c: 6cfb ldr r3, [r7, #76] ; 0x4c
- 800416e: 61bb str r3, [r7, #24]
+ 800416a: 46c0 nop ; (mov r8, r8)
+ 800416c: 68fb ldr r3, [r7, #12]
+ 800416e: 681b ldr r3, [r3, #0]
+ 8004170: 681a ldr r2, [r3, #0]
+ 8004172: 68fb ldr r3, [r7, #12]
+ 8004174: 681b ldr r3, [r3, #0]
+ 8004176: 4923 ldr r1, [pc, #140] ; (8004204 <UART_WaitOnFlagUntilTimeout+0x184>)
+ 8004178: 400a ands r2, r1
+ 800417a: 601a str r2, [r3, #0]
+ 800417c: 6cfb ldr r3, [r7, #76] ; 0x4c
+ 800417e: 61bb str r3, [r7, #24]
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
- 8004170: 69bb ldr r3, [r7, #24]
- 8004172: f383 8810 msr PRIMASK, r3
+ 8004180: 69bb ldr r3, [r7, #24]
+ 8004182: f383 8810 msr PRIMASK, r3
}
- 8004176: 46c0 nop ; (mov r8, r8)
+ 8004186: 46c0 nop ; (mov r8, r8)
__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
- 8004178: f3ef 8310 mrs r3, PRIMASK
- 800417c: 61fb str r3, [r7, #28]
+ 8004188: f3ef 8310 mrs r3, PRIMASK
+ 800418c: 61fb str r3, [r7, #28]
return(result);
- 800417e: 69fb ldr r3, [r7, #28]
+ 800418e: 69fb ldr r3, [r7, #28]
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
- 8004180: 64bb str r3, [r7, #72] ; 0x48
- 8004182: 2301 movs r3, #1
- 8004184: 623b str r3, [r7, #32]
+ 8004190: 64bb str r3, [r7, #72] ; 0x48
+ 8004192: 2301 movs r3, #1
+ 8004194: 623b str r3, [r7, #32]
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
- 8004186: 6a3b ldr r3, [r7, #32]
- 8004188: f383 8810 msr PRIMASK, r3
+ 8004196: 6a3b ldr r3, [r7, #32]
+ 8004198: f383 8810 msr PRIMASK, r3
}
- 800418c: 46c0 nop ; (mov r8, r8)
- 800418e: 68fb ldr r3, [r7, #12]
- 8004190: 681b ldr r3, [r3, #0]
- 8004192: 689a ldr r2, [r3, #8]
- 8004194: 68fb ldr r3, [r7, #12]
- 8004196: 681b ldr r3, [r3, #0]
- 8004198: 2101 movs r1, #1
- 800419a: 438a bics r2, r1
- 800419c: 609a str r2, [r3, #8]
- 800419e: 6cbb ldr r3, [r7, #72] ; 0x48
- 80041a0: 627b str r3, [r7, #36] ; 0x24
+ 800419c: 46c0 nop ; (mov r8, r8)
+ 800419e: 68fb ldr r3, [r7, #12]
+ 80041a0: 681b ldr r3, [r3, #0]
+ 80041a2: 689a ldr r2, [r3, #8]
+ 80041a4: 68fb ldr r3, [r7, #12]
+ 80041a6: 681b ldr r3, [r3, #0]
+ 80041a8: 2101 movs r1, #1
+ 80041aa: 438a bics r2, r1
+ 80041ac: 609a str r2, [r3, #8]
+ 80041ae: 6cbb ldr r3, [r7, #72] ; 0x48
+ 80041b0: 627b str r3, [r7, #36] ; 0x24
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
- 80041a2: 6a7b ldr r3, [r7, #36] ; 0x24
- 80041a4: f383 8810 msr PRIMASK, r3
+ 80041b2: 6a7b ldr r3, [r7, #36] ; 0x24
+ 80041b4: f383 8810 msr PRIMASK, r3
}
- 80041a8: 46c0 nop ; (mov r8, r8)
+ 80041b8: 46c0 nop ; (mov r8, r8)
huart->gState = HAL_UART_STATE_READY;
- 80041aa: 68fb ldr r3, [r7, #12]
- 80041ac: 2220 movs r2, #32
- 80041ae: 679a str r2, [r3, #120] ; 0x78
+ 80041ba: 68fb ldr r3, [r7, #12]
+ 80041bc: 2220 movs r2, #32
+ 80041be: 679a str r2, [r3, #120] ; 0x78
huart->RxState = HAL_UART_STATE_READY;
- 80041b0: 68fb ldr r3, [r7, #12]
- 80041b2: 2220 movs r2, #32
- 80041b4: 67da str r2, [r3, #124] ; 0x7c
+ 80041c0: 68fb ldr r3, [r7, #12]
+ 80041c2: 2220 movs r2, #32
+ 80041c4: 67da str r2, [r3, #124] ; 0x7c
huart->ErrorCode = HAL_UART_ERROR_RTO;
- 80041b6: 68fb ldr r3, [r7, #12]
- 80041b8: 2280 movs r2, #128 ; 0x80
- 80041ba: 2120 movs r1, #32
- 80041bc: 5099 str r1, [r3, r2]
+ 80041c6: 68fb ldr r3, [r7, #12]
+ 80041c8: 2280 movs r2, #128 ; 0x80
+ 80041ca: 2120 movs r1, #32
+ 80041cc: 5099 str r1, [r3, r2]
/* Process Unlocked */
__HAL_UNLOCK(huart);
- 80041be: 68fb ldr r3, [r7, #12]
- 80041c0: 2274 movs r2, #116 ; 0x74
- 80041c2: 2100 movs r1, #0
- 80041c4: 5499 strb r1, [r3, r2]
+ 80041ce: 68fb ldr r3, [r7, #12]
+ 80041d0: 2274 movs r2, #116 ; 0x74
+ 80041d2: 2100 movs r1, #0
+ 80041d4: 5499 strb r1, [r3, r2]
return HAL_TIMEOUT;
- 80041c6: 2303 movs r3, #3
- 80041c8: e010 b.n 80041ec <UART_WaitOnFlagUntilTimeout+0x17c>
+ 80041d6: 2303 movs r3, #3
+ 80041d8: e010 b.n 80041fc <UART_WaitOnFlagUntilTimeout+0x17c>
while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
- 80041ca: 68fb ldr r3, [r7, #12]
- 80041cc: 681b ldr r3, [r3, #0]
- 80041ce: 69db ldr r3, [r3, #28]
- 80041d0: 68ba ldr r2, [r7, #8]
- 80041d2: 4013 ands r3, r2
- 80041d4: 68ba ldr r2, [r7, #8]
- 80041d6: 1ad3 subs r3, r2, r3
- 80041d8: 425a negs r2, r3
- 80041da: 4153 adcs r3, r2
- 80041dc: b2db uxtb r3, r3
- 80041de: 001a movs r2, r3
- 80041e0: 1dfb adds r3, r7, #7
- 80041e2: 781b ldrb r3, [r3, #0]
- 80041e4: 429a cmp r2, r3
- 80041e6: d100 bne.n 80041ea <UART_WaitOnFlagUntilTimeout+0x17a>
- 80041e8: e74b b.n 8004082 <UART_WaitOnFlagUntilTimeout+0x12>
+ 80041da: 68fb ldr r3, [r7, #12]
+ 80041dc: 681b ldr r3, [r3, #0]
+ 80041de: 69db ldr r3, [r3, #28]
+ 80041e0: 68ba ldr r2, [r7, #8]
+ 80041e2: 4013 ands r3, r2
+ 80041e4: 68ba ldr r2, [r7, #8]
+ 80041e6: 1ad3 subs r3, r2, r3
+ 80041e8: 425a negs r2, r3
+ 80041ea: 4153 adcs r3, r2
+ 80041ec: b2db uxtb r3, r3
+ 80041ee: 001a movs r2, r3
+ 80041f0: 1dfb adds r3, r7, #7
+ 80041f2: 781b ldrb r3, [r3, #0]
+ 80041f4: 429a cmp r2, r3
+ 80041f6: d100 bne.n 80041fa <UART_WaitOnFlagUntilTimeout+0x17a>
+ 80041f8: e74b b.n 8004092 <UART_WaitOnFlagUntilTimeout+0x12>
}
}
}
}
return HAL_OK;
- 80041ea: 2300 movs r3, #0
+ 80041fa: 2300 movs r3, #0
}
- 80041ec: 0018 movs r0, r3
- 80041ee: 46bd mov sp, r7
- 80041f0: b014 add sp, #80 ; 0x50
- 80041f2: bd80 pop {r7, pc}
- 80041f4: fffffe5f .word 0xfffffe5f
+ 80041fc: 0018 movs r0, r3
+ 80041fe: 46bd mov sp, r7
+ 8004200: b014 add sp, #80 ; 0x50
+ 8004202: bd80 pop {r7, pc}
+ 8004204: fffffe5f .word 0xfffffe5f
-080041f8 <HAL_RS485Ex_Init>:
+08004208 <HAL_RS485Ex_Init>:
* oversampling rate).
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime,
uint32_t DeassertionTime)
{
- 80041f8: b580 push {r7, lr}
- 80041fa: b086 sub sp, #24
- 80041fc: af00 add r7, sp, #0
- 80041fe: 60f8 str r0, [r7, #12]
- 8004200: 60b9 str r1, [r7, #8]
- 8004202: 607a str r2, [r7, #4]
- 8004204: 603b str r3, [r7, #0]
+ 8004208: b580 push {r7, lr}
+ 800420a: b086 sub sp, #24
+ 800420c: af00 add r7, sp, #0
+ 800420e: 60f8 str r0, [r7, #12]
+ 8004210: 60b9 str r1, [r7, #8]
+ 8004212: 607a str r2, [r7, #4]
+ 8004214: 603b str r3, [r7, #0]
uint32_t temp;
/* Check the UART handle allocation */
if (huart == NULL)
- 8004206: 68fb ldr r3, [r7, #12]
- 8004208: 2b00 cmp r3, #0
- 800420a: d101 bne.n 8004210 <HAL_RS485Ex_Init+0x18>
+ 8004216: 68fb ldr r3, [r7, #12]
+ 8004218: 2b00 cmp r3, #0
+ 800421a: d101 bne.n 8004220 <HAL_RS485Ex_Init+0x18>
{
return HAL_ERROR;
- 800420c: 2301 movs r3, #1
- 800420e: e05b b.n 80042c8 <HAL_RS485Ex_Init+0xd0>
+ 800421c: 2301 movs r3, #1
+ 800421e: e05b b.n 80042d8 <HAL_RS485Ex_Init+0xd0>
assert_param(IS_UART_ASSERTIONTIME(AssertionTime));
/* Check the Driver Enable deassertion time */
assert_param(IS_UART_DEASSERTIONTIME(DeassertionTime));
if (huart->gState == HAL_UART_STATE_RESET)
- 8004210: 68fb ldr r3, [r7, #12]
- 8004212: 6f9b ldr r3, [r3, #120] ; 0x78
- 8004214: 2b00 cmp r3, #0
- 8004216: d107 bne.n 8004228 <HAL_RS485Ex_Init+0x30>
+ 8004220: 68fb ldr r3, [r7, #12]
+ 8004222: 6f9b ldr r3, [r3, #120] ; 0x78
+ 8004224: 2b00 cmp r3, #0
+ 8004226: d107 bne.n 8004238 <HAL_RS485Ex_Init+0x30>
{
/* Allocate lock resource and initialize it */
huart->Lock = HAL_UNLOCKED;
- 8004218: 68fb ldr r3, [r7, #12]
- 800421a: 2274 movs r2, #116 ; 0x74
- 800421c: 2100 movs r1, #0
- 800421e: 5499 strb r1, [r3, r2]
+ 8004228: 68fb ldr r3, [r7, #12]
+ 800422a: 2274 movs r2, #116 ; 0x74
+ 800422c: 2100 movs r1, #0
+ 800422e: 5499 strb r1, [r3, r2]
/* Init the low level hardware */
huart->MspInitCallback(huart);
#else
/* Init the low level hardware : GPIO, CLOCK, CORTEX */
HAL_UART_MspInit(huart);
- 8004220: 68fb ldr r3, [r7, #12]
- 8004222: 0018 movs r0, r3
- 8004224: f7fc fe88 bl 8000f38 <HAL_UART_MspInit>
+ 8004230: 68fb ldr r3, [r7, #12]
+ 8004232: 0018 movs r0, r3
+ 8004234: f7fc fe88 bl 8000f48 <HAL_UART_MspInit>
#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
}
huart->gState = HAL_UART_STATE_BUSY;
- 8004228: 68fb ldr r3, [r7, #12]
- 800422a: 2224 movs r2, #36 ; 0x24
- 800422c: 679a str r2, [r3, #120] ; 0x78
+ 8004238: 68fb ldr r3, [r7, #12]
+ 800423a: 2224 movs r2, #36 ; 0x24
+ 800423c: 679a str r2, [r3, #120] ; 0x78
/* Disable the Peripheral */
__HAL_UART_DISABLE(huart);
- 800422e: 68fb ldr r3, [r7, #12]
- 8004230: 681b ldr r3, [r3, #0]
- 8004232: 681a ldr r2, [r3, #0]
- 8004234: 68fb ldr r3, [r7, #12]
- 8004236: 681b ldr r3, [r3, #0]
- 8004238: 2101 movs r1, #1
- 800423a: 438a bics r2, r1
- 800423c: 601a str r2, [r3, #0]
+ 800423e: 68fb ldr r3, [r7, #12]
+ 8004240: 681b ldr r3, [r3, #0]
+ 8004242: 681a ldr r2, [r3, #0]
+ 8004244: 68fb ldr r3, [r7, #12]
+ 8004246: 681b ldr r3, [r3, #0]
+ 8004248: 2101 movs r1, #1
+ 800424a: 438a bics r2, r1
+ 800424c: 601a str r2, [r3, #0]
/* Set the UART Communication parameters */
if (UART_SetConfig(huart) == HAL_ERROR)
- 800423e: 68fb ldr r3, [r7, #12]
- 8004240: 0018 movs r0, r3
- 8004242: f7ff fbb7 bl 80039b4 <UART_SetConfig>
- 8004246: 0003 movs r3, r0
- 8004248: 2b01 cmp r3, #1
- 800424a: d101 bne.n 8004250 <HAL_RS485Ex_Init+0x58>
+ 800424e: 68fb ldr r3, [r7, #12]
+ 8004250: 0018 movs r0, r3
+ 8004252: f7ff fbb7 bl 80039c4 <UART_SetConfig>
+ 8004256: 0003 movs r3, r0
+ 8004258: 2b01 cmp r3, #1
+ 800425a: d101 bne.n 8004260 <HAL_RS485Ex_Init+0x58>
{
return HAL_ERROR;
- 800424c: 2301 movs r3, #1
- 800424e: e03b b.n 80042c8 <HAL_RS485Ex_Init+0xd0>
+ 800425c: 2301 movs r3, #1
+ 800425e: e03b b.n 80042d8 <HAL_RS485Ex_Init+0xd0>
}
if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
- 8004250: 68fb ldr r3, [r7, #12]
- 8004252: 6a5b ldr r3, [r3, #36] ; 0x24
- 8004254: 2b00 cmp r3, #0
- 8004256: d003 beq.n 8004260 <HAL_RS485Ex_Init+0x68>
+ 8004260: 68fb ldr r3, [r7, #12]
+ 8004262: 6a5b ldr r3, [r3, #36] ; 0x24
+ 8004264: 2b00 cmp r3, #0
+ 8004266: d003 beq.n 8004270 <HAL_RS485Ex_Init+0x68>
{
UART_AdvFeatureConfig(huart);
- 8004258: 68fb ldr r3, [r7, #12]
- 800425a: 0018 movs r0, r3
- 800425c: f7ff fe0c bl 8003e78 <UART_AdvFeatureConfig>
+ 8004268: 68fb ldr r3, [r7, #12]
+ 800426a: 0018 movs r0, r3
+ 800426c: f7ff fe0c bl 8003e88 <UART_AdvFeatureConfig>
}
/* Enable the Driver Enable mode by setting the DEM bit in the CR3 register */
SET_BIT(huart->Instance->CR3, USART_CR3_DEM);
- 8004260: 68fb ldr r3, [r7, #12]
- 8004262: 681b ldr r3, [r3, #0]
- 8004264: 689a ldr r2, [r3, #8]
- 8004266: 68fb ldr r3, [r7, #12]
- 8004268: 681b ldr r3, [r3, #0]
- 800426a: 2180 movs r1, #128 ; 0x80
- 800426c: 01c9 lsls r1, r1, #7
- 800426e: 430a orrs r2, r1
- 8004270: 609a str r2, [r3, #8]
+ 8004270: 68fb ldr r3, [r7, #12]
+ 8004272: 681b ldr r3, [r3, #0]
+ 8004274: 689a ldr r2, [r3, #8]
+ 8004276: 68fb ldr r3, [r7, #12]
+ 8004278: 681b ldr r3, [r3, #0]
+ 800427a: 2180 movs r1, #128 ; 0x80
+ 800427c: 01c9 lsls r1, r1, #7
+ 800427e: 430a orrs r2, r1
+ 8004280: 609a str r2, [r3, #8]
/* Set the Driver Enable polarity */
MODIFY_REG(huart->Instance->CR3, USART_CR3_DEP, Polarity);
- 8004272: 68fb ldr r3, [r7, #12]
- 8004274: 681b ldr r3, [r3, #0]
- 8004276: 689b ldr r3, [r3, #8]
- 8004278: 4a15 ldr r2, [pc, #84] ; (80042d0 <HAL_RS485Ex_Init+0xd8>)
- 800427a: 4013 ands r3, r2
- 800427c: 0019 movs r1, r3
- 800427e: 68fb ldr r3, [r7, #12]
- 8004280: 681b ldr r3, [r3, #0]
- 8004282: 68ba ldr r2, [r7, #8]
- 8004284: 430a orrs r2, r1
- 8004286: 609a str r2, [r3, #8]
+ 8004282: 68fb ldr r3, [r7, #12]
+ 8004284: 681b ldr r3, [r3, #0]
+ 8004286: 689b ldr r3, [r3, #8]
+ 8004288: 4a15 ldr r2, [pc, #84] ; (80042e0 <HAL_RS485Ex_Init+0xd8>)
+ 800428a: 4013 ands r3, r2
+ 800428c: 0019 movs r1, r3
+ 800428e: 68fb ldr r3, [r7, #12]
+ 8004290: 681b ldr r3, [r3, #0]
+ 8004292: 68ba ldr r2, [r7, #8]
+ 8004294: 430a orrs r2, r1
+ 8004296: 609a str r2, [r3, #8]
/* Set the Driver Enable assertion and deassertion times */
temp = (AssertionTime << UART_CR1_DEAT_ADDRESS_LSB_POS);
- 8004288: 687b ldr r3, [r7, #4]
- 800428a: 055b lsls r3, r3, #21
- 800428c: 617b str r3, [r7, #20]
+ 8004298: 687b ldr r3, [r7, #4]
+ 800429a: 055b lsls r3, r3, #21
+ 800429c: 617b str r3, [r7, #20]
temp |= (DeassertionTime << UART_CR1_DEDT_ADDRESS_LSB_POS);
- 800428e: 683b ldr r3, [r7, #0]
- 8004290: 041b lsls r3, r3, #16
- 8004292: 697a ldr r2, [r7, #20]
- 8004294: 4313 orrs r3, r2
- 8004296: 617b str r3, [r7, #20]
+ 800429e: 683b ldr r3, [r7, #0]
+ 80042a0: 041b lsls r3, r3, #16
+ 80042a2: 697a ldr r2, [r7, #20]
+ 80042a4: 4313 orrs r3, r2
+ 80042a6: 617b str r3, [r7, #20]
MODIFY_REG(huart->Instance->CR1, (USART_CR1_DEDT | USART_CR1_DEAT), temp);
- 8004298: 68fb ldr r3, [r7, #12]
- 800429a: 681b ldr r3, [r3, #0]
- 800429c: 681b ldr r3, [r3, #0]
- 800429e: 4a0d ldr r2, [pc, #52] ; (80042d4 <HAL_RS485Ex_Init+0xdc>)
- 80042a0: 4013 ands r3, r2
- 80042a2: 0019 movs r1, r3
- 80042a4: 68fb ldr r3, [r7, #12]
- 80042a6: 681b ldr r3, [r3, #0]
- 80042a8: 697a ldr r2, [r7, #20]
- 80042aa: 430a orrs r2, r1
- 80042ac: 601a str r2, [r3, #0]
-
- /* Enable the Peripheral */
- __HAL_UART_ENABLE(huart);
- 80042ae: 68fb ldr r3, [r7, #12]
- 80042b0: 681b ldr r3, [r3, #0]
- 80042b2: 681a ldr r2, [r3, #0]
+ 80042a8: 68fb ldr r3, [r7, #12]
+ 80042aa: 681b ldr r3, [r3, #0]
+ 80042ac: 681b ldr r3, [r3, #0]
+ 80042ae: 4a0d ldr r2, [pc, #52] ; (80042e4 <HAL_RS485Ex_Init+0xdc>)
+ 80042b0: 4013 ands r3, r2
+ 80042b2: 0019 movs r1, r3
80042b4: 68fb ldr r3, [r7, #12]
80042b6: 681b ldr r3, [r3, #0]
- 80042b8: 2101 movs r1, #1
+ 80042b8: 697a ldr r2, [r7, #20]
80042ba: 430a orrs r2, r1
80042bc: 601a str r2, [r3, #0]
+ /* Enable the Peripheral */
+ __HAL_UART_ENABLE(huart);
+ 80042be: 68fb ldr r3, [r7, #12]
+ 80042c0: 681b ldr r3, [r3, #0]
+ 80042c2: 681a ldr r2, [r3, #0]
+ 80042c4: 68fb ldr r3, [r7, #12]
+ 80042c6: 681b ldr r3, [r3, #0]
+ 80042c8: 2101 movs r1, #1
+ 80042ca: 430a orrs r2, r1
+ 80042cc: 601a str r2, [r3, #0]
+
/* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
return (UART_CheckIdleState(huart));
- 80042be: 68fb ldr r3, [r7, #12]
- 80042c0: 0018 movs r0, r3
- 80042c2: f7ff fe8d bl 8003fe0 <UART_CheckIdleState>
- 80042c6: 0003 movs r3, r0
+ 80042ce: 68fb ldr r3, [r7, #12]
+ 80042d0: 0018 movs r0, r3
+ 80042d2: f7ff fe8d bl 8003ff0 <UART_CheckIdleState>
+ 80042d6: 0003 movs r3, r0
}
- 80042c8: 0018 movs r0, r3
- 80042ca: 46bd mov sp, r7
- 80042cc: b006 add sp, #24
- 80042ce: bd80 pop {r7, pc}
- 80042d0: ffff7fff .word 0xffff7fff
- 80042d4: fc00ffff .word 0xfc00ffff
+ 80042d8: 0018 movs r0, r3
+ 80042da: 46bd mov sp, r7
+ 80042dc: b006 add sp, #24
+ 80042de: bd80 pop {r7, pc}
+ 80042e0: ffff7fff .word 0xffff7fff
+ 80042e4: fc00ffff .word 0xfc00ffff
-080042d8 <__libc_init_array>:
- 80042d8: b570 push {r4, r5, r6, lr}
- 80042da: 2600 movs r6, #0
- 80042dc: 4d0c ldr r5, [pc, #48] ; (8004310 <__libc_init_array+0x38>)
- 80042de: 4c0d ldr r4, [pc, #52] ; (8004314 <__libc_init_array+0x3c>)
- 80042e0: 1b64 subs r4, r4, r5
- 80042e2: 10a4 asrs r4, r4, #2
- 80042e4: 42a6 cmp r6, r4
- 80042e6: d109 bne.n 80042fc <__libc_init_array+0x24>
- 80042e8: 2600 movs r6, #0
- 80042ea: f000 f821 bl 8004330 <_init>
- 80042ee: 4d0a ldr r5, [pc, #40] ; (8004318 <__libc_init_array+0x40>)
- 80042f0: 4c0a ldr r4, [pc, #40] ; (800431c <__libc_init_array+0x44>)
- 80042f2: 1b64 subs r4, r4, r5
- 80042f4: 10a4 asrs r4, r4, #2
- 80042f6: 42a6 cmp r6, r4
- 80042f8: d105 bne.n 8004306 <__libc_init_array+0x2e>
- 80042fa: bd70 pop {r4, r5, r6, pc}
- 80042fc: 00b3 lsls r3, r6, #2
- 80042fe: 58eb ldr r3, [r5, r3]
- 8004300: 4798 blx r3
- 8004302: 3601 adds r6, #1
- 8004304: e7ee b.n 80042e4 <__libc_init_array+0xc>
- 8004306: 00b3 lsls r3, r6, #2
- 8004308: 58eb ldr r3, [r5, r3]
- 800430a: 4798 blx r3
- 800430c: 3601 adds r6, #1
- 800430e: e7f2 b.n 80042f6 <__libc_init_array+0x1e>
- 8004310: 080043bc .word 0x080043bc
- 8004314: 080043bc .word 0x080043bc
- 8004318: 080043bc .word 0x080043bc
- 800431c: 080043c0 .word 0x080043c0
+080042e8 <__libc_init_array>:
+ 80042e8: b570 push {r4, r5, r6, lr}
+ 80042ea: 2600 movs r6, #0
+ 80042ec: 4d0c ldr r5, [pc, #48] ; (8004320 <__libc_init_array+0x38>)
+ 80042ee: 4c0d ldr r4, [pc, #52] ; (8004324 <__libc_init_array+0x3c>)
+ 80042f0: 1b64 subs r4, r4, r5
+ 80042f2: 10a4 asrs r4, r4, #2
+ 80042f4: 42a6 cmp r6, r4
+ 80042f6: d109 bne.n 800430c <__libc_init_array+0x24>
+ 80042f8: 2600 movs r6, #0
+ 80042fa: f000 f821 bl 8004340 <_init>
+ 80042fe: 4d0a ldr r5, [pc, #40] ; (8004328 <__libc_init_array+0x40>)
+ 8004300: 4c0a ldr r4, [pc, #40] ; (800432c <__libc_init_array+0x44>)
+ 8004302: 1b64 subs r4, r4, r5
+ 8004304: 10a4 asrs r4, r4, #2
+ 8004306: 42a6 cmp r6, r4
+ 8004308: d105 bne.n 8004316 <__libc_init_array+0x2e>
+ 800430a: bd70 pop {r4, r5, r6, pc}
+ 800430c: 00b3 lsls r3, r6, #2
+ 800430e: 58eb ldr r3, [r5, r3]
+ 8004310: 4798 blx r3
+ 8004312: 3601 adds r6, #1
+ 8004314: e7ee b.n 80042f4 <__libc_init_array+0xc>
+ 8004316: 00b3 lsls r3, r6, #2
+ 8004318: 58eb ldr r3, [r5, r3]
+ 800431a: 4798 blx r3
+ 800431c: 3601 adds r6, #1
+ 800431e: e7f2 b.n 8004306 <__libc_init_array+0x1e>
+ 8004320: 080043cc .word 0x080043cc
+ 8004324: 080043cc .word 0x080043cc
+ 8004328: 080043cc .word 0x080043cc
+ 800432c: 080043d0 .word 0x080043d0
-08004320 <memset>:
- 8004320: 0003 movs r3, r0
- 8004322: 1882 adds r2, r0, r2
- 8004324: 4293 cmp r3, r2
- 8004326: d100 bne.n 800432a <memset+0xa>
- 8004328: 4770 bx lr
- 800432a: 7019 strb r1, [r3, #0]
- 800432c: 3301 adds r3, #1
- 800432e: e7f9 b.n 8004324 <memset+0x4>
+08004330 <memset>:
+ 8004330: 0003 movs r3, r0
+ 8004332: 1882 adds r2, r0, r2
+ 8004334: 4293 cmp r3, r2
+ 8004336: d100 bne.n 800433a <memset+0xa>
+ 8004338: 4770 bx lr
+ 800433a: 7019 strb r1, [r3, #0]
+ 800433c: 3301 adds r3, #1
+ 800433e: e7f9 b.n 8004334 <memset+0x4>
-08004330 <_init>:
- 8004330: b5f8 push {r3, r4, r5, r6, r7, lr}
- 8004332: 46c0 nop ; (mov r8, r8)
- 8004334: bcf8 pop {r3, r4, r5, r6, r7}
- 8004336: bc08 pop {r3}
- 8004338: 469e mov lr, r3
- 800433a: 4770 bx lr
+08004340 <_init>:
+ 8004340: b5f8 push {r3, r4, r5, r6, r7, lr}
+ 8004342: 46c0 nop ; (mov r8, r8)
+ 8004344: bcf8 pop {r3, r4, r5, r6, r7}
+ 8004346: bc08 pop {r3}
+ 8004348: 469e mov lr, r3
+ 800434a: 4770 bx lr
-0800433c <_fini>:
- 800433c: b5f8 push {r3, r4, r5, r6, r7, lr}
- 800433e: 46c0 nop ; (mov r8, r8)
- 8004340: bcf8 pop {r3, r4, r5, r6, r7}
- 8004342: bc08 pop {r3}
- 8004344: 469e mov lr, r3
- 8004346: 4770 bx lr
+0800434c <_fini>:
+ 800434c: b5f8 push {r3, r4, r5, r6, r7, lr}
+ 800434e: 46c0 nop ; (mov r8, r8)
+ 8004350: bcf8 pop {r3, r4, r5, r6, r7}
+ 8004352: bc08 pop {r3}
+ 8004354: 469e mov lr, r3
+ 8004356: 4770 bx lr
diff --git a/fw_hal/Debug/iaq_wired_sensor_hal.map b/fw_hal/Debug/iaq_wired_sensor_hal.map
index da69530..3bd4efa 100644
--- a/fw_hal/Debug/iaq_wired_sensor_hal.map
+++ b/fw_hal/Debug/iaq_wired_sensor_hal.map
@@ -3764,7 +3764,7 @@ LOAD /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.g
0x0000000008000000 g_pfnVectors
0x00000000080000c0 . = ALIGN (0x4)
-.text 0x00000000080000c0 0x4288
+.text 0x00000000080000c0 0x4298
0x00000000080000c0 . = ALIGN (0x4)
*(.text)
.text 0x00000000080000c0 0x48 /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crtbegin.o
@@ -3791,334 +3791,334 @@ LOAD /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.g
0x000000000800049c 0x3c ./Core/Src/i2c.o
0x000000000800049c i2c_init
.text.i2c_transmit
- 0x00000000080004d8 0x4c ./Core/Src/i2c.o
+ 0x00000000080004d8 0x50 ./Core/Src/i2c.o
0x00000000080004d8 i2c_transmit
.text.i2c_receive
- 0x0000000008000524 0x4c ./Core/Src/i2c.o
- 0x0000000008000524 i2c_receive
+ 0x0000000008000528 0x50 ./Core/Src/i2c.o
+ 0x0000000008000528 i2c_receive
.text.i2c_transmit_receive
- 0x0000000008000570 0x6c ./Core/Src/i2c.o
- 0x0000000008000570 i2c_transmit_receive
- .text.main 0x00000000080005dc 0x84 ./Core/Src/main.o
- 0x00000000080005dc main
+ 0x0000000008000578 0x74 ./Core/Src/i2c.o
+ 0x0000000008000578 i2c_transmit_receive
+ .text.main 0x00000000080005ec 0x84 ./Core/Src/main.o
+ 0x00000000080005ec main
.text.SystemClock_Config
- 0x0000000008000660 0xe8 ./Core/Src/main.o
- 0x0000000008000660 SystemClock_Config
+ 0x0000000008000670 0xe8 ./Core/Src/main.o
+ 0x0000000008000670 SystemClock_Config
.text.MX_I2C1_Init
- 0x0000000008000748 0x80 ./Core/Src/main.o
+ 0x0000000008000758 0x80 ./Core/Src/main.o
.text.MX_TIM2_Init
- 0x00000000080007c8 0x10c ./Core/Src/main.o
+ 0x00000000080007d8 0x10c ./Core/Src/main.o
.text.MX_TIM21_Init
- 0x00000000080008d4 0xb4 ./Core/Src/main.o
+ 0x00000000080008e4 0xb4 ./Core/Src/main.o
.text.MX_TIM22_Init
- 0x0000000008000988 0x130 ./Core/Src/main.o
+ 0x0000000008000998 0x130 ./Core/Src/main.o
.text.MX_USART2_UART_Init
- 0x0000000008000ab8 0x68 ./Core/Src/main.o
+ 0x0000000008000ac8 0x68 ./Core/Src/main.o
.text.MX_GPIO_Init
- 0x0000000008000b20 0x2c ./Core/Src/main.o
+ 0x0000000008000b30 0x2c ./Core/Src/main.o
.text.Error_Handler
- 0x0000000008000b4c 0xa ./Core/Src/main.o
- 0x0000000008000b4c Error_Handler
+ 0x0000000008000b5c 0xa ./Core/Src/main.o
+ 0x0000000008000b5c Error_Handler
.text.scd4x_send_cmd
- 0x0000000008000b56 0x4c ./Core/Src/scd4x.o
- 0x0000000008000b56 scd4x_send_cmd
- *fill* 0x0000000008000ba2 0x2
+ 0x0000000008000b66 0x4c ./Core/Src/scd4x.o
+ 0x0000000008000b66 scd4x_send_cmd
+ *fill* 0x0000000008000bb2 0x2
.text.scd4x_start_periodic_measurement
- 0x0000000008000ba4 0x18 ./Core/Src/scd4x.o
- 0x0000000008000ba4 scd4x_start_periodic_measurement
+ 0x0000000008000bb4 0x18 ./Core/Src/scd4x.o
+ 0x0000000008000bb4 scd4x_start_periodic_measurement
.text.scd4x_read_measurement
- 0x0000000008000bbc 0xd0 ./Core/Src/scd4x.o
- 0x0000000008000bbc scd4x_read_measurement
+ 0x0000000008000bcc 0xd0 ./Core/Src/scd4x.o
+ 0x0000000008000bcc scd4x_read_measurement
.text.sht4x_measure
- 0x0000000008000c8c 0xcc ./Core/Src/sht4x.o
- 0x0000000008000c8c sht4x_measure
+ 0x0000000008000c9c 0xcc ./Core/Src/sht4x.o
+ 0x0000000008000c9c sht4x_measure
.text.HAL_MspInit
- 0x0000000008000d58 0x28 ./Core/Src/stm32l0xx_hal_msp.o
- 0x0000000008000d58 HAL_MspInit
+ 0x0000000008000d68 0x28 ./Core/Src/stm32l0xx_hal_msp.o
+ 0x0000000008000d68 HAL_MspInit
.text.HAL_I2C_MspInit
- 0x0000000008000d80 0x88 ./Core/Src/stm32l0xx_hal_msp.o
- 0x0000000008000d80 HAL_I2C_MspInit
+ 0x0000000008000d90 0x88 ./Core/Src/stm32l0xx_hal_msp.o
+ 0x0000000008000d90 HAL_I2C_MspInit
.text.HAL_TIM_Base_MspInit
- 0x0000000008000e08 0x64 ./Core/Src/stm32l0xx_hal_msp.o
- 0x0000000008000e08 HAL_TIM_Base_MspInit
+ 0x0000000008000e18 0x64 ./Core/Src/stm32l0xx_hal_msp.o
+ 0x0000000008000e18 HAL_TIM_Base_MspInit
.text.HAL_TIM_MspPostInit
- 0x0000000008000e6c 0xcc ./Core/Src/stm32l0xx_hal_msp.o
- 0x0000000008000e6c HAL_TIM_MspPostInit
+ 0x0000000008000e7c 0xcc ./Core/Src/stm32l0xx_hal_msp.o
+ 0x0000000008000e7c HAL_TIM_MspPostInit
.text.HAL_UART_MspInit
- 0x0000000008000f38 0x88 ./Core/Src/stm32l0xx_hal_msp.o
- 0x0000000008000f38 HAL_UART_MspInit
+ 0x0000000008000f48 0x88 ./Core/Src/stm32l0xx_hal_msp.o
+ 0x0000000008000f48 HAL_UART_MspInit
.text.NMI_Handler
- 0x0000000008000fc0 0x6 ./Core/Src/stm32l0xx_it.o
- 0x0000000008000fc0 NMI_Handler
+ 0x0000000008000fd0 0x6 ./Core/Src/stm32l0xx_it.o
+ 0x0000000008000fd0 NMI_Handler
.text.HardFault_Handler
- 0x0000000008000fc6 0x6 ./Core/Src/stm32l0xx_it.o
- 0x0000000008000fc6 HardFault_Handler
+ 0x0000000008000fd6 0x6 ./Core/Src/stm32l0xx_it.o
+ 0x0000000008000fd6 HardFault_Handler
.text.SVC_Handler
- 0x0000000008000fcc 0xa ./Core/Src/stm32l0xx_it.o
- 0x0000000008000fcc SVC_Handler
+ 0x0000000008000fdc 0xa ./Core/Src/stm32l0xx_it.o
+ 0x0000000008000fdc SVC_Handler
.text.PendSV_Handler
- 0x0000000008000fd6 0xa ./Core/Src/stm32l0xx_it.o
- 0x0000000008000fd6 PendSV_Handler
+ 0x0000000008000fe6 0xa ./Core/Src/stm32l0xx_it.o
+ 0x0000000008000fe6 PendSV_Handler
.text.SysTick_Handler
- 0x0000000008000fe0 0xe ./Core/Src/stm32l0xx_it.o
- 0x0000000008000fe0 SysTick_Handler
+ 0x0000000008000ff0 0xe ./Core/Src/stm32l0xx_it.o
+ 0x0000000008000ff0 SysTick_Handler
.text.SystemInit
- 0x0000000008000fee 0xa ./Core/Src/system_stm32l0xx.o
- 0x0000000008000fee SystemInit
+ 0x0000000008000ffe 0xa ./Core/Src/system_stm32l0xx.o
+ 0x0000000008000ffe SystemInit
.text.Reset_Handler
- 0x0000000008000ff8 0x50 ./Core/Startup/startup_stm32l031g6ux.o
- 0x0000000008000ff8 Reset_Handler
+ 0x0000000008001008 0x50 ./Core/Startup/startup_stm32l031g6ux.o
+ 0x0000000008001008 Reset_Handler
.text.Default_Handler
- 0x0000000008001048 0x2 ./Core/Startup/startup_stm32l031g6ux.o
- 0x0000000008001048 ADC1_COMP_IRQHandler
- 0x0000000008001048 PVD_IRQHandler
- 0x0000000008001048 I2C1_IRQHandler
- 0x0000000008001048 SPI1_IRQHandler
- 0x0000000008001048 EXTI2_3_IRQHandler
- 0x0000000008001048 RTC_IRQHandler
- 0x0000000008001048 DMA1_Channel4_5_6_7_IRQHandler
- 0x0000000008001048 EXTI4_15_IRQHandler
- 0x0000000008001048 RCC_IRQHandler
- 0x0000000008001048 DMA1_Channel1_IRQHandler
- 0x0000000008001048 Default_Handler
- 0x0000000008001048 TIM22_IRQHandler
- 0x0000000008001048 EXTI0_1_IRQHandler
- 0x0000000008001048 TIM21_IRQHandler
- 0x0000000008001048 WWDG_IRQHandler
- 0x0000000008001048 LPUART1_IRQHandler
- 0x0000000008001048 TIM2_IRQHandler
- 0x0000000008001048 DMA1_Channel2_3_IRQHandler
- 0x0000000008001048 USART2_IRQHandler
- 0x0000000008001048 FLASH_IRQHandler
- 0x0000000008001048 LPTIM1_IRQHandler
- *fill* 0x000000000800104a 0x2
+ 0x0000000008001058 0x2 ./Core/Startup/startup_stm32l031g6ux.o
+ 0x0000000008001058 ADC1_COMP_IRQHandler
+ 0x0000000008001058 PVD_IRQHandler
+ 0x0000000008001058 I2C1_IRQHandler
+ 0x0000000008001058 SPI1_IRQHandler
+ 0x0000000008001058 EXTI2_3_IRQHandler
+ 0x0000000008001058 RTC_IRQHandler
+ 0x0000000008001058 DMA1_Channel4_5_6_7_IRQHandler
+ 0x0000000008001058 EXTI4_15_IRQHandler
+ 0x0000000008001058 RCC_IRQHandler
+ 0x0000000008001058 DMA1_Channel1_IRQHandler
+ 0x0000000008001058 Default_Handler
+ 0x0000000008001058 TIM22_IRQHandler
+ 0x0000000008001058 EXTI0_1_IRQHandler
+ 0x0000000008001058 TIM21_IRQHandler
+ 0x0000000008001058 WWDG_IRQHandler
+ 0x0000000008001058 LPUART1_IRQHandler
+ 0x0000000008001058 TIM2_IRQHandler
+ 0x0000000008001058 DMA1_Channel2_3_IRQHandler
+ 0x0000000008001058 USART2_IRQHandler
+ 0x0000000008001058 FLASH_IRQHandler
+ 0x0000000008001058 LPTIM1_IRQHandler
+ *fill* 0x000000000800105a 0x2
.text.HAL_Init
- 0x000000000800104c 0x40 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o
- 0x000000000800104c HAL_Init
+ 0x000000000800105c 0x40 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o
+ 0x000000000800105c HAL_Init
.text.HAL_InitTick
- 0x000000000800108c 0x68 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o
- 0x000000000800108c HAL_InitTick
+ 0x000000000800109c 0x68 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o
+ 0x000000000800109c HAL_InitTick
.text.HAL_IncTick
- 0x00000000080010f4 0x24 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o
- 0x00000000080010f4 HAL_IncTick
+ 0x0000000008001104 0x24 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o
+ 0x0000000008001104 HAL_IncTick
.text.HAL_GetTick
- 0x0000000008001118 0x14 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o
- 0x0000000008001118 HAL_GetTick
+ 0x0000000008001128 0x14 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o
+ 0x0000000008001128 HAL_GetTick
.text.HAL_Delay
- 0x000000000800112c 0x48 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o
- 0x000000000800112c HAL_Delay
+ 0x000000000800113c 0x48 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal.o
+ 0x000000000800113c HAL_Delay
.text.__NVIC_SetPriority
- 0x0000000008001174 0xdc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o
+ 0x0000000008001184 0xdc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o
.text.SysTick_Config
- 0x0000000008001250 0x48 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o
+ 0x0000000008001260 0x48 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o
.text.HAL_NVIC_SetPriority
- 0x0000000008001298 0x2a ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o
- 0x0000000008001298 HAL_NVIC_SetPriority
+ 0x00000000080012a8 0x2a ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o
+ 0x00000000080012a8 HAL_NVIC_SetPriority
.text.HAL_SYSTICK_Config
- 0x00000000080012c2 0x1a ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o
- 0x00000000080012c2 HAL_SYSTICK_Config
+ 0x00000000080012d2 0x1a ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_cortex.o
+ 0x00000000080012d2 HAL_SYSTICK_Config
.text.HAL_GPIO_Init
- 0x00000000080012dc 0x2dc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o
- 0x00000000080012dc HAL_GPIO_Init
+ 0x00000000080012ec 0x2dc ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_gpio.o
+ 0x00000000080012ec HAL_GPIO_Init
.text.HAL_I2C_Init
- 0x00000000080015b8 0x12c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o
- 0x00000000080015b8 HAL_I2C_Init
+ 0x00000000080015c8 0x12c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o
+ 0x00000000080015c8 HAL_I2C_Init
.text.HAL_I2C_Master_Transmit
- 0x00000000080016e4 0x210 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o
- 0x00000000080016e4 HAL_I2C_Master_Transmit
+ 0x00000000080016f4 0x210 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o
+ 0x00000000080016f4 HAL_I2C_Master_Transmit
.text.HAL_I2C_Master_Receive
- 0x00000000080018f4 0x210 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o
- 0x00000000080018f4 HAL_I2C_Master_Receive
+ 0x0000000008001904 0x210 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o
+ 0x0000000008001904 HAL_I2C_Master_Receive
.text.HAL_I2C_Mem_Read
- 0x0000000008001b04 0x268 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o
- 0x0000000008001b04 HAL_I2C_Mem_Read
+ 0x0000000008001b14 0x268 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o
+ 0x0000000008001b14 HAL_I2C_Mem_Read
.text.I2C_RequestMemoryRead
- 0x0000000008001d6c 0xc4 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o
+ 0x0000000008001d7c 0xc4 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o
.text.I2C_Flush_TXDR
- 0x0000000008001e30 0x44 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o
+ 0x0000000008001e40 0x44 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o
.text.I2C_WaitOnFlagUntilTimeout
- 0x0000000008001e74 0x7e ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o
+ 0x0000000008001e84 0x7e ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o
.text.I2C_WaitOnTXISFlagUntilTimeout
- 0x0000000008001ef2 0x7e ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o
+ 0x0000000008001f02 0x7e ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o
.text.I2C_WaitOnSTOPFlagUntilTimeout
- 0x0000000008001f70 0x78 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o
+ 0x0000000008001f80 0x78 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o
.text.I2C_WaitOnRXNEFlagUntilTimeout
- 0x0000000008001fe8 0xd8 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o
+ 0x0000000008001ff8 0xd8 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o
.text.I2C_IsAcknowledgeFailed
- 0x00000000080020c0 0xf4 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o
+ 0x00000000080020d0 0xf4 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o
.text.I2C_TransferConfig
- 0x00000000080021b4 0x6c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o
+ 0x00000000080021c4 0x6c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c.o
.text.HAL_I2CEx_ConfigAnalogFilter
- 0x0000000008002220 0x98 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o
- 0x0000000008002220 HAL_I2CEx_ConfigAnalogFilter
+ 0x0000000008002230 0x98 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o
+ 0x0000000008002230 HAL_I2CEx_ConfigAnalogFilter
.text.HAL_I2CEx_ConfigDigitalFilter
- 0x00000000080022b8 0x98 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o
- 0x00000000080022b8 HAL_I2CEx_ConfigDigitalFilter
+ 0x00000000080022c8 0x98 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_i2c_ex.o
+ 0x00000000080022c8 HAL_I2CEx_ConfigDigitalFilter
.text.HAL_RCC_OscConfig
- 0x0000000008002350 0x6f8 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o
- 0x0000000008002350 HAL_RCC_OscConfig
+ 0x0000000008002360 0x6f8 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o
+ 0x0000000008002360 HAL_RCC_OscConfig
.text.HAL_RCC_ClockConfig
- 0x0000000008002a48 0x290 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o
- 0x0000000008002a48 HAL_RCC_ClockConfig
+ 0x0000000008002a58 0x290 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o
+ 0x0000000008002a58 HAL_RCC_ClockConfig
.text.HAL_RCC_GetSysClockFreq
- 0x0000000008002cd8 0x14c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o
- 0x0000000008002cd8 HAL_RCC_GetSysClockFreq
+ 0x0000000008002ce8 0x14c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o
+ 0x0000000008002ce8 HAL_RCC_GetSysClockFreq
.text.HAL_RCC_GetHCLKFreq
- 0x0000000008002e24 0x14 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o
- 0x0000000008002e24 HAL_RCC_GetHCLKFreq
+ 0x0000000008002e34 0x14 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o
+ 0x0000000008002e34 HAL_RCC_GetHCLKFreq
.text.HAL_RCC_GetPCLK1Freq
- 0x0000000008002e38 0x2c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o
- 0x0000000008002e38 HAL_RCC_GetPCLK1Freq
+ 0x0000000008002e48 0x2c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o
+ 0x0000000008002e48 HAL_RCC_GetPCLK1Freq
.text.HAL_RCC_GetPCLK2Freq
- 0x0000000008002e64 0x2c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o
- 0x0000000008002e64 HAL_RCC_GetPCLK2Freq
+ 0x0000000008002e74 0x2c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc.o
+ 0x0000000008002e74 HAL_RCC_GetPCLK2Freq
.text.HAL_RCCEx_PeriphCLKConfig
- 0x0000000008002e90 0x24c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o
- 0x0000000008002e90 HAL_RCCEx_PeriphCLKConfig
+ 0x0000000008002ea0 0x24c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_rcc_ex.o
+ 0x0000000008002ea0 HAL_RCCEx_PeriphCLKConfig
.text.HAL_TIM_Base_Init
- 0x00000000080030dc 0x80 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o
- 0x00000000080030dc HAL_TIM_Base_Init
+ 0x00000000080030ec 0x80 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o
+ 0x00000000080030ec HAL_TIM_Base_Init
.text.HAL_TIM_PWM_Init
- 0x000000000800315c 0x80 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o
- 0x000000000800315c HAL_TIM_PWM_Init
+ 0x000000000800316c 0x80 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o
+ 0x000000000800316c HAL_TIM_PWM_Init
.text.HAL_TIM_PWM_MspInit
- 0x00000000080031dc 0x10 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o
- 0x00000000080031dc HAL_TIM_PWM_MspInit
+ 0x00000000080031ec 0x10 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o
+ 0x00000000080031ec HAL_TIM_PWM_MspInit
.text.HAL_TIM_PWM_ConfigChannel
- 0x00000000080031ec 0x18c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o
- 0x00000000080031ec HAL_TIM_PWM_ConfigChannel
+ 0x00000000080031fc 0x18c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o
+ 0x00000000080031fc HAL_TIM_PWM_ConfigChannel
.text.HAL_TIM_ConfigClockSource
- 0x0000000008003378 0x1a8 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o
- 0x0000000008003378 HAL_TIM_ConfigClockSource
+ 0x0000000008003388 0x1a8 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o
+ 0x0000000008003388 HAL_TIM_ConfigClockSource
.text.TIM_Base_SetConfig
- 0x0000000008003520 0xa8 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o
+ 0x0000000008003530 0xa8 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o
.text.TIM_OC1_SetConfig
- 0x00000000080035c8 0x78 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o
+ 0x00000000080035d8 0x78 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o
.text.TIM_OC2_SetConfig
- 0x0000000008003640 0x84 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o
+ 0x0000000008003650 0x84 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o
.text.TIM_OC3_SetConfig
- 0x00000000080036c4 0x80 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o
+ 0x00000000080036d4 0x80 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o
.text.TIM_OC4_SetConfig
- 0x0000000008003744 0x8c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o
+ 0x0000000008003754 0x8c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o
.text.TIM_TI1_ConfigInputStage
- 0x00000000080037d0 0x5c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o
+ 0x00000000080037e0 0x5c ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o
.text.TIM_TI2_ConfigInputStage
- 0x000000000800382c 0x64 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o
+ 0x000000000800383c 0x64 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o
.text.TIM_ITRx_SetConfig
- 0x0000000008003890 0x32 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o
- *fill* 0x00000000080038c2 0x2
+ 0x00000000080038a0 0x32 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o
+ *fill* 0x00000000080038d2 0x2
.text.TIM_ETR_SetConfig
- 0x00000000080038c4 0x40 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o
+ 0x00000000080038d4 0x40 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim.o
.text.HAL_TIMEx_MasterConfigSynchronization
- 0x0000000008003904 0xb0 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o
- 0x0000000008003904 HAL_TIMEx_MasterConfigSynchronization
+ 0x0000000008003914 0xb0 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_tim_ex.o
+ 0x0000000008003914 HAL_TIMEx_MasterConfigSynchronization
.text.UART_SetConfig
- 0x00000000080039b4 0x4c4 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o
- 0x00000000080039b4 UART_SetConfig
+ 0x00000000080039c4 0x4c4 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o
+ 0x00000000080039c4 UART_SetConfig
.text.UART_AdvFeatureConfig
- 0x0000000008003e78 0x168 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o
- 0x0000000008003e78 UART_AdvFeatureConfig
+ 0x0000000008003e88 0x168 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o
+ 0x0000000008003e88 UART_AdvFeatureConfig
.text.UART_CheckIdleState
- 0x0000000008003fe0 0x90 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o
- 0x0000000008003fe0 UART_CheckIdleState
+ 0x0000000008003ff0 0x90 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o
+ 0x0000000008003ff0 UART_CheckIdleState
.text.UART_WaitOnFlagUntilTimeout
- 0x0000000008004070 0x188 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o
- 0x0000000008004070 UART_WaitOnFlagUntilTimeout
+ 0x0000000008004080 0x188 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o
+ 0x0000000008004080 UART_WaitOnFlagUntilTimeout
.text.HAL_RS485Ex_Init
- 0x00000000080041f8 0xe0 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.o
- 0x00000000080041f8 HAL_RS485Ex_Init
+ 0x0000000008004208 0xe0 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart_ex.o
+ 0x0000000008004208 HAL_RS485Ex_Init
.text.__libc_init_array
- 0x00000000080042d8 0x48 /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-init.o)
- 0x00000000080042d8 __libc_init_array
- .text.memset 0x0000000008004320 0x10 /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-memset.o)
- 0x0000000008004320 memset
+ 0x00000000080042e8 0x48 /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-init.o)
+ 0x00000000080042e8 __libc_init_array
+ .text.memset 0x0000000008004330 0x10 /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/libc_nano.a(lib_a-memset.o)
+ 0x0000000008004330 memset
*(.glue_7)
- .glue_7 0x0000000008004330 0x0 linker stubs
+ .glue_7 0x0000000008004340 0x0 linker stubs
*(.glue_7t)
- .glue_7t 0x0000000008004330 0x0 linker stubs
+ .glue_7t 0x0000000008004340 0x0 linker stubs
*(.eh_frame)
- .eh_frame 0x0000000008004330 0x0 /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crtbegin.o
+ .eh_frame 0x0000000008004340 0x0 /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crtbegin.o
*(.init)
- .init 0x0000000008004330 0x4 /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crti.o
- 0x0000000008004330 _init
- .init 0x0000000008004334 0x8 /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crtn.o
+ .init 0x0000000008004340 0x4 /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crti.o
+ 0x0000000008004340 _init
+ .init 0x0000000008004344 0x8 /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crtn.o
*(.fini)
- .fini 0x000000000800433c 0x4 /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crti.o
- 0x000000000800433c _fini
- .fini 0x0000000008004340 0x8 /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crtn.o
- 0x0000000008004348 . = ALIGN (0x4)
- 0x0000000008004348 _etext = .
+ .fini 0x000000000800434c 0x4 /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crti.o
+ 0x000000000800434c _fini
+ .fini 0x0000000008004350 0x8 /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crtn.o
+ 0x0000000008004358 . = ALIGN (0x4)
+ 0x0000000008004358 _etext = .
-.vfp11_veneer 0x0000000008004348 0x0
- .vfp11_veneer 0x0000000008004348 0x0 linker stubs
+.vfp11_veneer 0x0000000008004358 0x0
+ .vfp11_veneer 0x0000000008004358 0x0 linker stubs
-.v4_bx 0x0000000008004348 0x0
- .v4_bx 0x0000000008004348 0x0 linker stubs
+.v4_bx 0x0000000008004358 0x0
+ .v4_bx 0x0000000008004358 0x0 linker stubs
-.iplt 0x0000000008004348 0x0
- .iplt 0x0000000008004348 0x0 /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crtbegin.o
+.iplt 0x0000000008004358 0x0
+ .iplt 0x0000000008004358 0x0 /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crtbegin.o
-.rodata 0x0000000008004348 0x6c
- 0x0000000008004348 . = ALIGN (0x4)
+.rodata 0x0000000008004358 0x6c
+ 0x0000000008004358 . = ALIGN (0x4)
*(.rodata)
*(.rodata*)
.rodata.AHBPrescTable
- 0x0000000008004348 0x10 ./Core/Src/system_stm32l0xx.o
- 0x0000000008004348 AHBPrescTable
+ 0x0000000008004358 0x10 ./Core/Src/system_stm32l0xx.o
+ 0x0000000008004358 AHBPrescTable
.rodata.APBPrescTable
- 0x0000000008004358 0x8 ./Core/Src/system_stm32l0xx.o
- 0x0000000008004358 APBPrescTable
+ 0x0000000008004368 0x8 ./Core/Src/system_stm32l0xx.o
+ 0x0000000008004368 APBPrescTable
.rodata.PLLMulTable
- 0x0000000008004360 0x9 ./Core/Src/system_stm32l0xx.o
- 0x0000000008004360 PLLMulTable
- *fill* 0x0000000008004369 0x3
+ 0x0000000008004370 0x9 ./Core/Src/system_stm32l0xx.o
+ 0x0000000008004370 PLLMulTable
+ *fill* 0x0000000008004379 0x3
.rodata.UART_SetConfig
- 0x000000000800436c 0x48 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o
- 0x00000000080043b4 . = ALIGN (0x4)
+ 0x000000000800437c 0x48 ./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_hal_uart.o
+ 0x00000000080043c4 . = ALIGN (0x4)
-.ARM.extab 0x00000000080043b4 0x0
- 0x00000000080043b4 . = ALIGN (0x4)
+.ARM.extab 0x00000000080043c4 0x0
+ 0x00000000080043c4 . = ALIGN (0x4)
*(.ARM.extab* .gnu.linkonce.armextab.*)
- 0x00000000080043b4 . = ALIGN (0x4)
+ 0x00000000080043c4 . = ALIGN (0x4)
-.ARM 0x00000000080043b4 0x8
- 0x00000000080043b4 . = ALIGN (0x4)
- 0x00000000080043b4 __exidx_start = .
+.ARM 0x00000000080043c4 0x8
+ 0x00000000080043c4 . = ALIGN (0x4)
+ 0x00000000080043c4 __exidx_start = .
*(.ARM.exidx*)
- .ARM.exidx 0x00000000080043b4 0x8 /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_udivmoddi4.o)
- 0x00000000080043bc __exidx_end = .
- 0x00000000080043bc . = ALIGN (0x4)
+ .ARM.exidx 0x00000000080043c4 0x8 /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/libgcc.a(_udivmoddi4.o)
+ 0x00000000080043cc __exidx_end = .
+ 0x00000000080043cc . = ALIGN (0x4)
-.rel.dyn 0x00000000080043bc 0x0
- .rel.iplt 0x00000000080043bc 0x0 /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crtbegin.o
+.rel.dyn 0x00000000080043cc 0x0
+ .rel.iplt 0x00000000080043cc 0x0 /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crtbegin.o
-.preinit_array 0x00000000080043bc 0x0
- 0x00000000080043bc . = ALIGN (0x4)
- 0x00000000080043bc PROVIDE (__preinit_array_start = .)
+.preinit_array 0x00000000080043cc 0x0
+ 0x00000000080043cc . = ALIGN (0x4)
+ 0x00000000080043cc PROVIDE (__preinit_array_start = .)
*(.preinit_array*)
- 0x00000000080043bc PROVIDE (__preinit_array_end = .)
- 0x00000000080043bc . = ALIGN (0x4)
+ 0x00000000080043cc PROVIDE (__preinit_array_end = .)
+ 0x00000000080043cc . = ALIGN (0x4)
-.init_array 0x00000000080043bc 0x4
- 0x00000000080043bc . = ALIGN (0x4)
- 0x00000000080043bc PROVIDE (__init_array_start = .)
+.init_array 0x00000000080043cc 0x4
+ 0x00000000080043cc . = ALIGN (0x4)
+ 0x00000000080043cc PROVIDE (__init_array_start = .)
*(SORT_BY_NAME(.init_array.*))
*(.init_array*)
- .init_array 0x00000000080043bc 0x4 /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crtbegin.o
- 0x00000000080043c0 PROVIDE (__init_array_end = .)
- 0x00000000080043c0 . = ALIGN (0x4)
+ .init_array 0x00000000080043cc 0x4 /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crtbegin.o
+ 0x00000000080043d0 PROVIDE (__init_array_end = .)
+ 0x00000000080043d0 . = ALIGN (0x4)
-.fini_array 0x00000000080043c0 0x4
- 0x00000000080043c0 . = ALIGN (0x4)
+.fini_array 0x00000000080043d0 0x4
+ 0x00000000080043d0 . = ALIGN (0x4)
[!provide] PROVIDE (__fini_array_start = .)
*(SORT_BY_NAME(.fini_array.*))
*(.fini_array*)
- .fini_array 0x00000000080043c0 0x4 /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crtbegin.o
+ .fini_array 0x00000000080043d0 0x4 /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crtbegin.o
[!provide] PROVIDE (__fini_array_end = .)
- 0x00000000080043c4 . = ALIGN (0x4)
- 0x00000000080043c4 _sidata = LOADADDR (.data)
+ 0x00000000080043d4 . = ALIGN (0x4)
+ 0x00000000080043d4 _sidata = LOADADDR (.data)
-.data 0x0000000020000000 0xc load address 0x00000000080043c4
+.data 0x0000000020000000 0xc load address 0x00000000080043d4
0x0000000020000000 . = ALIGN (0x4)
0x0000000020000000 _sdata = .
*(.data)
@@ -4138,11 +4138,11 @@ LOAD /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.g
*fill* 0x0000000020000009 0x3
0x000000002000000c _edata = .
-.igot.plt 0x000000002000000c 0x0 load address 0x00000000080043d0
+.igot.plt 0x000000002000000c 0x0 load address 0x00000000080043e0
.igot.plt 0x000000002000000c 0x0 /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.9-2020-q2-update.linux64_2.0.0.202105311346/tools/bin/../lib/gcc/arm-none-eabi/9.3.1/thumb/v6-m/nofp/crtbegin.o
0x000000002000000c . = ALIGN (0x4)
-.bss 0x000000002000000c 0x204 load address 0x00000000080043d0
+.bss 0x000000002000000c 0x204 load address 0x00000000080043e0
0x000000002000000c _sbss = .
0x000000002000000c __bss_start__ = _sbss
*(.bss)
@@ -4186,7 +4186,7 @@ LOAD /opt/st/stm32cubeide_1.6.1/plugins/com.st.stm32cube.ide.mcu.externaltools.g
0x0000000020000210 __bss_end__ = _ebss
._user_heap_stack
- 0x0000000020000210 0x600 load address 0x00000000080043d0
+ 0x0000000020000210 0x600 load address 0x00000000080043e0
0x0000000020000210 . = ALIGN (0x8)
[!provide] PROVIDE (end = .)
0x0000000020000210 PROVIDE (_end = .)
diff --git a/fw_hal/iaq_wired_sensor_hal.ioc b/fw_hal/iaq_wired_sensor_hal.ioc
index 62cf5df..fc3ed87 100644
--- a/fw_hal/iaq_wired_sensor_hal.ioc
+++ b/fw_hal/iaq_wired_sensor_hal.ioc
@@ -1,6 +1,7 @@
#MicroXplorer Configuration settings - do not modify
File.Version=6
-I2C1.IPParameters=Timing
+I2C1.IPParameters=Timing,NoStretchMode
+I2C1.NoStretchMode=I2C_NOSTRETCH_DISABLE
I2C1.Timing=0x40000A0B
KeepUserPlacement=false
Mcu.Family=STM32L0