Created timer for measurement and base for UART. Polished main a bit.
This commit is contained in:
David Žaitlík
parent
3abd90f197
commit
35e0e1fadc
@ -1,24 +1,24 @@
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[PreviousLibFiles]
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LibFiles=Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_crs.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_pwr.c;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_crs.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h;Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l011xx.h;Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h;Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h;Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/system_stm32l0xx.c;Drivers/CMSIS/Include/core_cm4.h;Drivers/CMSIS/Include/tz_context.h;Drivers/CMSIS/Include/cmsis_compiler.h;Drivers/CMSIS/Include/mpu_armv7.h;Drivers/CMSIS/Include/core_cm7.h;Drivers/CMSIS/Include/core_cm0.h;Drivers/CMSIS/Include/cmsis_armcc.h;Drivers/CMSIS/Include/core_cm23.h;Drivers/CMSIS/Include/core_sc000.h;Drivers/CMSIS/Include/cmsis_version.h;Drivers/CMSIS/Include/core_cm1.h;Drivers/CMSIS/Include/core_cm0plus.h;Drivers/CMSIS/Include/cmsis_armclang.h;Drivers/CMSIS/Include/cmsis_iccarm.h;Drivers/CMSIS/Include/cmsis_gcc.h;Drivers/CMSIS/Include/core_sc300.h;Drivers/CMSIS/Include/core_cm3.h;Drivers/CMSIS/Include/mpu_armv8.h;Drivers/CMSIS/Include/core_cm33.h;Drivers/CMSIS/Include/core_armv8mml.h;Drivers/CMSIS/Include/core_armv8mbl.h;
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LibFiles=Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_crs.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_pwr.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_crs.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h;Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h;Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l011xx.h;Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h;Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h;Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/system_stm32l0xx.c;Drivers/CMSIS/Include/cmsis_iccarm.h;Drivers/CMSIS/Include/cmsis_gcc.h;Drivers/CMSIS/Include/core_sc000.h;Drivers/CMSIS/Include/cmsis_armclang.h;Drivers/CMSIS/Include/core_cm1.h;Drivers/CMSIS/Include/core_armv8mbl.h;Drivers/CMSIS/Include/core_cm33.h;Drivers/CMSIS/Include/cmsis_version.h;Drivers/CMSIS/Include/cmsis_compiler.h;Drivers/CMSIS/Include/mpu_armv7.h;Drivers/CMSIS/Include/mpu_armv8.h;Drivers/CMSIS/Include/core_cm0plus.h;Drivers/CMSIS/Include/core_sc300.h;Drivers/CMSIS/Include/tz_context.h;Drivers/CMSIS/Include/core_cm0.h;Drivers/CMSIS/Include/core_cm7.h;Drivers/CMSIS/Include/core_cm23.h;Drivers/CMSIS/Include/core_armv8mml.h;Drivers/CMSIS/Include/core_cm4.h;Drivers/CMSIS/Include/cmsis_armcc.h;Drivers/CMSIS/Include/core_cm3.h;
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[PreviousUsedCubeIDEFiles]
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SourceFiles=Core/Src/main.c;Core/Src/stm32l0xx_it.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_pwr.c;Core/Src/system_stm32l0xx.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_pwr.c;Core/Src/system_stm32l0xx.c;Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/system_stm32l0xx.c;;
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SourceFiles=Core/Src/main.c;Core/Src/stm32l0xx_it.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_pwr.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c;Core/Src/system_stm32l0xx.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_pwr.c;Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c;Core/Src/system_stm32l0xx.c;Drivers/CMSIS/Device/ST/STM32L0xx/Source/Templates/system_stm32l0xx.c;;
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HeaderPath=Drivers/STM32L0xx_HAL_Driver/Inc;Drivers/CMSIS/Device/ST/STM32L0xx/Include;Drivers/CMSIS/Include;Core/Inc;
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CDefines=USE_FULL_LL_DRIVER;HSE_VALUE:8000000;HSE_STARTUP_TIMEOUT:100;LSE_STARTUP_TIMEOUT:5000;LSE_VALUE:32768;MSI_VALUE:2097000;HSI_VALUE:16000000;LSI_VALUE:37000;VDD_VALUE:3300;PREFETCH_ENABLE:0;INSTRUCTION_CACHE_ENABLE:1;DATA_CACHE_ENABLE:1;STM32L011xx;USE_FULL_LL_DRIVER;HSE_VALUE:8000000;HSE_STARTUP_TIMEOUT:100;LSE_STARTUP_TIMEOUT:5000;LSE_VALUE:32768;MSI_VALUE:2097000;HSI_VALUE:16000000;LSI_VALUE:37000;VDD_VALUE:3300;PREFETCH_ENABLE:0;INSTRUCTION_CACHE_ENABLE:1;DATA_CACHE_ENABLE:1;
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[PreviousGenFiles]
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AdvancedFolderStructure=true
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HeaderFileListSize=3
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HeaderFiles#0=/home/david/Personal/Projects/HDIoT/Smart_Household/Wired_Sensors/iaq_wired_sensor/fw/Core/Inc/stm32l0xx_it.h
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HeaderFiles#1=/home/david/Personal/Projects/HDIoT/Smart_Household/Wired_Sensors/iaq_wired_sensor/fw/Core/Inc/stm32_assert.h
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HeaderFiles#2=/home/david/Personal/Projects/HDIoT/Smart_Household/Wired_Sensors/iaq_wired_sensor/fw/Core/Inc/main.h
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HeaderFiles#0=/home/mrs/Personal/HDIoT/Smart_Household/iaq_wired_sensor/fw/Core/Inc/stm32l0xx_it.h
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HeaderFiles#1=/home/mrs/Personal/HDIoT/Smart_Household/iaq_wired_sensor/fw/Core/Inc/stm32_assert.h
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HeaderFiles#2=/home/mrs/Personal/HDIoT/Smart_Household/iaq_wired_sensor/fw/Core/Inc/main.h
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HeaderFolderListSize=1
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HeaderPath#0=/home/david/Personal/Projects/HDIoT/Smart_Household/Wired_Sensors/iaq_wired_sensor/fw/Core/Inc
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HeaderPath#0=/home/mrs/Personal/HDIoT/Smart_Household/iaq_wired_sensor/fw/Core/Inc
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HeaderFiles=;
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SourceFileListSize=2
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SourceFiles#0=/home/david/Personal/Projects/HDIoT/Smart_Household/Wired_Sensors/iaq_wired_sensor/fw/Core/Src/stm32l0xx_it.c
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SourceFiles#1=/home/david/Personal/Projects/HDIoT/Smart_Household/Wired_Sensors/iaq_wired_sensor/fw/Core/Src/main.c
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SourceFiles#0=/home/mrs/Personal/HDIoT/Smart_Household/iaq_wired_sensor/fw/Core/Src/stm32l0xx_it.c
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SourceFiles#1=/home/mrs/Personal/HDIoT/Smart_Household/iaq_wired_sensor/fw/Core/Src/main.c
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SourceFolderListSize=1
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SourcePath#0=/home/david/Personal/Projects/HDIoT/Smart_Household/Wired_Sensors/iaq_wired_sensor/fw/Core/Src
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SourcePath#0=/home/mrs/Personal/HDIoT/Smart_Household/iaq_wired_sensor/fw/Core/Src
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SourceFiles=;
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@ -28,8 +28,6 @@ extern "C" {
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#endif
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/* Includes ------------------------------------------------------------------*/
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#include "stm32l0xx_ll_dma.h"
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#include "stm32l0xx.h"
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#include "stm32l0xx_ll_i2c.h"
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#include "stm32l0xx_ll_lpuart.h"
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#include "stm32l0xx_ll_rcc.h"
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@ -40,6 +38,8 @@ extern "C" {
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#include "stm32l0xx_ll_cortex.h"
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#include "stm32l0xx_ll_utils.h"
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#include "stm32l0xx_ll_pwr.h"
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#include "stm32l0xx_ll_dma.h"
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#include "stm32l0xx_ll_tim.h"
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#include "stm32l0xx_ll_gpio.h"
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#if defined(USE_FULL_ASSERT)
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@ -51,6 +51,7 @@ extern "C" {
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#include "i2c.h"
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#include "scd4x.h"
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#include "sht4x.h"
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#include "sps30.h"
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/* USER CODE END Includes */
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/* Exported types ------------------------------------------------------------*/
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@ -95,7 +96,14 @@ void Error_Handler(void);
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0 bit for subpriority */
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#endif
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/* USER CODE BEGIN Private defines */
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#define MEASUREMENT_PERIOD_MS 600000
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extern uint8_t lpuart1_rx_message[255];
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extern uint8_t lpuart1_rx_message_index;
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extern uint8_t lpuart1_rx_message_len;
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extern uint8_t lpuart1_rx_done;
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extern uint8_t tim21_elapsed_period;
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/* USER CODE END Private defines */
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#ifdef __cplusplus
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@ -73,6 +73,6 @@ int8_t sps30_read_status_register ( void );
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int8_t sps30_read_firmware_version ( uint8_t * fw_ver_hi, uint8_t * fw_ver_lo );
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static uint8_t calculate_crc(uint8_t data[2]);
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uint8_t calculate_crc(uint8_t data[2]);
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#endif /* INC_SPS30_H_ */
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@ -38,7 +38,6 @@
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/* Exported constants --------------------------------------------------------*/
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/* USER CODE BEGIN EC */
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/* USER CODE END EC */
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/* Exported macro ------------------------------------------------------------*/
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@ -52,9 +51,9 @@ void HardFault_Handler(void);
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void SVC_Handler(void);
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void PendSV_Handler(void);
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void SysTick_Handler(void);
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void DMA1_Channel2_3_IRQHandler(void);
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void TIM21_IRQHandler(void);
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void LPUART1_IRQHandler(void);
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/* USER CODE BEGIN EFP */
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/* USER CODE END EFP */
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#ifdef __cplusplus
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@ -42,15 +42,22 @@
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/* Private variables ---------------------------------------------------------*/
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/* USER CODE BEGIN PV */
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/*
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* BASE CLOCK 12MHz
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* Desired interrupt period 60s
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*/
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const uint16_t tim21_prescaler = 60000-1; // 100Hz
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const uint16_t tim21_period = 12000-1; // 60s
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//const uint16_t tim21_period = 1200-1; // 6s
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//const uint16_t tim21_period = 200-1; // 1s
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/* USER CODE END PV */
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/* Private function prototypes -----------------------------------------------*/
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void SystemClock_Config(void);
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static void MX_GPIO_Init(void);
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static void MX_DMA_Init(void);
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static void MX_I2C1_Init(void);
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static void MX_LPUART1_UART_Init(void);
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static void MX_TIM21_Init(void);
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/* USER CODE BEGIN PFP */
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/* USER CODE END PFP */
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@ -92,12 +99,21 @@ int main(void)
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/* Initialize all configured peripherals */
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MX_GPIO_Init();
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MX_DMA_Init();
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MX_I2C1_Init();
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MX_LPUART1_UART_Init();
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MX_TIM21_Init();
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/* USER CODE BEGIN 2 */
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/* Enable I2C for sensors */
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LL_I2C_Enable(I2C1);
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/* Enable UART for RS485 */
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LL_LPUART_Enable(LPUART1);
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/* Start the timer for measurement triggering */
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LL_TIM_EnableCounter(TIM21);
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LL_TIM_EnableIT_UPDATE(TIM21);
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/*LL_TIM_GenerateEvent_UPDATE(TIM2);*/
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/* I2C context init (for SHT4x and SCD4x) */
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i2c_context_t i2c_context;
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i2c_context.i2c = I2C1;
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@ -107,47 +123,100 @@ int main(void)
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/* Infinite loop */
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/* USER CODE BEGIN WHILE */
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uint8_t uart_data_dummy = 0;
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//scd4x_perform_factory_reset();
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//LL_mDelay(2000);
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scd4x_start_periodic_measurement();
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uint8_t sps30_fw_v_hi, sps30_fw_v_lo;
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sps30_read_firmware_version(&sps30_fw_v_hi, &sps30_fw_v_lo);
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uint8_t scd4x_is_connected = 0;
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if (scd4x_start_periodic_measurement() == SCD4X_OK)
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{
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scd4x_is_connected = 1;
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}
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/* Attempt to start SPS30 measurement and check if it's connected */
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sps30_reset();
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sps30_start_measurement();
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LL_mDelay(2000);
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uint8_t sps30_is_connected = 0;
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if (sps30_start_measurement() == SPS30_OK)
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{
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sps30_is_connected = 1;
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}
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/* Variables to store the measured data */
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int CO2, T_SCD4x, RH_SCD4x;
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int T_SHT4x, RH_SHT4x;
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uint16_t sps30_measured_data[10];
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/*
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sps30_start_fan_cleaning();
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LL_mDelay(15000);
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*/
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/* Wait 1000ms for sensors initialization */
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/* SHT4x Init Time: max 1 ms (datasheet pg. 8) */
|
||||
/* SCD4x Init Time: max 1000 ms (datasheet pg. 6) */
|
||||
/* SPS30 Init Time: max 30000 ms (datasheet pg. 2) */
|
||||
LL_mDelay(1000);
|
||||
|
||||
/* Turn on LED to signal ready state */
|
||||
LL_GPIO_ResetOutputPin(LED_B_GPIO_Port, LED_B_Pin);
|
||||
|
||||
/* Enter the main loop */
|
||||
while (1)
|
||||
{
|
||||
/* UART RX is done */
|
||||
if (lpuart1_rx_done == 1)
|
||||
{
|
||||
/* Process the message */
|
||||
/* process_modbus_message(lpuart1_rx_message, lpuart1_rx_message_len); */
|
||||
|
||||
/* Reset the RX DONE flag */
|
||||
lpuart1_rx_done = 0;
|
||||
}
|
||||
|
||||
/* It is time for measurement */
|
||||
if (tim21_elapsed_period == 1)
|
||||
{
|
||||
/* TODO: Check the data */
|
||||
/* Read SHT4x data (always connected) */
|
||||
sht4x_measure(&T_SHT4x, &RH_SHT4x);
|
||||
|
||||
/* Read SCD4x data (if connected) */
|
||||
if (scd4x_is_connected == 1)
|
||||
{
|
||||
scd4x_read_measurement(&CO2, &T_SCD4x, &RH_SCD4x);
|
||||
}
|
||||
|
||||
/* Read SPS30 data (if connected) */
|
||||
if (sps30_is_connected == 1)
|
||||
{
|
||||
sps30_read_measured_values(sps30_measured_data, 10);
|
||||
}
|
||||
|
||||
/* Toggle LED for now */
|
||||
/* TODO: Remove LED Toggle */
|
||||
LL_GPIO_TogglePin(LED_B_GPIO_Port, LED_B_Pin);
|
||||
|
||||
/* TODO: Process data and light a desired color of LED */
|
||||
|
||||
/* Reset the TIM21 Elapsed Period Flag */
|
||||
tim21_elapsed_period = 0;
|
||||
}
|
||||
/* TEST START */
|
||||
/* TODO: DELETE TEST */
|
||||
|
||||
/* RS485 test */
|
||||
/*LL_LPUART_SetDESignalPolarity(LPUART1, 1);
|
||||
LL_LPUART_TransmitData8(LPUART1, uart_data_dummy);
|
||||
uart_data_dummy++;*/
|
||||
|
||||
/* SHT41 measurement */
|
||||
sht4x_measure(&T_SHT4x, &RH_SHT4x);
|
||||
LL_mDelay(10);
|
||||
/*sht4x_measure(&T_SHT4x, &RH_SHT4x);
|
||||
LL_mDelay(10);*/
|
||||
|
||||
/* SCD4x measurement */
|
||||
scd4x_read_measurement(&CO2, &T_SCD4x, &RH_SCD4x);
|
||||
LL_mDelay(10);
|
||||
/*scd4x_read_measurement(&CO2, &T_SCD4x, &RH_SCD4x);
|
||||
LL_mDelay(10);*/
|
||||
|
||||
/* SPS30 measurement*/
|
||||
sps30_read_measured_values(sps30_measured_data, 10);
|
||||
/*sps30_read_measured_values(sps30_measured_data, 10);*/
|
||||
|
||||
/* SLEEP */
|
||||
LL_mDelay(1000);
|
||||
/*LL_mDelay(1000);*/
|
||||
|
||||
/* TEST END */
|
||||
/* USER CODE END WHILE */
|
||||
|
||||
/* USER CODE BEGIN 3 */
|
||||
}
|
||||
/* USER CODE END 3 */
|
||||
@ -164,29 +233,36 @@ void SystemClock_Config(void)
|
||||
{
|
||||
}
|
||||
LL_PWR_SetRegulVoltageScaling(LL_PWR_REGU_VOLTAGE_SCALE1);
|
||||
LL_RCC_MSI_Enable();
|
||||
LL_RCC_HSI_Enable();
|
||||
|
||||
/* Wait till MSI is ready */
|
||||
while(LL_RCC_MSI_IsReady() != 1)
|
||||
/* Wait till HSI is ready */
|
||||
while(LL_RCC_HSI_IsReady() != 1)
|
||||
{
|
||||
|
||||
}
|
||||
LL_RCC_HSI_SetCalibTrimming(16);
|
||||
LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI, LL_RCC_PLL_MUL_3, LL_RCC_PLL_DIV_4);
|
||||
LL_RCC_PLL_Enable();
|
||||
|
||||
/* Wait till PLL is ready */
|
||||
while(LL_RCC_PLL_IsReady() != 1)
|
||||
{
|
||||
|
||||
}
|
||||
LL_RCC_MSI_SetRange(LL_RCC_MSIRANGE_5);
|
||||
LL_RCC_MSI_SetCalibTrimming(0);
|
||||
LL_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_1);
|
||||
LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_1);
|
||||
LL_RCC_SetAPB2Prescaler(LL_RCC_APB2_DIV_1);
|
||||
LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_MSI);
|
||||
LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL);
|
||||
|
||||
/* Wait till System clock is ready */
|
||||
while(LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_MSI)
|
||||
while(LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL)
|
||||
{
|
||||
|
||||
}
|
||||
|
||||
LL_Init1msTick(2097000);
|
||||
LL_Init1msTick(12000000);
|
||||
|
||||
LL_SetSystemCoreClock(2097000);
|
||||
LL_SetSystemCoreClock(12000000);
|
||||
LL_RCC_SetLPUARTClockSource(LL_RCC_LPUART1_CLKSOURCE_PCLK1);
|
||||
LL_RCC_SetI2CClockSource(LL_RCC_I2C1_CLKSOURCE_PCLK1);
|
||||
}
|
||||
@ -241,7 +317,7 @@ static void MX_I2C1_Init(void)
|
||||
LL_I2C_DisableGeneralCall(I2C1);
|
||||
LL_I2C_EnableClockStretching(I2C1);
|
||||
I2C_InitStruct.PeripheralMode = LL_I2C_MODE_I2C;
|
||||
I2C_InitStruct.Timing = 0x00000708;
|
||||
I2C_InitStruct.Timing = 0x40000A0B;
|
||||
I2C_InitStruct.AnalogFilter = LL_I2C_ANALOGFILTER_ENABLE;
|
||||
I2C_InitStruct.DigitalFilter = 0;
|
||||
I2C_InitStruct.OwnAddress1 = 0;
|
||||
@ -274,9 +350,11 @@ static void MX_LPUART1_UART_Init(void)
|
||||
LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_LPUART1);
|
||||
|
||||
LL_IOP_GRP1_EnableClock(LL_IOP_GRP1_PERIPH_GPIOA);
|
||||
LL_IOP_GRP1_EnableClock(LL_IOP_GRP1_PERIPH_GPIOB);
|
||||
/**LPUART1 GPIO Configuration
|
||||
PA0-CK_IN ------> LPUART1_RX
|
||||
PA1 ------> LPUART1_TX
|
||||
PB1 ------> LPUART1_DE
|
||||
*/
|
||||
GPIO_InitStruct.Pin = LL_GPIO_PIN_0;
|
||||
GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE;
|
||||
@ -294,55 +372,80 @@ static void MX_LPUART1_UART_Init(void)
|
||||
GPIO_InitStruct.Alternate = LL_GPIO_AF_6;
|
||||
LL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
||||
|
||||
/* LPUART1 DMA Init */
|
||||
GPIO_InitStruct.Pin = LL_GPIO_PIN_1;
|
||||
GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE;
|
||||
GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH;
|
||||
GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;
|
||||
GPIO_InitStruct.Pull = LL_GPIO_PULL_NO;
|
||||
GPIO_InitStruct.Alternate = LL_GPIO_AF_4;
|
||||
LL_GPIO_Init(GPIOB, &GPIO_InitStruct);
|
||||
|
||||
/* LPUART1_RX Init */
|
||||
LL_DMA_SetPeriphRequest(DMA1, LL_DMA_CHANNEL_3, LL_DMA_REQUEST_5);
|
||||
|
||||
LL_DMA_SetDataTransferDirection(DMA1, LL_DMA_CHANNEL_3, LL_DMA_DIRECTION_PERIPH_TO_MEMORY);
|
||||
|
||||
LL_DMA_SetChannelPriorityLevel(DMA1, LL_DMA_CHANNEL_3, LL_DMA_PRIORITY_MEDIUM);
|
||||
|
||||
LL_DMA_SetMode(DMA1, LL_DMA_CHANNEL_3, LL_DMA_MODE_CIRCULAR);
|
||||
|
||||
LL_DMA_SetPeriphIncMode(DMA1, LL_DMA_CHANNEL_3, LL_DMA_PERIPH_NOINCREMENT);
|
||||
|
||||
LL_DMA_SetMemoryIncMode(DMA1, LL_DMA_CHANNEL_3, LL_DMA_MEMORY_INCREMENT);
|
||||
|
||||
LL_DMA_SetPeriphSize(DMA1, LL_DMA_CHANNEL_3, LL_DMA_PDATAALIGN_BYTE);
|
||||
|
||||
LL_DMA_SetMemorySize(DMA1, LL_DMA_CHANNEL_3, LL_DMA_MDATAALIGN_BYTE);
|
||||
/* LPUART1 interrupt Init */
|
||||
NVIC_SetPriority(LPUART1_IRQn, 0);
|
||||
NVIC_EnableIRQ(LPUART1_IRQn);
|
||||
|
||||
/* USER CODE BEGIN LPUART1_Init 1 */
|
||||
|
||||
/* USER CODE END LPUART1_Init 1 */
|
||||
LPUART_InitStruct.BaudRate = 115200;
|
||||
LPUART_InitStruct.DataWidth = LL_LPUART_DATAWIDTH_8B;
|
||||
LPUART_InitStruct.DataWidth = LL_LPUART_DATAWIDTH_9B;
|
||||
LPUART_InitStruct.StopBits = LL_LPUART_STOPBITS_1;
|
||||
LPUART_InitStruct.Parity = LL_LPUART_PARITY_NONE;
|
||||
LPUART_InitStruct.Parity = LL_LPUART_PARITY_EVEN;
|
||||
LPUART_InitStruct.TransferDirection = LL_LPUART_DIRECTION_TX_RX;
|
||||
LPUART_InitStruct.HardwareFlowControl = LL_LPUART_HWCONTROL_NONE;
|
||||
LL_LPUART_Init(LPUART1, &LPUART_InitStruct);
|
||||
LL_LPUART_EnableDEMode(LPUART1);
|
||||
LL_LPUART_SetDESignalPolarity(LPUART1, LL_LPUART_DE_POLARITY_HIGH);
|
||||
LL_LPUART_SetDEAssertionTime(LPUART1, 0);
|
||||
LL_LPUART_SetDEDeassertionTime(LPUART1, 0);
|
||||
/* USER CODE BEGIN LPUART1_Init 2 */
|
||||
|
||||
/* Enable IDLE Interrupt */
|
||||
LL_LPUART_EnableIT_IDLE(LPUART1);
|
||||
|
||||
/* Enable RX Not Empty Interrupt */
|
||||
LL_LPUART_EnableIT_RXNE(LPUART1);
|
||||
|
||||
/* USER CODE END LPUART1_Init 2 */
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* Enable DMA controller clock
|
||||
* @brief TIM21 Initialization Function
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
static void MX_DMA_Init(void)
|
||||
static void MX_TIM21_Init(void)
|
||||
{
|
||||
|
||||
/* Init with LL driver */
|
||||
/* DMA controller clock enable */
|
||||
LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_DMA1);
|
||||
/* USER CODE BEGIN TIM21_Init 0 */
|
||||
|
||||
/* DMA interrupt init */
|
||||
/* DMA1_Channel2_3_IRQn interrupt configuration */
|
||||
NVIC_SetPriority(DMA1_Channel2_3_IRQn, 0);
|
||||
NVIC_EnableIRQ(DMA1_Channel2_3_IRQn);
|
||||
/* USER CODE END TIM21_Init 0 */
|
||||
|
||||
LL_TIM_InitTypeDef TIM_InitStruct = {0};
|
||||
|
||||
/* Peripheral clock enable */
|
||||
LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_TIM21);
|
||||
|
||||
/* TIM21 interrupt Init */
|
||||
NVIC_SetPriority(TIM21_IRQn, 0);
|
||||
NVIC_EnableIRQ(TIM21_IRQn);
|
||||
|
||||
/* USER CODE BEGIN TIM21_Init 1 */
|
||||
|
||||
/* USER CODE END TIM21_Init 1 */
|
||||
TIM_InitStruct.Prescaler = tim21_prescaler;
|
||||
TIM_InitStruct.CounterMode = LL_TIM_COUNTERMODE_UP;
|
||||
TIM_InitStruct.Autoreload = tim21_period;
|
||||
TIM_InitStruct.ClockDivision = LL_TIM_CLOCKDIVISION_DIV1;
|
||||
LL_TIM_Init(TIM21, &TIM_InitStruct);
|
||||
LL_TIM_EnableARRPreload(TIM21);
|
||||
LL_TIM_SetClockSource(TIM21, LL_TIM_CLOCKSOURCE_INTERNAL);
|
||||
LL_TIM_SetTriggerOutput(TIM21, LL_TIM_TRGO_RESET);
|
||||
LL_TIM_DisableMasterSlaveMode(TIM21);
|
||||
/* USER CODE BEGIN TIM21_Init 2 */
|
||||
|
||||
/* USER CODE END TIM21_Init 2 */
|
||||
|
||||
}
|
||||
|
||||
@ -357,6 +460,7 @@ static void MX_GPIO_Init(void)
|
||||
|
||||
/* GPIO Ports Clock Enable */
|
||||
LL_IOP_GRP1_EnableClock(LL_IOP_GRP1_PERIPH_GPIOA);
|
||||
LL_IOP_GRP1_EnableClock(LL_IOP_GRP1_PERIPH_GPIOB);
|
||||
|
||||
/**/
|
||||
LL_GPIO_SetOutputPin(LED_B_GPIO_Port, LED_B_Pin);
|
||||
|
||||
@ -176,7 +176,7 @@ int8_t sps30_read_firmware_version ( uint8_t * fw_ver_hi, uint8_t * fw_ver_lo )
|
||||
}
|
||||
|
||||
|
||||
static uint8_t calculate_crc(uint8_t data[2])
|
||||
uint8_t calculate_crc(uint8_t data[2])
|
||||
{
|
||||
uint8_t crc = 0xFF;
|
||||
for(uint8_t i = 0; i < 2; i++) {
|
||||
|
||||
@ -42,12 +42,17 @@
|
||||
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* USER CODE BEGIN PV */
|
||||
uint8_t lpuart1_rx_message[255];
|
||||
uint8_t lpuart1_rx_message_index = 0;
|
||||
uint8_t lpuart1_rx_message_len = 0;
|
||||
uint8_t lpuart1_rx_done = 0;
|
||||
|
||||
uint8_t tim21_elapsed_period = 0;
|
||||
/* USER CODE END PV */
|
||||
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* USER CODE BEGIN PFP */
|
||||
|
||||
void LPUART1_CharReception_Callback( void );
|
||||
/* USER CODE END PFP */
|
||||
|
||||
/* Private user code ---------------------------------------------------------*/
|
||||
@ -141,20 +146,58 @@ void SysTick_Handler(void)
|
||||
/******************************************************************************/
|
||||
|
||||
/**
|
||||
* @brief This function handles DMA1 channel 2 and channel 3 interrupts.
|
||||
* @brief This function handles TIM21 global interrupt.
|
||||
*/
|
||||
void DMA1_Channel2_3_IRQHandler(void)
|
||||
void TIM21_IRQHandler(void)
|
||||
{
|
||||
/* USER CODE BEGIN DMA1_Channel2_3_IRQn 0 */
|
||||
/* USER CODE BEGIN TIM21_IRQn 0 */
|
||||
LL_TIM_ClearFlag_UPDATE(TIM21);
|
||||
tim21_elapsed_period = 1;
|
||||
|
||||
/* USER CODE END DMA1_Channel2_3_IRQn 0 */
|
||||
/* USER CODE END TIM21_IRQn 0 */
|
||||
/* USER CODE BEGIN TIM21_IRQn 1 */
|
||||
|
||||
/* USER CODE BEGIN DMA1_Channel2_3_IRQn 1 */
|
||||
/* USER CODE END TIM21_IRQn 1 */
|
||||
}
|
||||
|
||||
/* USER CODE END DMA1_Channel2_3_IRQn 1 */
|
||||
/**
|
||||
* @brief This function handles LPUART1 global interrupt / LPUART1 wake-up interrupt through EXTI line 28.
|
||||
*/
|
||||
void LPUART1_IRQHandler(void)
|
||||
{
|
||||
/* USER CODE BEGIN LPUART1_IRQn 0 */
|
||||
|
||||
|
||||
/* Check RXNE flag value in SR register */
|
||||
if(LL_LPUART_IsActiveFlag_RXNE(LPUART1) && LL_LPUART_IsEnabledIT_RXNE(LPUART1))
|
||||
{
|
||||
/* RXNE flag will be cleared by reading of DR register (done in call) */
|
||||
/* Call function in charge of handling Character reception */
|
||||
LPUART1_CharReception_Callback();
|
||||
}
|
||||
|
||||
/* USER CODE END LPUART1_IRQn 0 */
|
||||
/* USER CODE BEGIN LPUART1_IRQn 1 */
|
||||
/* If the IDLE flag is active */
|
||||
if (LL_LPUART_IsActiveFlag_IDLE(LPUART1) == 1)
|
||||
{
|
||||
/* Clear the IDLE flag */
|
||||
LL_LPUART_ClearFlag_IDLE(LPUART1);
|
||||
|
||||
/* Reset the buffer index */
|
||||
lpuart1_rx_message_len = lpuart1_rx_message_index + 1;
|
||||
lpuart1_rx_message_index = 0;
|
||||
lpuart1_rx_done = 1;
|
||||
}
|
||||
/* USER CODE END LPUART1_IRQn 1 */
|
||||
}
|
||||
|
||||
/* USER CODE BEGIN 1 */
|
||||
|
||||
void LPUART1_CharReception_Callback( void )
|
||||
{
|
||||
uint16_t lpuart1_rx_bit = LL_LPUART_ReceiveData9(LPUART1);
|
||||
lpuart1_rx_message[lpuart1_rx_message_index] = (uint8_t)lpuart1_rx_bit;
|
||||
lpuart1_rx_message_index++;
|
||||
}
|
||||
/* USER CODE END 1 */
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
||||
3289
fw/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h
Normal file
3289
fw/Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_tim.h
Normal file
File diff suppressed because it is too large
Load Diff
@ -223,7 +223,6 @@ __STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks)
|
||||
SysTick->LOAD = (uint32_t)((HCLKFrequency / Ticks) - 1UL); /* set reload register */
|
||||
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
|
||||
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
|
||||
SysTick_CTRL_TICKINT_Msk |
|
||||
SysTick_CTRL_ENABLE_Msk; /* Enable the Systick Timer */
|
||||
}
|
||||
|
||||
|
||||
847
fw/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c
Normal file
847
fw/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_tim.c
Normal file
@ -0,0 +1,847 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32l0xx_ll_tim.c
|
||||
* @author MCD Application Team
|
||||
* @brief TIM LL module driver.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
#if defined(USE_FULL_LL_DRIVER)
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32l0xx_ll_tim.h"
|
||||
#include "stm32l0xx_ll_bus.h"
|
||||
|
||||
#ifdef USE_FULL_ASSERT
|
||||
#include "stm32_assert.h"
|
||||
#else
|
||||
#define assert_param(expr) ((void)0U)
|
||||
#endif /* USE_FULL_ASSERT */
|
||||
|
||||
/** @addtogroup STM32L0xx_LL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined (TIM2) || defined (TIM3) || defined (TIM21) || defined (TIM22) || defined (TIM6) || defined (TIM7)
|
||||
|
||||
/** @addtogroup TIM_LL
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private types -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private constants ---------------------------------------------------------*/
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @addtogroup TIM_LL_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
#define IS_LL_TIM_COUNTERMODE(__VALUE__) (((__VALUE__) == LL_TIM_COUNTERMODE_UP) \
|
||||
|| ((__VALUE__) == LL_TIM_COUNTERMODE_DOWN) \
|
||||
|| ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP) \
|
||||
|| ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_DOWN) \
|
||||
|| ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP_DOWN))
|
||||
|
||||
#define IS_LL_TIM_CLOCKDIVISION(__VALUE__) (((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV1) \
|
||||
|| ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV2) \
|
||||
|| ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV4))
|
||||
|
||||
#define IS_LL_TIM_OCMODE(__VALUE__) (((__VALUE__) == LL_TIM_OCMODE_FROZEN) \
|
||||
|| ((__VALUE__) == LL_TIM_OCMODE_ACTIVE) \
|
||||
|| ((__VALUE__) == LL_TIM_OCMODE_INACTIVE) \
|
||||
|| ((__VALUE__) == LL_TIM_OCMODE_TOGGLE) \
|
||||
|| ((__VALUE__) == LL_TIM_OCMODE_FORCED_INACTIVE) \
|
||||
|| ((__VALUE__) == LL_TIM_OCMODE_FORCED_ACTIVE) \
|
||||
|| ((__VALUE__) == LL_TIM_OCMODE_PWM1) \
|
||||
|| ((__VALUE__) == LL_TIM_OCMODE_PWM2))
|
||||
|
||||
#define IS_LL_TIM_OCSTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCSTATE_DISABLE) \
|
||||
|| ((__VALUE__) == LL_TIM_OCSTATE_ENABLE))
|
||||
|
||||
#define IS_LL_TIM_OCPOLARITY(__VALUE__) (((__VALUE__) == LL_TIM_OCPOLARITY_HIGH) \
|
||||
|| ((__VALUE__) == LL_TIM_OCPOLARITY_LOW))
|
||||
|
||||
#define IS_LL_TIM_ACTIVEINPUT(__VALUE__) (((__VALUE__) == LL_TIM_ACTIVEINPUT_DIRECTTI) \
|
||||
|| ((__VALUE__) == LL_TIM_ACTIVEINPUT_INDIRECTTI) \
|
||||
|| ((__VALUE__) == LL_TIM_ACTIVEINPUT_TRC))
|
||||
|
||||
#define IS_LL_TIM_ICPSC(__VALUE__) (((__VALUE__) == LL_TIM_ICPSC_DIV1) \
|
||||
|| ((__VALUE__) == LL_TIM_ICPSC_DIV2) \
|
||||
|| ((__VALUE__) == LL_TIM_ICPSC_DIV4) \
|
||||
|| ((__VALUE__) == LL_TIM_ICPSC_DIV8))
|
||||
|
||||
#define IS_LL_TIM_IC_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_IC_FILTER_FDIV1) \
|
||||
|| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N2) \
|
||||
|| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N4) \
|
||||
|| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N8) \
|
||||
|| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N6) \
|
||||
|| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N8) \
|
||||
|| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N6) \
|
||||
|| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N8) \
|
||||
|| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N6) \
|
||||
|| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N8) \
|
||||
|| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N5) \
|
||||
|| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N6) \
|
||||
|| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N8) \
|
||||
|| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N5) \
|
||||
|| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N6) \
|
||||
|| ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N8))
|
||||
|
||||
#define IS_LL_TIM_IC_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
|
||||
|| ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING) \
|
||||
|| ((__VALUE__) == LL_TIM_IC_POLARITY_BOTHEDGE))
|
||||
|
||||
#define IS_LL_TIM_ENCODERMODE(__VALUE__) (((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI1) \
|
||||
|| ((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI2) \
|
||||
|| ((__VALUE__) == LL_TIM_ENCODERMODE_X4_TI12))
|
||||
|
||||
#define IS_LL_TIM_IC_POLARITY_ENCODER(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
|
||||
|| ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/** @defgroup TIM_LL_Private_Functions TIM Private Functions
|
||||
* @{
|
||||
*/
|
||||
static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
|
||||
static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
|
||||
static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
|
||||
static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
|
||||
static ErrorStatus IC1Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
|
||||
static ErrorStatus IC2Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
|
||||
static ErrorStatus IC3Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
|
||||
static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @addtogroup TIM_LL_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup TIM_LL_EF_Init
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Set TIMx registers to their reset values.
|
||||
* @param TIMx Timer instance
|
||||
* @retval An ErrorStatus enumeration value:
|
||||
* - SUCCESS: TIMx registers are de-initialized
|
||||
* - ERROR: invalid TIMx instance
|
||||
*/
|
||||
ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx)
|
||||
{
|
||||
ErrorStatus result = SUCCESS;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_TIM_INSTANCE(TIMx));
|
||||
|
||||
if (TIMx == TIM2)
|
||||
{
|
||||
LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM2);
|
||||
LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM2);
|
||||
}
|
||||
#if defined(TIM3)
|
||||
else if (TIMx == TIM3)
|
||||
{
|
||||
LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM3);
|
||||
LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM3);
|
||||
}
|
||||
#endif /* TIM3 */
|
||||
#if defined(TIM6)
|
||||
else if (TIMx == TIM6)
|
||||
{
|
||||
LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM6);
|
||||
LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM6);
|
||||
}
|
||||
#endif /* TIM6 */
|
||||
#if defined(TIM7)
|
||||
else if (TIMx == TIM7)
|
||||
{
|
||||
LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM7);
|
||||
LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM7);
|
||||
}
|
||||
#endif /* TIM7 */
|
||||
else if (TIMx == TIM21)
|
||||
{
|
||||
LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM21);
|
||||
LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM21);
|
||||
}
|
||||
#if defined(TIM22)
|
||||
else if (TIMx == TIM22)
|
||||
{
|
||||
LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM22);
|
||||
LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM22);
|
||||
}
|
||||
#endif /* TIM22 */
|
||||
else
|
||||
{
|
||||
result = ERROR;
|
||||
}
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the fields of the time base unit configuration data structure
|
||||
* to their default values.
|
||||
* @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (time base unit configuration data structure)
|
||||
* @retval None
|
||||
*/
|
||||
void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct)
|
||||
{
|
||||
/* Set the default configuration */
|
||||
TIM_InitStruct->Prescaler = (uint16_t)0x0000;
|
||||
TIM_InitStruct->CounterMode = LL_TIM_COUNTERMODE_UP;
|
||||
TIM_InitStruct->Autoreload = 0xFFFFFFFFU;
|
||||
TIM_InitStruct->ClockDivision = LL_TIM_CLOCKDIVISION_DIV1;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configure the TIMx time base unit.
|
||||
* @param TIMx Timer Instance
|
||||
* @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (TIMx time base unit configuration data structure)
|
||||
* @retval An ErrorStatus enumeration value:
|
||||
* - SUCCESS: TIMx registers are de-initialized
|
||||
* - ERROR: not applicable
|
||||
*/
|
||||
ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct)
|
||||
{
|
||||
uint32_t tmpcr1;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_TIM_INSTANCE(TIMx));
|
||||
assert_param(IS_LL_TIM_COUNTERMODE(TIM_InitStruct->CounterMode));
|
||||
assert_param(IS_LL_TIM_CLOCKDIVISION(TIM_InitStruct->ClockDivision));
|
||||
|
||||
tmpcr1 = LL_TIM_ReadReg(TIMx, CR1);
|
||||
|
||||
if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
|
||||
{
|
||||
/* Select the Counter Mode */
|
||||
MODIFY_REG(tmpcr1, (TIM_CR1_DIR | TIM_CR1_CMS), TIM_InitStruct->CounterMode);
|
||||
}
|
||||
|
||||
if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
|
||||
{
|
||||
/* Set the clock division */
|
||||
MODIFY_REG(tmpcr1, TIM_CR1_CKD, TIM_InitStruct->ClockDivision);
|
||||
}
|
||||
|
||||
/* Write to TIMx CR1 */
|
||||
LL_TIM_WriteReg(TIMx, CR1, tmpcr1);
|
||||
|
||||
/* Set the Autoreload value */
|
||||
LL_TIM_SetAutoReload(TIMx, TIM_InitStruct->Autoreload);
|
||||
|
||||
/* Set the Prescaler value */
|
||||
LL_TIM_SetPrescaler(TIMx, TIM_InitStruct->Prescaler);
|
||||
/* Generate an update event to reload the Prescaler
|
||||
and the repetition counter value (if applicable) immediately */
|
||||
LL_TIM_GenerateEvent_UPDATE(TIMx);
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the fields of the TIMx output channel configuration data
|
||||
* structure to their default values.
|
||||
* @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (the output channel configuration data structure)
|
||||
* @retval None
|
||||
*/
|
||||
void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
|
||||
{
|
||||
/* Set the default configuration */
|
||||
TIM_OC_InitStruct->OCMode = LL_TIM_OCMODE_FROZEN;
|
||||
TIM_OC_InitStruct->OCState = LL_TIM_OCSTATE_DISABLE;
|
||||
TIM_OC_InitStruct->CompareValue = 0x00000000U;
|
||||
TIM_OC_InitStruct->OCPolarity = LL_TIM_OCPOLARITY_HIGH;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configure the TIMx output channel.
|
||||
* @param TIMx Timer Instance
|
||||
* @param Channel This parameter can be one of the following values:
|
||||
* @arg @ref LL_TIM_CHANNEL_CH1
|
||||
* @arg @ref LL_TIM_CHANNEL_CH2
|
||||
* @arg @ref LL_TIM_CHANNEL_CH3
|
||||
* @arg @ref LL_TIM_CHANNEL_CH4
|
||||
* @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (TIMx output channel configuration data structure)
|
||||
* @retval An ErrorStatus enumeration value:
|
||||
* - SUCCESS: TIMx output channel is initialized
|
||||
* - ERROR: TIMx output channel is not initialized
|
||||
*/
|
||||
ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
|
||||
{
|
||||
ErrorStatus result = ERROR;
|
||||
|
||||
switch (Channel)
|
||||
{
|
||||
case LL_TIM_CHANNEL_CH1:
|
||||
result = OC1Config(TIMx, TIM_OC_InitStruct);
|
||||
break;
|
||||
case LL_TIM_CHANNEL_CH2:
|
||||
result = OC2Config(TIMx, TIM_OC_InitStruct);
|
||||
break;
|
||||
case LL_TIM_CHANNEL_CH3:
|
||||
result = OC3Config(TIMx, TIM_OC_InitStruct);
|
||||
break;
|
||||
case LL_TIM_CHANNEL_CH4:
|
||||
result = OC4Config(TIMx, TIM_OC_InitStruct);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the fields of the TIMx input channel configuration data
|
||||
* structure to their default values.
|
||||
* @param TIM_ICInitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (the input channel configuration data structure)
|
||||
* @retval None
|
||||
*/
|
||||
void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
|
||||
{
|
||||
/* Set the default configuration */
|
||||
TIM_ICInitStruct->ICPolarity = LL_TIM_IC_POLARITY_RISING;
|
||||
TIM_ICInitStruct->ICActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
|
||||
TIM_ICInitStruct->ICPrescaler = LL_TIM_ICPSC_DIV1;
|
||||
TIM_ICInitStruct->ICFilter = LL_TIM_IC_FILTER_FDIV1;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configure the TIMx input channel.
|
||||
* @param TIMx Timer Instance
|
||||
* @param Channel This parameter can be one of the following values:
|
||||
* @arg @ref LL_TIM_CHANNEL_CH1
|
||||
* @arg @ref LL_TIM_CHANNEL_CH2
|
||||
* @arg @ref LL_TIM_CHANNEL_CH3
|
||||
* @arg @ref LL_TIM_CHANNEL_CH4
|
||||
* @param TIM_IC_InitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (TIMx input channel configuration data structure)
|
||||
* @retval An ErrorStatus enumeration value:
|
||||
* - SUCCESS: TIMx output channel is initialized
|
||||
* - ERROR: TIMx output channel is not initialized
|
||||
*/
|
||||
ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct)
|
||||
{
|
||||
ErrorStatus result = ERROR;
|
||||
|
||||
switch (Channel)
|
||||
{
|
||||
case LL_TIM_CHANNEL_CH1:
|
||||
result = IC1Config(TIMx, TIM_IC_InitStruct);
|
||||
break;
|
||||
case LL_TIM_CHANNEL_CH2:
|
||||
result = IC2Config(TIMx, TIM_IC_InitStruct);
|
||||
break;
|
||||
case LL_TIM_CHANNEL_CH3:
|
||||
result = IC3Config(TIMx, TIM_IC_InitStruct);
|
||||
break;
|
||||
case LL_TIM_CHANNEL_CH4:
|
||||
result = IC4Config(TIMx, TIM_IC_InitStruct);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Fills each TIM_EncoderInitStruct field with its default value
|
||||
* @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (encoder interface configuration data structure)
|
||||
* @retval None
|
||||
*/
|
||||
void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
|
||||
{
|
||||
/* Set the default configuration */
|
||||
TIM_EncoderInitStruct->EncoderMode = LL_TIM_ENCODERMODE_X2_TI1;
|
||||
TIM_EncoderInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING;
|
||||
TIM_EncoderInitStruct->IC1ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
|
||||
TIM_EncoderInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1;
|
||||
TIM_EncoderInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1;
|
||||
TIM_EncoderInitStruct->IC2Polarity = LL_TIM_IC_POLARITY_RISING;
|
||||
TIM_EncoderInitStruct->IC2ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
|
||||
TIM_EncoderInitStruct->IC2Prescaler = LL_TIM_ICPSC_DIV1;
|
||||
TIM_EncoderInitStruct->IC2Filter = LL_TIM_IC_FILTER_FDIV1;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configure the encoder interface of the timer instance.
|
||||
* @param TIMx Timer Instance
|
||||
* @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (TIMx encoder interface configuration data structure)
|
||||
* @retval An ErrorStatus enumeration value:
|
||||
* - SUCCESS: TIMx registers are de-initialized
|
||||
* - ERROR: not applicable
|
||||
*/
|
||||
ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
|
||||
{
|
||||
uint32_t tmpccmr1;
|
||||
uint32_t tmpccer;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx));
|
||||
assert_param(IS_LL_TIM_ENCODERMODE(TIM_EncoderInitStruct->EncoderMode));
|
||||
assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC1Polarity));
|
||||
assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC1ActiveInput));
|
||||
assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC1Prescaler));
|
||||
assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC1Filter));
|
||||
assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC2Polarity));
|
||||
assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC2ActiveInput));
|
||||
assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC2Prescaler));
|
||||
assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC2Filter));
|
||||
|
||||
/* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
|
||||
TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
|
||||
|
||||
/* Get the TIMx CCMR1 register value */
|
||||
tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
|
||||
|
||||
/* Get the TIMx CCER register value */
|
||||
tmpccer = LL_TIM_ReadReg(TIMx, CCER);
|
||||
|
||||
/* Configure TI1 */
|
||||
tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC);
|
||||
tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1ActiveInput >> 16U);
|
||||
tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Filter >> 16U);
|
||||
tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Prescaler >> 16U);
|
||||
|
||||
/* Configure TI2 */
|
||||
tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC);
|
||||
tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2ActiveInput >> 8U);
|
||||
tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Filter >> 8U);
|
||||
tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Prescaler >> 8U);
|
||||
|
||||
/* Set TI1 and TI2 polarity and enable TI1 and TI2 */
|
||||
tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
|
||||
tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC1Polarity);
|
||||
tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC2Polarity << 4U);
|
||||
tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
|
||||
|
||||
/* Set encoder mode */
|
||||
LL_TIM_SetEncoderMode(TIMx, TIM_EncoderInitStruct->EncoderMode);
|
||||
|
||||
/* Write to TIMx CCMR1 */
|
||||
LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
|
||||
|
||||
/* Write to TIMx CCER */
|
||||
LL_TIM_WriteReg(TIMx, CCER, tmpccer);
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup TIM_LL_Private_Functions TIM Private Functions
|
||||
* @brief Private functions
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @brief Configure the TIMx output channel 1.
|
||||
* @param TIMx Timer Instance
|
||||
* @param TIM_OCInitStruct pointer to the the TIMx output channel 1 configuration data structure
|
||||
* @retval An ErrorStatus enumeration value:
|
||||
* - SUCCESS: TIMx registers are de-initialized
|
||||
* - ERROR: not applicable
|
||||
*/
|
||||
static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
|
||||
{
|
||||
uint32_t tmpccmr1;
|
||||
uint32_t tmpccer;
|
||||
uint32_t tmpcr2;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_TIM_CC1_INSTANCE(TIMx));
|
||||
assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
|
||||
assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
|
||||
assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
|
||||
|
||||
/* Disable the Channel 1: Reset the CC1E Bit */
|
||||
CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E);
|
||||
|
||||
/* Get the TIMx CCER register value */
|
||||
tmpccer = LL_TIM_ReadReg(TIMx, CCER);
|
||||
|
||||
/* Get the TIMx CR2 register value */
|
||||
tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
|
||||
|
||||
/* Get the TIMx CCMR1 register value */
|
||||
tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
|
||||
|
||||
/* Reset Capture/Compare selection Bits */
|
||||
CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC1S);
|
||||
|
||||
/* Set the Output Compare Mode */
|
||||
MODIFY_REG(tmpccmr1, TIM_CCMR1_OC1M, TIM_OCInitStruct->OCMode);
|
||||
|
||||
/* Set the Output Compare Polarity */
|
||||
MODIFY_REG(tmpccer, TIM_CCER_CC1P, TIM_OCInitStruct->OCPolarity);
|
||||
|
||||
/* Set the Output State */
|
||||
MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState);
|
||||
|
||||
/* Write to TIMx CR2 */
|
||||
LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
|
||||
|
||||
/* Write to TIMx CCMR1 */
|
||||
LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
|
||||
|
||||
/* Set the Capture Compare Register value */
|
||||
LL_TIM_OC_SetCompareCH1(TIMx, TIM_OCInitStruct->CompareValue);
|
||||
|
||||
/* Write to TIMx CCER */
|
||||
LL_TIM_WriteReg(TIMx, CCER, tmpccer);
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configure the TIMx output channel 2.
|
||||
* @param TIMx Timer Instance
|
||||
* @param TIM_OCInitStruct pointer to the the TIMx output channel 2 configuration data structure
|
||||
* @retval An ErrorStatus enumeration value:
|
||||
* - SUCCESS: TIMx registers are de-initialized
|
||||
* - ERROR: not applicable
|
||||
*/
|
||||
static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
|
||||
{
|
||||
uint32_t tmpccmr1;
|
||||
uint32_t tmpccer;
|
||||
uint32_t tmpcr2;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_TIM_CC2_INSTANCE(TIMx));
|
||||
assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
|
||||
assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
|
||||
assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
|
||||
|
||||
/* Disable the Channel 2: Reset the CC2E Bit */
|
||||
CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E);
|
||||
|
||||
/* Get the TIMx CCER register value */
|
||||
tmpccer = LL_TIM_ReadReg(TIMx, CCER);
|
||||
|
||||
/* Get the TIMx CR2 register value */
|
||||
tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
|
||||
|
||||
/* Get the TIMx CCMR1 register value */
|
||||
tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
|
||||
|
||||
/* Reset Capture/Compare selection Bits */
|
||||
CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC2S);
|
||||
|
||||
/* Select the Output Compare Mode */
|
||||
MODIFY_REG(tmpccmr1, TIM_CCMR1_OC2M, TIM_OCInitStruct->OCMode << 8U);
|
||||
|
||||
/* Set the Output Compare Polarity */
|
||||
MODIFY_REG(tmpccer, TIM_CCER_CC2P, TIM_OCInitStruct->OCPolarity << 4U);
|
||||
|
||||
/* Set the Output State */
|
||||
MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U);
|
||||
|
||||
/* Write to TIMx CR2 */
|
||||
LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
|
||||
|
||||
/* Write to TIMx CCMR1 */
|
||||
LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
|
||||
|
||||
/* Set the Capture Compare Register value */
|
||||
LL_TIM_OC_SetCompareCH2(TIMx, TIM_OCInitStruct->CompareValue);
|
||||
|
||||
/* Write to TIMx CCER */
|
||||
LL_TIM_WriteReg(TIMx, CCER, tmpccer);
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configure the TIMx output channel 3.
|
||||
* @param TIMx Timer Instance
|
||||
* @param TIM_OCInitStruct pointer to the the TIMx output channel 3 configuration data structure
|
||||
* @retval An ErrorStatus enumeration value:
|
||||
* - SUCCESS: TIMx registers are de-initialized
|
||||
* - ERROR: not applicable
|
||||
*/
|
||||
static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
|
||||
{
|
||||
uint32_t tmpccmr2;
|
||||
uint32_t tmpccer;
|
||||
uint32_t tmpcr2;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_TIM_CC3_INSTANCE(TIMx));
|
||||
assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
|
||||
assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
|
||||
assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
|
||||
|
||||
/* Disable the Channel 3: Reset the CC3E Bit */
|
||||
CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E);
|
||||
|
||||
/* Get the TIMx CCER register value */
|
||||
tmpccer = LL_TIM_ReadReg(TIMx, CCER);
|
||||
|
||||
/* Get the TIMx CR2 register value */
|
||||
tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
|
||||
|
||||
/* Get the TIMx CCMR2 register value */
|
||||
tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
|
||||
|
||||
/* Reset Capture/Compare selection Bits */
|
||||
CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S);
|
||||
|
||||
/* Select the Output Compare Mode */
|
||||
MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode);
|
||||
|
||||
/* Set the Output Compare Polarity */
|
||||
MODIFY_REG(tmpccer, TIM_CCER_CC3P, TIM_OCInitStruct->OCPolarity << 8U);
|
||||
|
||||
/* Set the Output State */
|
||||
MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U);
|
||||
|
||||
/* Write to TIMx CR2 */
|
||||
LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
|
||||
|
||||
/* Write to TIMx CCMR2 */
|
||||
LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
|
||||
|
||||
/* Set the Capture Compare Register value */
|
||||
LL_TIM_OC_SetCompareCH3(TIMx, TIM_OCInitStruct->CompareValue);
|
||||
|
||||
/* Write to TIMx CCER */
|
||||
LL_TIM_WriteReg(TIMx, CCER, tmpccer);
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configure the TIMx output channel 4.
|
||||
* @param TIMx Timer Instance
|
||||
* @param TIM_OCInitStruct pointer to the the TIMx output channel 4 configuration data structure
|
||||
* @retval An ErrorStatus enumeration value:
|
||||
* - SUCCESS: TIMx registers are de-initialized
|
||||
* - ERROR: not applicable
|
||||
*/
|
||||
static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
|
||||
{
|
||||
uint32_t tmpccmr2;
|
||||
uint32_t tmpccer;
|
||||
uint32_t tmpcr2;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_TIM_CC4_INSTANCE(TIMx));
|
||||
assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
|
||||
assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
|
||||
assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
|
||||
|
||||
/* Disable the Channel 4: Reset the CC4E Bit */
|
||||
CLEAR_BIT(TIMx->CCER, TIM_CCER_CC4E);
|
||||
|
||||
/* Get the TIMx CCER register value */
|
||||
tmpccer = LL_TIM_ReadReg(TIMx, CCER);
|
||||
|
||||
/* Get the TIMx CR2 register value */
|
||||
tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
|
||||
|
||||
/* Get the TIMx CCMR2 register value */
|
||||
tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
|
||||
|
||||
/* Reset Capture/Compare selection Bits */
|
||||
CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S);
|
||||
|
||||
/* Select the Output Compare Mode */
|
||||
MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U);
|
||||
|
||||
/* Set the Output Compare Polarity */
|
||||
MODIFY_REG(tmpccer, TIM_CCER_CC4P, TIM_OCInitStruct->OCPolarity << 12U);
|
||||
|
||||
/* Set the Output State */
|
||||
MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U);
|
||||
|
||||
/* Write to TIMx CR2 */
|
||||
LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
|
||||
|
||||
/* Write to TIMx CCMR2 */
|
||||
LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
|
||||
|
||||
/* Set the Capture Compare Register value */
|
||||
LL_TIM_OC_SetCompareCH4(TIMx, TIM_OCInitStruct->CompareValue);
|
||||
|
||||
/* Write to TIMx CCER */
|
||||
LL_TIM_WriteReg(TIMx, CCER, tmpccer);
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Configure the TIMx input channel 1.
|
||||
* @param TIMx Timer Instance
|
||||
* @param TIM_ICInitStruct pointer to the the TIMx input channel 1 configuration data structure
|
||||
* @retval An ErrorStatus enumeration value:
|
||||
* - SUCCESS: TIMx registers are de-initialized
|
||||
* - ERROR: not applicable
|
||||
*/
|
||||
static ErrorStatus IC1Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_TIM_CC1_INSTANCE(TIMx));
|
||||
assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
|
||||
assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
|
||||
assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
|
||||
assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
|
||||
|
||||
/* Disable the Channel 1: Reset the CC1E Bit */
|
||||
TIMx->CCER &= (uint32_t)~TIM_CCER_CC1E;
|
||||
|
||||
/* Select the Input and set the filter and the prescaler value */
|
||||
MODIFY_REG(TIMx->CCMR1,
|
||||
(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC),
|
||||
(TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
|
||||
|
||||
/* Select the Polarity and set the CC1E Bit */
|
||||
MODIFY_REG(TIMx->CCER,
|
||||
(TIM_CCER_CC1P | TIM_CCER_CC1NP),
|
||||
(TIM_ICInitStruct->ICPolarity | TIM_CCER_CC1E));
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configure the TIMx input channel 2.
|
||||
* @param TIMx Timer Instance
|
||||
* @param TIM_ICInitStruct pointer to the the TIMx input channel 2 configuration data structure
|
||||
* @retval An ErrorStatus enumeration value:
|
||||
* - SUCCESS: TIMx registers are de-initialized
|
||||
* - ERROR: not applicable
|
||||
*/
|
||||
static ErrorStatus IC2Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_TIM_CC2_INSTANCE(TIMx));
|
||||
assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
|
||||
assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
|
||||
assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
|
||||
assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
|
||||
|
||||
/* Disable the Channel 2: Reset the CC2E Bit */
|
||||
TIMx->CCER &= (uint32_t)~TIM_CCER_CC2E;
|
||||
|
||||
/* Select the Input and set the filter and the prescaler value */
|
||||
MODIFY_REG(TIMx->CCMR1,
|
||||
(TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC),
|
||||
(TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
|
||||
|
||||
/* Select the Polarity and set the CC2E Bit */
|
||||
MODIFY_REG(TIMx->CCER,
|
||||
(TIM_CCER_CC2P | TIM_CCER_CC2NP),
|
||||
((TIM_ICInitStruct->ICPolarity << 4U) | TIM_CCER_CC2E));
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configure the TIMx input channel 3.
|
||||
* @param TIMx Timer Instance
|
||||
* @param TIM_ICInitStruct pointer to the the TIMx input channel 3 configuration data structure
|
||||
* @retval An ErrorStatus enumeration value:
|
||||
* - SUCCESS: TIMx registers are de-initialized
|
||||
* - ERROR: not applicable
|
||||
*/
|
||||
static ErrorStatus IC3Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_TIM_CC3_INSTANCE(TIMx));
|
||||
assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
|
||||
assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
|
||||
assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
|
||||
assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
|
||||
|
||||
/* Disable the Channel 3: Reset the CC3E Bit */
|
||||
TIMx->CCER &= (uint32_t)~TIM_CCER_CC3E;
|
||||
|
||||
/* Select the Input and set the filter and the prescaler value */
|
||||
MODIFY_REG(TIMx->CCMR2,
|
||||
(TIM_CCMR2_CC3S | TIM_CCMR2_IC3F | TIM_CCMR2_IC3PSC),
|
||||
(TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
|
||||
|
||||
/* Select the Polarity and set the CC3E Bit */
|
||||
MODIFY_REG(TIMx->CCER,
|
||||
(TIM_CCER_CC3P | TIM_CCER_CC3NP),
|
||||
((TIM_ICInitStruct->ICPolarity << 8U) | TIM_CCER_CC3E));
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configure the TIMx input channel 4.
|
||||
* @param TIMx Timer Instance
|
||||
* @param TIM_ICInitStruct pointer to the the TIMx input channel 4 configuration data structure
|
||||
* @retval An ErrorStatus enumeration value:
|
||||
* - SUCCESS: TIMx registers are de-initialized
|
||||
* - ERROR: not applicable
|
||||
*/
|
||||
static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_TIM_CC4_INSTANCE(TIMx));
|
||||
assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
|
||||
assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
|
||||
assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
|
||||
assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
|
||||
|
||||
/* Disable the Channel 4: Reset the CC4E Bit */
|
||||
TIMx->CCER &= (uint32_t)~TIM_CCER_CC4E;
|
||||
|
||||
/* Select the Input and set the filter and the prescaler value */
|
||||
MODIFY_REG(TIMx->CCMR2,
|
||||
(TIM_CCMR2_CC4S | TIM_CCMR2_IC4F | TIM_CCMR2_IC4PSC),
|
||||
(TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
|
||||
|
||||
/* Select the Polarity and set the CC2E Bit */
|
||||
MODIFY_REG(TIMx->CCER,
|
||||
(TIM_CCER_CC4P | TIM_CCER_CC4NP),
|
||||
((TIM_ICInitStruct->ICPolarity << 12U) | TIM_CCER_CC4E));
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* TIM1 || TIM3 || TIM21 || TIM22 || TIM6 || TIM7 */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* USE_FULL_LL_DRIVER */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
@ -8,110 +8,119 @@ ProjectManager.ProjectFileName=iaq_wired_sensor.ioc
|
||||
ProjectManager.KeepUserCode=true
|
||||
PA10.Mode=I2C
|
||||
Mcu.UserName=STM32L011F4Ux
|
||||
Mcu.PinsNb=10
|
||||
Mcu.PinsNb=12
|
||||
ProjectManager.NoMain=false
|
||||
TIM21.IPParameters=Prescaler,Period,AutoReloadPreload,ClockDivision
|
||||
PA0-CK_IN.Mode=Asynchronous
|
||||
RCC.LPUARTFreq_Value=2097000
|
||||
RCC.PLLCLKFreq_Value=24000000
|
||||
ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-LL-true,2-MX_DMA_Init-DMA-false-LL-true,3-SystemClock_Config-RCC-false-LL-false,4-MX_I2C1_Init-I2C1-false-LL-true,5-MX_LPUART1_UART_Init-LPUART1-false-LL-true
|
||||
Dma.LPUART1_RX.0.MemDataAlignment=DMA_MDATAALIGN_BYTE
|
||||
RCC.LPUARTFreq_Value=12000000
|
||||
RCC.PLLCLKFreq_Value=12000000
|
||||
ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-LL-true,2-SystemClock_Config-RCC-false-LL-false,3-MX_I2C1_Init-I2C1-false-LL-true,4-MX_LPUART1_UART_Init-LPUART1-false-LL-true,5-MX_TIM21_Init-TIM21-false-LL-true
|
||||
RCC.RTCFreq_Value=37000
|
||||
LPUART1.WordLength=UART_WORDLENGTH_8B
|
||||
TIM21.ClockDivision=TIM_CLOCKDIVISION_DIV1
|
||||
LPUART1.WordLength=UART_WORDLENGTH_9B
|
||||
ProjectManager.DefaultFWLocation=true
|
||||
PA6.GPIO_Label=LED_G
|
||||
PA6.PinState=GPIO_PIN_SET
|
||||
RCC.USART2Freq_Value=2097000
|
||||
Dma.LPUART1_RX.0.Direction=DMA_PERIPH_TO_MEMORY
|
||||
Dma.LPUART1_RX.0.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority
|
||||
PA6.GPIO_Label=LED_G
|
||||
RCC.USART2Freq_Value=12000000
|
||||
NVIC.SVC_IRQn=true\:0\:0\:false\:false\:true\:false\:false
|
||||
ProjectManager.DeletePrevious=true
|
||||
RCC.TimerFreq_Value=12000000
|
||||
PA5.PinState=GPIO_PIN_SET
|
||||
Dma.LPUART1_RX.0.Instance=DMA1_Channel3
|
||||
LPUART1.IPParameters=BaudRate,SwapParam,OneBitSampling,WordLength
|
||||
LPUART1.IPParameters=BaudRate,SwapParam,OneBitSampling,WordLength,Parity
|
||||
PinOutPanel.RotationAngle=0
|
||||
RCC.FamilyName=M
|
||||
RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
|
||||
ProjectManager.StackSize=0x400
|
||||
Dma.LPUART1_RX.0.PeriphInc=DMA_PINC_DISABLE
|
||||
RCC.WatchDogFreq_Value=37000
|
||||
PA13.Signal=SYS_SWDIO
|
||||
Mcu.IP4=RCC
|
||||
Mcu.IP4=SYS
|
||||
RCC.HSI16_VALUE=16000000
|
||||
Mcu.IP5=SYS
|
||||
Mcu.IP2=LPUART1
|
||||
Mcu.IP3=NVIC
|
||||
RCC.FCLKCortexFreq_Value=12000000
|
||||
Mcu.IP5=TIM21
|
||||
I2C1.IPParameters=Timing
|
||||
Mcu.IP2=NVIC
|
||||
Mcu.IP3=RCC
|
||||
LPUART1.OneBitSampling=UART_ONE_BIT_SAMPLE_ENABLE
|
||||
Mcu.IP0=DMA
|
||||
Mcu.IP0=I2C1
|
||||
PA9.Mode=I2C
|
||||
Mcu.IP1=I2C1
|
||||
Mcu.IP1=LPUART1
|
||||
TIM21.Period=tim21_period
|
||||
RCC.PLLDIV=RCC_PLLDIV_4
|
||||
Mcu.UserConstants=
|
||||
PA7.PinState=GPIO_PIN_SET
|
||||
ProjectManager.TargetToolchain=STM32CubeIDE
|
||||
Mcu.ThirdPartyNb=0
|
||||
NVIC.LPUART1_IRQn=true\:0\:0\:false\:false\:true\:true\:true
|
||||
RCC.HCLKFreq_Value=12000000
|
||||
Mcu.IPNb=6
|
||||
ProjectManager.PreviousToolchain=
|
||||
RCC.APB2TimFreq_Value=2097000
|
||||
RCC.APB2TimFreq_Value=12000000
|
||||
PA9.Signal=I2C1_SCL
|
||||
Mcu.Pin6=PA10
|
||||
Mcu.Pin7=PA13
|
||||
I2C1.Timing=0x40000A0B
|
||||
LPUART1.Parity=UART_PARITY_EVEN
|
||||
Mcu.Pin6=PA9
|
||||
Mcu.Pin7=PA10
|
||||
ProjectManager.RegisterCallBack=
|
||||
Mcu.Pin8=PA14
|
||||
Mcu.Pin9=VP_SYS_VS_Systick
|
||||
Mcu.Pin8=PA13
|
||||
Mcu.Pin9=PA14
|
||||
PA0-CK_IN.GPIO_PuPd=GPIO_PULLUP
|
||||
RCC.LSE_VALUE=32768
|
||||
PA1.GPIO_PuPd=GPIO_PULLUP
|
||||
PA1.Signal=LPUART1_TX
|
||||
RCC.AHBFreq_Value=2097000
|
||||
RCC.AHBFreq_Value=12000000
|
||||
Mcu.Pin0=PA0-CK_IN
|
||||
Mcu.Pin1=PA1
|
||||
GPIO.groupedBy=Group By Peripherals
|
||||
Mcu.Pin2=PA5
|
||||
Mcu.Pin3=PA6
|
||||
Mcu.Pin4=PA7
|
||||
Mcu.Pin5=PA9
|
||||
Dma.LPUART1_RX.0.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
|
||||
Mcu.Pin5=PB1
|
||||
PA5.Signal=GPIO_Output
|
||||
ProjectManager.ProjectBuild=false
|
||||
RCC.HSE_VALUE=8000000
|
||||
RCC.MCOPinFreq_Value=12000000
|
||||
board=custom
|
||||
RCC.VCOOutputFreq_Value=48000000
|
||||
Dma.LPUART1_RX.0.MemInc=DMA_MINC_ENABLE
|
||||
NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false\:true
|
||||
ProjectManager.LastFirmware=true
|
||||
ProjectManager.FirmwarePackage=STM32Cube FW_L0 V1.12.0
|
||||
PA0-CK_IN.Signal=LPUART1_RX
|
||||
MxDb.Version=DB.6.0.10
|
||||
RCC.APB2Freq_Value=2097000
|
||||
MxDb.Version=DB.6.0.21
|
||||
RCC.APB2Freq_Value=12000000
|
||||
PA1.Mode=Asynchronous
|
||||
PA1.GPIOParameters=GPIO_PuPd
|
||||
ProjectManager.BackupPrevious=false
|
||||
MxCube.Version=6.1.0
|
||||
RCC.I2C1Freq_Value=2097000
|
||||
MxCube.Version=6.2.1
|
||||
VP_TIM21_VS_ClockSourceINT.Mode=Internal
|
||||
RCC.I2C1Freq_Value=12000000
|
||||
PA14.Mode=Serial_Wire
|
||||
TIM21.AutoReloadPreload=TIM_AUTORELOAD_PRELOAD_ENABLE
|
||||
TIM21.Prescaler=tim21_prescaler
|
||||
File.Version=6
|
||||
VP_SYS_VS_Systick.Mode=SysTick
|
||||
TIM21.IPParametersWithoutCheck=Prescaler,Period
|
||||
PA9.Locked=true
|
||||
NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false
|
||||
Dma.LPUART1_RX.0.Priority=DMA_PRIORITY_MEDIUM
|
||||
NVIC.TIM21_IRQn=true\:0\:0\:false\:false\:true\:true\:true
|
||||
NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false
|
||||
PA13.Mode=Serial_Wire
|
||||
ProjectManager.FreePins=false
|
||||
RCC.IPParameters=AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,FamilyName,HSE_VALUE,HSI16_VALUE,HSI_VALUE,I2C1Freq_Value,LPTIMFreq_Value,LPUARTFreq_Value,LSE_VALUE,LSI_VALUE,MSI_VALUE,PLLCLKFreq_Value,PWRFreq_Value,RTCFreq_Value,RTCHSEDivFreq_Value,SYSCLKFreq_VALUE,TIMFreq_Value,USART2Freq_Value,VCOOutputFreq_Value,WatchDogFreq_Value
|
||||
RCC.IPParameters=AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI16_VALUE,HSI_VALUE,I2C1Freq_Value,LPTIMFreq_Value,LPUARTFreq_Value,LSE_VALUE,LSI_VALUE,MCOPinFreq_Value,MSI_VALUE,PLLCLKFreq_Value,PLLDIV,PWRFreq_Value,RTCFreq_Value,RTCHSEDivFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,TIMFreq_Value,TimerFreq_Value,USART2Freq_Value,VCOOutputFreq_Value,WatchDogFreq_Value
|
||||
ProjectManager.AskForMigrate=true
|
||||
Mcu.Name=STM32L011F(3-4)Ux
|
||||
Dma.RequestsNb=1
|
||||
ProjectManager.HalAssertFull=false
|
||||
LPUART1.BaudRate=115200
|
||||
RCC.RTCHSEDivFreq_Value=4000000
|
||||
ProjectManager.ProjectName=iaq_wired_sensor
|
||||
ProjectManager.UnderRoot=true
|
||||
ProjectManager.CoupleFile=false
|
||||
RCC.SYSCLKFreq_VALUE=2097000
|
||||
RCC.SYSCLKFreq_VALUE=12000000
|
||||
Mcu.Package=UFQFPN20
|
||||
PB1.Signal=LPUART1_DE
|
||||
PA6.Signal=GPIO_Output
|
||||
PA7.GPIO_Label=LED_R
|
||||
Dma.LPUART1_RX.0.Mode=DMA_CIRCULAR
|
||||
PA7.Locked=true
|
||||
PA5.Locked=true
|
||||
PA7.Locked=true
|
||||
LPUART1.SwapParam=UART_ADVFEATURE_SWAP_DISABLE
|
||||
PA5.GPIO_Label=LED_B
|
||||
NVIC.ForceEnableDMAVector=true
|
||||
@ -124,20 +133,22 @@ PA10.Signal=I2C1_SDA
|
||||
PA14.Signal=SYS_SWCLK
|
||||
ProjectManager.HeapSize=0x200
|
||||
NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false
|
||||
PB1.Mode=Hardware Flow Control (RS485)
|
||||
PA5.GPIOParameters=PinState,GPIO_Label
|
||||
ProjectManager.ComputerToolchain=false
|
||||
RCC.HSI_VALUE=16000000
|
||||
NVIC.DMA1_Channel2_3_IRQn=true\:0\:0\:false\:false\:true\:false\:true
|
||||
RCC.APB1TimFreq_Value=2097000
|
||||
RCC.PWRFreq_Value=2097000
|
||||
RCC.APB1Freq_Value=2097000
|
||||
Dma.Request0=LPUART1_RX
|
||||
Mcu.Pin11=VP_TIM21_VS_ClockSourceINT
|
||||
Mcu.Pin10=VP_SYS_VS_Systick
|
||||
RCC.APB1TimFreq_Value=12000000
|
||||
RCC.PWRFreq_Value=12000000
|
||||
RCC.APB1Freq_Value=12000000
|
||||
PA7.GPIOParameters=PinState,GPIO_Label
|
||||
ProjectManager.CustomerFirmwarePackage=
|
||||
ProjectManager.DeviceId=STM32L011F4Ux
|
||||
ProjectManager.LibraryCopy=1
|
||||
RCC.LPTIMFreq_Value=2097000
|
||||
RCC.LPTIMFreq_Value=12000000
|
||||
PA7.Signal=GPIO_Output
|
||||
RCC.TIMFreq_Value=2097000
|
||||
VP_TIM21_VS_ClockSourceINT.Signal=TIM21_VS_ClockSourceINT
|
||||
RCC.TIMFreq_Value=12000000
|
||||
PA6.Locked=true
|
||||
isbadioc=false
|
||||
|
||||
Loading…
Reference in New Issue
Block a user