diff --git a/PCB/_autosave-iaq_wired_sensor.sch b/PCB/_autosave-iaq_wired_sensor.sch
new file mode 100644
index 0000000..7f53a18
--- /dev/null
+++ b/PCB/_autosave-iaq_wired_sensor.sch
@@ -0,0 +1,1968 @@
+EESchema Schematic File Version 4
+EELAYER 30 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
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+F 3 "https://www.sensirion.com/fileadmin/user_upload/customers/sensirion/Dokumente/2_Humidity_Sensors/Datasheets/Sensirion_Humidity_Sensors_SHT4x_Datasheet.pdf" H 1250 6300 50 0001 C CNN
+F 4 "Sensirion AG" H 1250 5900 50 0001 C CNN "Manufacturer"
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+ 1 1250 6250
+ -1 0 0 -1
+$EndComp
+$Comp
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+$Comp
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+F 1 "GND" H 2905 1302 50 0000 C CNN
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+ 1 2900 1475
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+$EndComp
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+$EndComp
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+F 3 "https://product.tdk.com/info/en/catalog/datasheets/mlcc_commercial_soft_en.pdf?ref_disty=digikey" H 675 3150 50 0001 C CNN
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+F 13 "Kyocera International Inc. Electronic Components" H 1575 2750 50 0001 C CNN "Alt_Manufacturer"
+F 14 "CM05X5R105K35AH" H 1575 2650 50 0001 C CNN "Alt_Code"
+ 1 675 3150
+ 1 0 0 -1
+$EndComp
+$Comp
+L iaq_wired_sensor-rescue:C0402_1uF_35V_X5R-HD_Capacitors C12
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+F 3 "https://product.tdk.com/info/en/catalog/datasheets/mlcc_commercial_soft_en.pdf?ref_disty=digikey" H 1175 3150 50 0001 C CNN
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+F 7 "TDK Corporation" H 1175 2750 50 0001 C CNN "Manufacturer"
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+F 11 "3416060" H 1175 2350 50 0001 C CNN "Farnell"
+F 12 "X" H 1175 2250 50 0001 C CNN "TME"
+F 13 "Kyocera International Inc. Electronic Components" H 2075 2750 50 0001 C CNN "Alt_Manufacturer"
+F 14 "CM05X5R105K35AH" H 2075 2650 50 0001 C CNN "Alt_Code"
+ 1 1175 3150
+ 1 0 0 -1
+$EndComp
+Wire Notes Line
+ 3800 550 9550 550
+Text Notes 7050 3400 0 50 ~ 10
+I2C Voltage Level Conversion
+Text Notes 8200 3400 0 50 Italic 0
+(3V3 -> 5V)
+$Comp
+L iaq_wired_sensor-rescue:+3V3-HD_Power_Symbols #PWR026
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+F 1 "+3V3" H 7040 1798 50 0000 C CNN
+F 2 "" H 7025 1625 50 0001 C CNN
+F 3 "" H 7025 1625 50 0001 C CNN
+ 1 7025 1625
+ 1 0 0 -1
+$EndComp
+$Comp
+L iaq_wired_sensor-rescue:GND-HD_Power_Symbols #PWR027
+U 1 1 60270BBD
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+F 3 "" H 7025 1925 50 0001 C CNN
+ 1 7025 1925
+ 1 0 0 -1
+$EndComp
+$Comp
+L iaq_wired_sensor-rescue:C0402_100nF_50V_X7R-HD_Capacitors C33
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+F 3 "https://search.murata.co.jp/Ceramy/image/img/A01X/G101/ENG/GRM155R71H104KE14-01.pdf" H 7025 1775 50 0001 C CNN
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+ 1 7025 1775
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+$EndComp
+$Comp
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+ 1 6525 1625
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+$Comp
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+ 1 6525 1925
+ 1 0 0 -1
+$EndComp
+$Comp
+L iaq_wired_sensor-rescue:C0402_100nF_50V_X7R-HD_Capacitors C32
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+F 3 "https://search.murata.co.jp/Ceramy/image/img/A01X/G101/ENG/GRM155R71H104KE14-01.pdf" H 6525 1775 50 0001 C CNN
+F 4 "100nF" H 6640 1775 50 0000 L CNN "Capacitance"
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+F 13 "TDK Corporation" H 7425 1375 50 0001 C CNN "Alt_Manufacturer"
+F 14 "C1005X7R1H104K050BB" H 7425 1275 50 0001 C CNN "Alt_Code"
+ 1 6525 1775
+ 1 0 0 -1
+$EndComp
+$Comp
+L iaq_wired_sensor-rescue:GND-HD_Power_Symbols #PWR018
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+ 1 6025 1925
+ 1 0 0 -1
+$EndComp
+$Comp
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+U 1 1 6026C580
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+ 1 6025 1625
+ 1 0 0 -1
+$EndComp
+$Comp
+L iaq_wired_sensor-rescue:C0603_10uF_16V_X5R-HD_Capacitors C31
+U 1 1 6026BA20
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+F 3 "*" H 6025 1775 50 0001 C CNN
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+F 6 "X5R" H 6025 1775 50 0001 C CNN "Dielectric"
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+F 13 "Murata Electronics" H 6975 1375 50 0001 C CNN "Alt_Manufacturer"
+F 14 "GRM188R61C106MA73D" H 6975 1275 50 0001 C CNN "Alt_Code"
+ 1 6025 1775
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+Wire Notes Line
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+ 5300 6950 550 6950
+Wire Notes Line
+ 550 6950 550 5350
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+ 550 5350 5300 5350
+Text Notes 550 5350 0 50 ~ 10
+Sensors
+Text Notes 3800 550 0 50 ~ 10
+Microcontroller
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+Wire Notes Line
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+Wire Notes Line
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+Wire Notes Line
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+Wire Notes Line
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+Text Notes 7600 700 0 50 ~ 0
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+Text Notes 7600 1950 0 50 ~ 0
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diff --git a/fw/.settings/language.settings.xml b/fw/.settings/language.settings.xml
index 87c8372..3740b5b 100644
--- a/fw/.settings/language.settings.xml
+++ b/fw/.settings/language.settings.xml
@@ -1,27 +1,52 @@
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/fw/Core/Inc/sht4x.h b/fw/Core/Inc/sht4x.h
index 0e133f3..0bc88d4 100644
--- a/fw/Core/Inc/sht4x.h
+++ b/fw/Core/Inc/sht4x.h
@@ -47,8 +47,8 @@ typedef enum {
* Function prototypes
*/
-int sht4x_send_cmd(sht4x_cmd_t cmd);
-int sht4x_read_data(uint8_t *buffer, int len);
-int sht4x_measure(int *temperature, int *relative_humidity);
+int8_t sht4x_send_cmd(sht4x_cmd_t cmd);
+int8_t sht4x_read_data(uint8_t *buffer, int len);
+int8_t sht4x_measure(int *temperature, int *relative_humidity);
#endif /* INC_SHT4X_H_ */
diff --git a/fw/Core/Src/main.c b/fw/Core/Src/main.c
index 2b27a57..40fbdbf 100644
--- a/fw/Core/Src/main.c
+++ b/fw/Core/Src/main.c
@@ -112,15 +112,20 @@ int main(void)
i2c_context_t i2c_context;
i2c_context.i2c = I2C1;
i2c_init(&i2c_context);
+
+
/* USER CODE END 2 */
/* Infinite loop */
/* USER CODE BEGIN WHILE */
- int T, RH;
- sht4x_measure(&T, &RH);
while (1)
{
/* USER CODE END WHILE */
+
+ int T, RH;
+ sht4x_measure(&T, &RH);
+
+ LL_mDelay(1000);
/* USER CODE BEGIN 3 */
}
/* USER CODE END 3 */
diff --git a/fw/Core/Src/sht4x.c b/fw/Core/Src/sht4x.c
index 50521da..1034402 100644
--- a/fw/Core/Src/sht4x.c
+++ b/fw/Core/Src/sht4x.c
@@ -7,30 +7,30 @@
#include "sht4x.h"
-int sht4x_send_cmd(sht4x_cmd_t cmd)
+int8_t sht4x_send_cmd(sht4x_cmd_t cmd)
{
}
-int sht4x_read_data(uint8_t *buffer, int len)
+int8_t sht4x_read_data(uint8_t *buffer, int len)
{
}
-int sht4x_measure(int *temperature, int *relative_humidity)
+int8_t sht4x_measure(int *temperature, int *relative_humidity)
{
uint8_t buffer[32];
int result;
// start measurement
buffer[0] = START_MEAS_HIGH_PRECISION;
- result = i2c_transmit(SHT4X_I2C_ADDRESS, buffer, 1);
+ result = i2c_transmit(SHT4X_I2C_ADDRESS<<1, buffer, 1);
if (result != I2C_OK) {
return SHT4X_ERROR;
}
LL_mDelay(100); // 10 ms should be enough
// read out
- result = i2c_receive(SHT4X_I2C_ADDRESS, buffer, 6);
+ result = i2c_receive(SHT4X_I2C_ADDRESS<<1, buffer, 6);
if (result != I2C_OK) {
return SHT4X_ERROR;
}
diff --git a/fw/Debug/Core/Src/i2c.d b/fw/Debug/Core/Src/i2c.d
new file mode 100644
index 0000000..dfdd36f
--- /dev/null
+++ b/fw/Debug/Core/Src/i2c.d
@@ -0,0 +1,27 @@
+Core/Src/i2c.o: ../Core/Src/i2c.c ../Core/Inc/i2c.h \
+ ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h \
+ ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l011xx.h \
+ ../Drivers/CMSIS/Include/core_cm0plus.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h
+
+../Core/Inc/i2c.h:
+
+../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h:
+
+../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h:
+
+../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l011xx.h:
+
+../Drivers/CMSIS/Include/core_cm0plus.h:
+
+../Drivers/CMSIS/Include/cmsis_version.h:
+
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+
+../Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h:
diff --git a/fw/Debug/Core/Src/i2c.o b/fw/Debug/Core/Src/i2c.o
new file mode 100644
index 0000000..c3b60a7
Binary files /dev/null and b/fw/Debug/Core/Src/i2c.o differ
diff --git a/fw/Debug/Core/Src/i2c.su b/fw/Debug/Core/Src/i2c.su
new file mode 100644
index 0000000..4085855
--- /dev/null
+++ b/fw/Debug/Core/Src/i2c.su
@@ -0,0 +1,3 @@
+i2c.c:12:5:i2c_init 0 static
+i2c.c:21:5:i2c_transmit 16 static
+i2c.c:47:5:i2c_receive 20 static
diff --git a/fw/Debug/Core/Src/led.d b/fw/Debug/Core/Src/led.d
new file mode 100644
index 0000000..db75ca4
--- /dev/null
+++ b/fw/Debug/Core/Src/led.d
@@ -0,0 +1,27 @@
+Core/Src/led.o: ../Core/Src/led.c ../Core/Inc/led.h \
+ ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h \
+ ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l011xx.h \
+ ../Drivers/CMSIS/Include/core_cm0plus.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h
+
+../Core/Inc/led.h:
+
+../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h:
+
+../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h:
+
+../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l011xx.h:
+
+../Drivers/CMSIS/Include/core_cm0plus.h:
+
+../Drivers/CMSIS/Include/cmsis_version.h:
+
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+
+../Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h:
diff --git a/fw/Debug/Core/Src/led.o b/fw/Debug/Core/Src/led.o
new file mode 100644
index 0000000..9f923f1
Binary files /dev/null and b/fw/Debug/Core/Src/led.o differ
diff --git a/fw/Debug/Core/Src/led.su b/fw/Debug/Core/Src/led.su
new file mode 100644
index 0000000..6ec046d
--- /dev/null
+++ b/fw/Debug/Core/Src/led.su
@@ -0,0 +1,6 @@
+led.c:42:6:led_set_color 16 static
+led.c:49:6:led_gpio_off 0 static
+led.c:57:6:led_gpio_on 0 static
+led.c:69:6:led_off 0 static
+led.c:81:6:led_pwm_handler 20 static
+led.c:127:6:led_init 16 static
diff --git a/fw/Debug/Core/Src/main.d b/fw/Debug/Core/Src/main.d
new file mode 100644
index 0000000..44fc05c
--- /dev/null
+++ b/fw/Debug/Core/Src/main.d
@@ -0,0 +1,67 @@
+Core/Src/main.o: ../Core/Src/main.c ../Core/Inc/main.h \
+ ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h \
+ ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l011xx.h \
+ ../Drivers/CMSIS/Include/core_cm0plus.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h \
+ ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h \
+ ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h \
+ ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h \
+ ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_crs.h \
+ ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h \
+ ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h \
+ ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h \
+ ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h \
+ ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h \
+ ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h \
+ ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h \
+ ../Core/Inc/led.h ../Core/Inc/i2c.h ../Core/Inc/sht4x.h
+
+../Core/Inc/main.h:
+
+../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h:
+
+../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h:
+
+../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l011xx.h:
+
+../Drivers/CMSIS/Include/core_cm0plus.h:
+
+../Drivers/CMSIS/Include/cmsis_version.h:
+
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+
+../Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h:
+
+../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h:
+
+../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h:
+
+../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h:
+
+../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_crs.h:
+
+../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h:
+
+../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h:
+
+../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h:
+
+../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h:
+
+../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h:
+
+../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h:
+
+../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h:
+
+../Core/Inc/led.h:
+
+../Core/Inc/i2c.h:
+
+../Core/Inc/sht4x.h:
diff --git a/fw/Debug/Core/Src/main.o b/fw/Debug/Core/Src/main.o
new file mode 100644
index 0000000..874205c
Binary files /dev/null and b/fw/Debug/Core/Src/main.o differ
diff --git a/fw/Debug/Core/Src/main.su b/fw/Debug/Core/Src/main.su
new file mode 100644
index 0000000..b906929
--- /dev/null
+++ b/fw/Debug/Core/Src/main.su
@@ -0,0 +1,5 @@
+stm32l0xx_ll_bus.h:440:22:LL_APB1_GRP1_EnableClock 8 static
+stm32l0xx_ll_bus.h:987:22:LL_IOP_GRP1_EnableClock 8 static
+main.c:138:6:SystemClock_Config 8 static
+main.c:67:5:main 96 static
+main.c:397:6:Error_Handler 0 static,ignoring_inline_asm
diff --git a/fw/Debug/Core/Src/sht4x.d b/fw/Debug/Core/Src/sht4x.d
new file mode 100644
index 0000000..135fe2f
--- /dev/null
+++ b/fw/Debug/Core/Src/sht4x.d
@@ -0,0 +1,30 @@
+Core/Src/sht4x.o: ../Core/Src/sht4x.c ../Core/Inc/sht4x.h \
+ ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h \
+ ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l011xx.h \
+ ../Drivers/CMSIS/Include/core_cm0plus.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h \
+ ../Core/Inc/i2c.h
+
+../Core/Inc/sht4x.h:
+
+../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h:
+
+../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h:
+
+../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l011xx.h:
+
+../Drivers/CMSIS/Include/core_cm0plus.h:
+
+../Drivers/CMSIS/Include/cmsis_version.h:
+
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+
+../Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h:
+
+../Core/Inc/i2c.h:
diff --git a/fw/Debug/Core/Src/sht4x.o b/fw/Debug/Core/Src/sht4x.o
new file mode 100644
index 0000000..a547c57
Binary files /dev/null and b/fw/Debug/Core/Src/sht4x.o differ
diff --git a/fw/Debug/Core/Src/sht4x.su b/fw/Debug/Core/Src/sht4x.su
new file mode 100644
index 0000000..a0b763f
--- /dev/null
+++ b/fw/Debug/Core/Src/sht4x.su
@@ -0,0 +1,3 @@
+sht4x.c:10:8:sht4x_send_cmd 0 static
+sht4x.c:15:8:sht4x_read_data 0 static
+sht4x.c:20:8:sht4x_measure 48 static
diff --git a/fw/Debug/Core/Src/stm32l0xx_it.d b/fw/Debug/Core/Src/stm32l0xx_it.d
new file mode 100644
index 0000000..b4fd024
--- /dev/null
+++ b/fw/Debug/Core/Src/stm32l0xx_it.d
@@ -0,0 +1,72 @@
+Core/Src/stm32l0xx_it.o: ../Core/Src/stm32l0xx_it.c ../Core/Inc/main.h \
+ ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h \
+ ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l011xx.h \
+ ../Drivers/CMSIS/Include/core_cm0plus.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h \
+ ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h \
+ ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h \
+ ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h \
+ ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_crs.h \
+ ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h \
+ ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h \
+ ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h \
+ ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h \
+ ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h \
+ ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h \
+ ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h \
+ ../Core/Inc/led.h ../Core/Inc/i2c.h ../Core/Inc/sht4x.h \
+ ../Core/Inc/stm32l0xx_it.h ../Core/Inc/led.h
+
+../Core/Inc/main.h:
+
+../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h:
+
+../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h:
+
+../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l011xx.h:
+
+../Drivers/CMSIS/Include/core_cm0plus.h:
+
+../Drivers/CMSIS/Include/cmsis_version.h:
+
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+
+../Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h:
+
+../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h:
+
+../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h:
+
+../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h:
+
+../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_crs.h:
+
+../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h:
+
+../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h:
+
+../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h:
+
+../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_cortex.h:
+
+../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h:
+
+../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h:
+
+../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h:
+
+../Core/Inc/led.h:
+
+../Core/Inc/i2c.h:
+
+../Core/Inc/sht4x.h:
+
+../Core/Inc/stm32l0xx_it.h:
+
+../Core/Inc/led.h:
diff --git a/fw/Debug/Core/Src/stm32l0xx_it.o b/fw/Debug/Core/Src/stm32l0xx_it.o
new file mode 100644
index 0000000..8b17c7b
Binary files /dev/null and b/fw/Debug/Core/Src/stm32l0xx_it.o differ
diff --git a/fw/Debug/Core/Src/stm32l0xx_it.su b/fw/Debug/Core/Src/stm32l0xx_it.su
new file mode 100644
index 0000000..18c00ec
--- /dev/null
+++ b/fw/Debug/Core/Src/stm32l0xx_it.su
@@ -0,0 +1,6 @@
+stm32l0xx_it.c:71:6:NMI_Handler 0 static
+stm32l0xx_it.c:86:6:HardFault_Handler 0 static
+stm32l0xx_it.c:101:6:SVC_Handler 0 static
+stm32l0xx_it.c:114:6:PendSV_Handler 0 static
+stm32l0xx_it.c:127:6:SysTick_Handler 8 static
+stm32l0xx_it.c:148:6:DMA1_Channel2_3_IRQHandler 0 static
diff --git a/fw/Debug/Core/Src/subdir.mk b/fw/Debug/Core/Src/subdir.mk
new file mode 100644
index 0000000..af661f4
--- /dev/null
+++ b/fw/Debug/Core/Src/subdir.mk
@@ -0,0 +1,55 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+# Toolchain: GNU Tools for STM32 (9-2020-q2-update)
+################################################################################
+
+# Add inputs and outputs from these tool invocations to the build variables
+C_SRCS += \
+../Core/Src/i2c.c \
+../Core/Src/led.c \
+../Core/Src/main.c \
+../Core/Src/sht4x.c \
+../Core/Src/stm32l0xx_it.c \
+../Core/Src/syscalls.c \
+../Core/Src/sysmem.c \
+../Core/Src/system_stm32l0xx.c
+
+OBJS += \
+./Core/Src/i2c.o \
+./Core/Src/led.o \
+./Core/Src/main.o \
+./Core/Src/sht4x.o \
+./Core/Src/stm32l0xx_it.o \
+./Core/Src/syscalls.o \
+./Core/Src/sysmem.o \
+./Core/Src/system_stm32l0xx.o
+
+C_DEPS += \
+./Core/Src/i2c.d \
+./Core/Src/led.d \
+./Core/Src/main.d \
+./Core/Src/sht4x.d \
+./Core/Src/stm32l0xx_it.d \
+./Core/Src/syscalls.d \
+./Core/Src/sysmem.d \
+./Core/Src/system_stm32l0xx.d
+
+
+# Each subdirectory must supply rules for building sources it contributes
+Core/Src/i2c.o: ../Core/Src/i2c.c Core/Src/subdir.mk
+ arm-none-eabi-gcc "$<" -mcpu=cortex-m0plus -std=gnu11 -g3 -DSTM32L011xx -DDEBUG -DUSE_FULL_LL_DRIVER '-DHSE_VALUE=8000000' '-DHSE_STARTUP_TIMEOUT=100' '-DLSE_STARTUP_TIMEOUT=5000' '-DLSE_VALUE=32768' '-DMSI_VALUE=2097000' '-DHSI_VALUE=16000000' '-DLSI_VALUE=37000' '-DVDD_VALUE=3300' '-DPREFETCH_ENABLE=0' '-DINSTRUCTION_CACHE_ENABLE=1' '-DDATA_CACHE_ENABLE=1' -c -I../Core/Inc -I../Drivers/STM32L0xx_HAL_Driver/Inc -I../Drivers/CMSIS/Device/ST/STM32L0xx/Include -I../Drivers/CMSIS/Include -Os -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Core/Src/i2c.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@"
+Core/Src/led.o: ../Core/Src/led.c Core/Src/subdir.mk
+ arm-none-eabi-gcc "$<" -mcpu=cortex-m0plus -std=gnu11 -g3 -DSTM32L011xx -DDEBUG -DUSE_FULL_LL_DRIVER '-DHSE_VALUE=8000000' '-DHSE_STARTUP_TIMEOUT=100' '-DLSE_STARTUP_TIMEOUT=5000' '-DLSE_VALUE=32768' '-DMSI_VALUE=2097000' '-DHSI_VALUE=16000000' '-DLSI_VALUE=37000' '-DVDD_VALUE=3300' '-DPREFETCH_ENABLE=0' '-DINSTRUCTION_CACHE_ENABLE=1' '-DDATA_CACHE_ENABLE=1' -c -I../Core/Inc -I../Drivers/STM32L0xx_HAL_Driver/Inc -I../Drivers/CMSIS/Device/ST/STM32L0xx/Include -I../Drivers/CMSIS/Include -Os -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Core/Src/led.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@"
+Core/Src/main.o: ../Core/Src/main.c Core/Src/subdir.mk
+ arm-none-eabi-gcc "$<" -mcpu=cortex-m0plus -std=gnu11 -g3 -DSTM32L011xx -DDEBUG -DUSE_FULL_LL_DRIVER '-DHSE_VALUE=8000000' '-DHSE_STARTUP_TIMEOUT=100' '-DLSE_STARTUP_TIMEOUT=5000' '-DLSE_VALUE=32768' '-DMSI_VALUE=2097000' '-DHSI_VALUE=16000000' '-DLSI_VALUE=37000' '-DVDD_VALUE=3300' '-DPREFETCH_ENABLE=0' '-DINSTRUCTION_CACHE_ENABLE=1' '-DDATA_CACHE_ENABLE=1' -c -I../Core/Inc -I../Drivers/STM32L0xx_HAL_Driver/Inc -I../Drivers/CMSIS/Device/ST/STM32L0xx/Include -I../Drivers/CMSIS/Include -Os -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Core/Src/main.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@"
+Core/Src/sht4x.o: ../Core/Src/sht4x.c Core/Src/subdir.mk
+ arm-none-eabi-gcc "$<" -mcpu=cortex-m0plus -std=gnu11 -g3 -DSTM32L011xx -DDEBUG -DUSE_FULL_LL_DRIVER '-DHSE_VALUE=8000000' '-DHSE_STARTUP_TIMEOUT=100' '-DLSE_STARTUP_TIMEOUT=5000' '-DLSE_VALUE=32768' '-DMSI_VALUE=2097000' '-DHSI_VALUE=16000000' '-DLSI_VALUE=37000' '-DVDD_VALUE=3300' '-DPREFETCH_ENABLE=0' '-DINSTRUCTION_CACHE_ENABLE=1' '-DDATA_CACHE_ENABLE=1' -c -I../Core/Inc -I../Drivers/STM32L0xx_HAL_Driver/Inc -I../Drivers/CMSIS/Device/ST/STM32L0xx/Include -I../Drivers/CMSIS/Include -Os -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Core/Src/sht4x.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@"
+Core/Src/stm32l0xx_it.o: ../Core/Src/stm32l0xx_it.c Core/Src/subdir.mk
+ arm-none-eabi-gcc "$<" -mcpu=cortex-m0plus -std=gnu11 -g3 -DSTM32L011xx -DDEBUG -DUSE_FULL_LL_DRIVER '-DHSE_VALUE=8000000' '-DHSE_STARTUP_TIMEOUT=100' '-DLSE_STARTUP_TIMEOUT=5000' '-DLSE_VALUE=32768' '-DMSI_VALUE=2097000' '-DHSI_VALUE=16000000' '-DLSI_VALUE=37000' '-DVDD_VALUE=3300' '-DPREFETCH_ENABLE=0' '-DINSTRUCTION_CACHE_ENABLE=1' '-DDATA_CACHE_ENABLE=1' -c -I../Core/Inc -I../Drivers/STM32L0xx_HAL_Driver/Inc -I../Drivers/CMSIS/Device/ST/STM32L0xx/Include -I../Drivers/CMSIS/Include -Os -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Core/Src/stm32l0xx_it.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@"
+Core/Src/syscalls.o: ../Core/Src/syscalls.c Core/Src/subdir.mk
+ arm-none-eabi-gcc "$<" -mcpu=cortex-m0plus -std=gnu11 -g3 -DSTM32L011xx -DDEBUG -DUSE_FULL_LL_DRIVER '-DHSE_VALUE=8000000' '-DHSE_STARTUP_TIMEOUT=100' '-DLSE_STARTUP_TIMEOUT=5000' '-DLSE_VALUE=32768' '-DMSI_VALUE=2097000' '-DHSI_VALUE=16000000' '-DLSI_VALUE=37000' '-DVDD_VALUE=3300' '-DPREFETCH_ENABLE=0' '-DINSTRUCTION_CACHE_ENABLE=1' '-DDATA_CACHE_ENABLE=1' -c -I../Core/Inc -I../Drivers/STM32L0xx_HAL_Driver/Inc -I../Drivers/CMSIS/Device/ST/STM32L0xx/Include -I../Drivers/CMSIS/Include -Os -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Core/Src/syscalls.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@"
+Core/Src/sysmem.o: ../Core/Src/sysmem.c Core/Src/subdir.mk
+ arm-none-eabi-gcc "$<" -mcpu=cortex-m0plus -std=gnu11 -g3 -DSTM32L011xx -DDEBUG -DUSE_FULL_LL_DRIVER '-DHSE_VALUE=8000000' '-DHSE_STARTUP_TIMEOUT=100' '-DLSE_STARTUP_TIMEOUT=5000' '-DLSE_VALUE=32768' '-DMSI_VALUE=2097000' '-DHSI_VALUE=16000000' '-DLSI_VALUE=37000' '-DVDD_VALUE=3300' '-DPREFETCH_ENABLE=0' '-DINSTRUCTION_CACHE_ENABLE=1' '-DDATA_CACHE_ENABLE=1' -c -I../Core/Inc -I../Drivers/STM32L0xx_HAL_Driver/Inc -I../Drivers/CMSIS/Device/ST/STM32L0xx/Include -I../Drivers/CMSIS/Include -Os -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Core/Src/sysmem.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@"
+Core/Src/system_stm32l0xx.o: ../Core/Src/system_stm32l0xx.c Core/Src/subdir.mk
+ arm-none-eabi-gcc "$<" -mcpu=cortex-m0plus -std=gnu11 -g3 -DSTM32L011xx -DDEBUG -DUSE_FULL_LL_DRIVER '-DHSE_VALUE=8000000' '-DHSE_STARTUP_TIMEOUT=100' '-DLSE_STARTUP_TIMEOUT=5000' '-DLSE_VALUE=32768' '-DMSI_VALUE=2097000' '-DHSI_VALUE=16000000' '-DLSI_VALUE=37000' '-DVDD_VALUE=3300' '-DPREFETCH_ENABLE=0' '-DINSTRUCTION_CACHE_ENABLE=1' '-DDATA_CACHE_ENABLE=1' -c -I../Core/Inc -I../Drivers/STM32L0xx_HAL_Driver/Inc -I../Drivers/CMSIS/Device/ST/STM32L0xx/Include -I../Drivers/CMSIS/Include -Os -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Core/Src/system_stm32l0xx.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@"
+
diff --git a/fw/Debug/Core/Src/syscalls.d b/fw/Debug/Core/Src/syscalls.d
new file mode 100644
index 0000000..8667c70
--- /dev/null
+++ b/fw/Debug/Core/Src/syscalls.d
@@ -0,0 +1 @@
+Core/Src/syscalls.o: ../Core/Src/syscalls.c
diff --git a/fw/Debug/Core/Src/syscalls.o b/fw/Debug/Core/Src/syscalls.o
new file mode 100644
index 0000000..b0ef4b4
Binary files /dev/null and b/fw/Debug/Core/Src/syscalls.o differ
diff --git a/fw/Debug/Core/Src/syscalls.su b/fw/Debug/Core/Src/syscalls.su
new file mode 100644
index 0000000..c872039
--- /dev/null
+++ b/fw/Debug/Core/Src/syscalls.su
@@ -0,0 +1,18 @@
+syscalls.c:48:6:initialise_monitor_handles 0 static
+syscalls.c:52:5:_getpid 0 static
+syscalls.c:57:5:_kill 8 static
+syscalls.c:63:6:_exit 8 static
+syscalls.c:69:27:_read 16 static
+syscalls.c:81:27:_write 16 static
+syscalls.c:92:5:_close 0 static
+syscalls.c:98:5:_fstat 0 static
+syscalls.c:104:5:_isatty 0 static
+syscalls.c:109:5:_lseek 0 static
+syscalls.c:114:5:_open 0 static
+syscalls.c:120:5:_wait 8 static
+syscalls.c:126:5:_unlink 8 static
+syscalls.c:132:5:_times 0 static
+syscalls.c:137:5:_stat 0 static
+syscalls.c:143:5:_link 8 static
+syscalls.c:149:5:_fork 8 static
+syscalls.c:155:5:_execve 8 static
diff --git a/fw/Debug/Core/Src/sysmem.d b/fw/Debug/Core/Src/sysmem.d
new file mode 100644
index 0000000..74fecf9
--- /dev/null
+++ b/fw/Debug/Core/Src/sysmem.d
@@ -0,0 +1 @@
+Core/Src/sysmem.o: ../Core/Src/sysmem.c
diff --git a/fw/Debug/Core/Src/sysmem.o b/fw/Debug/Core/Src/sysmem.o
new file mode 100644
index 0000000..acba301
Binary files /dev/null and b/fw/Debug/Core/Src/sysmem.o differ
diff --git a/fw/Debug/Core/Src/sysmem.su b/fw/Debug/Core/Src/sysmem.su
new file mode 100644
index 0000000..c9ac5ce
--- /dev/null
+++ b/fw/Debug/Core/Src/sysmem.su
@@ -0,0 +1 @@
+sysmem.c:54:7:_sbrk 8 static
diff --git a/fw/Debug/Core/Src/system_stm32l0xx.d b/fw/Debug/Core/Src/system_stm32l0xx.d
new file mode 100644
index 0000000..92dd183
--- /dev/null
+++ b/fw/Debug/Core/Src/system_stm32l0xx.d
@@ -0,0 +1,22 @@
+Core/Src/system_stm32l0xx.o: ../Core/Src/system_stm32l0xx.c \
+ ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l011xx.h \
+ ../Drivers/CMSIS/Include/core_cm0plus.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h
+
+../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h:
+
+../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l011xx.h:
+
+../Drivers/CMSIS/Include/core_cm0plus.h:
+
+../Drivers/CMSIS/Include/cmsis_version.h:
+
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+
+../Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h:
diff --git a/fw/Debug/Core/Src/system_stm32l0xx.o b/fw/Debug/Core/Src/system_stm32l0xx.o
new file mode 100644
index 0000000..99fa31a
Binary files /dev/null and b/fw/Debug/Core/Src/system_stm32l0xx.o differ
diff --git a/fw/Debug/Core/Src/system_stm32l0xx.su b/fw/Debug/Core/Src/system_stm32l0xx.su
new file mode 100644
index 0000000..f548a45
--- /dev/null
+++ b/fw/Debug/Core/Src/system_stm32l0xx.su
@@ -0,0 +1,2 @@
+system_stm32l0xx.c:154:6:SystemInit 0 static
+system_stm32l0xx.c:200:6:SystemCoreClockUpdate 16 static
diff --git a/fw/Debug/Core/Startup/startup_stm32l011f4ux.d b/fw/Debug/Core/Startup/startup_stm32l011f4ux.d
new file mode 100644
index 0000000..7f6eea2
--- /dev/null
+++ b/fw/Debug/Core/Startup/startup_stm32l011f4ux.d
@@ -0,0 +1,2 @@
+Core/Startup/startup_stm32l011f4ux.o: \
+ ../Core/Startup/startup_stm32l011f4ux.s
diff --git a/fw/Debug/Core/Startup/startup_stm32l011f4ux.o b/fw/Debug/Core/Startup/startup_stm32l011f4ux.o
new file mode 100644
index 0000000..6e4550b
Binary files /dev/null and b/fw/Debug/Core/Startup/startup_stm32l011f4ux.o differ
diff --git a/fw/Debug/Core/Startup/subdir.mk b/fw/Debug/Core/Startup/subdir.mk
new file mode 100644
index 0000000..3fa16c8
--- /dev/null
+++ b/fw/Debug/Core/Startup/subdir.mk
@@ -0,0 +1,20 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+# Toolchain: GNU Tools for STM32 (9-2020-q2-update)
+################################################################################
+
+# Add inputs and outputs from these tool invocations to the build variables
+S_SRCS += \
+../Core/Startup/startup_stm32l011f4ux.s
+
+OBJS += \
+./Core/Startup/startup_stm32l011f4ux.o
+
+S_DEPS += \
+./Core/Startup/startup_stm32l011f4ux.d
+
+
+# Each subdirectory must supply rules for building sources it contributes
+Core/Startup/startup_stm32l011f4ux.o: ../Core/Startup/startup_stm32l011f4ux.s Core/Startup/subdir.mk
+ arm-none-eabi-gcc -mcpu=cortex-m0plus -g3 -c -x assembler-with-cpp -MMD -MP -MF"Core/Startup/startup_stm32l011f4ux.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" "$<"
+
diff --git a/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.d b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.d
new file mode 100644
index 0000000..737ad9a
--- /dev/null
+++ b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.d
@@ -0,0 +1,29 @@
+Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.o: \
+ ../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c \
+ ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h \
+ ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l011xx.h \
+ ../Drivers/CMSIS/Include/core_cm0plus.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h \
+ ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h
+
+../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_dma.h:
+
+../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h:
+
+../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l011xx.h:
+
+../Drivers/CMSIS/Include/core_cm0plus.h:
+
+../Drivers/CMSIS/Include/cmsis_version.h:
+
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+
+../Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h:
+
+../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h:
diff --git a/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.o b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.o
new file mode 100644
index 0000000..28b4bd9
Binary files /dev/null and b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.o differ
diff --git a/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.su b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.su
new file mode 100644
index 0000000..7e34b01
--- /dev/null
+++ b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.su
@@ -0,0 +1,3 @@
+stm32l0xx_ll_dma.c:150:13:LL_DMA_DeInit 16 static
+stm32l0xx_ll_dma.c:275:13:LL_DMA_Init 16 static
+stm32l0xx_ll_dma.c:343:6:LL_DMA_StructInit 0 static
diff --git a/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.d b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.d
new file mode 100644
index 0000000..2cc017f
--- /dev/null
+++ b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.d
@@ -0,0 +1,26 @@
+Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.o: \
+ ../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c \
+ ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h \
+ ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l011xx.h \
+ ../Drivers/CMSIS/Include/core_cm0plus.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h
+
+../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_exti.h:
+
+../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h:
+
+../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l011xx.h:
+
+../Drivers/CMSIS/Include/core_cm0plus.h:
+
+../Drivers/CMSIS/Include/cmsis_version.h:
+
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+
+../Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h:
diff --git a/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.o b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.o
new file mode 100644
index 0000000..bf76e61
Binary files /dev/null and b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.o differ
diff --git a/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.su b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.su
new file mode 100644
index 0000000..ca187b5
--- /dev/null
+++ b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.su
@@ -0,0 +1,3 @@
+stm32l0xx_ll_exti.c:80:10:LL_EXTI_DeInit 0 static
+stm32l0xx_ll_exti.c:105:10:LL_EXTI_Init 8 static
+stm32l0xx_ll_exti.c:186:6:LL_EXTI_StructInit 0 static
diff --git a/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.d b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.d
new file mode 100644
index 0000000..84a1bfe
--- /dev/null
+++ b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.d
@@ -0,0 +1,29 @@
+Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.o: \
+ ../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c \
+ ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h \
+ ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l011xx.h \
+ ../Drivers/CMSIS/Include/core_cm0plus.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h \
+ ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h
+
+../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_gpio.h:
+
+../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h:
+
+../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l011xx.h:
+
+../Drivers/CMSIS/Include/core_cm0plus.h:
+
+../Drivers/CMSIS/Include/cmsis_version.h:
+
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+
+../Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h:
+
+../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h:
diff --git a/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.o b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.o
new file mode 100644
index 0000000..23f8214
Binary files /dev/null and b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.o differ
diff --git a/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.su b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.su
new file mode 100644
index 0000000..bc587a1
--- /dev/null
+++ b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.su
@@ -0,0 +1,3 @@
+stm32l0xx_ll_gpio.c:96:13:LL_GPIO_DeInit 0 static
+stm32l0xx_ll_gpio.c:157:13:LL_GPIO_Init 32 static
+stm32l0xx_ll_gpio.c:231:6:LL_GPIO_StructInit 0 static
diff --git a/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.d b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.d
new file mode 100644
index 0000000..94e870b
--- /dev/null
+++ b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.d
@@ -0,0 +1,29 @@
+Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.o: \
+ ../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c \
+ ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h \
+ ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l011xx.h \
+ ../Drivers/CMSIS/Include/core_cm0plus.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h \
+ ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h
+
+../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_i2c.h:
+
+../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h:
+
+../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l011xx.h:
+
+../Drivers/CMSIS/Include/core_cm0plus.h:
+
+../Drivers/CMSIS/Include/cmsis_version.h:
+
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+
+../Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h:
+
+../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h:
diff --git a/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.o b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.o
new file mode 100644
index 0000000..b6f0046
Binary files /dev/null and b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.o differ
diff --git a/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.su b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.su
new file mode 100644
index 0000000..bfa06c8
--- /dev/null
+++ b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.su
@@ -0,0 +1,3 @@
+stm32l0xx_ll_i2c.c:87:13:LL_I2C_DeInit 0 static
+stm32l0xx_ll_i2c.c:139:13:LL_I2C_Init 12 static
+stm32l0xx_ll_i2c.c:207:6:LL_I2C_StructInit 0 static
diff --git a/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.d b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.d
new file mode 100644
index 0000000..45688ed
--- /dev/null
+++ b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.d
@@ -0,0 +1,32 @@
+Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.o: \
+ ../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c \
+ ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h \
+ ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l011xx.h \
+ ../Drivers/CMSIS/Include/core_cm0plus.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h \
+ ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h \
+ ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h
+
+../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_lpuart.h:
+
+../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h:
+
+../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l011xx.h:
+
+../Drivers/CMSIS/Include/core_cm0plus.h:
+
+../Drivers/CMSIS/Include/cmsis_version.h:
+
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+
+../Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h:
+
+../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h:
+
+../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h:
diff --git a/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.o b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.o
new file mode 100644
index 0000000..fabf774
Binary files /dev/null and b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.o differ
diff --git a/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.su b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.su
new file mode 100644
index 0000000..2af37eb
--- /dev/null
+++ b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.su
@@ -0,0 +1,3 @@
+stm32l0xx_ll_lpuart.c:117:13:LL_LPUART_DeInit 0 static
+stm32l0xx_ll_lpuart.c:155:13:LL_LPUART_Init 24 static
+stm32l0xx_ll_lpuart.c:232:6:LL_LPUART_StructInit 0 static
diff --git a/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_pwr.d b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_pwr.d
new file mode 100644
index 0000000..b22a85d
--- /dev/null
+++ b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_pwr.d
@@ -0,0 +1,29 @@
+Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_pwr.o: \
+ ../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_pwr.c \
+ ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h \
+ ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l011xx.h \
+ ../Drivers/CMSIS/Include/core_cm0plus.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h \
+ ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h
+
+../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h:
+
+../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h:
+
+../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l011xx.h:
+
+../Drivers/CMSIS/Include/core_cm0plus.h:
+
+../Drivers/CMSIS/Include/cmsis_version.h:
+
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+
+../Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h:
+
+../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h:
diff --git a/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_pwr.o b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_pwr.o
new file mode 100644
index 0000000..e423123
Binary files /dev/null and b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_pwr.o differ
diff --git a/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_pwr.su b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_pwr.su
new file mode 100644
index 0000000..68038bc
--- /dev/null
+++ b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_pwr.su
@@ -0,0 +1 @@
+stm32l0xx_ll_pwr.c:56:13:LL_PWR_DeInit 0 static
diff --git a/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.d b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.d
new file mode 100644
index 0000000..748ea46
--- /dev/null
+++ b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.d
@@ -0,0 +1,26 @@
+Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.o: \
+ ../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c \
+ ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h \
+ ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l011xx.h \
+ ../Drivers/CMSIS/Include/core_cm0plus.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h
+
+../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h:
+
+../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h:
+
+../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l011xx.h:
+
+../Drivers/CMSIS/Include/core_cm0plus.h:
+
+../Drivers/CMSIS/Include/cmsis_version.h:
+
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+
+../Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h:
diff --git a/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.o b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.o
new file mode 100644
index 0000000..1cd68e3
Binary files /dev/null and b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.o differ
diff --git a/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.su b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.su
new file mode 100644
index 0000000..0819a7b
--- /dev/null
+++ b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.su
@@ -0,0 +1,13 @@
+stm32l0xx_ll_rcc.h:802:26:LL_RCC_HSI_IsReady 0 static
+stm32l0xx_ll_rcc.h:2097:26:LL_RCC_IsActiveFlag_HSIDIV 0 static
+stm32l0xx_ll_rcc.c:112:13:LL_RCC_DeInit 16 static,ignoring_inline_asm
+stm32l0xx_ll_rcc.c:622:10:RCC_GetHCLKClockFreq 0 static
+stm32l0xx_ll_rcc.c:633:10:RCC_GetPCLK1ClockFreq 0 static
+stm32l0xx_ll_rcc.c:644:10:RCC_GetPCLK2ClockFreq 0 static
+stm32l0xx_ll_rcc.c:654:10:RCC_PLL_GetFreqDomain_SYS 8 static
+stm32l0xx_ll_rcc.c:579:10:RCC_GetSystemClockFreq 8 static
+stm32l0xx_ll_rcc.c:222:6:LL_RCC_GetSystemClocksFreq 8 static
+stm32l0xx_ll_rcc.c:247:10:LL_RCC_GetUSARTClockFreq 8 static
+stm32l0xx_ll_rcc.c:344:10:LL_RCC_GetI2CClockFreq 8 static
+stm32l0xx_ll_rcc.c:423:10:LL_RCC_GetLPUARTClockFreq 8 static
+stm32l0xx_ll_rcc.c:474:10:LL_RCC_GetLPTIMClockFreq 8 static
diff --git a/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.d b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.d
new file mode 100644
index 0000000..577cc36
--- /dev/null
+++ b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.d
@@ -0,0 +1,35 @@
+Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.o: \
+ ../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c \
+ ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h \
+ ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h \
+ ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l011xx.h \
+ ../Drivers/CMSIS/Include/core_cm0plus.h \
+ ../Drivers/CMSIS/Include/cmsis_version.h \
+ ../Drivers/CMSIS/Include/cmsis_compiler.h \
+ ../Drivers/CMSIS/Include/cmsis_gcc.h \
+ ../Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h \
+ ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h \
+ ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h \
+ ../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h
+
+../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_rcc.h:
+
+../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h:
+
+../Drivers/CMSIS/Device/ST/STM32L0xx/Include/stm32l011xx.h:
+
+../Drivers/CMSIS/Include/core_cm0plus.h:
+
+../Drivers/CMSIS/Include/cmsis_version.h:
+
+../Drivers/CMSIS/Include/cmsis_compiler.h:
+
+../Drivers/CMSIS/Include/cmsis_gcc.h:
+
+../Drivers/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h:
+
+../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_utils.h:
+
+../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_system.h:
+
+../Drivers/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_pwr.h:
diff --git a/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.o b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.o
new file mode 100644
index 0000000..19bf0e5
Binary files /dev/null and b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.o differ
diff --git a/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.su b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.su
new file mode 100644
index 0000000..ab2a69f
--- /dev/null
+++ b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.su
@@ -0,0 +1,7 @@
+stm32l0xx_ll_utils.c:147:6:LL_Init1msTick 8 static
+stm32l0xx_ll_utils.c:163:6:LL_mDelay 8 static
+stm32l0xx_ll_utils.c:225:6:LL_SetSystemCoreClock 0 static
+stm32l0xx_ll_utils.c:239:13:LL_SetFlashLatency 8 static
+stm32l0xx_ll_utils.c:521:20:UTILS_EnablePLLAndSwitchSystem 16 static
+stm32l0xx_ll_utils.c:338:13:LL_PLL_ConfigSystemClock_HSI 24 static
+stm32l0xx_ll_utils.c:397:13:LL_PLL_ConfigSystemClock_HSE 24 static
diff --git a/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/subdir.mk b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/subdir.mk
new file mode 100644
index 0000000..40b8c42
--- /dev/null
+++ b/fw/Debug/Drivers/STM32L0xx_HAL_Driver/Src/subdir.mk
@@ -0,0 +1,55 @@
+################################################################################
+# Automatically-generated file. Do not edit!
+# Toolchain: GNU Tools for STM32 (9-2020-q2-update)
+################################################################################
+
+# Add inputs and outputs from these tool invocations to the build variables
+C_SRCS += \
+../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c \
+../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c \
+../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c \
+../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c \
+../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c \
+../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_pwr.c \
+../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c \
+../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c
+
+OBJS += \
+./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.o \
+./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.o \
+./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.o \
+./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.o \
+./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.o \
+./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_pwr.o \
+./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.o \
+./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.o
+
+C_DEPS += \
+./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.d \
+./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.d \
+./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.d \
+./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.d \
+./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.d \
+./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_pwr.d \
+./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.d \
+./Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.d
+
+
+# Each subdirectory must supply rules for building sources it contributes
+Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.o: ../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.c Drivers/STM32L0xx_HAL_Driver/Src/subdir.mk
+ arm-none-eabi-gcc "$<" -mcpu=cortex-m0plus -std=gnu11 -g3 -DSTM32L011xx -DDEBUG -DUSE_FULL_LL_DRIVER '-DHSE_VALUE=8000000' '-DHSE_STARTUP_TIMEOUT=100' '-DLSE_STARTUP_TIMEOUT=5000' '-DLSE_VALUE=32768' '-DMSI_VALUE=2097000' '-DHSI_VALUE=16000000' '-DLSI_VALUE=37000' '-DVDD_VALUE=3300' '-DPREFETCH_ENABLE=0' '-DINSTRUCTION_CACHE_ENABLE=1' '-DDATA_CACHE_ENABLE=1' -c -I../Core/Inc -I../Drivers/STM32L0xx_HAL_Driver/Inc -I../Drivers/CMSIS/Device/ST/STM32L0xx/Include -I../Drivers/CMSIS/Include -Os -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_dma.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@"
+Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.o: ../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.c Drivers/STM32L0xx_HAL_Driver/Src/subdir.mk
+ arm-none-eabi-gcc "$<" -mcpu=cortex-m0plus -std=gnu11 -g3 -DSTM32L011xx -DDEBUG -DUSE_FULL_LL_DRIVER '-DHSE_VALUE=8000000' '-DHSE_STARTUP_TIMEOUT=100' '-DLSE_STARTUP_TIMEOUT=5000' '-DLSE_VALUE=32768' '-DMSI_VALUE=2097000' '-DHSI_VALUE=16000000' '-DLSI_VALUE=37000' '-DVDD_VALUE=3300' '-DPREFETCH_ENABLE=0' '-DINSTRUCTION_CACHE_ENABLE=1' '-DDATA_CACHE_ENABLE=1' -c -I../Core/Inc -I../Drivers/STM32L0xx_HAL_Driver/Inc -I../Drivers/CMSIS/Device/ST/STM32L0xx/Include -I../Drivers/CMSIS/Include -Os -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_exti.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@"
+Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.o: ../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.c Drivers/STM32L0xx_HAL_Driver/Src/subdir.mk
+ arm-none-eabi-gcc "$<" -mcpu=cortex-m0plus -std=gnu11 -g3 -DSTM32L011xx -DDEBUG -DUSE_FULL_LL_DRIVER '-DHSE_VALUE=8000000' '-DHSE_STARTUP_TIMEOUT=100' '-DLSE_STARTUP_TIMEOUT=5000' '-DLSE_VALUE=32768' '-DMSI_VALUE=2097000' '-DHSI_VALUE=16000000' '-DLSI_VALUE=37000' '-DVDD_VALUE=3300' '-DPREFETCH_ENABLE=0' '-DINSTRUCTION_CACHE_ENABLE=1' '-DDATA_CACHE_ENABLE=1' -c -I../Core/Inc -I../Drivers/STM32L0xx_HAL_Driver/Inc -I../Drivers/CMSIS/Device/ST/STM32L0xx/Include -I../Drivers/CMSIS/Include -Os -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_gpio.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@"
+Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.o: ../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.c Drivers/STM32L0xx_HAL_Driver/Src/subdir.mk
+ arm-none-eabi-gcc "$<" -mcpu=cortex-m0plus -std=gnu11 -g3 -DSTM32L011xx -DDEBUG -DUSE_FULL_LL_DRIVER '-DHSE_VALUE=8000000' '-DHSE_STARTUP_TIMEOUT=100' '-DLSE_STARTUP_TIMEOUT=5000' '-DLSE_VALUE=32768' '-DMSI_VALUE=2097000' '-DHSI_VALUE=16000000' '-DLSI_VALUE=37000' '-DVDD_VALUE=3300' '-DPREFETCH_ENABLE=0' '-DINSTRUCTION_CACHE_ENABLE=1' '-DDATA_CACHE_ENABLE=1' -c -I../Core/Inc -I../Drivers/STM32L0xx_HAL_Driver/Inc -I../Drivers/CMSIS/Device/ST/STM32L0xx/Include -I../Drivers/CMSIS/Include -Os -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_i2c.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@"
+Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.o: ../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.c Drivers/STM32L0xx_HAL_Driver/Src/subdir.mk
+ arm-none-eabi-gcc "$<" -mcpu=cortex-m0plus -std=gnu11 -g3 -DSTM32L011xx -DDEBUG -DUSE_FULL_LL_DRIVER '-DHSE_VALUE=8000000' '-DHSE_STARTUP_TIMEOUT=100' '-DLSE_STARTUP_TIMEOUT=5000' '-DLSE_VALUE=32768' '-DMSI_VALUE=2097000' '-DHSI_VALUE=16000000' '-DLSI_VALUE=37000' '-DVDD_VALUE=3300' '-DPREFETCH_ENABLE=0' '-DINSTRUCTION_CACHE_ENABLE=1' '-DDATA_CACHE_ENABLE=1' -c -I../Core/Inc -I../Drivers/STM32L0xx_HAL_Driver/Inc -I../Drivers/CMSIS/Device/ST/STM32L0xx/Include -I../Drivers/CMSIS/Include -Os -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_lpuart.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@"
+Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_pwr.o: ../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_pwr.c Drivers/STM32L0xx_HAL_Driver/Src/subdir.mk
+ arm-none-eabi-gcc "$<" -mcpu=cortex-m0plus -std=gnu11 -g3 -DSTM32L011xx -DDEBUG -DUSE_FULL_LL_DRIVER '-DHSE_VALUE=8000000' '-DHSE_STARTUP_TIMEOUT=100' '-DLSE_STARTUP_TIMEOUT=5000' '-DLSE_VALUE=32768' '-DMSI_VALUE=2097000' '-DHSI_VALUE=16000000' '-DLSI_VALUE=37000' '-DVDD_VALUE=3300' '-DPREFETCH_ENABLE=0' '-DINSTRUCTION_CACHE_ENABLE=1' '-DDATA_CACHE_ENABLE=1' -c -I../Core/Inc -I../Drivers/STM32L0xx_HAL_Driver/Inc -I../Drivers/CMSIS/Device/ST/STM32L0xx/Include -I../Drivers/CMSIS/Include -Os -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_pwr.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@"
+Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.o: ../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.c Drivers/STM32L0xx_HAL_Driver/Src/subdir.mk
+ arm-none-eabi-gcc "$<" -mcpu=cortex-m0plus -std=gnu11 -g3 -DSTM32L011xx -DDEBUG -DUSE_FULL_LL_DRIVER '-DHSE_VALUE=8000000' '-DHSE_STARTUP_TIMEOUT=100' '-DLSE_STARTUP_TIMEOUT=5000' '-DLSE_VALUE=32768' '-DMSI_VALUE=2097000' '-DHSI_VALUE=16000000' '-DLSI_VALUE=37000' '-DVDD_VALUE=3300' '-DPREFETCH_ENABLE=0' '-DINSTRUCTION_CACHE_ENABLE=1' '-DDATA_CACHE_ENABLE=1' -c -I../Core/Inc -I../Drivers/STM32L0xx_HAL_Driver/Inc -I../Drivers/CMSIS/Device/ST/STM32L0xx/Include -I../Drivers/CMSIS/Include -Os -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_rcc.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@"
+Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.o: ../Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.c Drivers/STM32L0xx_HAL_Driver/Src/subdir.mk
+ arm-none-eabi-gcc "$<" -mcpu=cortex-m0plus -std=gnu11 -g3 -DSTM32L011xx -DDEBUG -DUSE_FULL_LL_DRIVER '-DHSE_VALUE=8000000' '-DHSE_STARTUP_TIMEOUT=100' '-DLSE_STARTUP_TIMEOUT=5000' '-DLSE_VALUE=32768' '-DMSI_VALUE=2097000' '-DHSI_VALUE=16000000' '-DLSI_VALUE=37000' '-DVDD_VALUE=3300' '-DPREFETCH_ENABLE=0' '-DINSTRUCTION_CACHE_ENABLE=1' '-DDATA_CACHE_ENABLE=1' -c -I../Core/Inc -I../Drivers/STM32L0xx_HAL_Driver/Inc -I../Drivers/CMSIS/Device/ST/STM32L0xx/Include -I../Drivers/CMSIS/Include -Os -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32L0xx_HAL_Driver/Src/stm32l0xx_ll_utils.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@"
+
diff --git a/fw/Debug/iaq_wired_sensor.bin b/fw/Debug/iaq_wired_sensor.bin
new file mode 100755
index 0000000..d652507
Binary files /dev/null and b/fw/Debug/iaq_wired_sensor.bin differ
diff --git a/fw/Debug/iaq_wired_sensor.elf b/fw/Debug/iaq_wired_sensor.elf
new file mode 100755
index 0000000..ce8e2a6
Binary files /dev/null and b/fw/Debug/iaq_wired_sensor.elf differ
diff --git a/fw/Debug/iaq_wired_sensor.list b/fw/Debug/iaq_wired_sensor.list
new file mode 100644
index 0000000..1b67c2c
--- /dev/null
+++ b/fw/Debug/iaq_wired_sensor.list
@@ -0,0 +1,3017 @@
+
+iaq_wired_sensor.elf: file format elf32-littlearm
+
+Sections:
+Idx Name Size VMA LMA File off Algn
+ 0 .isr_vector 000000c0 08000000 08000000 00010000 2**0
+ CONTENTS, ALLOC, LOAD, READONLY, DATA
+ 1 .text 00001080 080000c0 080000c0 000100c0 2**2
+ CONTENTS, ALLOC, LOAD, READONLY, CODE
+ 2 .rodata 00000024 08001140 08001140 00011140 2**0
+ CONTENTS, ALLOC, LOAD, READONLY, DATA
+ 3 .ARM.extab 00000000 08001164 08001164 00020004 2**0
+ CONTENTS
+ 4 .ARM 00000008 08001164 08001164 00011164 2**2
+ CONTENTS, ALLOC, LOAD, READONLY, DATA
+ 5 .preinit_array 00000000 0800116c 0800116c 00020004 2**0
+ CONTENTS, ALLOC, LOAD, DATA
+ 6 .init_array 00000004 0800116c 0800116c 0001116c 2**2
+ CONTENTS, ALLOC, LOAD, DATA
+ 7 .fini_array 00000004 08001170 08001170 00011170 2**2
+ CONTENTS, ALLOC, LOAD, DATA
+ 8 .data 00000004 20000000 08001174 00020000 2**2
+ CONTENTS, ALLOC, LOAD, DATA
+ 9 .bss 00000044 20000004 08001178 00020004 2**2
+ ALLOC
+ 10 ._user_heap_stack 00000600 20000048 08001178 00020048 2**0
+ ALLOC
+ 11 .ARM.attributes 00000028 00000000 00000000 00020004 2**0
+ CONTENTS, READONLY
+ 12 .debug_info 000060ed 00000000 00000000 0002002c 2**0
+ CONTENTS, READONLY, DEBUGGING, OCTETS
+ 13 .debug_abbrev 000018b5 00000000 00000000 00026119 2**0
+ CONTENTS, READONLY, DEBUGGING, OCTETS
+ 14 .debug_loc 00002594 00000000 00000000 000279ce 2**0
+ CONTENTS, READONLY, DEBUGGING, OCTETS
+ 15 .debug_aranges 000002d0 00000000 00000000 00029f68 2**3
+ CONTENTS, READONLY, DEBUGGING, OCTETS
+ 16 .debug_ranges 00000bc0 00000000 00000000 0002a238 2**3
+ CONTENTS, READONLY, DEBUGGING, OCTETS
+ 17 .debug_macro 0000b51a 00000000 00000000 0002adf8 2**0
+ CONTENTS, READONLY, DEBUGGING, OCTETS
+ 18 .debug_line 00005761 00000000 00000000 00036312 2**0
+ CONTENTS, READONLY, DEBUGGING, OCTETS
+ 19 .debug_str 00039767 00000000 00000000 0003ba73 2**0
+ CONTENTS, READONLY, DEBUGGING, OCTETS
+ 20 .comment 00000053 00000000 00000000 000751da 2**0
+ CONTENTS, READONLY
+ 21 .debug_frame 00000614 00000000 00000000 00075230 2**2
+ CONTENTS, READONLY, DEBUGGING, OCTETS
+
+Disassembly of section .text:
+
+080000c0 <__do_global_dtors_aux>:
+ 80000c0: b510 push {r4, lr}
+ 80000c2: 4c06 ldr r4, [pc, #24] ; (80000dc <__do_global_dtors_aux+0x1c>)
+ 80000c4: 7823 ldrb r3, [r4, #0]
+ 80000c6: 2b00 cmp r3, #0
+ 80000c8: d107 bne.n 80000da <__do_global_dtors_aux+0x1a>
+ 80000ca: 4b05 ldr r3, [pc, #20] ; (80000e0 <__do_global_dtors_aux+0x20>)
+ 80000cc: 2b00 cmp r3, #0
+ 80000ce: d002 beq.n 80000d6 <__do_global_dtors_aux+0x16>
+ 80000d0: 4804 ldr r0, [pc, #16] ; (80000e4 <__do_global_dtors_aux+0x24>)
+ 80000d2: e000 b.n 80000d6 <__do_global_dtors_aux+0x16>
+ 80000d4: bf00 nop
+ 80000d6: 2301 movs r3, #1
+ 80000d8: 7023 strb r3, [r4, #0]
+ 80000da: bd10 pop {r4, pc}
+ 80000dc: 20000004 .word 0x20000004
+ 80000e0: 00000000 .word 0x00000000
+ 80000e4: 08001128 .word 0x08001128
+
+080000e8 :
+ 80000e8: 4b04 ldr r3, [pc, #16] ; (80000fc )
+ 80000ea: b510 push {r4, lr}
+ 80000ec: 2b00 cmp r3, #0
+ 80000ee: d003 beq.n 80000f8
+ 80000f0: 4903 ldr r1, [pc, #12] ; (8000100 )
+ 80000f2: 4804 ldr r0, [pc, #16] ; (8000104 )
+ 80000f4: e000 b.n 80000f8
+ 80000f6: bf00 nop
+ 80000f8: bd10 pop {r4, pc}
+ 80000fa: 46c0 nop ; (mov r8, r8)
+ 80000fc: 00000000 .word 0x00000000
+ 8000100: 20000008 .word 0x20000008
+ 8000104: 08001128 .word 0x08001128
+
+08000108 <__udivsi3>:
+ 8000108: 2200 movs r2, #0
+ 800010a: 0843 lsrs r3, r0, #1
+ 800010c: 428b cmp r3, r1
+ 800010e: d374 bcc.n 80001fa <__udivsi3+0xf2>
+ 8000110: 0903 lsrs r3, r0, #4
+ 8000112: 428b cmp r3, r1
+ 8000114: d35f bcc.n 80001d6 <__udivsi3+0xce>
+ 8000116: 0a03 lsrs r3, r0, #8
+ 8000118: 428b cmp r3, r1
+ 800011a: d344 bcc.n 80001a6 <__udivsi3+0x9e>
+ 800011c: 0b03 lsrs r3, r0, #12
+ 800011e: 428b cmp r3, r1
+ 8000120: d328 bcc.n 8000174 <__udivsi3+0x6c>
+ 8000122: 0c03 lsrs r3, r0, #16
+ 8000124: 428b cmp r3, r1
+ 8000126: d30d bcc.n 8000144 <__udivsi3+0x3c>
+ 8000128: 22ff movs r2, #255 ; 0xff
+ 800012a: 0209 lsls r1, r1, #8
+ 800012c: ba12 rev r2, r2
+ 800012e: 0c03 lsrs r3, r0, #16
+ 8000130: 428b cmp r3, r1
+ 8000132: d302 bcc.n 800013a <__udivsi3+0x32>
+ 8000134: 1212 asrs r2, r2, #8
+ 8000136: 0209 lsls r1, r1, #8
+ 8000138: d065 beq.n 8000206 <__udivsi3+0xfe>
+ 800013a: 0b03 lsrs r3, r0, #12
+ 800013c: 428b cmp r3, r1
+ 800013e: d319 bcc.n 8000174 <__udivsi3+0x6c>
+ 8000140: e000 b.n 8000144 <__udivsi3+0x3c>
+ 8000142: 0a09 lsrs r1, r1, #8
+ 8000144: 0bc3 lsrs r3, r0, #15
+ 8000146: 428b cmp r3, r1
+ 8000148: d301 bcc.n 800014e <__udivsi3+0x46>
+ 800014a: 03cb lsls r3, r1, #15
+ 800014c: 1ac0 subs r0, r0, r3
+ 800014e: 4152 adcs r2, r2
+ 8000150: 0b83 lsrs r3, r0, #14
+ 8000152: 428b cmp r3, r1
+ 8000154: d301 bcc.n 800015a <__udivsi3+0x52>
+ 8000156: 038b lsls r3, r1, #14
+ 8000158: 1ac0 subs r0, r0, r3
+ 800015a: 4152 adcs r2, r2
+ 800015c: 0b43 lsrs r3, r0, #13
+ 800015e: 428b cmp r3, r1
+ 8000160: d301 bcc.n 8000166 <__udivsi3+0x5e>
+ 8000162: 034b lsls r3, r1, #13
+ 8000164: 1ac0 subs r0, r0, r3
+ 8000166: 4152 adcs r2, r2
+ 8000168: 0b03 lsrs r3, r0, #12
+ 800016a: 428b cmp r3, r1
+ 800016c: d301 bcc.n 8000172 <__udivsi3+0x6a>
+ 800016e: 030b lsls r3, r1, #12
+ 8000170: 1ac0 subs r0, r0, r3
+ 8000172: 4152 adcs r2, r2
+ 8000174: 0ac3 lsrs r3, r0, #11
+ 8000176: 428b cmp r3, r1
+ 8000178: d301 bcc.n 800017e <__udivsi3+0x76>
+ 800017a: 02cb lsls r3, r1, #11
+ 800017c: 1ac0 subs r0, r0, r3
+ 800017e: 4152 adcs r2, r2
+ 8000180: 0a83 lsrs r3, r0, #10
+ 8000182: 428b cmp r3, r1
+ 8000184: d301 bcc.n 800018a <__udivsi3+0x82>
+ 8000186: 028b lsls r3, r1, #10
+ 8000188: 1ac0 subs r0, r0, r3
+ 800018a: 4152 adcs r2, r2
+ 800018c: 0a43 lsrs r3, r0, #9
+ 800018e: 428b cmp r3, r1
+ 8000190: d301 bcc.n 8000196 <__udivsi3+0x8e>
+ 8000192: 024b lsls r3, r1, #9
+ 8000194: 1ac0 subs r0, r0, r3
+ 8000196: 4152 adcs r2, r2
+ 8000198: 0a03 lsrs r3, r0, #8
+ 800019a: 428b cmp r3, r1
+ 800019c: d301 bcc.n 80001a2 <__udivsi3+0x9a>
+ 800019e: 020b lsls r3, r1, #8
+ 80001a0: 1ac0 subs r0, r0, r3
+ 80001a2: 4152 adcs r2, r2
+ 80001a4: d2cd bcs.n 8000142 <__udivsi3+0x3a>
+ 80001a6: 09c3 lsrs r3, r0, #7
+ 80001a8: 428b cmp r3, r1
+ 80001aa: d301 bcc.n 80001b0 <__udivsi3+0xa8>
+ 80001ac: 01cb lsls r3, r1, #7
+ 80001ae: 1ac0 subs r0, r0, r3
+ 80001b0: 4152 adcs r2, r2
+ 80001b2: 0983 lsrs r3, r0, #6
+ 80001b4: 428b cmp r3, r1
+ 80001b6: d301 bcc.n 80001bc <__udivsi3+0xb4>
+ 80001b8: 018b lsls r3, r1, #6
+ 80001ba: 1ac0 subs r0, r0, r3
+ 80001bc: 4152 adcs r2, r2
+ 80001be: 0943 lsrs r3, r0, #5
+ 80001c0: 428b cmp r3, r1
+ 80001c2: d301 bcc.n 80001c8 <__udivsi3+0xc0>
+ 80001c4: 014b lsls r3, r1, #5
+ 80001c6: 1ac0 subs r0, r0, r3
+ 80001c8: 4152 adcs r2, r2
+ 80001ca: 0903 lsrs r3, r0, #4
+ 80001cc: 428b cmp r3, r1
+ 80001ce: d301 bcc.n 80001d4 <__udivsi3+0xcc>
+ 80001d0: 010b lsls r3, r1, #4
+ 80001d2: 1ac0 subs r0, r0, r3
+ 80001d4: 4152 adcs r2, r2
+ 80001d6: 08c3 lsrs r3, r0, #3
+ 80001d8: 428b cmp r3, r1
+ 80001da: d301 bcc.n 80001e0 <__udivsi3+0xd8>
+ 80001dc: 00cb lsls r3, r1, #3
+ 80001de: 1ac0 subs r0, r0, r3
+ 80001e0: 4152 adcs r2, r2
+ 80001e2: 0883 lsrs r3, r0, #2
+ 80001e4: 428b cmp r3, r1
+ 80001e6: d301 bcc.n 80001ec <__udivsi3+0xe4>
+ 80001e8: 008b lsls r3, r1, #2
+ 80001ea: 1ac0 subs r0, r0, r3
+ 80001ec: 4152 adcs r2, r2
+ 80001ee: 0843 lsrs r3, r0, #1
+ 80001f0: 428b cmp r3, r1
+ 80001f2: d301 bcc.n 80001f8 <__udivsi3+0xf0>
+ 80001f4: 004b lsls r3, r1, #1
+ 80001f6: 1ac0 subs r0, r0, r3
+ 80001f8: 4152 adcs r2, r2
+ 80001fa: 1a41 subs r1, r0, r1
+ 80001fc: d200 bcs.n 8000200 <__udivsi3+0xf8>
+ 80001fe: 4601 mov r1, r0
+ 8000200: 4152 adcs r2, r2
+ 8000202: 4610 mov r0, r2
+ 8000204: 4770 bx lr
+ 8000206: e7ff b.n 8000208 <__udivsi3+0x100>
+ 8000208: b501 push {r0, lr}
+ 800020a: 2000 movs r0, #0
+ 800020c: f000 f8f0 bl 80003f0 <__aeabi_idiv0>
+ 8000210: bd02 pop {r1, pc}
+ 8000212: 46c0 nop ; (mov r8, r8)
+
+08000214 <__aeabi_uidivmod>:
+ 8000214: 2900 cmp r1, #0
+ 8000216: d0f7 beq.n 8000208 <__udivsi3+0x100>
+ 8000218: e776 b.n 8000108 <__udivsi3>
+ 800021a: 4770 bx lr
+
+0800021c <__divsi3>:
+ 800021c: 4603 mov r3, r0
+ 800021e: 430b orrs r3, r1
+ 8000220: d47f bmi.n 8000322 <__divsi3+0x106>
+ 8000222: 2200 movs r2, #0
+ 8000224: 0843 lsrs r3, r0, #1
+ 8000226: 428b cmp r3, r1
+ 8000228: d374 bcc.n 8000314 <__divsi3+0xf8>
+ 800022a: 0903 lsrs r3, r0, #4
+ 800022c: 428b cmp r3, r1
+ 800022e: d35f bcc.n 80002f0 <__divsi3+0xd4>
+ 8000230: 0a03 lsrs r3, r0, #8
+ 8000232: 428b cmp r3, r1
+ 8000234: d344 bcc.n 80002c0 <__divsi3+0xa4>
+ 8000236: 0b03 lsrs r3, r0, #12
+ 8000238: 428b cmp r3, r1
+ 800023a: d328 bcc.n 800028e <__divsi3+0x72>
+ 800023c: 0c03 lsrs r3, r0, #16
+ 800023e: 428b cmp r3, r1
+ 8000240: d30d bcc.n 800025e <__divsi3+0x42>
+ 8000242: 22ff movs r2, #255 ; 0xff
+ 8000244: 0209 lsls r1, r1, #8
+ 8000246: ba12 rev r2, r2
+ 8000248: 0c03 lsrs r3, r0, #16
+ 800024a: 428b cmp r3, r1
+ 800024c: d302 bcc.n 8000254 <__divsi3+0x38>
+ 800024e: 1212 asrs r2, r2, #8
+ 8000250: 0209 lsls r1, r1, #8
+ 8000252: d065 beq.n 8000320 <__divsi3+0x104>
+ 8000254: 0b03 lsrs r3, r0, #12
+ 8000256: 428b cmp r3, r1
+ 8000258: d319 bcc.n 800028e <__divsi3+0x72>
+ 800025a: e000 b.n 800025e <__divsi3+0x42>
+ 800025c: 0a09 lsrs r1, r1, #8
+ 800025e: 0bc3 lsrs r3, r0, #15
+ 8000260: 428b cmp r3, r1
+ 8000262: d301 bcc.n 8000268 <__divsi3+0x4c>
+ 8000264: 03cb lsls r3, r1, #15
+ 8000266: 1ac0 subs r0, r0, r3
+ 8000268: 4152 adcs r2, r2
+ 800026a: 0b83 lsrs r3, r0, #14
+ 800026c: 428b cmp r3, r1
+ 800026e: d301 bcc.n 8000274 <__divsi3+0x58>
+ 8000270: 038b lsls r3, r1, #14
+ 8000272: 1ac0 subs r0, r0, r3
+ 8000274: 4152 adcs r2, r2
+ 8000276: 0b43 lsrs r3, r0, #13
+ 8000278: 428b cmp r3, r1
+ 800027a: d301 bcc.n 8000280 <__divsi3+0x64>
+ 800027c: 034b lsls r3, r1, #13
+ 800027e: 1ac0 subs r0, r0, r3
+ 8000280: 4152 adcs r2, r2
+ 8000282: 0b03 lsrs r3, r0, #12
+ 8000284: 428b cmp r3, r1
+ 8000286: d301 bcc.n 800028c <__divsi3+0x70>
+ 8000288: 030b lsls r3, r1, #12
+ 800028a: 1ac0 subs r0, r0, r3
+ 800028c: 4152 adcs r2, r2
+ 800028e: 0ac3 lsrs r3, r0, #11
+ 8000290: 428b cmp r3, r1
+ 8000292: d301 bcc.n 8000298 <__divsi3+0x7c>
+ 8000294: 02cb lsls r3, r1, #11
+ 8000296: 1ac0 subs r0, r0, r3
+ 8000298: 4152 adcs r2, r2
+ 800029a: 0a83 lsrs r3, r0, #10
+ 800029c: 428b cmp r3, r1
+ 800029e: d301 bcc.n 80002a4 <__divsi3+0x88>
+ 80002a0: 028b lsls r3, r1, #10
+ 80002a2: 1ac0 subs r0, r0, r3
+ 80002a4: 4152 adcs r2, r2
+ 80002a6: 0a43 lsrs r3, r0, #9
+ 80002a8: 428b cmp r3, r1
+ 80002aa: d301 bcc.n 80002b0 <__divsi3+0x94>
+ 80002ac: 024b lsls r3, r1, #9
+ 80002ae: 1ac0 subs r0, r0, r3
+ 80002b0: 4152 adcs r2, r2
+ 80002b2: 0a03 lsrs r3, r0, #8
+ 80002b4: 428b cmp r3, r1
+ 80002b6: d301 bcc.n 80002bc <__divsi3+0xa0>
+ 80002b8: 020b lsls r3, r1, #8
+ 80002ba: 1ac0 subs r0, r0, r3
+ 80002bc: 4152 adcs r2, r2
+ 80002be: d2cd bcs.n 800025c <__divsi3+0x40>
+ 80002c0: 09c3 lsrs r3, r0, #7
+ 80002c2: 428b cmp r3, r1
+ 80002c4: d301 bcc.n 80002ca <__divsi3+0xae>
+ 80002c6: 01cb lsls r3, r1, #7
+ 80002c8: 1ac0 subs r0, r0, r3
+ 80002ca: 4152 adcs r2, r2
+ 80002cc: 0983 lsrs r3, r0, #6
+ 80002ce: 428b cmp r3, r1
+ 80002d0: d301 bcc.n 80002d6 <__divsi3+0xba>
+ 80002d2: 018b lsls r3, r1, #6
+ 80002d4: 1ac0 subs r0, r0, r3
+ 80002d6: 4152 adcs r2, r2
+ 80002d8: 0943 lsrs r3, r0, #5
+ 80002da: 428b cmp r3, r1
+ 80002dc: d301 bcc.n 80002e2 <__divsi3+0xc6>
+ 80002de: 014b lsls r3, r1, #5
+ 80002e0: 1ac0 subs r0, r0, r3
+ 80002e2: 4152 adcs r2, r2
+ 80002e4: 0903 lsrs r3, r0, #4
+ 80002e6: 428b cmp r3, r1
+ 80002e8: d301 bcc.n 80002ee <__divsi3+0xd2>
+ 80002ea: 010b lsls r3, r1, #4
+ 80002ec: 1ac0 subs r0, r0, r3
+ 80002ee: 4152 adcs r2, r2
+ 80002f0: 08c3 lsrs r3, r0, #3
+ 80002f2: 428b cmp r3, r1
+ 80002f4: d301 bcc.n 80002fa <__divsi3+0xde>
+ 80002f6: 00cb lsls r3, r1, #3
+ 80002f8: 1ac0 subs r0, r0, r3
+ 80002fa: 4152 adcs r2, r2
+ 80002fc: 0883 lsrs r3, r0, #2
+ 80002fe: 428b cmp r3, r1
+ 8000300: d301 bcc.n 8000306 <__divsi3+0xea>
+ 8000302: 008b lsls r3, r1, #2
+ 8000304: 1ac0 subs r0, r0, r3
+ 8000306: 4152 adcs r2, r2
+ 8000308: 0843 lsrs r3, r0, #1
+ 800030a: 428b cmp r3, r1
+ 800030c: d301 bcc.n 8000312 <__divsi3+0xf6>
+ 800030e: 004b lsls r3, r1, #1
+ 8000310: 1ac0 subs r0, r0, r3
+ 8000312: 4152 adcs r2, r2
+ 8000314: 1a41 subs r1, r0, r1
+ 8000316: d200 bcs.n 800031a <__divsi3+0xfe>
+ 8000318: 4601 mov r1, r0
+ 800031a: 4152 adcs r2, r2
+ 800031c: 4610 mov r0, r2
+ 800031e: 4770 bx lr
+ 8000320: e05d b.n 80003de <__divsi3+0x1c2>
+ 8000322: 0fca lsrs r2, r1, #31
+ 8000324: d000 beq.n 8000328 <__divsi3+0x10c>
+ 8000326: 4249 negs r1, r1
+ 8000328: 1003 asrs r3, r0, #32
+ 800032a: d300 bcc.n 800032e <__divsi3+0x112>
+ 800032c: 4240 negs r0, r0
+ 800032e: 4053 eors r3, r2
+ 8000330: 2200 movs r2, #0
+ 8000332: 469c mov ip, r3
+ 8000334: 0903 lsrs r3, r0, #4
+ 8000336: 428b cmp r3, r1
+ 8000338: d32d bcc.n 8000396 <__divsi3+0x17a>
+ 800033a: 0a03 lsrs r3, r0, #8
+ 800033c: 428b cmp r3, r1
+ 800033e: d312 bcc.n 8000366 <__divsi3+0x14a>
+ 8000340: 22fc movs r2, #252 ; 0xfc
+ 8000342: 0189 lsls r1, r1, #6
+ 8000344: ba12 rev r2, r2
+ 8000346: 0a03 lsrs r3, r0, #8
+ 8000348: 428b cmp r3, r1
+ 800034a: d30c bcc.n 8000366 <__divsi3+0x14a>
+ 800034c: 0189 lsls r1, r1, #6
+ 800034e: 1192 asrs r2, r2, #6
+ 8000350: 428b cmp r3, r1
+ 8000352: d308 bcc.n 8000366 <__divsi3+0x14a>
+ 8000354: 0189 lsls r1, r1, #6
+ 8000356: 1192 asrs r2, r2, #6
+ 8000358: 428b cmp r3, r1
+ 800035a: d304 bcc.n 8000366 <__divsi3+0x14a>
+ 800035c: 0189 lsls r1, r1, #6
+ 800035e: d03a beq.n 80003d6 <__divsi3+0x1ba>
+ 8000360: 1192 asrs r2, r2, #6
+ 8000362: e000 b.n 8000366 <__divsi3+0x14a>
+ 8000364: 0989 lsrs r1, r1, #6
+ 8000366: 09c3 lsrs r3, r0, #7
+ 8000368: 428b cmp r3, r1
+ 800036a: d301 bcc.n 8000370 <__divsi3+0x154>
+ 800036c: 01cb lsls r3, r1, #7
+ 800036e: 1ac0 subs r0, r0, r3
+ 8000370: 4152 adcs r2, r2
+ 8000372: 0983 lsrs r3, r0, #6
+ 8000374: 428b cmp r3, r1
+ 8000376: d301 bcc.n 800037c <__divsi3+0x160>
+ 8000378: 018b lsls r3, r1, #6
+ 800037a: 1ac0 subs r0, r0, r3
+ 800037c: 4152 adcs r2, r2
+ 800037e: 0943 lsrs r3, r0, #5
+ 8000380: 428b cmp r3, r1
+ 8000382: d301 bcc.n 8000388 <__divsi3+0x16c>
+ 8000384: 014b lsls r3, r1, #5
+ 8000386: 1ac0 subs r0, r0, r3
+ 8000388: 4152 adcs r2, r2
+ 800038a: 0903 lsrs r3, r0, #4
+ 800038c: 428b cmp r3, r1
+ 800038e: d301 bcc.n 8000394 <__divsi3+0x178>
+ 8000390: 010b lsls r3, r1, #4
+ 8000392: 1ac0 subs r0, r0, r3
+ 8000394: 4152 adcs r2, r2
+ 8000396: 08c3 lsrs r3, r0, #3
+ 8000398: 428b cmp r3, r1
+ 800039a: d301 bcc.n 80003a0 <__divsi3+0x184>
+ 800039c: 00cb lsls r3, r1, #3
+ 800039e: 1ac0 subs r0, r0, r3
+ 80003a0: 4152 adcs r2, r2
+ 80003a2: 0883 lsrs r3, r0, #2
+ 80003a4: 428b cmp r3, r1
+ 80003a6: d301 bcc.n 80003ac <__divsi3+0x190>
+ 80003a8: 008b lsls r3, r1, #2
+ 80003aa: 1ac0 subs r0, r0, r3
+ 80003ac: 4152 adcs r2, r2
+ 80003ae: d2d9 bcs.n 8000364 <__divsi3+0x148>
+ 80003b0: 0843 lsrs r3, r0, #1
+ 80003b2: 428b cmp r3, r1
+ 80003b4: d301 bcc.n 80003ba <__divsi3+0x19e>
+ 80003b6: 004b lsls r3, r1, #1
+ 80003b8: 1ac0 subs r0, r0, r3
+ 80003ba: 4152 adcs r2, r2
+ 80003bc: 1a41 subs r1, r0, r1
+ 80003be: d200 bcs.n 80003c2 <__divsi3+0x1a6>
+ 80003c0: 4601 mov r1, r0
+ 80003c2: 4663 mov r3, ip
+ 80003c4: 4152 adcs r2, r2
+ 80003c6: 105b asrs r3, r3, #1
+ 80003c8: 4610 mov r0, r2
+ 80003ca: d301 bcc.n 80003d0 <__divsi3+0x1b4>
+ 80003cc: 4240 negs r0, r0
+ 80003ce: 2b00 cmp r3, #0
+ 80003d0: d500 bpl.n 80003d4 <__divsi3+0x1b8>
+ 80003d2: 4249 negs r1, r1
+ 80003d4: 4770 bx lr
+ 80003d6: 4663 mov r3, ip
+ 80003d8: 105b asrs r3, r3, #1
+ 80003da: d300 bcc.n 80003de <__divsi3+0x1c2>
+ 80003dc: 4240 negs r0, r0
+ 80003de: b501 push {r0, lr}
+ 80003e0: 2000 movs r0, #0
+ 80003e2: f000 f805 bl 80003f0 <__aeabi_idiv0>
+ 80003e6: bd02 pop {r1, pc}
+
+080003e8 <__aeabi_idivmod>:
+ 80003e8: 2900 cmp r1, #0
+ 80003ea: d0f8 beq.n 80003de <__divsi3+0x1c2>
+ 80003ec: e716 b.n 800021c <__divsi3>
+ 80003ee: 4770 bx lr
+
+080003f0 <__aeabi_idiv0>:
+ 80003f0: 4770 bx lr
+ 80003f2: 46c0 nop ; (mov r8, r8)
+
+080003f4 <__aeabi_uldivmod>:
+ 80003f4: 2b00 cmp r3, #0
+ 80003f6: d111 bne.n 800041c <__aeabi_uldivmod+0x28>
+ 80003f8: 2a00 cmp r2, #0
+ 80003fa: d10f bne.n 800041c <__aeabi_uldivmod+0x28>
+ 80003fc: 2900 cmp r1, #0
+ 80003fe: d100 bne.n 8000402 <__aeabi_uldivmod+0xe>
+ 8000400: 2800 cmp r0, #0
+ 8000402: d002 beq.n 800040a <__aeabi_uldivmod+0x16>
+ 8000404: 2100 movs r1, #0
+ 8000406: 43c9 mvns r1, r1
+ 8000408: 1c08 adds r0, r1, #0
+ 800040a: b407 push {r0, r1, r2}
+ 800040c: 4802 ldr r0, [pc, #8] ; (8000418 <__aeabi_uldivmod+0x24>)
+ 800040e: a102 add r1, pc, #8 ; (adr r1, 8000418 <__aeabi_uldivmod+0x24>)
+ 8000410: 1840 adds r0, r0, r1
+ 8000412: 9002 str r0, [sp, #8]
+ 8000414: bd03 pop {r0, r1, pc}
+ 8000416: 46c0 nop ; (mov r8, r8)
+ 8000418: ffffffd9 .word 0xffffffd9
+ 800041c: b403 push {r0, r1}
+ 800041e: 4668 mov r0, sp
+ 8000420: b501 push {r0, lr}
+ 8000422: 9802 ldr r0, [sp, #8]
+ 8000424: f000 f806 bl 8000434 <__udivmoddi4>
+ 8000428: 9b01 ldr r3, [sp, #4]
+ 800042a: 469e mov lr, r3
+ 800042c: b002 add sp, #8
+ 800042e: bc0c pop {r2, r3}
+ 8000430: 4770 bx lr
+ 8000432: 46c0 nop ; (mov r8, r8)
+
+08000434 <__udivmoddi4>:
+ 8000434: b5f0 push {r4, r5, r6, r7, lr}
+ 8000436: 4657 mov r7, sl
+ 8000438: 464e mov r6, r9
+ 800043a: 4645 mov r5, r8
+ 800043c: 46de mov lr, fp
+ 800043e: b5e0 push {r5, r6, r7, lr}
+ 8000440: 0004 movs r4, r0
+ 8000442: 000d movs r5, r1
+ 8000444: 4692 mov sl, r2
+ 8000446: 4699 mov r9, r3
+ 8000448: b083 sub sp, #12
+ 800044a: 428b cmp r3, r1
+ 800044c: d830 bhi.n 80004b0 <__udivmoddi4+0x7c>
+ 800044e: d02d beq.n 80004ac <__udivmoddi4+0x78>
+ 8000450: 4649 mov r1, r9
+ 8000452: 4650 mov r0, sl
+ 8000454: f000 f8ba bl 80005cc <__clzdi2>
+ 8000458: 0029 movs r1, r5
+ 800045a: 0006 movs r6, r0
+ 800045c: 0020 movs r0, r4
+ 800045e: f000 f8b5 bl 80005cc <__clzdi2>
+ 8000462: 1a33 subs r3, r6, r0
+ 8000464: 4698 mov r8, r3
+ 8000466: 3b20 subs r3, #32
+ 8000468: 469b mov fp, r3
+ 800046a: d433 bmi.n 80004d4 <__udivmoddi4+0xa0>
+ 800046c: 465a mov r2, fp
+ 800046e: 4653 mov r3, sl
+ 8000470: 4093 lsls r3, r2
+ 8000472: 4642 mov r2, r8
+ 8000474: 001f movs r7, r3
+ 8000476: 4653 mov r3, sl
+ 8000478: 4093 lsls r3, r2
+ 800047a: 001e movs r6, r3
+ 800047c: 42af cmp r7, r5
+ 800047e: d83a bhi.n 80004f6 <__udivmoddi4+0xc2>
+ 8000480: 42af cmp r7, r5
+ 8000482: d100 bne.n 8000486 <__udivmoddi4+0x52>
+ 8000484: e078 b.n 8000578 <__udivmoddi4+0x144>
+ 8000486: 465b mov r3, fp
+ 8000488: 1ba4 subs r4, r4, r6
+ 800048a: 41bd sbcs r5, r7
+ 800048c: 2b00 cmp r3, #0
+ 800048e: da00 bge.n 8000492 <__udivmoddi4+0x5e>
+ 8000490: e075 b.n 800057e <__udivmoddi4+0x14a>
+ 8000492: 2200 movs r2, #0
+ 8000494: 2300 movs r3, #0
+ 8000496: 9200 str r2, [sp, #0]
+ 8000498: 9301 str r3, [sp, #4]
+ 800049a: 2301 movs r3, #1
+ 800049c: 465a mov r2, fp
+ 800049e: 4093 lsls r3, r2
+ 80004a0: 9301 str r3, [sp, #4]
+ 80004a2: 2301 movs r3, #1
+ 80004a4: 4642 mov r2, r8
+ 80004a6: 4093 lsls r3, r2
+ 80004a8: 9300 str r3, [sp, #0]
+ 80004aa: e028 b.n 80004fe <__udivmoddi4+0xca>
+ 80004ac: 4282 cmp r2, r0
+ 80004ae: d9cf bls.n 8000450 <__udivmoddi4+0x1c>
+ 80004b0: 2200 movs r2, #0
+ 80004b2: 2300 movs r3, #0
+ 80004b4: 9200 str r2, [sp, #0]
+ 80004b6: 9301 str r3, [sp, #4]
+ 80004b8: 9b0c ldr r3, [sp, #48] ; 0x30
+ 80004ba: 2b00 cmp r3, #0
+ 80004bc: d001 beq.n 80004c2 <__udivmoddi4+0x8e>
+ 80004be: 601c str r4, [r3, #0]
+ 80004c0: 605d str r5, [r3, #4]
+ 80004c2: 9800 ldr r0, [sp, #0]
+ 80004c4: 9901 ldr r1, [sp, #4]
+ 80004c6: b003 add sp, #12
+ 80004c8: bcf0 pop {r4, r5, r6, r7}
+ 80004ca: 46bb mov fp, r7
+ 80004cc: 46b2 mov sl, r6
+ 80004ce: 46a9 mov r9, r5
+ 80004d0: 46a0 mov r8, r4
+ 80004d2: bdf0 pop {r4, r5, r6, r7, pc}
+ 80004d4: 4642 mov r2, r8
+ 80004d6: 2320 movs r3, #32
+ 80004d8: 1a9b subs r3, r3, r2
+ 80004da: 4652 mov r2, sl
+ 80004dc: 40da lsrs r2, r3
+ 80004de: 4641 mov r1, r8
+ 80004e0: 0013 movs r3, r2
+ 80004e2: 464a mov r2, r9
+ 80004e4: 408a lsls r2, r1
+ 80004e6: 0017 movs r7, r2
+ 80004e8: 4642 mov r2, r8
+ 80004ea: 431f orrs r7, r3
+ 80004ec: 4653 mov r3, sl
+ 80004ee: 4093 lsls r3, r2
+ 80004f0: 001e movs r6, r3
+ 80004f2: 42af cmp r7, r5
+ 80004f4: d9c4 bls.n 8000480 <__udivmoddi4+0x4c>
+ 80004f6: 2200 movs r2, #0
+ 80004f8: 2300 movs r3, #0
+ 80004fa: 9200 str r2, [sp, #0]
+ 80004fc: 9301 str r3, [sp, #4]
+ 80004fe: 4643 mov r3, r8
+ 8000500: 2b00 cmp r3, #0
+ 8000502: d0d9 beq.n 80004b8 <__udivmoddi4+0x84>
+ 8000504: 07fb lsls r3, r7, #31
+ 8000506: 0872 lsrs r2, r6, #1
+ 8000508: 431a orrs r2, r3
+ 800050a: 4646 mov r6, r8
+ 800050c: 087b lsrs r3, r7, #1
+ 800050e: e00e b.n 800052e <__udivmoddi4+0xfa>
+ 8000510: 42ab cmp r3, r5
+ 8000512: d101 bne.n 8000518 <__udivmoddi4+0xe4>
+ 8000514: 42a2 cmp r2, r4
+ 8000516: d80c bhi.n 8000532 <__udivmoddi4+0xfe>
+ 8000518: 1aa4 subs r4, r4, r2
+ 800051a: 419d sbcs r5, r3
+ 800051c: 2001 movs r0, #1
+ 800051e: 1924 adds r4, r4, r4
+ 8000520: 416d adcs r5, r5
+ 8000522: 2100 movs r1, #0
+ 8000524: 3e01 subs r6, #1
+ 8000526: 1824 adds r4, r4, r0
+ 8000528: 414d adcs r5, r1
+ 800052a: 2e00 cmp r6, #0
+ 800052c: d006 beq.n 800053c <__udivmoddi4+0x108>
+ 800052e: 42ab cmp r3, r5
+ 8000530: d9ee bls.n 8000510 <__udivmoddi4+0xdc>
+ 8000532: 3e01 subs r6, #1
+ 8000534: 1924 adds r4, r4, r4
+ 8000536: 416d adcs r5, r5
+ 8000538: 2e00 cmp r6, #0
+ 800053a: d1f8 bne.n 800052e <__udivmoddi4+0xfa>
+ 800053c: 9800 ldr r0, [sp, #0]
+ 800053e: 9901 ldr r1, [sp, #4]
+ 8000540: 465b mov r3, fp
+ 8000542: 1900 adds r0, r0, r4
+ 8000544: 4169 adcs r1, r5
+ 8000546: 2b00 cmp r3, #0
+ 8000548: db24 blt.n 8000594 <__udivmoddi4+0x160>
+ 800054a: 002b movs r3, r5
+ 800054c: 465a mov r2, fp
+ 800054e: 4644 mov r4, r8
+ 8000550: 40d3 lsrs r3, r2
+ 8000552: 002a movs r2, r5
+ 8000554: 40e2 lsrs r2, r4
+ 8000556: 001c movs r4, r3
+ 8000558: 465b mov r3, fp
+ 800055a: 0015 movs r5, r2
+ 800055c: 2b00 cmp r3, #0
+ 800055e: db2a blt.n 80005b6 <__udivmoddi4+0x182>
+ 8000560: 0026 movs r6, r4
+ 8000562: 409e lsls r6, r3
+ 8000564: 0033 movs r3, r6
+ 8000566: 0026 movs r6, r4
+ 8000568: 4647 mov r7, r8
+ 800056a: 40be lsls r6, r7
+ 800056c: 0032 movs r2, r6
+ 800056e: 1a80 subs r0, r0, r2
+ 8000570: 4199 sbcs r1, r3
+ 8000572: 9000 str r0, [sp, #0]
+ 8000574: 9101 str r1, [sp, #4]
+ 8000576: e79f b.n 80004b8 <__udivmoddi4+0x84>
+ 8000578: 42a3 cmp r3, r4
+ 800057a: d8bc bhi.n 80004f6 <__udivmoddi4+0xc2>
+ 800057c: e783 b.n 8000486 <__udivmoddi4+0x52>
+ 800057e: 4642 mov r2, r8
+ 8000580: 2320 movs r3, #32
+ 8000582: 2100 movs r1, #0
+ 8000584: 1a9b subs r3, r3, r2
+ 8000586: 2200 movs r2, #0
+ 8000588: 9100 str r1, [sp, #0]
+ 800058a: 9201 str r2, [sp, #4]
+ 800058c: 2201 movs r2, #1
+ 800058e: 40da lsrs r2, r3
+ 8000590: 9201 str r2, [sp, #4]
+ 8000592: e786 b.n 80004a2 <__udivmoddi4+0x6e>
+ 8000594: 4642 mov r2, r8
+ 8000596: 2320 movs r3, #32
+ 8000598: 1a9b subs r3, r3, r2
+ 800059a: 002a movs r2, r5
+ 800059c: 4646 mov r6, r8
+ 800059e: 409a lsls r2, r3
+ 80005a0: 0023 movs r3, r4
+ 80005a2: 40f3 lsrs r3, r6
+ 80005a4: 4644 mov r4, r8
+ 80005a6: 4313 orrs r3, r2
+ 80005a8: 002a movs r2, r5
+ 80005aa: 40e2 lsrs r2, r4
+ 80005ac: 001c movs r4, r3
+ 80005ae: 465b mov r3, fp
+ 80005b0: 0015 movs r5, r2
+ 80005b2: 2b00 cmp r3, #0
+ 80005b4: dad4 bge.n 8000560 <__udivmoddi4+0x12c>
+ 80005b6: 4642 mov r2, r8
+ 80005b8: 002f movs r7, r5
+ 80005ba: 2320 movs r3, #32
+ 80005bc: 0026 movs r6, r4
+ 80005be: 4097 lsls r7, r2
+ 80005c0: 1a9b subs r3, r3, r2
+ 80005c2: 40de lsrs r6, r3
+ 80005c4: 003b movs r3, r7
+ 80005c6: 4333 orrs r3, r6
+ 80005c8: e7cd b.n 8000566 <__udivmoddi4+0x132>
+ 80005ca: 46c0 nop ; (mov r8, r8)
+
+080005cc <__clzdi2>:
+ 80005cc: b510 push {r4, lr}
+ 80005ce: 2900 cmp r1, #0
+ 80005d0: d103 bne.n 80005da <__clzdi2+0xe>
+ 80005d2: f000 f807 bl 80005e4 <__clzsi2>
+ 80005d6: 3020 adds r0, #32
+ 80005d8: e002 b.n 80005e0 <__clzdi2+0x14>
+ 80005da: 1c08 adds r0, r1, #0
+ 80005dc: f000 f802 bl 80005e4 <__clzsi2>
+ 80005e0: bd10 pop {r4, pc}
+ 80005e2: 46c0 nop ; (mov r8, r8)
+
+080005e4 <__clzsi2>:
+ 80005e4: 211c movs r1, #28
+ 80005e6: 2301 movs r3, #1
+ 80005e8: 041b lsls r3, r3, #16
+ 80005ea: 4298 cmp r0, r3
+ 80005ec: d301 bcc.n 80005f2 <__clzsi2+0xe>
+ 80005ee: 0c00 lsrs r0, r0, #16
+ 80005f0: 3910 subs r1, #16
+ 80005f2: 0a1b lsrs r3, r3, #8
+ 80005f4: 4298 cmp r0, r3
+ 80005f6: d301 bcc.n 80005fc <__clzsi2+0x18>
+ 80005f8: 0a00 lsrs r0, r0, #8
+ 80005fa: 3908 subs r1, #8
+ 80005fc: 091b lsrs r3, r3, #4
+ 80005fe: 4298 cmp r0, r3
+ 8000600: d301 bcc.n 8000606 <__clzsi2+0x22>
+ 8000602: 0900 lsrs r0, r0, #4
+ 8000604: 3904 subs r1, #4
+ 8000606: a202 add r2, pc, #8 ; (adr r2, 8000610 <__clzsi2+0x2c>)
+ 8000608: 5c10 ldrb r0, [r2, r0]
+ 800060a: 1840 adds r0, r0, r1
+ 800060c: 4770 bx lr
+ 800060e: 46c0 nop ; (mov r8, r8)
+ 8000610: 02020304 .word 0x02020304
+ 8000614: 01010101 .word 0x01010101
+ ...
+
+08000620 :
+
+i2c_context_t *i2c_context;
+
+int i2c_init(i2c_context_t *context)
+{
+ if (context == NULL) {
+ 8000620: 2800 cmp r0, #0
+ 8000622: d003 beq.n 800062c
+ return I2C_ERROR;
+ }
+ i2c_context = context;
+ 8000624: 4b03 ldr r3, [pc, #12] ; (8000634 )
+ 8000626: 6018 str r0, [r3, #0]
+ return I2C_OK;
+ 8000628: 2000 movs r0, #0
+}
+ 800062a: 4770 bx lr
+ return I2C_ERROR;
+ 800062c: 2001 movs r0, #1
+ 800062e: 4240 negs r0, r0
+ 8000630: e7fb b.n 800062a
+ 8000632: 46c0 nop ; (mov r8, r8)
+ 8000634: 20000024 .word 0x20000024
+
+08000638 :
+
+int i2c_transmit(uint8_t address, uint8_t *buffer, int len)
+{
+ LL_I2C_HandleTransfer(i2c_context->i2c, address, LL_I2C_ADDRSLAVE_7BIT, len,
+ 8000638: 4b15 ldr r3, [pc, #84] ; (8000690 )
+{
+ 800063a: b570 push {r4, r5, r6, lr}
+ LL_I2C_HandleTransfer(i2c_context->i2c, address, LL_I2C_ADDRSLAVE_7BIT, len,
+ 800063c: 681b ldr r3, [r3, #0]
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_HandleTransfer(I2C_TypeDef *I2Cx, uint32_t SlaveAddr, uint32_t SlaveAddrSize,
+ uint32_t TransferSize, uint32_t EndMode, uint32_t Request)
+{
+ MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD | I2C_CR2_ADD10 |
+ 800063e: 0414 lsls r4, r2, #16
+ 8000640: 681b ldr r3, [r3, #0]
+ 8000642: 4304 orrs r4, r0
+ 8000644: 685d ldr r5, [r3, #4]
+ 8000646: 4813 ldr r0, [pc, #76] ; (8000694 )
+ 8000648: 4005 ands r5, r0
+ 800064a: 4813 ldr r0, [pc, #76] ; (8000698 )
+ 800064c: 432c orrs r4, r5
+ 800064e: 4304 orrs r4, r0
+ 8000650: 605c str r4, [r3, #4]
+ return ((READ_BIT(I2Cx->ISR, I2C_ISR_STOPF) == (I2C_ISR_STOPF)) ? 1UL : 0UL);
+ 8000652: 2020 movs r0, #32
+ (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) |
+ I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_RELOAD |
+ I2C_CR2_NBYTES | I2C_CR2_AUTOEND | I2C_CR2_HEAD10R,
+ SlaveAddr | SlaveAddrSize | (TransferSize << I2C_CR2_NBYTES_Pos) | EndMode | Request);
+}
+ 8000654: 2400 movs r4, #0
+ return ((READ_BIT(I2Cx->ISR, I2C_ISR_TXE) == (I2C_ISR_TXE)) ? 1UL : 0UL);
+ 8000656: 2501 movs r5, #1
+ return ((READ_BIT(I2Cx->ISR, I2C_ISR_STOPF) == (I2C_ISR_STOPF)) ? 1UL : 0UL);
+ 8000658: 699e ldr r6, [r3, #24]
+ 800065a: 4206 tst r6, r0
+ 800065c: d00d beq.n 800067a
+ SET_BIT(I2Cx->ICR, I2C_ICR_STOPCF);
+ 800065e: 69d9 ldr r1, [r3, #28]
+ 8000660: 4301 orrs r1, r0
+ 8000662: 61d9 str r1, [r3, #28]
+ return ((READ_BIT(I2Cx->ISR, I2C_ISR_NACKF) == (I2C_ISR_NACKF)) ? 1UL : 0UL);
+ 8000664: 6999 ldr r1, [r3, #24]
+ 8000666: 2310 movs r3, #16
+ 8000668: 0008 movs r0, r1
+ 800066a: 4018 ands r0, r3
+ 800066c: 4219 tst r1, r3
+ 800066e: d10d bne.n 800068c
+ }
+ LL_I2C_ClearFlag_STOP(i2c_context->i2c);
+ if (LL_I2C_IsActiveFlag_NACK(i2c_context->i2c)) {
+ return I2C_ERROR_NACK;
+ }
+ if (len != i) {
+ 8000670: 42a2 cmp r2, r4
+ 8000672: d001 beq.n 8000678
+ // this will probably never happen, as NACK flag
+ // is raised everytime len != number of TXed bytes
+ return I2C_ERROR_TX_INCOMPLETE;
+ 8000674: 2003 movs r0, #3
+ return I2C_ERROR_NACK;
+ 8000676: 4240 negs r0, r0
+ }
+ return I2C_OK;
+}
+ 8000678: bd70 pop {r4, r5, r6, pc}
+ return ((READ_BIT(I2Cx->ISR, I2C_ISR_TXE) == (I2C_ISR_TXE)) ? 1UL : 0UL);
+ 800067a: 699e ldr r6, [r3, #24]
+ if (LL_I2C_IsActiveFlag_TXE(i2c_context->i2c)) {
+ 800067c: 422e tst r6, r5
+ 800067e: d0eb beq.n 8000658
+ if (i < len) {
+ 8000680: 42a2 cmp r2, r4
+ 8000682: dde9 ble.n 8000658
+ * @param Data Value between Min_Data=0x00 and Max_Data=0xFF
+ * @retval None
+ */
+__STATIC_INLINE void LL_I2C_TransmitData8(I2C_TypeDef *I2Cx, uint8_t Data)
+{
+ WRITE_REG(I2Cx->TXDR, Data);
+ 8000684: 5d0e ldrb r6, [r1, r4]
+ 8000686: 3401 adds r4, #1
+ 8000688: 629e str r6, [r3, #40] ; 0x28
+}
+ 800068a: e7e5 b.n 8000658
+ return I2C_ERROR_NACK;
+ 800068c: 2002 movs r0, #2
+ 800068e: e7f2 b.n 8000676
+ 8000690: 20000024 .word 0x20000024
+ 8000694: fc008000 .word 0xfc008000
+ 8000698: 82002000 .word 0x82002000
+
+0800069c :
+
+int i2c_receive(uint8_t address, uint8_t *buffer, int len)
+{
+ 800069c: b5f0 push {r4, r5, r6, r7, lr}
+ LL_I2C_HandleTransfer(i2c_context->i2c, address, LL_I2C_ADDRSLAVE_7BIT, len,
+ 800069e: 4d12 ldr r5, [pc, #72] ; (80006e8 )
+ 80006a0: 682b ldr r3, [r5, #0]
+ 80006a2: 681c ldr r4, [r3, #0]
+ MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD | I2C_CR2_ADD10 |
+ 80006a4: 0413 lsls r3, r2, #16
+ 80006a6: 6866 ldr r6, [r4, #4]
+ 80006a8: 4303 orrs r3, r0
+ 80006aa: 4810 ldr r0, [pc, #64] ; (80006ec )
+ 80006ac: 4006 ands r6, r0
+ 80006ae: 4810 ldr r0, [pc, #64] ; (80006f0 )
+ 80006b0: 4333 orrs r3, r6
+ 80006b2: 4303 orrs r3, r0
+ 80006b4: 6063 str r3, [r4, #4]
+ return ((READ_BIT(I2Cx->ISR, I2C_ISR_RXNE) == (I2C_ISR_RXNE)) ? 1UL : 0UL);
+ 80006b6: 2604 movs r6, #4
+}
+ 80006b8: 2300 movs r3, #0
+ return ((READ_BIT(I2Cx->ISR, I2C_ISR_STOPF) == (I2C_ISR_STOPF)) ? 1UL : 0UL);
+ 80006ba: 2420 movs r4, #32
+ LL_I2C_MODE_AUTOEND, LL_I2C_GENERATE_START_READ);
+ int i = 0;
+ while (!LL_I2C_IsActiveFlag_STOP(i2c_context->i2c)) {
+ 80006bc: 6828 ldr r0, [r5, #0]
+ 80006be: 6800 ldr r0, [r0, #0]
+ 80006c0: 6987 ldr r7, [r0, #24]
+ 80006c2: 4227 tst r7, r4
+ 80006c4: d108 bne.n 80006d8
+ return ((READ_BIT(I2Cx->ISR, I2C_ISR_RXNE) == (I2C_ISR_RXNE)) ? 1UL : 0UL);
+ 80006c6: 6987 ldr r7, [r0, #24]
+ 80006c8: 4237 tst r7, r6
+ 80006ca: d0f9 beq.n 80006c0
+ if (LL_I2C_IsActiveFlag_RXNE(i2c_context->i2c)) {
+ if (i < len) {
+ 80006cc: 429a cmp r2, r3
+ 80006ce: ddf7 ble.n 80006c0
+ return (uint8_t)(READ_BIT(I2Cx->RXDR, I2C_RXDR_RXDATA));
+ 80006d0: 6a40 ldr r0, [r0, #36] ; 0x24
+ 80006d2: 54c8 strb r0, [r1, r3]
+ 80006d4: 3301 adds r3, #1
+ 80006d6: e7f1 b.n 80006bc
+ SET_BIT(I2Cx->ICR, I2C_ICR_STOPCF);
+ 80006d8: 69c1 ldr r1, [r0, #28]
+ 80006da: 430c orrs r4, r1
+ 80006dc: 61c4 str r4, [r0, #28]
+ }
+ LL_I2C_ClearFlag_STOP(i2c_context->i2c);
+ if (len != i) {
+ return I2C_ERROR_RX_INCOMPLETE;
+ }
+ return I2C_OK; // TODO error detection
+ 80006de: 2000 movs r0, #0
+ if (len != i) {
+ 80006e0: 429a cmp r2, r3
+ 80006e2: d000 beq.n 80006e6
+ return I2C_ERROR_RX_INCOMPLETE;
+ 80006e4: 3804 subs r0, #4
+}
+ 80006e6: bdf0 pop {r4, r5, r6, r7, pc}
+ 80006e8: 20000024 .word 0x20000024
+ 80006ec: fc008000 .word 0xfc008000
+ 80006f0: 82002400 .word 0x82002400
+
+080006f4 :
+ * uint8_t blue: blue color intensity, possible values 0 ... 255
+ * NOTE: if (color * led_pwm_max) < 255, LED will be off
+ */
+void led_set_color(uint8_t red, uint8_t green, uint8_t blue)
+{
+ led_red_intensity = (int)red * led_pwm_max / 255;
+ 80006f4: 4b0c ldr r3, [pc, #48] ; (8000728 )
+{
+ 80006f6: b570 push {r4, r5, r6, lr}
+ led_red_intensity = (int)red * led_pwm_max / 255;
+ 80006f8: 681c ldr r4, [r3, #0]
+{
+ 80006fa: 000d movs r5, r1
+ led_red_intensity = (int)red * led_pwm_max / 255;
+ 80006fc: 4360 muls r0, r4
+ 80006fe: 21ff movs r1, #255 ; 0xff
+{
+ 8000700: 0016 movs r6, r2
+ led_red_intensity = (int)red * led_pwm_max / 255;
+ 8000702: f7ff fd8b bl 800021c <__divsi3>
+ 8000706: 4b09 ldr r3, [pc, #36] ; (800072c )
+ led_green_intensity = (int)green * led_pwm_max / 255;
+ 8000708: 21ff movs r1, #255 ; 0xff
+ led_red_intensity = (int)red * led_pwm_max / 255;
+ 800070a: 6018 str r0, [r3, #0]
+ led_green_intensity = (int)green * led_pwm_max / 255;
+ 800070c: 0028 movs r0, r5
+ 800070e: 4360 muls r0, r4
+ 8000710: f7ff fd84 bl 800021c <__divsi3>
+ 8000714: 4b06 ldr r3, [pc, #24] ; (8000730 )
+ led_blue_intensity = (int)blue * led_pwm_max / 255;
+ 8000716: 21ff movs r1, #255 ; 0xff
+ led_green_intensity = (int)green * led_pwm_max / 255;
+ 8000718: 6018 str r0, [r3, #0]
+ led_blue_intensity = (int)blue * led_pwm_max / 255;
+ 800071a: 0020 movs r0, r4
+ 800071c: 4370 muls r0, r6
+ 800071e: f7ff fd7d bl 800021c <__divsi3>
+ 8000722: 4b04 ldr r3, [pc, #16] ; (8000734 )
+ 8000724: 6018 str r0, [r3, #0]
+}
+ 8000726: bd70 pop {r4, r5, r6, pc}
+ 8000728: 2000002c .word 0x2000002c
+ 800072c: 20000030 .word 0x20000030
+ 8000730: 20000028 .word 0x20000028
+ 8000734: 20000038 .word 0x20000038
+
+08000738 :
+ */
+void led_pwm_handler()
+{
+ int new_red_state, new_green_state, new_blue_state;
+
+ if (led_context == NULL) {
+ 8000738: 4b27 ldr r3, [pc, #156] ; (80007d8 )
+{
+ 800073a: b5f0 push {r4, r5, r6, r7, lr}
+ if (led_context == NULL) {
+ 800073c: 681a ldr r2, [r3, #0]
+ 800073e: 2a00 cmp r2, #0
+ 8000740: d049 beq.n 80007d6
+ // led_pwm_handler() may be called before led_init() was called;
+ // this would result in a crash
+ return;
+ }
+
+ new_red_state = led_pwm_counter >= led_red_intensity ? 1 : 0;
+ 8000742: 4926 ldr r1, [pc, #152] ; (80007dc )
+ 8000744: 4b26 ldr r3, [pc, #152] ; (80007e0 )
+ 8000746: 6808 ldr r0, [r1, #0]
+ 8000748: 681b ldr r3, [r3, #0]
+ 800074a: 0fc5 lsrs r5, r0, #31
+ 800074c: 17d9 asrs r1, r3, #31
+ 800074e: 4283 cmp r3, r0
+ 8000750: 414d adcs r5, r1
+ new_green_state = led_pwm_counter >= led_green_intensity ? 1 : 0;
+ 8000752: 4824 ldr r0, [pc, #144] ; (80007e4 )
+ new_blue_state = led_pwm_counter >= led_blue_intensity ? 1 : 0;
+ // SysTick() is called at 1 kHz frequency, we don't want to call HAL_GPIO_WritePin() every time
+ if (led_red_state != new_red_state) {
+ 8000754: 4f24 ldr r7, [pc, #144] ; (80007e8 )
+ new_green_state = led_pwm_counter >= led_green_intensity ? 1 : 0;
+ 8000756: 6800 ldr r0, [r0, #0]
+ 8000758: 0fc4 lsrs r4, r0, #31
+ 800075a: 4283 cmp r3, r0
+ 800075c: 414c adcs r4, r1
+ new_blue_state = led_pwm_counter >= led_blue_intensity ? 1 : 0;
+ 800075e: 4823 ldr r0, [pc, #140] ; (80007ec )
+ 8000760: 6800 ldr r0, [r0, #0]
+ 8000762: 0fc6 lsrs r6, r0, #31
+ 8000764: 4283 cmp r3, r0
+ 8000766: 4171 adcs r1, r6
+ 8000768: 468c mov ip, r1
+ if (led_red_state != new_red_state) {
+ 800076a: 6839 ldr r1, [r7, #0]
+ 800076c: 42a9 cmp r1, r5
+ 800076e: d00b beq.n 8000788
+ * @arg @ref LL_GPIO_PIN_ALL
+ * @retval None
+ */
+__STATIC_INLINE void LL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
+{
+ uint32_t odr = READ_REG(GPIOx->ODR);
+ 8000770: 6811 ldr r1, [r2, #0]
+ WRITE_REG(GPIOx->BSRR, ((odr & PinMask) << 16u) | (~odr & PinMask));
+ 8000772: 6850 ldr r0, [r2, #4]
+ uint32_t odr = READ_REG(GPIOx->ODR);
+ 8000774: 694e ldr r6, [r1, #20]
+ WRITE_REG(GPIOx->BSRR, ((odr & PinMask) << 16u) | (~odr & PinMask));
+ 8000776: 6851 ldr r1, [r2, #4]
+ 8000778: 4030 ands r0, r6
+ 800077a: 43b1 bics r1, r6
+ 800077c: 000e movs r6, r1
+ 800077e: 0400 lsls r0, r0, #16
+ 8000780: 6811 ldr r1, [r2, #0]
+ 8000782: 4306 orrs r6, r0
+ 8000784: 618e str r6, [r1, #24]
+ LL_GPIO_TogglePin(led_context->red_led_port, led_context->red_led_pin);
+ led_red_state = new_red_state;
+ 8000786: 603d str r5, [r7, #0]
+ }
+ if (led_green_state != new_green_state) {
+ 8000788: 4e19 ldr r6, [pc, #100] ; (80007f0 )
+ 800078a: 6831 ldr r1, [r6, #0]
+ 800078c: 42a1 cmp r1, r4
+ 800078e: d00a beq.n 80007a6
+ LL_GPIO_TogglePin(led_context->green_led_port, led_context->green_led_pin);
+ 8000790: 6897 ldr r7, [r2, #8]
+ 8000792: 68d1 ldr r1, [r2, #12]
+ uint32_t odr = READ_REG(GPIOx->ODR);
+ 8000794: 6978 ldr r0, [r7, #20]
+ WRITE_REG(GPIOx->BSRR, ((odr & PinMask) << 16u) | (~odr & PinMask));
+ 8000796: 68d5 ldr r5, [r2, #12]
+ 8000798: 4381 bics r1, r0
+ 800079a: 4005 ands r5, r0
+ 800079c: 0008 movs r0, r1
+ 800079e: 042d lsls r5, r5, #16
+ 80007a0: 4328 orrs r0, r5
+ 80007a2: 61b8 str r0, [r7, #24]
+ led_green_state = new_green_state;
+ 80007a4: 6034 str r4, [r6, #0]
+ }
+ if (led_blue_state != new_blue_state) {
+ 80007a6: 4c13 ldr r4, [pc, #76] ; (80007f4 )
+ 80007a8: 6821 ldr r1, [r4, #0]
+ 80007aa: 4561 cmp r1, ip
+ 80007ac: d00a beq.n 80007c4
+ LL_GPIO_TogglePin(led_context->blue_led_port, led_context->blue_led_pin);
+ 80007ae: 6915 ldr r5, [r2, #16]
+ 80007b0: 6950 ldr r0, [r2, #20]
+ uint32_t odr = READ_REG(GPIOx->ODR);
+ 80007b2: 696e ldr r6, [r5, #20]
+ WRITE_REG(GPIOx->BSRR, ((odr & PinMask) << 16u) | (~odr & PinMask));
+ 80007b4: 0032 movs r2, r6
+ 80007b6: 4002 ands r2, r0
+ 80007b8: 0412 lsls r2, r2, #16
+ 80007ba: 43b0 bics r0, r6
+ 80007bc: 4302 orrs r2, r0
+ 80007be: 61aa str r2, [r5, #24]
+ led_blue_state = new_blue_state;
+ 80007c0: 4662 mov r2, ip
+ 80007c2: 6022 str r2, [r4, #0]
+ }
+ if (++led_pwm_counter >= led_pwm_max) {
+ 80007c4: 490c ldr r1, [pc, #48] ; (80007f8 )
+ 80007c6: 4a06 ldr r2, [pc, #24] ; (80007e0 )
+ 80007c8: 6809 ldr r1, [r1, #0]
+ 80007ca: 3301 adds r3, #1
+ 80007cc: 6013 str r3, [r2, #0]
+ 80007ce: 428b cmp r3, r1
+ 80007d0: db01 blt.n 80007d6
+ led_pwm_counter = 0;
+ 80007d2: 2300 movs r3, #0
+ 80007d4: 6013 str r3, [r2, #0]
+ }
+}
+ 80007d6: bdf0 pop {r4, r5, r6, r7, pc}
+ 80007d8: 20000020 .word 0x20000020
+ 80007dc: 20000030 .word 0x20000030
+ 80007e0: 20000034 .word 0x20000034
+ 80007e4: 20000028 .word 0x20000028
+ 80007e8: 20000044 .word 0x20000044
+ 80007ec: 20000038 .word 0x20000038
+ 80007f0: 20000040 .word 0x20000040
+ 80007f4: 2000003c .word 0x2000003c
+ 80007f8: 2000002c .word 0x2000002c
+
+080007fc :
+ * Frequency of led_pwm_handler() calls. Eequal to timer frequency if timer callback is used,
+ * e.g. if led_pwm_handler() is called within SysTick_Handler(), then frequency is
+ * HAL_TICK_FREQ_1KHZ
+ */
+void led_init(led_context_t *context, int pwm_freq, int pwm_handler_freq)
+{
+ 80007fc: b570 push {r4, r5, r6, lr}
+ 80007fe: 0004 movs r4, r0
+ 8000800: 0010 movs r0, r2
+ // save context
+ led_context = context;
+ // Initial values
+ led_red_intensity = 0;
+ 8000802: 2200 movs r2, #0
+ led_context = context;
+ 8000804: 4b11 ldr r3, [pc, #68] ; (800084c )
+ led_red_state = 1; // state is inverted (LEDs are sinking current into MCU)
+ 8000806: 4d12 ldr r5, [pc, #72] ; (8000850 )
+ led_context = context;
+ 8000808: 601c str r4, [r3, #0]
+ led_red_intensity = 0;
+ 800080a: 4b12 ldr r3, [pc, #72] ; (8000854 )
+ 800080c: 601a str r2, [r3, #0]
+ led_red_state = 1; // state is inverted (LEDs are sinking current into MCU)
+ 800080e: 2301 movs r3, #1
+ 8000810: 602b str r3, [r5, #0]
+ led_green_intensity = 0;
+ 8000812: 4d11 ldr r5, [pc, #68] ; (8000858 )
+ 8000814: 602a str r2, [r5, #0]
+ led_green_state = 1;
+ 8000816: 4d11 ldr r5, [pc, #68] ; (800085c )
+ 8000818: 602b str r3, [r5, #0]
+ led_blue_intensity = 0;
+ 800081a: 4d11 ldr r5, [pc, #68] ; (8000860 )
+ 800081c: 602a str r2, [r5, #0]
+ led_blue_state = 1;
+ 800081e: 4a11 ldr r2, [pc, #68] ; (8000864 )
+ 8000820: 6013 str r3, [r2, #0]
+ // calculate PWM counter overflow value (max value)
+ // e.g. for 1 kHz handler freq and 25 Hz PWM freq, we only have
+ // resolution of 40 steps for pwm
+ led_pwm_max = pwm_handler_freq / pwm_freq;
+ 8000822: f7ff fcfb bl 800021c <__divsi3>
+ // turn off all LEDs (inverted)
+ led_gpio_on(led_context->red_led_port, led_context->red_led_pin);
+ 8000826: 6822 ldr r2, [r4, #0]
+ led_pwm_max = pwm_handler_freq / pwm_freq;
+ 8000828: 4b0f ldr r3, [pc, #60] ; (8000868 )
+ port_value |= pin_mask;
+ 800082a: 6861 ldr r1, [r4, #4]
+ led_pwm_max = pwm_handler_freq / pwm_freq;
+ 800082c: 6018 str r0, [r3, #0]
+ return (uint32_t)(READ_REG(GPIOx->IDR));
+ 800082e: 6913 ldr r3, [r2, #16]
+ port_value |= pin_mask;
+ 8000830: 430b orrs r3, r1
+ WRITE_REG(GPIOx->ODR, PortValue);
+ 8000832: 6153 str r3, [r2, #20]
+ led_gpio_on(led_context->green_led_port, led_context->green_led_pin);
+ 8000834: 68a2 ldr r2, [r4, #8]
+ port_value |= pin_mask;
+ 8000836: 68e1 ldr r1, [r4, #12]
+ return (uint32_t)(READ_REG(GPIOx->IDR));
+ 8000838: 6913 ldr r3, [r2, #16]
+ 800083a: 430b orrs r3, r1
+ WRITE_REG(GPIOx->ODR, PortValue);
+ 800083c: 6153 str r3, [r2, #20]
+ led_gpio_on(led_context->blue_led_port, led_context->blue_led_pin);
+ 800083e: 6922 ldr r2, [r4, #16]
+ port_value |= pin_mask;
+ 8000840: 6961 ldr r1, [r4, #20]
+ return (uint32_t)(READ_REG(GPIOx->IDR));
+ 8000842: 6913 ldr r3, [r2, #16]
+ 8000844: 430b orrs r3, r1
+ WRITE_REG(GPIOx->ODR, PortValue);
+ 8000846: 6153 str r3, [r2, #20]
+}
+ 8000848: bd70 pop {r4, r5, r6, pc}
+ 800084a: 46c0 nop ; (mov r8, r8)
+ 800084c: 20000020 .word 0x20000020
+ 8000850: 20000044 .word 0x20000044
+ 8000854: 20000030 .word 0x20000030
+ 8000858: 20000028 .word 0x20000028
+ 800085c: 20000040 .word 0x20000040
+ 8000860: 20000038 .word 0x20000038
+ 8000864: 2000003c .word 0x2000003c
+ 8000868: 2000002c .word 0x2000002c
+
+0800086c :
+ * @retval None
+*/
+__STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs)
+{
+ __IO uint32_t tmpreg;
+ SET_BIT(RCC->APB1ENR, Periphs);
+ 800086c: 4b05 ldr r3, [pc, #20] ; (8000884 )
+{
+ 800086e: b082 sub sp, #8
+ SET_BIT(RCC->APB1ENR, Periphs);
+ 8000870: 6b9a ldr r2, [r3, #56] ; 0x38
+ 8000872: 4302 orrs r2, r0
+ 8000874: 639a str r2, [r3, #56] ; 0x38
+ /* Delay after an RCC peripheral clock enabling */
+ tmpreg = READ_BIT(RCC->APB1ENR, Periphs);
+ 8000876: 6b9b ldr r3, [r3, #56] ; 0x38
+ 8000878: 4018 ands r0, r3
+ 800087a: 9001 str r0, [sp, #4]
+ (void)tmpreg;
+ 800087c: 9b01 ldr r3, [sp, #4]
+}
+ 800087e: b002 add sp, #8
+ 8000880: 4770 bx lr
+ 8000882: 46c0 nop ; (mov r8, r8)
+ 8000884: 40021000 .word 0x40021000
+
+08000888 :
+ * @retval None
+*/
+__STATIC_INLINE void LL_IOP_GRP1_EnableClock(uint32_t Periphs)
+{
+ __IO uint32_t tmpreg;
+ SET_BIT(RCC->IOPENR, Periphs);
+ 8000888: 4b05 ldr r3, [pc, #20] ; (80008a0 )
+{
+ 800088a: b082 sub sp, #8
+ SET_BIT(RCC->IOPENR, Periphs);
+ 800088c: 6ada ldr r2, [r3, #44] ; 0x2c
+ 800088e: 4302 orrs r2, r0
+ 8000890: 62da str r2, [r3, #44] ; 0x2c
+ /* Delay after an RCC peripheral clock enabling */
+ tmpreg = READ_BIT(RCC->IOPENR, Periphs);
+ 8000892: 6adb ldr r3, [r3, #44] ; 0x2c
+ 8000894: 4018 ands r0, r3
+ 8000896: 9001 str r0, [sp, #4]
+ (void)tmpreg;
+ 8000898: 9b01 ldr r3, [sp, #4]
+}
+ 800089a: b002 add sp, #8
+ 800089c: 4770 bx lr
+ 800089e: 46c0 nop ; (mov r8, r8)
+ 80008a0: 40021000 .word 0x40021000
+
+080008a4 :
+ * @arg @ref LL_FLASH_LATENCY_1
+ * @retval None
+ */
+__STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency)
+{
+ MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency);
+ 80008a4: 2201 movs r2, #1
+ 80008a6: 4b24 ldr r3, [pc, #144] ; (8000938 )
+/**
+ * @brief System Clock Configuration
+ * @retval None
+ */
+void SystemClock_Config(void)
+{
+ 80008a8: b510 push {r4, lr}
+ 80008aa: 6819 ldr r1, [r3, #0]
+ 80008ac: 4391 bics r1, r2
+ 80008ae: 6019 str r1, [r3, #0]
+ * @arg @ref LL_FLASH_LATENCY_0
+ * @arg @ref LL_FLASH_LATENCY_1
+ */
+__STATIC_INLINE uint32_t LL_FLASH_GetLatency(void)
+{
+ return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY));
+ 80008b0: 6819 ldr r1, [r3, #0]
+ LL_FLASH_SetLatency(LL_FLASH_LATENCY_0);
+ while(LL_FLASH_GetLatency()!= LL_FLASH_LATENCY_0)
+ 80008b2: 4211 tst r1, r2
+ 80008b4: d1fc bne.n 80008b0
+ * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE3
+ * @retval None
+ */
+__STATIC_INLINE void LL_PWR_SetRegulVoltageScaling(uint32_t VoltageScaling)
+{
+ MODIFY_REG(PWR->CR, PWR_CR_VOS, VoltageScaling);
+ 80008b6: 4921 ldr r1, [pc, #132] ; (800093c )
+ 80008b8: 4a21 ldr r2, [pc, #132] ; (8000940 )
+ 80008ba: 680b ldr r3, [r1, #0]
+ * @rmtoll CR MSION LL_RCC_MSI_Enable
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_MSI_Enable(void)
+{
+ SET_BIT(RCC->CR, RCC_CR_MSION);
+ 80008bc: 4c21 ldr r4, [pc, #132] ; (8000944 )
+ 80008be: 401a ands r2, r3
+ 80008c0: 2380 movs r3, #128 ; 0x80
+ 80008c2: 011b lsls r3, r3, #4
+ 80008c4: 4313 orrs r3, r2
+ 80008c6: 600b str r3, [r1, #0]
+ 80008c8: 2380 movs r3, #128 ; 0x80
+ 80008ca: 6822 ldr r2, [r4, #0]
+ 80008cc: 005b lsls r3, r3, #1
+ 80008ce: 4313 orrs r3, r2
+ 80008d0: 6023 str r3, [r4, #0]
+ * @rmtoll CR MSIRDY LL_RCC_MSI_IsReady
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_MSI_IsReady(void)
+{
+ return ((READ_BIT(RCC->CR, RCC_CR_MSIRDY) == RCC_CR_MSIRDY) ? 1UL : 0UL);
+ 80008d2: 2380 movs r3, #128 ; 0x80
+ 80008d4: 009b lsls r3, r3, #2
+ 80008d6: 6822 ldr r2, [r4, #0]
+ 80008d8: 421a tst r2, r3
+ 80008da: d0fc beq.n 80008d6
+ * @arg @ref LL_RCC_MSIRANGE_6
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_MSI_SetRange(uint32_t Range)
+{
+ MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSIRANGE, Range);
+ 80008dc: 6863 ldr r3, [r4, #4]
+ 80008de: 4a1a ldr r2, [pc, #104] ; (8000948 )
+ 80008e0: 401a ands r2, r3
+ 80008e2: 23a0 movs r3, #160 ; 0xa0
+ 80008e4: 021b lsls r3, r3, #8
+ 80008e6: 4313 orrs r3, r2
+ * @arg @ref LL_RCC_SYSCLK_DIV_512
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler)
+{
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler);
+ 80008e8: 22f0 movs r2, #240 ; 0xf0
+ MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSIRANGE, Range);
+ 80008ea: 6063 str r3, [r4, #4]
+ MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSITRIM, Value << RCC_ICSCR_MSITRIM_Pos);
+ 80008ec: 6863 ldr r3, [r4, #4]
+ 80008ee: 021b lsls r3, r3, #8
+ 80008f0: 0a1b lsrs r3, r3, #8
+ 80008f2: 6063 str r3, [r4, #4]
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler);
+ 80008f4: 68e3 ldr r3, [r4, #12]
+ 80008f6: 4393 bics r3, r2
+ 80008f8: 60e3 str r3, [r4, #12]
+ * @arg @ref LL_RCC_APB1_DIV_16
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)
+{
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, Prescaler);
+ 80008fa: 68e3 ldr r3, [r4, #12]
+ 80008fc: 4a13 ldr r2, [pc, #76] ; (800094c )
+ 80008fe: 4013 ands r3, r2
+ 8000900: 60e3 str r3, [r4, #12]
+ * @arg @ref LL_RCC_APB2_DIV_16
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler)
+{
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler);
+ 8000902: 68e3 ldr r3, [r4, #12]
+ 8000904: 4a12 ldr r2, [pc, #72] ; (8000950 )
+ 8000906: 4013 ands r3, r2
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source);
+ 8000908: 2203 movs r2, #3
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler);
+ 800090a: 60e3 str r3, [r4, #12]
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source);
+ 800090c: 68e3 ldr r3, [r4, #12]
+ 800090e: 4393 bics r3, r2
+ 8000910: 60e3 str r3, [r4, #12]
+ return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS));
+ 8000912: 230c movs r3, #12
+ 8000914: 68e2 ldr r2, [r4, #12]
+ LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_1);
+ LL_RCC_SetAPB2Prescaler(LL_RCC_APB2_DIV_1);
+ LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_MSI);
+
+ /* Wait till System clock is ready */
+ while(LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_MSI)
+ 8000916: 421a tst r2, r3
+ 8000918: d1fc bne.n 8000914
+ {
+
+ }
+
+ LL_Init1msTick(2097000);
+ 800091a: 480e ldr r0, [pc, #56] ; (8000954 )
+ 800091c: f000 fbac bl 8001078
+
+ LL_SetSystemCoreClock(2097000);
+ 8000920: 480c ldr r0, [pc, #48] ; (8000954 )
+ 8000922: f000 fbcf bl 80010c4
+ * @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetLPUARTClockSource(uint32_t LPUARTxSource)
+{
+ MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART1SEL, LPUARTxSource);
+ 8000926: 6ce3 ldr r3, [r4, #76] ; 0x4c
+ 8000928: 4a0b ldr r2, [pc, #44] ; (8000958 )
+ 800092a: 4013 ands r3, r2
+ 800092c: 64e3 str r3, [r4, #76] ; 0x4c
+ * (*) value not defined in all devices.
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_SetI2CClockSource(uint32_t I2CxSource)
+{
+ MODIFY_REG(RCC->CCIPR, ((I2CxSource >> 4U) & 0x000FF000U), ((I2CxSource << 4U) & 0x000FF000U));
+ 800092e: 6ce3 ldr r3, [r4, #76] ; 0x4c
+ 8000930: 4a0a ldr r2, [pc, #40] ; (800095c )
+ 8000932: 4013 ands r3, r2
+ 8000934: 64e3 str r3, [r4, #76] ; 0x4c
+ LL_RCC_SetLPUARTClockSource(LL_RCC_LPUART1_CLKSOURCE_PCLK1);
+ LL_RCC_SetI2CClockSource(LL_RCC_I2C1_CLKSOURCE_PCLK1);
+}
+ 8000936: bd10 pop {r4, pc}
+ 8000938: 40022000 .word 0x40022000
+ 800093c: 40007000 .word 0x40007000
+ 8000940: ffffe7ff .word 0xffffe7ff
+ 8000944: 40021000 .word 0x40021000
+ 8000948: ffff1fff .word 0xffff1fff
+ 800094c: fffff8ff .word 0xfffff8ff
+ 8000950: ffffc7ff .word 0xffffc7ff
+ 8000954: 001fff68 .word 0x001fff68
+ 8000958: fffff3ff .word 0xfffff3ff
+ 800095c: ffffcfff .word 0xffffcfff
+
+08000960 :
+{
+ 8000960: b5f0 push {r4, r5, r6, r7, lr}
+ SET_BIT(RCC->APB2ENR, Periphs);
+ 8000962: 2501 movs r5, #1
+ LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR);
+ 8000964: 2080 movs r0, #128 ; 0x80
+ 8000966: 4eac ldr r6, [pc, #688] ; (8000c18 )
+{
+ 8000968: b093 sub sp, #76 ; 0x4c
+ 800096a: 6b73 ldr r3, [r6, #52] ; 0x34
+ LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR);
+ 800096c: 0540 lsls r0, r0, #21
+ 800096e: 432b orrs r3, r5
+ 8000970: 6373 str r3, [r6, #52] ; 0x34
+ tmpreg = READ_BIT(RCC->APB2ENR, Periphs);
+ 8000972: 6b73 ldr r3, [r6, #52] ; 0x34
+ WRITE_REG(GPIOx->BSRR, PinMask);
+ 8000974: 2780 movs r7, #128 ; 0x80
+ 8000976: 402b ands r3, r5
+ 8000978: 9303 str r3, [sp, #12]
+ (void)tmpreg;
+ 800097a: 9b03 ldr r3, [sp, #12]
+ 800097c: f7ff ff76 bl 800086c
+ SystemClock_Config();
+ 8000980: f7ff ff90 bl 80008a4
+ * @param None
+ * @retval None
+ */
+static void MX_GPIO_Init(void)
+{
+ LL_GPIO_InitTypeDef GPIO_InitStruct = {0};
+ 8000984: 2218 movs r2, #24
+ 8000986: 2100 movs r1, #0
+ 8000988: a80b add r0, sp, #44 ; 0x2c
+ 800098a: f000 fbc5 bl 8001118
+
+ /* GPIO Ports Clock Enable */
+ LL_IOP_GRP1_EnableClock(LL_IOP_GRP1_PERIPH_GPIOA);
+ 800098e: 0028 movs r0, r5
+ 8000990: f7ff ff7a bl 8000888
+ LL_IOP_GRP1_EnableClock(LL_IOP_GRP1_PERIPH_GPIOB);
+ 8000994: 2002 movs r0, #2
+ 8000996: f7ff ff77 bl 8000888
+ 800099a: 23a0 movs r3, #160 ; 0xa0
+ 800099c: 2220 movs r2, #32
+ 800099e: 2140 movs r1, #64 ; 0x40
+ LL_GPIO_SetOutputPin(LED_R_GPIO_Port, LED_R_Pin);
+
+ /**/
+ GPIO_InitStruct.Pin = LED_B_Pin;
+ GPIO_InitStruct.Mode = LL_GPIO_MODE_OUTPUT;
+ GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_LOW;
+ 80009a0: 2400 movs r4, #0
+ 80009a2: 05db lsls r3, r3, #23
+ GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;
+ GPIO_InitStruct.Pull = LL_GPIO_PULL_NO;
+ LL_GPIO_Init(LED_B_GPIO_Port, &GPIO_InitStruct);
+ 80009a4: a80b add r0, sp, #44 ; 0x2c
+ 80009a6: 619a str r2, [r3, #24]
+ 80009a8: 6199 str r1, [r3, #24]
+ 80009aa: 619f str r7, [r3, #24]
+ 80009ac: 0001 movs r1, r0
+ 80009ae: 0018 movs r0, r3
+ GPIO_InitStruct.Pin = LED_B_Pin;
+ 80009b0: 920b str r2, [sp, #44] ; 0x2c
+ GPIO_InitStruct.Mode = LL_GPIO_MODE_OUTPUT;
+ 80009b2: 950c str r5, [sp, #48] ; 0x30
+ GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_LOW;
+ 80009b4: 940d str r4, [sp, #52] ; 0x34
+ GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;
+ 80009b6: 940e str r4, [sp, #56] ; 0x38
+ GPIO_InitStruct.Pull = LL_GPIO_PULL_NO;
+ 80009b8: 940f str r4, [sp, #60] ; 0x3c
+ LL_GPIO_Init(LED_B_GPIO_Port, &GPIO_InitStruct);
+ 80009ba: f000 f9de bl 8000d7a
+
+ /**/
+ GPIO_InitStruct.Pin = LED_G_Pin;
+ 80009be: 2040 movs r0, #64 ; 0x40
+ 80009c0: 900b str r0, [sp, #44] ; 0x2c
+ GPIO_InitStruct.Mode = LL_GPIO_MODE_OUTPUT;
+ GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_LOW;
+ GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;
+ GPIO_InitStruct.Pull = LL_GPIO_PULL_NO;
+ LL_GPIO_Init(LED_G_GPIO_Port, &GPIO_InitStruct);
+ 80009c2: 20a0 movs r0, #160 ; 0xa0
+ 80009c4: a90b add r1, sp, #44 ; 0x2c
+ 80009c6: 05c0 lsls r0, r0, #23
+ GPIO_InitStruct.Mode = LL_GPIO_MODE_OUTPUT;
+ 80009c8: 950c str r5, [sp, #48] ; 0x30
+ GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_LOW;
+ 80009ca: 940d str r4, [sp, #52] ; 0x34
+ GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;
+ 80009cc: 940e str r4, [sp, #56] ; 0x38
+ GPIO_InitStruct.Pull = LL_GPIO_PULL_NO;
+ 80009ce: 940f str r4, [sp, #60] ; 0x3c
+ LL_GPIO_Init(LED_G_GPIO_Port, &GPIO_InitStruct);
+ 80009d0: f000 f9d3 bl 8000d7a
+ GPIO_InitStruct.Pin = LED_R_Pin;
+ GPIO_InitStruct.Mode = LL_GPIO_MODE_OUTPUT;
+ GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_LOW;
+ GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;
+ GPIO_InitStruct.Pull = LL_GPIO_PULL_NO;
+ LL_GPIO_Init(LED_R_GPIO_Port, &GPIO_InitStruct);
+ 80009d4: 20a0 movs r0, #160 ; 0xa0
+ 80009d6: a90b add r1, sp, #44 ; 0x2c
+ 80009d8: 05c0 lsls r0, r0, #23
+ GPIO_InitStruct.Pin = LED_R_Pin;
+ 80009da: 970b str r7, [sp, #44] ; 0x2c
+ GPIO_InitStruct.Mode = LL_GPIO_MODE_OUTPUT;
+ 80009dc: 950c str r5, [sp, #48] ; 0x30
+ GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_LOW;
+ 80009de: 940d str r4, [sp, #52] ; 0x34
+ GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;
+ 80009e0: 940e str r4, [sp, #56] ; 0x38
+ GPIO_InitStruct.Pull = LL_GPIO_PULL_NO;
+ 80009e2: 940f str r4, [sp, #60] ; 0x3c
+ LL_GPIO_Init(LED_R_GPIO_Port, &GPIO_InitStruct);
+ 80009e4: f000 f9c9 bl 8000d7a
+ SET_BIT(RCC->AHBENR, Periphs);
+ 80009e8: 6b33 ldr r3, [r6, #48] ; 0x30
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) >= 0)
+ {
+ NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ 80009ea: 21c2 movs r1, #194 ; 0xc2
+ 80009ec: 432b orrs r3, r5
+ 80009ee: 6333 str r3, [r6, #48] ; 0x30
+ tmpreg = READ_BIT(RCC->AHBENR, Periphs);
+ 80009f0: 6b33 ldr r3, [r6, #48] ; 0x30
+ NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ 80009f2: 2680 movs r6, #128 ; 0x80
+ 80009f4: 402b ands r3, r5
+ 80009f6: 9304 str r3, [sp, #16]
+ (void)tmpreg;
+ 80009f8: 9b04 ldr r3, [sp, #16]
+ NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ 80009fa: 4b88 ldr r3, [pc, #544] ; (8000c1c )
+ 80009fc: 0089 lsls r1, r1, #2
+ 80009fe: 585a ldr r2, [r3, r1]
+ 8000a00: 4887 ldr r0, [pc, #540] ; (8000c20 )
+ NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ 8000a02: 00f6 lsls r6, r6, #3
+ NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ 8000a04: 4002 ands r2, r0
+ 8000a06: 505a str r2, [r3, r1]
+ LL_I2C_InitTypeDef I2C_InitStruct = {0};
+ 8000a08: a80b add r0, sp, #44 ; 0x2c
+ NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ 8000a0a: 601e str r6, [r3, #0]
+ 8000a0c: 0021 movs r1, r4
+ 8000a0e: 221c movs r2, #28
+ 8000a10: f000 fb82 bl 8001118
+ LL_GPIO_InitTypeDef GPIO_InitStruct = {0};
+ 8000a14: 2218 movs r2, #24
+ 8000a16: 0021 movs r1, r4
+ 8000a18: a805 add r0, sp, #20
+ 8000a1a: f000 fb7d bl 8001118
+ LL_IOP_GRP1_EnableClock(LL_IOP_GRP1_PERIPH_GPIOA);
+ 8000a1e: 0028 movs r0, r5
+ 8000a20: f7ff ff32 bl 8000888
+ GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH;
+ 8000a24: 2003 movs r0, #3
+ GPIO_InitStruct.Pin = LL_GPIO_PIN_9;
+ 8000a26: 2380 movs r3, #128 ; 0x80
+ GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH;
+ 8000a28: 9007 str r0, [sp, #28]
+ LL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+ 8000a2a: 20a0 movs r0, #160 ; 0xa0
+ GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE;
+ 8000a2c: 3f7e subs r7, #126 ; 0x7e
+ GPIO_InitStruct.Pin = LL_GPIO_PIN_9;
+ 8000a2e: 009b lsls r3, r3, #2
+ LL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+ 8000a30: a905 add r1, sp, #20
+ 8000a32: 05c0 lsls r0, r0, #23
+ GPIO_InitStruct.Pin = LL_GPIO_PIN_9;
+ 8000a34: 9305 str r3, [sp, #20]
+ GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE;
+ 8000a36: 9706 str r7, [sp, #24]
+ GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_OPENDRAIN;
+ 8000a38: 9508 str r5, [sp, #32]
+ GPIO_InitStruct.Pull = LL_GPIO_PULL_UP;
+ 8000a3a: 9509 str r5, [sp, #36] ; 0x24
+ GPIO_InitStruct.Alternate = LL_GPIO_AF_1;
+ 8000a3c: 950a str r5, [sp, #40] ; 0x28
+ LL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+ 8000a3e: f000 f99c bl 8000d7a
+ GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH;
+ 8000a42: 2003 movs r0, #3
+ 8000a44: 9007 str r0, [sp, #28]
+ LL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+ 8000a46: 20a0 movs r0, #160 ; 0xa0
+ GPIO_InitStruct.Pin = LL_GPIO_PIN_10;
+ 8000a48: 9605 str r6, [sp, #20]
+ LL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+ 8000a4a: ae05 add r6, sp, #20
+ 8000a4c: 0031 movs r1, r6
+ 8000a4e: 05c0 lsls r0, r0, #23
+ GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE;
+ 8000a50: 9706 str r7, [sp, #24]
+ GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_OPENDRAIN;
+ 8000a52: 9508 str r5, [sp, #32]
+ GPIO_InitStruct.Pull = LL_GPIO_PULL_UP;
+ 8000a54: 9509 str r5, [sp, #36] ; 0x24
+ GPIO_InitStruct.Alternate = LL_GPIO_AF_1;
+ 8000a56: 950a str r5, [sp, #40] ; 0x28
+ LL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+ 8000a58: f000 f98f bl 8000d7a
+ LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_I2C1);
+ 8000a5c: 2080 movs r0, #128 ; 0x80
+ 8000a5e: 0380 lsls r0, r0, #14
+ 8000a60: f7ff ff04 bl 800086c
+ SET_BIT(I2Cx->CR2, I2C_CR2_AUTOEND);
+ 8000a64: 2380 movs r3, #128 ; 0x80
+ 8000a66: 4e6f ldr r6, [pc, #444] ; (8000c24 )
+ 8000a68: 049b lsls r3, r3, #18
+ 8000a6a: 6872 ldr r2, [r6, #4]
+ LL_I2C_Init(I2C1, &I2C_InitStruct);
+ 8000a6c: a90b add r1, sp, #44 ; 0x2c
+ 8000a6e: 4313 orrs r3, r2
+ 8000a70: 6073 str r3, [r6, #4]
+ CLEAR_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN);
+ 8000a72: 68f3 ldr r3, [r6, #12]
+ 8000a74: 4a6c ldr r2, [pc, #432] ; (8000c28 )
+ 8000a76: 0030 movs r0, r6
+ 8000a78: 4013 ands r3, r2
+ 8000a7a: 60f3 str r3, [r6, #12]
+ CLEAR_BIT(I2Cx->CR1, I2C_CR1_GCEN);
+ 8000a7c: 6833 ldr r3, [r6, #0]
+ 8000a7e: 4a6b ldr r2, [pc, #428] ; (8000c2c )
+ 8000a80: 4013 ands r3, r2
+ 8000a82: 6033 str r3, [r6, #0]
+ CLEAR_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH);
+ 8000a84: 6833 ldr r3, [r6, #0]
+ 8000a86: 4a6a ldr r2, [pc, #424] ; (8000c30 )
+ 8000a88: 4013 ands r3, r2
+ 8000a8a: 6033 str r3, [r6, #0]
+ I2C_InitStruct.Timing = 0x00000708;
+ 8000a8c: 23e1 movs r3, #225 ; 0xe1
+ 8000a8e: 00db lsls r3, r3, #3
+ I2C_InitStruct.PeripheralMode = LL_I2C_MODE_I2C;
+ 8000a90: 940b str r4, [sp, #44] ; 0x2c
+ I2C_InitStruct.Timing = 0x00000708;
+ 8000a92: 930c str r3, [sp, #48] ; 0x30
+ I2C_InitStruct.AnalogFilter = LL_I2C_ANALOGFILTER_ENABLE;
+ 8000a94: 940d str r4, [sp, #52] ; 0x34
+ I2C_InitStruct.DigitalFilter = 0;
+ 8000a96: 940e str r4, [sp, #56] ; 0x38
+ I2C_InitStruct.OwnAddress1 = 0;
+ 8000a98: 940f str r4, [sp, #60] ; 0x3c
+ I2C_InitStruct.TypeAcknowledge = LL_I2C_ACK;
+ 8000a9a: 9410 str r4, [sp, #64] ; 0x40
+ I2C_InitStruct.OwnAddrSize = LL_I2C_OWNADDRESS1_7BIT;
+ 8000a9c: 9411 str r4, [sp, #68] ; 0x44
+ LL_I2C_Init(I2C1, &I2C_InitStruct);
+ 8000a9e: f000 f9bd bl 8000e1c
+ MODIFY_REG(I2Cx->OAR2, I2C_OAR2_OA2 | I2C_OAR2_OA2MSK, OwnAddress2 | OwnAddrMask);
+ 8000aa2: 68f3 ldr r3, [r6, #12]
+ 8000aa4: 4a63 ldr r2, [pc, #396] ; (8000c34 )
+ LL_LPUART_InitTypeDef LPUART_InitStruct = {0};
+ 8000aa6: 0021 movs r1, r4
+ 8000aa8: 4013 ands r3, r2
+ 8000aaa: 60f3 str r3, [r6, #12]
+ 8000aac: ab05 add r3, sp, #20
+ 8000aae: 2218 movs r2, #24
+ 8000ab0: 0018 movs r0, r3
+ 8000ab2: f000 fb31 bl 8001118
+ LL_GPIO_InitTypeDef GPIO_InitStruct = {0};
+ 8000ab6: ab0b add r3, sp, #44 ; 0x2c
+ 8000ab8: 2218 movs r2, #24
+ 8000aba: 0021 movs r1, r4
+ 8000abc: 0018 movs r0, r3
+ 8000abe: f000 fb2b bl 8001118
+ LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_LPUART1);
+ 8000ac2: 2080 movs r0, #128 ; 0x80
+ 8000ac4: 02c0 lsls r0, r0, #11
+ 8000ac6: f7ff fed1 bl 800086c
+ LL_IOP_GRP1_EnableClock(LL_IOP_GRP1_PERIPH_GPIOA);
+ 8000aca: 0028 movs r0, r5
+ 8000acc: f7ff fedc bl 8000888
+ LL_IOP_GRP1_EnableClock(LL_IOP_GRP1_PERIPH_GPIOB);
+ 8000ad0: 0038 movs r0, r7
+ 8000ad2: f7ff fed9 bl 8000888
+ GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH;
+ 8000ad6: 2003 movs r0, #3
+ GPIO_InitStruct.Alternate = LL_GPIO_AF_6;
+ 8000ad8: 2106 movs r1, #6
+ GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH;
+ 8000ada: 900d str r0, [sp, #52] ; 0x34
+ LL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+ 8000adc: 20a0 movs r0, #160 ; 0xa0
+ 8000ade: ab0b add r3, sp, #44 ; 0x2c
+ GPIO_InitStruct.Alternate = LL_GPIO_AF_6;
+ 8000ae0: 9110 str r1, [sp, #64] ; 0x40
+ LL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+ 8000ae2: 05c0 lsls r0, r0, #23
+ 8000ae4: 0019 movs r1, r3
+ GPIO_InitStruct.Pin = LL_GPIO_PIN_0;
+ 8000ae6: 950b str r5, [sp, #44] ; 0x2c
+ GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE;
+ 8000ae8: 970c str r7, [sp, #48] ; 0x30
+ GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;
+ 8000aea: 940e str r4, [sp, #56] ; 0x38
+ GPIO_InitStruct.Pull = LL_GPIO_PULL_NO;
+ 8000aec: 940f str r4, [sp, #60] ; 0x3c
+ LL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+ 8000aee: f000 f944 bl 8000d7a
+ GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH;
+ 8000af2: 2003 movs r0, #3
+ GPIO_InitStruct.Alternate = LL_GPIO_AF_6;
+ 8000af4: 2106 movs r1, #6
+ GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH;
+ 8000af6: 900d str r0, [sp, #52] ; 0x34
+ LL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+ 8000af8: 20a0 movs r0, #160 ; 0xa0
+ GPIO_InitStruct.Alternate = LL_GPIO_AF_6;
+ 8000afa: 9110 str r1, [sp, #64] ; 0x40
+ LL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+ 8000afc: 05c0 lsls r0, r0, #23
+ 8000afe: a90b add r1, sp, #44 ; 0x2c
+ GPIO_InitStruct.Pin = LL_GPIO_PIN_1;
+ 8000b00: 970b str r7, [sp, #44] ; 0x2c
+ GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE;
+ 8000b02: 970c str r7, [sp, #48] ; 0x30
+ GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;
+ 8000b04: 940e str r4, [sp, #56] ; 0x38
+ GPIO_InitStruct.Pull = LL_GPIO_PULL_NO;
+ 8000b06: 940f str r4, [sp, #60] ; 0x3c
+ LL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+ 8000b08: f000 f937 bl 8000d7a
+ GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH;
+ 8000b0c: 2003 movs r0, #3
+ GPIO_InitStruct.Alternate = LL_GPIO_AF_4;
+ 8000b0e: 2304 movs r3, #4
+ GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH;
+ 8000b10: 900d str r0, [sp, #52] ; 0x34
+ LL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+ 8000b12: a90b add r1, sp, #44 ; 0x2c
+ 8000b14: 4848 ldr r0, [pc, #288] ; (8000c38 )
+ GPIO_InitStruct.Pin = LL_GPIO_PIN_1;
+ 8000b16: 970b str r7, [sp, #44] ; 0x2c
+ GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE;
+ 8000b18: 970c str r7, [sp, #48] ; 0x30
+ GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;
+ 8000b1a: 940e str r4, [sp, #56] ; 0x38
+ GPIO_InitStruct.Pull = LL_GPIO_PULL_NO;
+ 8000b1c: 940f str r4, [sp, #60] ; 0x3c
+ GPIO_InitStruct.Alternate = LL_GPIO_AF_4;
+ 8000b1e: 9310 str r3, [sp, #64] ; 0x40
+ LL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+ 8000b20: f000 f92b bl 8000d7a
+ * @arg @ref LL_DMA_REQUEST_15
+ * @retval None
+ */
+__STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Request)
+{
+ MODIFY_REG(((DMA_Request_TypeDef *)((uint32_t)((uint32_t)DMAx + DMA_CSELR_OFFSET)))->CSELR,
+ 8000b24: 4945 ldr r1, [pc, #276] ; (8000c3c )
+ 8000b26: 4a46 ldr r2, [pc, #280] ; (8000c40 )
+ 8000b28: 680b ldr r3, [r1, #0]
+ MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PINC,
+ 8000b2a: 2040 movs r0, #64 ; 0x40
+ MODIFY_REG(((DMA_Request_TypeDef *)((uint32_t)((uint32_t)DMAx + DMA_CSELR_OFFSET)))->CSELR,
+ 8000b2c: 401a ands r2, r3
+ 8000b2e: 23a0 movs r3, #160 ; 0xa0
+ 8000b30: 00db lsls r3, r3, #3
+ 8000b32: 4313 orrs r3, r2
+ 8000b34: 600b str r3, [r1, #0]
+ MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
+ 8000b36: 4b43 ldr r3, [pc, #268] ; (8000c44 )
+ 8000b38: 4943 ldr r1, [pc, #268] ; (8000c48 )
+ 8000b3a: 681a ldr r2, [r3, #0]
+ MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MINC,
+ 8000b3c: 377e adds r7, #126 ; 0x7e
+ MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
+ 8000b3e: 400a ands r2, r1
+ 8000b40: 601a str r2, [r3, #0]
+ MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PL,
+ 8000b42: 681a ldr r2, [r3, #0]
+ 8000b44: 4941 ldr r1, [pc, #260] ; (8000c4c )
+ 8000b46: 4011 ands r1, r2
+ 8000b48: 2280 movs r2, #128 ; 0x80
+ 8000b4a: 0152 lsls r2, r2, #5
+ 8000b4c: 430a orrs r2, r1
+ MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_CIRC,
+ 8000b4e: 2120 movs r1, #32
+ MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PL,
+ 8000b50: 601a str r2, [r3, #0]
+ MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_CIRC,
+ 8000b52: 681a ldr r2, [r3, #0]
+ 8000b54: 438a bics r2, r1
+ 8000b56: 430a orrs r2, r1
+ 8000b58: 601a str r2, [r3, #0]
+ MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PINC,
+ 8000b5a: 681a ldr r2, [r3, #0]
+ MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PSIZE,
+ 8000b5c: 493c ldr r1, [pc, #240] ; (8000c50 )
+ MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PINC,
+ 8000b5e: 4382 bics r2, r0
+ 8000b60: 601a str r2, [r3, #0]
+ MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MINC,
+ 8000b62: 681a ldr r2, [r3, #0]
+ 8000b64: 43ba bics r2, r7
+ 8000b66: 433a orrs r2, r7
+ 8000b68: 601a str r2, [r3, #0]
+ MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PSIZE,
+ 8000b6a: 681a ldr r2, [r3, #0]
+ LL_LPUART_Init(LPUART1, &LPUART_InitStruct);
+ 8000b6c: 4f39 ldr r7, [pc, #228] ; (8000c54 )
+ 8000b6e: 400a ands r2, r1
+ 8000b70: 601a str r2, [r3, #0]
+ MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MSIZE,
+ 8000b72: 681a ldr r2, [r3, #0]
+ 8000b74: 4938 ldr r1, [pc, #224] ; (8000c58 )
+ 8000b76: 0038 movs r0, r7
+ 8000b78: 400a ands r2, r1
+ 8000b7a: 601a str r2, [r3, #0]
+ LPUART_InitStruct.BaudRate = 115200;
+ 8000b7c: 23e1 movs r3, #225 ; 0xe1
+ 8000b7e: 025b lsls r3, r3, #9
+ 8000b80: 9305 str r3, [sp, #20]
+ LPUART_InitStruct.TransferDirection = LL_LPUART_DIRECTION_TX_RX;
+ 8000b82: 230c movs r3, #12
+ LL_LPUART_Init(LPUART1, &LPUART_InitStruct);
+ 8000b84: a905 add r1, sp, #20
+ LPUART_InitStruct.DataWidth = LL_LPUART_DATAWIDTH_8B;
+ 8000b86: 9406 str r4, [sp, #24]
+ LPUART_InitStruct.StopBits = LL_LPUART_STOPBITS_1;
+ 8000b88: 9407 str r4, [sp, #28]
+ LPUART_InitStruct.Parity = LL_LPUART_PARITY_NONE;
+ 8000b8a: 9408 str r4, [sp, #32]
+ LPUART_InitStruct.TransferDirection = LL_LPUART_DIRECTION_TX_RX;
+ 8000b8c: 9309 str r3, [sp, #36] ; 0x24
+ LPUART_InitStruct.HardwareFlowControl = LL_LPUART_HWCONTROL_NONE;
+ 8000b8e: 940a str r4, [sp, #40] ; 0x28
+ LL_LPUART_Init(LPUART1, &LPUART_InitStruct);
+ 8000b90: f000 f97e bl 8000e90
+ * @param LPUARTx LPUART Instance
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_EnableDEMode(USART_TypeDef *LPUARTx)
+{
+ SET_BIT(LPUARTx->CR3, USART_CR3_DEM);
+ 8000b94: 2380 movs r3, #128 ; 0x80
+ 8000b96: 68ba ldr r2, [r7, #8]
+ 8000b98: 01db lsls r3, r3, #7
+ 8000b9a: 4313 orrs r3, r2
+ 8000b9c: 60bb str r3, [r7, #8]
+ * @arg @ref LL_LPUART_DE_POLARITY_LOW
+ * @retval None
+ */
+__STATIC_INLINE void LL_LPUART_SetDESignalPolarity(USART_TypeDef *LPUARTx, uint32_t Polarity)
+{
+ MODIFY_REG(LPUARTx->CR3, USART_CR3_DEP, Polarity);
+ 8000b9e: 68bb ldr r3, [r7, #8]
+ 8000ba0: 4a21 ldr r2, [pc, #132] ; (8000c28 )
+ led_context.green_led_pin = LED_G_Pin;
+ 8000ba2: 2040 movs r0, #64 ; 0x40
+ 8000ba4: 4013 ands r3, r2
+ 8000ba6: 60bb str r3, [r7, #8]
+ MODIFY_REG(LPUARTx->CR1, USART_CR1_DEAT, Time << USART_CR1_DEAT_Pos);
+ 8000ba8: 683b ldr r3, [r7, #0]
+ 8000baa: 4a2c ldr r2, [pc, #176] ; (8000c5c )
+ led_context.blue_led_pin = LED_B_Pin;
+ 8000bac: 2120 movs r1, #32
+ 8000bae: 401a ands r2, r3
+ 8000bb0: 23a0 movs r3, #160 ; 0xa0
+ 8000bb2: 049b lsls r3, r3, #18
+ 8000bb4: 4313 orrs r3, r2
+ 8000bb6: 603b str r3, [r7, #0]
+ MODIFY_REG(LPUARTx->CR1, USART_CR1_DEDT, Time << USART_CR1_DEDT_Pos);
+ 8000bb8: 683b ldr r3, [r7, #0]
+ 8000bba: 4a29 ldr r2, [pc, #164] ; (8000c60 )
+ 8000bbc: 401a ands r2, r3
+ 8000bbe: 23a0 movs r3, #160 ; 0xa0
+ 8000bc0: 035b lsls r3, r3, #13
+ 8000bc2: 4313 orrs r3, r2
+ 8000bc4: 603b str r3, [r7, #0]
+ SET_BIT(I2Cx->CR1, I2C_CR1_PE);
+ 8000bc6: 6833 ldr r3, [r6, #0]
+ led_init(&led_context, 50, 1000);
+ 8000bc8: 22fa movs r2, #250 ; 0xfa
+ 8000bca: 432b orrs r3, r5
+ 8000bcc: 6033 str r3, [r6, #0]
+ SET_BIT(LPUARTx->CR1, USART_CR1_UE);
+ 8000bce: 683b ldr r3, [r7, #0]
+ 8000bd0: 0092 lsls r2, r2, #2
+ 8000bd2: 431d orrs r5, r3
+ led_context.red_led_port = LED_R_GPIO_Port;
+ 8000bd4: 23a0 movs r3, #160 ; 0xa0
+ 8000bd6: 603d str r5, [r7, #0]
+ led_context.red_led_pin = LED_R_Pin;
+ 8000bd8: 2780 movs r7, #128 ; 0x80
+ led_context.red_led_port = LED_R_GPIO_Port;
+ 8000bda: 05db lsls r3, r3, #23
+ led_context.green_led_pin = LED_G_Pin;
+ 8000bdc: 900e str r0, [sp, #56] ; 0x38
+ led_context.blue_led_pin = LED_B_Pin;
+ 8000bde: 9110 str r1, [sp, #64] ; 0x40
+ led_init(&led_context, 50, 1000);
+ 8000be0: a80b add r0, sp, #44 ; 0x2c
+ 8000be2: 3112 adds r1, #18
+ led_context.red_led_port = LED_R_GPIO_Port;
+ 8000be4: 930b str r3, [sp, #44] ; 0x2c
+ led_context.green_led_port = LED_G_GPIO_Port;
+ 8000be6: 930d str r3, [sp, #52] ; 0x34
+ led_context.blue_led_port = LED_B_GPIO_Port;
+ 8000be8: 930f str r3, [sp, #60] ; 0x3c
+ led_context.red_led_pin = LED_R_Pin;
+ 8000bea: 970c str r7, [sp, #48] ; 0x30
+ led_init(&led_context, 50, 1000);
+ 8000bec: f7ff fe06 bl 80007fc
+ led_set_color(0, 20, 0);
+ 8000bf0: 0022 movs r2, r4
+ 8000bf2: 0020 movs r0, r4
+ 8000bf4: 2114 movs r1, #20
+ 8000bf6: f7ff fd7d bl 80006f4
+ LL_mDelay(1000);
+ 8000bfa: 24fa movs r4, #250 ; 0xfa
+ i2c_init(&i2c_context);
+ 8000bfc: a801 add r0, sp, #4
+ i2c_context.i2c = I2C1;
+ 8000bfe: 9601 str r6, [sp, #4]
+ i2c_init(&i2c_context);
+ 8000c00: f7ff fd0e bl 8000620
+ LL_mDelay(1000);
+ 8000c04: 00a4 lsls r4, r4, #2
+ sht4x_measure(&T, &RH);
+ 8000c06: a905 add r1, sp, #20
+ 8000c08: a802 add r0, sp, #8
+ 8000c0a: f000 f82b bl 8000c64
+ LL_mDelay(1000);
+ 8000c0e: 0020 movs r0, r4
+ 8000c10: f000 fa42 bl 8001098
+ while (1)
+ 8000c14: e7f7 b.n 8000c06
+ 8000c16: 46c0 nop ; (mov r8, r8)
+ 8000c18: 40021000 .word 0x40021000
+ 8000c1c: e000e100 .word 0xe000e100
+ 8000c20: ff00ffff .word 0xff00ffff
+ 8000c24: 40005400 .word 0x40005400
+ 8000c28: ffff7fff .word 0xffff7fff
+ 8000c2c: fff7ffff .word 0xfff7ffff
+ 8000c30: fffdffff .word 0xfffdffff
+ 8000c34: fffff801 .word 0xfffff801
+ 8000c38: 50000400 .word 0x50000400
+ 8000c3c: 400200a8 .word 0x400200a8
+ 8000c40: fffff0ff .word 0xfffff0ff
+ 8000c44: 40020030 .word 0x40020030
+ 8000c48: ffffbfef .word 0xffffbfef
+ 8000c4c: ffffcfff .word 0xffffcfff
+ 8000c50: fffffcff .word 0xfffffcff
+ 8000c54: 40004800 .word 0x40004800
+ 8000c58: fffff3ff .word 0xfffff3ff
+ 8000c5c: fc1fffff .word 0xfc1fffff
+ 8000c60: ffe0ffff .word 0xffe0ffff
+
+08000c64 :
+{
+
+}
+
+int8_t sht4x_measure(int *temperature, int *relative_humidity)
+{
+ 8000c64: b570 push {r4, r5, r6, lr}
+ 8000c66: b088 sub sp, #32
+ uint8_t buffer[32];
+ int result;
+
+ // start measurement
+ buffer[0] = START_MEAS_HIGH_PRECISION;
+ 8000c68: 466a mov r2, sp
+ 8000c6a: 23fd movs r3, #253 ; 0xfd
+{
+ 8000c6c: 0006 movs r6, r0
+ 8000c6e: 000d movs r5, r1
+ buffer[0] = START_MEAS_HIGH_PRECISION;
+ 8000c70: 7013 strb r3, [r2, #0]
+ result = i2c_transmit(SHT4X_I2C_ADDRESS<<1, buffer, 1);
+ 8000c72: 4669 mov r1, sp
+ 8000c74: 2201 movs r2, #1
+ 8000c76: 2088 movs r0, #136 ; 0x88
+ 8000c78: f7ff fcde bl 8000638
+ if (result != I2C_OK) {
+ 8000c7c: 2800 cmp r0, #0
+ 8000c7e: d003 beq.n 8000c88
+ return SHT4X_ERROR;
+ 8000c80: 2001 movs r0, #1
+ 8000c82: 4240 negs r0, r0
+ }
+ *temperature = t_degC;
+ *relative_humidity = rh_pRH;
+
+ return SHT4X_OK;
+}
+ 8000c84: b008 add sp, #32
+ 8000c86: bd70 pop {r4, r5, r6, pc}
+ LL_mDelay(100); // 10 ms should be enough
+ 8000c88: 2064 movs r0, #100 ; 0x64
+ 8000c8a: f000 fa05 bl 8001098
+ result = i2c_receive(SHT4X_I2C_ADDRESS<<1, buffer, 6);
+ 8000c8e: 2206 movs r2, #6
+ 8000c90: 4669 mov r1, sp
+ 8000c92: 2088 movs r0, #136 ; 0x88
+ 8000c94: f7ff fd02 bl 800069c
+ if (result != I2C_OK) {
+ 8000c98: 2800 cmp r0, #0
+ 8000c9a: d1f1 bne.n 8000c80
+ uint32_t rh_ticks = (buffer[3] << 8) + buffer[4];
+ 8000c9c: 466b mov r3, sp
+ 8000c9e: 78d8 ldrb r0, [r3, #3]
+ 8000ca0: 791b ldrb r3, [r3, #4]
+ 8000ca2: 0200 lsls r0, r0, #8
+ 8000ca4: 18c0 adds r0, r0, r3
+ int rh_pRH = -6 + 125 * rh_ticks / 65535;
+ 8000ca6: 237d movs r3, #125 ; 0x7d
+ 8000ca8: 490d ldr r1, [pc, #52] ; (8000ce0 )
+ 8000caa: 4358 muls r0, r3
+ 8000cac: f7ff fa2c bl 8000108 <__udivsi3>
+ 8000cb0: 1f84 subs r4, r0, #6
+ 8000cb2: 43e3 mvns r3, r4
+ 8000cb4: 17db asrs r3, r3, #31
+ 8000cb6: 401c ands r4, r3
+ uint32_t t_ticks = (buffer[0] << 8) + buffer[1];
+ 8000cb8: 466b mov r3, sp
+ 8000cba: 466a mov r2, sp
+ 8000cbc: 781b ldrb r3, [r3, #0]
+ 8000cbe: 7850 ldrb r0, [r2, #1]
+ 8000cc0: 021b lsls r3, r3, #8
+ 8000cc2: 181b adds r3, r3, r0
+ int t_degC = -45 + 175 * t_ticks / 65535;
+ 8000cc4: 20af movs r0, #175 ; 0xaf
+ 8000cc6: 4906 ldr r1, [pc, #24] ; (8000ce0 )
+ 8000cc8: 4358 muls r0, r3
+ 8000cca: f7ff fa1d bl 8000108 <__udivsi3>
+ 8000cce: 382d subs r0, #45 ; 0x2d
+ *temperature = t_degC;
+ 8000cd0: 6030 str r0, [r6, #0]
+ *relative_humidity = rh_pRH;
+ 8000cd2: 2c64 cmp r4, #100 ; 0x64
+ 8000cd4: dd00 ble.n 8000cd8
+ 8000cd6: 2464 movs r4, #100 ; 0x64
+ return SHT4X_OK;
+ 8000cd8: 2000 movs r0, #0
+ *relative_humidity = rh_pRH;
+ 8000cda: 602c str r4, [r5, #0]
+ return SHT4X_OK;
+ 8000cdc: e7d2 b.n 8000c84
+ 8000cde: 46c0 nop ; (mov r8, r8)
+ 8000ce0: 0000ffff .word 0x0000ffff
+
+08000ce4 :
+{
+ /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
+
+ /* USER CODE END NonMaskableInt_IRQn 0 */
+ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
+ while (1)
+ 8000ce4: e7fe b.n 8000ce4
+
+08000ce6 :
+void HardFault_Handler(void)
+{
+ /* USER CODE BEGIN HardFault_IRQn 0 */
+
+ /* USER CODE END HardFault_IRQn 0 */
+ while (1)
+ 8000ce6: e7fe b.n 8000ce6
+
+08000ce8 :
+
+ /* USER CODE END SVC_IRQn 0 */
+ /* USER CODE BEGIN SVC_IRQn 1 */
+
+ /* USER CODE END SVC_IRQn 1 */
+}
+ 8000ce8: 4770 bx lr
+
+08000cea :
+ 8000cea: 4770 bx lr
+
+08000cec :
+
+/**
+ * @brief This function handles System tick timer.
+ */
+void SysTick_Handler(void)
+{
+ 8000cec: b510 push {r4, lr}
+ /* USER CODE BEGIN SysTick_IRQn 0 */
+
+ /* USER CODE END SysTick_IRQn 0 */
+
+ /* USER CODE BEGIN SysTick_IRQn 1 */
+ led_pwm_handler();
+ 8000cee: f7ff fd23 bl 8000738
+ /* USER CODE END SysTick_IRQn 1 */
+}
+ 8000cf2: bd10 pop {r4, pc}
+
+08000cf4 :
+ 8000cf4: 4770 bx lr
+
+08000cf6 :
+{
+ /* Configure the Vector Table location add offset address ------------------*/
+#if defined (USER_VECT_TAB_ADDRESS)
+ SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+#endif /* USER_VECT_TAB_ADDRESS */
+}
+ 8000cf6: 4770 bx lr
+
+08000cf8 :
+
+ .section .text.Reset_Handler
+ .weak Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+ ldr r0, =_estack
+ 8000cf8: 4813 ldr r0, [pc, #76] ; (8000d48 )
+ mov sp, r0 /* set stack pointer */
+ 8000cfa: 4685 mov sp, r0
+
+/*Check if boot space corresponds to system memory*/
+
+ LDR R0,=0x00000004
+ 8000cfc: 4813 ldr r0, [pc, #76] ; (8000d4c )
+ LDR R1, [R0]
+ 8000cfe: 6801 ldr r1, [r0, #0]
+ LSRS R1, R1, #24
+ 8000d00: 0e09 lsrs r1, r1, #24
+ LDR R2,=0x1F
+ 8000d02: 4a13 ldr r2, [pc, #76] ; (8000d50 )
+ CMP R1, R2
+ 8000d04: 4291 cmp r1, r2
+ BNE ApplicationStart
+ 8000d06: d105 bne.n 8000d14
+
+ /*SYSCFG clock enable*/
+ LDR R0,=0x40021034
+ 8000d08: 4812 ldr r0, [pc, #72] ; (8000d54 )
+ LDR R1,=0x00000001
+ 8000d0a: 4913 ldr r1, [pc, #76] ; (8000d58 )
+ STR R1, [R0]
+ 8000d0c: 6001 str r1, [r0, #0]
+
+/*Set CFGR1 register with flash memory remap at address 0*/
+ LDR R0,=0x40010000
+ 8000d0e: 4813 ldr r0, [pc, #76] ; (8000d5c )
+ LDR R1,=0x00000000
+ 8000d10: 4913 ldr r1, [pc, #76] ; (8000d60 )
+ STR R1, [R0]
+ 8000d12: 6001 str r1, [r0, #0]
+
+08000d14 :
+
+ApplicationStart:
+/* Copy the data segment initializers from flash to SRAM */
+ ldr r0, =_sdata
+ 8000d14: 4813 ldr r0, [pc, #76] ; (8000d64 )
+ ldr r1, =_edata
+ 8000d16: 4914 ldr r1, [pc, #80] ; (8000d68 )
+ ldr r2, =_sidata
+ 8000d18: 4a14 ldr r2, [pc, #80] ; (8000d6c )
+ movs r3, #0
+ 8000d1a: 2300 movs r3, #0
+ b LoopCopyDataInit
+ 8000d1c: e002 b.n 8000d24
+
+08000d1e :
+
+CopyDataInit:
+ ldr r4, [r2, r3]
+ 8000d1e: 58d4 ldr r4, [r2, r3]
+ str r4, [r0, r3]
+ 8000d20: 50c4 str r4, [r0, r3]
+ adds r3, r3, #4
+ 8000d22: 3304 adds r3, #4
+
+08000d24 :
+
+LoopCopyDataInit:
+ adds r4, r0, r3
+ 8000d24: 18c4 adds r4, r0, r3
+ cmp r4, r1
+ 8000d26: 428c cmp r4, r1
+ bcc CopyDataInit
+ 8000d28: d3f9 bcc.n 8000d1e
+
+/* Zero fill the bss segment. */
+ ldr r2, =_sbss
+ 8000d2a: 4a11 ldr r2, [pc, #68] ; (8000d70 )
+ ldr r4, =_ebss
+ 8000d2c: 4c11 ldr r4, [pc, #68] ; (8000d74 )
+ movs r3, #0
+ 8000d2e: 2300 movs r3, #0
+ b LoopFillZerobss
+ 8000d30: e001 b.n 8000d36
+
+08000d32 :
+
+FillZerobss:
+ str r3, [r2]
+ 8000d32: 6013 str r3, [r2, #0]
+ adds r2, r2, #4
+ 8000d34: 3204 adds r2, #4
+
+08000d36 :
+
+LoopFillZerobss:
+ cmp r2, r4
+ 8000d36: 42a2 cmp r2, r4
+ bcc FillZerobss
+ 8000d38: d3fb bcc.n 8000d32
+
+/* Call the clock system intitialization function.*/
+ bl SystemInit
+ 8000d3a: f7ff ffdc bl 8000cf6
+/* Call static constructors */
+ bl __libc_init_array
+ 8000d3e: f000 f9c7 bl 80010d0 <__libc_init_array>
+/* Call the application's entry point.*/
+ bl main
+ 8000d42: f7ff fe0d bl 8000960
+
+08000d46 :
+
+LoopForever:
+ b LoopForever
+ 8000d46: e7fe b.n 8000d46
+ ldr r0, =_estack
+ 8000d48: 20000800 .word 0x20000800
+ LDR R0,=0x00000004
+ 8000d4c: 00000004 .word 0x00000004
+ LDR R2,=0x1F
+ 8000d50: 0000001f .word 0x0000001f
+ LDR R0,=0x40021034
+ 8000d54: 40021034 .word 0x40021034
+ LDR R1,=0x00000001
+ 8000d58: 00000001 .word 0x00000001
+ LDR R0,=0x40010000
+ 8000d5c: 40010000 .word 0x40010000
+ LDR R1,=0x00000000
+ 8000d60: 00000000 .word 0x00000000
+ ldr r0, =_sdata
+ 8000d64: 20000000 .word 0x20000000
+ ldr r1, =_edata
+ 8000d68: 20000004 .word 0x20000004
+ ldr r2, =_sidata
+ 8000d6c: 08001174 .word 0x08001174
+ ldr r2, =_sbss
+ 8000d70: 20000004 .word 0x20000004
+ ldr r4, =_ebss
+ 8000d74: 20000048 .word 0x20000048
+
+08000d78 :
+ * @retval : None
+*/
+ .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+ b Infinite_Loop
+ 8000d78: e7fe b.n 8000d78
+
+08000d7a :
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: GPIO registers are initialized according to GPIO_InitStruct content
+ * - ERROR: Not applicable
+ */
+ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct)
+{
+ 8000d7a: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr}
+ uint32_t pinpos = 0x00000000U;
+ 8000d7c: 2300 movs r3, #0
+{
+ 8000d7e: 0002 movs r2, r0
+ /* ------------------------- Configure the port pins ---------------- */
+ /* Initialize pinpos on first pin set */
+ /* pinpos = 0; useless as already done in default initialization */
+
+ /* Configure the port pins */
+ while (((GPIO_InitStruct->Pin) >> pinpos) != 0x00000000U)
+ 8000d80: 680c ldr r4, [r1, #0]
+ }
+
+ /* Pin Mode configuration */
+ LL_GPIO_SetPinMode(GPIOx, currentpin, GPIO_InitStruct->Mode);
+ }
+ pinpos++;
+ 8000d82: 9300 str r3, [sp, #0]
+ while (((GPIO_InitStruct->Pin) >> pinpos) != 0x00000000U)
+ 8000d84: 0020 movs r0, r4
+ 8000d86: 9b00 ldr r3, [sp, #0]
+ 8000d88: 40d8 lsrs r0, r3
+ 8000d8a: d100 bne.n 8000d8e
+ }
+
+
+ return (SUCCESS);
+}
+ 8000d8c: bdfe pop {r1, r2, r3, r4, r5, r6, r7, pc}
+ currentpin = (GPIO_InitStruct->Pin) & (0x00000001U << pinpos);
+ 8000d8e: 2001 movs r0, #1
+ 8000d90: 9b00 ldr r3, [sp, #0]
+ 8000d92: 4098 lsls r0, r3
+ 8000d94: 0023 movs r3, r4
+ 8000d96: 4003 ands r3, r0
+ if (currentpin)
+ 8000d98: 4204 tst r4, r0
+ 8000d9a: d031 beq.n 8000e00
+ if ((GPIO_InitStruct->Mode == LL_GPIO_MODE_OUTPUT) || (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE))
+ 8000d9c: 6848 ldr r0, [r1, #4]
+ 8000d9e: 2503 movs r5, #3
+ 8000da0: 9001 str r0, [sp, #4]
+ 8000da2: 0018 movs r0, r3
+ 8000da4: 4358 muls r0, r3
+ 8000da6: 4345 muls r5, r0
+ 8000da8: 9e01 ldr r6, [sp, #4]
+ 8000daa: 43ed mvns r5, r5
+ 8000dac: 1e77 subs r7, r6, #1
+ 8000dae: 2f01 cmp r7, #1
+ 8000db0: d80b bhi.n 8000dca
+ MODIFY_REG(GPIOx->OSPEEDR, ((Pin * Pin) * GPIO_OSPEEDER_OSPEED0), ((Pin * Pin) * Speed));
+ 8000db2: 688f ldr r7, [r1, #8]
+ 8000db4: 6896 ldr r6, [r2, #8]
+ 8000db6: 4347 muls r7, r0
+ 8000db8: 402e ands r6, r5
+ 8000dba: 4337 orrs r7, r6
+ 8000dbc: 6097 str r7, [r2, #8]
+ MODIFY_REG(GPIOx->OTYPER, PinMask, (PinMask * OutputType));
+ 8000dbe: 6857 ldr r7, [r2, #4]
+ 8000dc0: 68ce ldr r6, [r1, #12]
+ 8000dc2: 43a7 bics r7, r4
+ 8000dc4: 4374 muls r4, r6
+ 8000dc6: 433c orrs r4, r7
+ 8000dc8: 6054 str r4, [r2, #4]
+ MODIFY_REG(GPIOx->PUPDR, ((Pin * Pin) * GPIO_PUPDR_PUPD0), ((Pin * Pin) * Pull));
+ 8000dca: 690c ldr r4, [r1, #16]
+ 8000dcc: 68d7 ldr r7, [r2, #12]
+ 8000dce: 4344 muls r4, r0
+ 8000dd0: 402f ands r7, r5
+ 8000dd2: 433c orrs r4, r7
+ 8000dd4: 60d4 str r4, [r2, #12]
+ if (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE)
+ 8000dd6: 9c01 ldr r4, [sp, #4]
+ 8000dd8: 2c02 cmp r4, #2
+ 8000dda: d10b bne.n 8000df4
+ if (currentpin < LL_GPIO_PIN_8)
+ 8000ddc: 694f ldr r7, [r1, #20]
+ 8000dde: 2bff cmp r3, #255 ; 0xff
+ 8000de0: d811 bhi.n 8000e06
+ MODIFY_REG(GPIOx->AFR[0], ((((Pin * Pin) * Pin) * Pin) * GPIO_AFRL_AFSEL0),
+ 8000de2: 0003 movs r3, r0
+ 8000de4: 260f movs r6, #15
+ 8000de6: 4343 muls r3, r0
+ 8000de8: 435e muls r6, r3
+ 8000dea: 437b muls r3, r7
+ 8000dec: 6a14 ldr r4, [r2, #32]
+ 8000dee: 43b4 bics r4, r6
+ 8000df0: 431c orrs r4, r3
+ 8000df2: 6214 str r4, [r2, #32]
+ MODIFY_REG(GPIOx->MODER, ((Pin * Pin) * GPIO_MODER_MODE0), ((Pin * Pin) * Mode));
+ 8000df4: 6813 ldr r3, [r2, #0]
+ 8000df6: 401d ands r5, r3
+ 8000df8: 9b01 ldr r3, [sp, #4]
+ 8000dfa: 4358 muls r0, r3
+ 8000dfc: 4305 orrs r5, r0
+ 8000dfe: 6015 str r5, [r2, #0]
+ pinpos++;
+ 8000e00: 9b00 ldr r3, [sp, #0]
+ 8000e02: 3301 adds r3, #1
+ 8000e04: e7bc b.n 8000d80
+ MODIFY_REG(GPIOx->AFR[1], (((((Pin >> 8U) * (Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U)) * GPIO_AFRH_AFSEL8),
+ 8000e06: 260f movs r6, #15
+ 8000e08: 0a1b lsrs r3, r3, #8
+ 8000e0a: 435b muls r3, r3
+ 8000e0c: 435b muls r3, r3
+ 8000e0e: 435e muls r6, r3
+ 8000e10: 437b muls r3, r7
+ 8000e12: 6a54 ldr r4, [r2, #36] ; 0x24
+ 8000e14: 43b4 bics r4, r6
+ 8000e16: 431c orrs r4, r3
+ 8000e18: 6254 str r4, [r2, #36] ; 0x24
+}
+ 8000e1a: e7eb b.n 8000df4
+
+08000e1c :
+ CLEAR_BIT(I2Cx->CR1, I2C_CR1_PE);
+ 8000e1c: 2201 movs r2, #1
+ 8000e1e: 6803 ldr r3, [r0, #0]
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: I2C registers are initialized
+ * - ERROR: Not applicable
+ */
+ErrorStatus LL_I2C_Init(I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct)
+{
+ 8000e20: b530 push {r4, r5, lr}
+ 8000e22: 4393 bics r3, r2
+ 8000e24: 6003 str r3, [r0, #0]
+ MODIFY_REG(I2Cx->CR1, I2C_CR1_ANFOFF | I2C_CR1_DNF, AnalogFilter | (DigitalFilter << I2C_CR1_DNF_Pos));
+ 8000e26: 68cb ldr r3, [r1, #12]
+ 8000e28: 688d ldr r5, [r1, #8]
+ 8000e2a: 021b lsls r3, r3, #8
+ 8000e2c: 6804 ldr r4, [r0, #0]
+ 8000e2e: 432b orrs r3, r5
+ 8000e30: 4d14 ldr r5, [pc, #80] ; (8000e84 )
+ 8000e32: 402c ands r4, r5
+ 8000e34: 4323 orrs r3, r4
+ 8000e36: 6003 str r3, [r0, #0]
+ WRITE_REG(I2Cx->TIMINGR, Timing);
+ 8000e38: 684b ldr r3, [r1, #4]
+ * Disable, Configure and Enable I2Cx device own address 1 with parameters :
+ * - OwnAddress1: I2C_OAR1_OA1[9:0] bits
+ * - OwnAddrSize: I2C_OAR1_OA1MODE bit
+ */
+ LL_I2C_DisableOwnAddress1(I2Cx);
+ LL_I2C_SetOwnAddress1(I2Cx, I2C_InitStruct->OwnAddress1, I2C_InitStruct->OwnAddrSize);
+ 8000e3a: 690d ldr r5, [r1, #16]
+ 8000e3c: 6103 str r3, [r0, #16]
+ SET_BIT(I2Cx->CR1, I2C_CR1_PE);
+ 8000e3e: 6803 ldr r3, [r0, #0]
+ 8000e40: 431a orrs r2, r3
+ 8000e42: 6002 str r2, [r0, #0]
+ CLEAR_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN);
+ 8000e44: 6882 ldr r2, [r0, #8]
+ 8000e46: 4b10 ldr r3, [pc, #64] ; (8000e88 )
+ 8000e48: 401a ands r2, r3
+ 8000e4a: 6082 str r2, [r0, #8]
+ MODIFY_REG(I2Cx->OAR1, I2C_OAR1_OA1 | I2C_OAR1_OA1MODE, OwnAddress1 | OwnAddrSize);
+ 8000e4c: 6884 ldr r4, [r0, #8]
+ 8000e4e: 698a ldr r2, [r1, #24]
+ 8000e50: 0ae4 lsrs r4, r4, #11
+ 8000e52: 02e4 lsls r4, r4, #11
+ 8000e54: 432a orrs r2, r5
+ 8000e56: 4322 orrs r2, r4
+ 8000e58: 6082 str r2, [r0, #8]
+
+ /* OwnAdress1 == 0 is reserved for General Call address */
+ if (I2C_InitStruct->OwnAddress1 != 0U)
+ 8000e5a: 001c movs r4, r3
+ 8000e5c: 2d00 cmp r5, #0
+ 8000e5e: d004 beq.n 8000e6a
+ SET_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN);
+ 8000e60: 2380 movs r3, #128 ; 0x80
+ 8000e62: 6882 ldr r2, [r0, #8]
+ 8000e64: 021b lsls r3, r3, #8
+ 8000e66: 4313 orrs r3, r2
+ 8000e68: 6083 str r3, [r0, #8]
+ MODIFY_REG(I2Cx->CR1, I2C_CR1_SMBHEN | I2C_CR1_SMBDEN, PeripheralMode);
+ 8000e6a: 6802 ldr r2, [r0, #0]
+ 8000e6c: 4b07 ldr r3, [pc, #28] ; (8000e8c )
+ 8000e6e: 401a ands r2, r3
+ 8000e70: 680b ldr r3, [r1, #0]
+ 8000e72: 431a orrs r2, r3
+ 8000e74: 6002 str r2, [r0, #0]
+ MODIFY_REG(I2Cx->CR2, I2C_CR2_NACK, TypeAcknowledge);
+ 8000e76: 6843 ldr r3, [r0, #4]
+ 8000e78: 694a ldr r2, [r1, #20]
+ 8000e7a: 4023 ands r3, r4
+ 8000e7c: 4313 orrs r3, r2
+ 8000e7e: 6043 str r3, [r0, #4]
+ * - TypeAcknowledge: I2C_CR2_NACK bit
+ */
+ LL_I2C_AcknowledgeNextData(I2Cx, I2C_InitStruct->TypeAcknowledge);
+
+ return SUCCESS;
+}
+ 8000e80: 2000 movs r0, #0
+ 8000e82: bd30 pop {r4, r5, pc}
+ 8000e84: ffffe0ff .word 0xffffe0ff
+ 8000e88: ffff7fff .word 0xffff7fff
+ 8000e8c: ffcfffff .word 0xffcfffff
+
+08000e90 :
+ return ((READ_BIT(LPUARTx->CR1, USART_CR1_UE) == (USART_CR1_UE)) ? 1UL : 0UL);
+ 8000e90: 6802 ldr r2, [r0, #0]
+ * @retval An ErrorStatus enumeration value:
+ * - SUCCESS: LPUART registers are initialized according to LPUART_InitStruct content
+ * - ERROR: Problem occurred during LPUART Registers initialization
+ */
+ErrorStatus LL_LPUART_Init(USART_TypeDef *LPUARTx, LL_LPUART_InitTypeDef *LPUART_InitStruct)
+{
+ 8000e92: b5f8 push {r3, r4, r5, r6, r7, lr}
+ 8000e94: 2301 movs r3, #1
+ 8000e96: 0015 movs r5, r2
+ 8000e98: 0004 movs r4, r0
+ 8000e9a: 000e movs r6, r1
+ 8000e9c: 401d ands r5, r3
+ assert_param(IS_LL_LPUART_DIRECTION(LPUART_InitStruct->TransferDirection));
+ assert_param(IS_LL_LPUART_HWCONTROL(LPUART_InitStruct->HardwareFlowControl));
+
+ /* LPUART needs to be in disabled state, in order to be able to configure some bits in
+ CRx registers. Otherwise (LPUART not in Disabled state) => return ERROR */
+ if (LL_LPUART_IsEnabled(LPUARTx) == 0U)
+ 8000e9e: 421a tst r2, r3
+ 8000ea0: d001 beq.n 8000ea6
+ ErrorStatus status = ERROR;
+ 8000ea2: 2001 movs r0, #1
+ }
+
+ }
+
+ return (status);
+}
+ 8000ea4: bdf8 pop {r3, r4, r5, r6, r7, pc}
+ MODIFY_REG(LPUARTx->CR1,
+ 8000ea6: 684b ldr r3, [r1, #4]
+ 8000ea8: 68c9 ldr r1, [r1, #12]
+ 8000eaa: 6802 ldr r2, [r0, #0]
+ 8000eac: 430b orrs r3, r1
+ 8000eae: 6931 ldr r1, [r6, #16]
+ 8000eb0: 430b orrs r3, r1
+ 8000eb2: 4913 ldr r1, [pc, #76] ; (8000f00 )
+ 8000eb4: 400a ands r2, r1
+ 8000eb6: 4313 orrs r3, r2
+ 8000eb8: 6003 str r3, [r0, #0]
+ MODIFY_REG(LPUARTx->CR2, USART_CR2_STOP, StopBits);
+ 8000eba: 6843 ldr r3, [r0, #4]
+ 8000ebc: 4a11 ldr r2, [pc, #68] ; (8000f04 )
+ 8000ebe: 4013 ands r3, r2
+ 8000ec0: 68b2 ldr r2, [r6, #8]
+ 8000ec2: 4313 orrs r3, r2
+ 8000ec4: 6043 str r3, [r0, #4]
+ MODIFY_REG(LPUARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE, HardwareFlowControl);
+ 8000ec6: 6883 ldr r3, [r0, #8]
+ 8000ec8: 4a0f ldr r2, [pc, #60] ; (8000f08 )
+ 8000eca: 4013 ands r3, r2
+ 8000ecc: 6972 ldr r2, [r6, #20]
+ 8000ece: 4313 orrs r3, r2
+ 8000ed0: 6083 str r3, [r0, #8]
+ periphclk = LL_RCC_GetLPUARTClockFreq(LL_RCC_LPUART1_CLKSOURCE);
+ 8000ed2: 20c0 movs r0, #192 ; 0xc0
+ 8000ed4: 0100 lsls r0, r0, #4
+ 8000ed6: f000 f899 bl 800100c
+ if ((periphclk != LL_RCC_PERIPH_FREQUENCY_NO)
+ 8000eda: 2800 cmp r0, #0
+ 8000edc: d0e1 beq.n 8000ea2
+ && (LPUART_InitStruct->BaudRate != 0U))
+ 8000ede: 6832 ldr r2, [r6, #0]
+ 8000ee0: 2a00 cmp r2, #0
+ 8000ee2: d0de beq.n 8000ea2
+ LPUARTx->BRR = __LL_LPUART_DIV(PeriphClk, BaudRate);
+ 8000ee4: 0029 movs r1, r5
+ 8000ee6: 0e07 lsrs r7, r0, #24
+ 8000ee8: 0206 lsls r6, r0, #8
+ 8000eea: 0850 lsrs r0, r2, #1
+ 8000eec: 1980 adds r0, r0, r6
+ 8000eee: 4179 adcs r1, r7
+ 8000ef0: 002b movs r3, r5
+ 8000ef2: f7ff fa7f bl 80003f4 <__aeabi_uldivmod>
+ 8000ef6: 0300 lsls r0, r0, #12
+ 8000ef8: 0b00 lsrs r0, r0, #12
+ 8000efa: 60e0 str r0, [r4, #12]
+ status = SUCCESS;
+ 8000efc: 0028 movs r0, r5
+}
+ 8000efe: e7d1 b.n 8000ea4
+ 8000f00: efffe9f3 .word 0xefffe9f3
+ 8000f04: ffffcfff .word 0xffffcfff
+ 8000f08: fffffcff .word 0xfffffcff
+
+08000f0c :
+ return ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) == RCC_CR_HSIRDY) ? 1UL : 0UL);
+ 8000f0c: 4b02 ldr r3, [pc, #8] ; (8000f18 )
+ 8000f0e: 6818 ldr r0, [r3, #0]
+ 8000f10: 0740 lsls r0, r0, #29
+ 8000f12: 0fc0 lsrs r0, r0, #31
+}
+ 8000f14: 4770 bx lr
+ 8000f16: 46c0 nop ; (mov r8, r8)
+ 8000f18: 40021000 .word 0x40021000
+
+08000f1c :
+ * @rmtoll CR HSIDIVF LL_RCC_IsActiveFlag_HSIDIV
+ * @retval State of bit (1 or 0).
+ */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIDIV(void)
+{
+ return ((READ_BIT(RCC->CR, RCC_CR_HSIDIVF) == RCC_CR_HSIDIVF) ? 1UL : 0UL);
+ 8000f1c: 4b02 ldr r3, [pc, #8] ; (8000f28 )
+ 8000f1e: 6818 ldr r0, [r3, #0]
+ 8000f20: 06c0 lsls r0, r0, #27
+ 8000f22: 0fc0 lsrs r0, r0, #31
+}
+ 8000f24: 4770 bx lr
+ 8000f26: 46c0 nop ; (mov r8, r8)
+ 8000f28: 40021000 .word 0x40021000
+
+08000f2c :
+ return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE));
+ 8000f2c: 4b03 ldr r3, [pc, #12] ; (8000f3c )
+ * @retval HCLK clock frequency (in Hz)
+ */
+uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency)
+{
+ /* HCLK clock frequency */
+ return __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, LL_RCC_GetAHBPrescaler());
+ 8000f2e: 4a04 ldr r2, [pc, #16] ; (8000f40 )
+ 8000f30: 68db ldr r3, [r3, #12]
+ 8000f32: 061b lsls r3, r3, #24
+ 8000f34: 0f1b lsrs r3, r3, #28
+ 8000f36: 5cd3 ldrb r3, [r2, r3]
+ 8000f38: 40d8 lsrs r0, r3
+}
+ 8000f3a: 4770 bx lr
+ 8000f3c: 40021000 .word 0x40021000
+ 8000f40: 08001140 .word 0x08001140
+
+08000f44 :
+ return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1));
+ 8000f44: 4b03 ldr r3, [pc, #12] ; (8000f54 )
+ * @retval PCLK1 clock frequency (in Hz)
+ */
+uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency)
+{
+ /* PCLK1 clock frequency */
+ return __LL_RCC_CALC_PCLK1_FREQ(HCLK_Frequency, LL_RCC_GetAPB1Prescaler());
+ 8000f46: 4a04 ldr r2, [pc, #16] ; (8000f58 )
+ 8000f48: 68db ldr r3, [r3, #12]
+ 8000f4a: 055b lsls r3, r3, #21
+ 8000f4c: 0f5b lsrs r3, r3, #29
+ 8000f4e: 5cd3 ldrb r3, [r2, r3]
+ 8000f50: 40d8 lsrs r0, r3
+}
+ 8000f52: 4770 bx lr
+ 8000f54: 40021000 .word 0x40021000
+ 8000f58: 08001150 .word 0x08001150
+
+08000f5c :
+/**
+ * @brief Return PLL clock frequency used for system domain
+ * @retval PLL clock frequency (in Hz)
+ */
+uint32_t RCC_PLL_GetFreqDomain_SYS(void)
+{
+ 8000f5c: b510 push {r4, lr}
+ return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC));
+ 8000f5e: 4c0e ldr r4, [pc, #56] ; (8000f98 )
+ 8000f60: 68e3 ldr r3, [r4, #12]
+ /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL divider) * PLL Multiplicator */
+
+ /* Get PLL source */
+ pllsource = LL_RCC_PLL_GetMainSource();
+
+ switch (pllsource)
+ 8000f62: 03db lsls r3, r3, #15
+ 8000f64: d415 bmi.n 8000f92
+ {
+ case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
+ if (LL_RCC_IsActiveFlag_HSIDIV() != 0U)
+ 8000f66: f7ff ffd9 bl 8000f1c
+ {
+ pllinputfreq = (HSI_VALUE >> 2U);
+ }
+ else
+ {
+ pllinputfreq = HSI_VALUE;
+ 8000f6a: 1e43 subs r3, r0, #1
+ 8000f6c: 4198 sbcs r0, r3
+ 8000f6e: 4b0b ldr r3, [pc, #44] ; (8000f9c )
+ 8000f70: 4240 negs r0, r0
+ 8000f72: 4018 ands r0, r3
+ 8000f74: 4b0a ldr r3, [pc, #40] ; (8000fa0 )
+ 8000f76: 18c0 adds r0, r0, r3
+ return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLMUL));
+ 8000f78: 68e3 ldr r3, [r4, #12]
+
+ default: /* HSE used as PLL clock source */
+ pllinputfreq = HSE_VALUE;
+ break;
+ }
+ return __LL_RCC_CALC_PLLCLK_FREQ(pllinputfreq, LL_RCC_PLL_GetMultiplicator(), LL_RCC_PLL_GetDivider());
+ 8000f7a: 4a0a ldr r2, [pc, #40] ; (8000fa4 )
+ return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLDIV));
+ 8000f7c: 68e1 ldr r1, [r4, #12]
+ 8000f7e: 029b lsls r3, r3, #10
+ 8000f80: 0f1b lsrs r3, r3, #28
+ 8000f82: 5cd3 ldrb r3, [r2, r3]
+ 8000f84: 0209 lsls r1, r1, #8
+ 8000f86: 0f89 lsrs r1, r1, #30
+ 8000f88: 4358 muls r0, r3
+ 8000f8a: 3101 adds r1, #1
+ 8000f8c: f7ff f8bc bl 8000108 <__udivsi3>
+}
+ 8000f90: bd10 pop {r4, pc}
+ pllinputfreq = HSE_VALUE;
+ 8000f92: 4805 ldr r0, [pc, #20] ; (8000fa8 )
+ 8000f94: e7f0 b.n 8000f78
+ 8000f96: 46c0 nop ; (mov r8, r8)
+ 8000f98: 40021000 .word 0x40021000
+ 8000f9c: ff48e500 .word 0xff48e500
+ 8000fa0: 00f42400 .word 0x00f42400
+ 8000fa4: 08001158 .word 0x08001158
+ 8000fa8: 007a1200 .word 0x007a1200
+
+08000fac :
+ return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS));
+ 8000fac: 210c movs r1, #12
+ 8000fae: 4a13 ldr r2, [pc, #76] ; (8000ffc )
+{
+ 8000fb0: b510 push {r4, lr}
+ 8000fb2: 68d3 ldr r3, [r2, #12]
+ 8000fb4: 400b ands r3, r1
+ 8000fb6: 0011 movs r1, r2
+ switch (LL_RCC_GetSysClkSource())
+ 8000fb8: 2b08 cmp r3, #8
+ 8000fba: d01d beq.n 8000ff8
+ 8000fbc: d805 bhi.n 8000fca
+ 8000fbe: 2b00 cmp r3, #0
+ 8000fc0: d008 beq.n 8000fd4
+ 8000fc2: 2b04 cmp r3, #4
+ 8000fc4: d00e beq.n 8000fe4
+ return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_MSIRANGE));
+ 8000fc6: 684b ldr r3, [r1, #4]
+ 8000fc8: e005 b.n 8000fd6
+ 8000fca: 2b0c cmp r3, #12
+ 8000fcc: d1fb bne.n 8000fc6
+ frequency = RCC_PLL_GetFreqDomain_SYS();
+ 8000fce: f7ff ffc5 bl 8000f5c
+ break;
+ 8000fd2: e010 b.n 8000ff6
+ 8000fd4: 6853 ldr r3, [r2, #4]
+ frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_GetRange());
+ 8000fd6: 2080 movs r0, #128 ; 0x80
+ 8000fd8: 041b lsls r3, r3, #16
+ 8000fda: 0f5b lsrs r3, r3, #29
+ 8000fdc: 3301 adds r3, #1
+ 8000fde: 0200 lsls r0, r0, #8
+ 8000fe0: 4098 lsls r0, r3
+ return frequency;
+ 8000fe2: e008 b.n 8000ff6
+ if (LL_RCC_IsActiveFlag_HSIDIV() != 0U)
+ 8000fe4: f7ff ff9a bl 8000f1c
+ frequency = HSI_VALUE;
+ 8000fe8: 1e43 subs r3, r0, #1
+ 8000fea: 4198 sbcs r0, r3
+ 8000fec: 4b04 ldr r3, [pc, #16] ; (8001000 )
+ 8000fee: 4240 negs r0, r0
+ 8000ff0: 4018 ands r0, r3
+ 8000ff2: 4b04 ldr r3, [pc, #16] ; (8001004 )
+ 8000ff4: 18c0 adds r0, r0, r3
+}
+ 8000ff6: bd10 pop {r4, pc}
+ switch (LL_RCC_GetSysClkSource())
+ 8000ff8: 4803 ldr r0, [pc, #12] ; (8001008 )
+ 8000ffa: e7fc b.n 8000ff6
+ 8000ffc: 40021000 .word 0x40021000
+ 8001000: ff48e500 .word 0xff48e500
+ 8001004: 00f42400 .word 0x00f42400
+ 8001008: 007a1200 .word 0x007a1200
+
+0800100c :
+ return (uint32_t)(READ_BIT(RCC->CCIPR, LPUARTx));
+ 800100c: 4a17 ldr r2, [pc, #92] ; (800106c )
+{
+ 800100e: b510 push {r4, lr}
+ 8001010: 6cd3 ldr r3, [r2, #76] ; 0x4c
+ 8001012: 4018 ands r0, r3
+ switch (LL_RCC_GetLPUARTClockSource(LPUARTxSource))
+ 8001014: 2380 movs r3, #128 ; 0x80
+ 8001016: 011b lsls r3, r3, #4
+ 8001018: 4298 cmp r0, r3
+ 800101a: d00a beq.n 8001032
+ 800101c: 23c0 movs r3, #192 ; 0xc0
+ 800101e: 011b lsls r3, r3, #4
+ 8001020: 4298 cmp r0, r3
+ 8001022: d014 beq.n 800104e
+ 8001024: 2380 movs r3, #128 ; 0x80
+ 8001026: 00db lsls r3, r3, #3
+ 8001028: 4298 cmp r0, r3
+ 800102a: d115 bne.n 8001058
+ lpuart_frequency = RCC_GetSystemClockFreq();
+ 800102c: f7ff ffbe bl 8000fac
+}
+ 8001030: bd10 pop {r4, pc}
+ if (LL_RCC_HSI_IsReady() != 0U)
+ 8001032: f7ff ff6b bl 8000f0c
+ 8001036: 2800 cmp r0, #0
+ 8001038: d00c beq.n 8001054
+ if (LL_RCC_IsActiveFlag_HSIDIV() != 0U)
+ 800103a: f7ff ff6f bl 8000f1c
+ lpuart_frequency = HSI_VALUE;
+ 800103e: 1e43 subs r3, r0, #1
+ 8001040: 4198 sbcs r0, r3
+ 8001042: 4b0b ldr r3, [pc, #44] ; (8001070 )
+ 8001044: 4240 negs r0, r0
+ 8001046: 4018 ands r0, r3
+ 8001048: 4b0a ldr r3, [pc, #40] ; (8001074 )
+ 800104a: 18c0 adds r0, r0, r3
+ 800104c: e7f0 b.n 8001030
+ return ((READ_BIT(RCC->CSR, RCC_CSR_LSERDY) == RCC_CSR_LSERDY) ? 1UL : 0UL);
+ 800104e: 6d13 ldr r3, [r2, #80] ; 0x50
+ 8001050: 059b lsls r3, r3, #22
+ 8001052: d408 bmi.n 8001066
+ uint32_t lpuart_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
+ 8001054: 2000 movs r0, #0
+ 8001056: e7eb b.n 8001030
+ lpuart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
+ 8001058: f7ff ffa8 bl 8000fac
+ 800105c: f7ff ff66 bl 8000f2c
+ 8001060: f7ff ff70 bl 8000f44